Pixel driving circuit and driving method thereof, display panel, and display device

Abstract

A pixel driving circuit and a driving method thereof, a display panel, and a display device, wherein the pixel driving circuit comprises: a driving circuit (1), a control circuit (2), a first reset circuit (3), a second reset circuit (4), and a coupling circuit (5), wherein the driving circuit (1) is used to input a driving current to a third node (N3) through a second node (N2) according to a signal of a first node (N1); the control circuit (2) is used to respond to a signal of an enable signal terminal (EM) to connect a first power supply terminal (VDD) and a second node (N2), and to respond to a signal of the enable signal terminal (EM) to connect a third node (N3) and a fourth node (N4); the first reset circuit (3) is used to respond to a signal of a reset signal terminal (Re) to connect an initial signal terminal (V init) to a fourth node (N4); the second reset circuit (4) is used to transmit a signal from the first power supply terminal (VDD) to the first node (N1) in response to a signal from the reset signal terminal (Re); the coupling circuit (5) is connected between the first node (N1) and the fourth node (N4); wherein the drive circuit (1), the control circuit (2), the first reset circuit (3) and the second reset circuit (4) all include transistors, and the transistors in the drive circuit (1), the control circuit (2), the first reset circuit (3) and the second reset circuit (4) are all N-type transistors, and at least part of the transistors in the first reset circuit (3) are oxide transistors, and at least part of the transistors in the second reset circuit (4) are oxide transistors. The pixel drive circuit can be driven by only one set of gate drive circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] In the related art, the pixel driving circuit can be formed by using LTPO (Low temperature polycrystalline TFT + Oxide TFT) technology. LTPO technology forms a pixel driving circuit by combining an N-type oxide transistor and a P-type low temperature polycrystalline silicon transistor. However, the pixel driving circuit formed by LTPO technology requires two sets of gate driving circuits to provide gate driving signals to the N-type transistor and the P-type transistor respectively.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0004] Public Content

[0005] According to one aspect of the present disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes: a driving circuit, a control circuit, a first reset circuit, a second reset circuit, and a coupling circuit, wherein the driving circuit is connected to a first node, a second node, and a third node, and is used to input a driving current to the third node through the second node according to a signal of the first node. The control circuit is connected to a first power supply terminal, a second node, a third node, a fourth node, and an enable signal terminal, and is used to respond to a signal of the enable signal terminal to connect the first power supply terminal and the second node, and to respond to a signal of the enable signal terminal to connect the third node and the fourth node. The first reset circuit is connected to the fourth node, a reset signal terminal, and an initial signal terminal, and is used to respond to a signal of the reset signal terminal to transmit a signal of the initial signal terminal to the fourth node. The second reset circuit is connected to the first node, the first power supply terminal, and the reset signal terminal, and is used to respond to a signal of the reset signal terminal to transmit a signal of the first power supply terminal to the first node. The coupling circuit is connected between the first node and the fourth node; wherein the drive circuit, the control circuit, the first reset circuit, and the second reset circuit all include transistors, and the transistors in the drive circuit, the control circuit, the first reset circuit, and the second reset circuit are all N-type transistors, and the transistors in the first reset circuit are at least partially oxide transistors, and the transistors in the second reset circuit are at least partially oxide transistors.

[0006] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes: a data writing circuit and a threshold compensation circuit, wherein the data writing circuit is connected to the second node, the data signal terminal, and the gate driving signal terminal, and is used to respond to the signal of the gate driving signal terminal to transmit the signal of the data signal terminal to the second node; the threshold compensation circuit is connected to the third node, the first node, and the gate driving signal terminal, and is used to respond to the signal of the gate driving signal terminal to connect the first node and the third node; wherein the data writing circuit and the threshold compensation circuit both include transistors, and the transistors in the data writing circuit and the threshold compensation circuit are both N-type transistors.

[0007] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes: a data writing circuit and a threshold compensation circuit, wherein the data writing circuit is connected to the third node, the data signal terminal, and the gate driving signal terminal, and is used to respond to the signal of the gate driving signal terminal to transmit the signal of the data signal terminal to the third node; the threshold compensation circuit is connected to the second node, the first node, and the gate driving signal terminal, and is used to respond to the signal of the gate driving signal terminal to connect the first node and the second node; wherein the data writing circuit and the threshold compensation circuit both include transistors, and the transistors in the data writing circuit and the threshold compensation circuit are both N-type transistors.

[0008] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node. The control circuit includes: a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected to the enable signal terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second node, the gate of the sixth transistor is connected to the enable signal terminal, the first electrode is connected to the third node, and the second electrode is connected to the fourth node. The first reset circuit includes: a first transistor, the gate of the first transistor is connected to the reset signal terminal, the first electrode is connected to the initial signal terminal, and the second electrode is connected to the fourth node. The second reset circuit includes: a second transistor, the gate of the second transistor is connected to the reset signal terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the first node. The coupling circuit includes a capacitor, and the capacitor is connected between the first node and the fourth node. Among them, the driving transistor, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are N-type transistors, and the first transistor and the second transistor are oxide transistors.

[0009] In an exemplary embodiment of the present disclosure, the data writing circuit includes: a fourth transistor, the gate of the fourth transistor is connected to the gate drive signal terminal, the first electrode is connected to the data signal terminal, and the second electrode is connected to the second node. The threshold compensation circuit includes: a seventh transistor, the gate of the seventh transistor is connected to the gate drive signal terminal, the first electrode is connected to the first node, and the second electrode is connected to the third node. The fourth transistor and the seventh transistor are N-type transistors.

[0010] In an exemplary embodiment of the present disclosure, the transistors in the data writing circuit, the threshold compensation circuit, the control circuit, and the driving circuit are N-type low-temperature polysilicon transistors.

[0011] According to one aspect of the present disclosure, a pixel driving circuit driving method is provided, for driving the above-mentioned pixel driving circuit, wherein the driving method comprises:

[0012] In the reset phase, a valid level is input to the reset signal terminal, and an invalid level is input to the enable signal terminal;

[0013] In the light emitting stage, an invalid level is input to the reset signal terminal, and a valid level is input to the enable signal terminal.

[0014] According to one aspect of the present disclosure, a pixel driving circuit driving method is provided, for driving the above-mentioned pixel driving circuit, wherein the driving method comprises:

[0015] In the reset stage, a valid level is input to the reset signal terminal, and an invalid level is input to the enable signal terminal and the gate drive signal terminal;

[0016] In the threshold compensation stage, a valid level is input to the gate drive signal terminal, and an invalid level is input to the reset signal terminal and the enable signal terminal;

[0017] In the light emitting stage, an invalid level is input to the reset signal terminal and the gate driving signal terminal, and a valid level is input to the enable signal terminal.

[0018] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned pixel driving circuit.

[0019] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit, and the pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor. The first electrode of the first transistor is connected to an initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the second transistor is connected to a power line, and the second electrode is connected to the gate of the driving transistor; the gate of the fifth transistor is connected to an enable signal line, the first electrode is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the gate of the sixth transistor is connected to the enable signal line, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the gate of the fourth transistor is connected to a gate drive signal line, the first electrode is connected to a data line, and the second electrode is connected to the first electrode of the driving transistor; the gate of the seventh transistor is connected to the gate drive signal line, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the sixth transistor. The driving transistor, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the fourth transistor, and the seventh transistor are N-type transistors, and the first transistor and the second transistor are oxide transistors.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes: a substrate, a first active layer, a first conductive layer, and a second active layer, wherein the first active layer is located on one side of the substrate, and the first active layer includes a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion; wherein the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; the first conductive layer is located on the side of the first active portion away from the substrate substrate On one side of the board, the first conductive layer includes a first conductive portion, the gate drive signal line, and the enable signal line; wherein the first conductive portion covers the third active portion on the orthographic projection of the substrate substrate, the first conductive portion is used to form the gate of the driving transistor, and the orthographic projection of the gate drive signal line on the substrate substrate and the orthographic projection of the enable signal line on the substrate substrate extend along a first direction; the second active layer is located on the side of the first conductive layer away from the substrate substrate, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

[0021] In an exemplary embodiment of the present disclosure, the first conductive layer is also used to form a first electrode of the capacitor, and the display panel also includes: a second conductive layer, the second conductive layer is located between the first conductive layer and the second active layer, the second conductive layer includes a second conductive portion, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the second conductive portion is used to form a second electrode of the capacitor.

[0022] In an exemplary embodiment of the present disclosure, the orthographic projection of the first conductive portion on the substrate substrate is located between the orthographic projection of the gate drive signal line on the substrate substrate and the orthographic projection of the enable signal line on the substrate substrate; the orthographic projection of the first active portion on the substrate substrate is located on a side where the orthographic projection of the enable signal line on the substrate substrate is away from the orthographic projection of the first conductive portion on the substrate substrate, and the orthographic projection of the second active portion on the substrate substrate is located on a side where the orthographic projection of the gate drive signal line on the substrate substrate is away from the orthographic projection of the first conductive portion on the substrate substrate; the display panel further includes: a third conductive layer, the third conductive layer is located on the side where the second active layer is away from the substrate substrate On one side of the base substrate, the third conductive layer includes a first reset signal line and a second reset signal line; wherein, the orthographic projection of the first reset signal line on the base substrate extends along the first direction, the orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the first active part on the base substrate, and a partial structure of the first reset signal line is used to form a first gate of the first transistor; the orthographic projection of the second reset signal line on the base substrate extends along the first direction, the orthographic projection of the second reset signal line on the base substrate covers the orthographic projection of the second active part on the base substrate, and a partial structure of the second reset signal line is used to form a first gate of the second transistor.

[0023] In an exemplary embodiment of the present disclosure, the display panel also includes: a second conductive layer, the second conductive layer is located between the first conductive layer and the second active layer, the second conductive layer includes a third reset signal line and a fourth reset signal line; wherein, the orthographic projection of the third reset signal line on the base substrate extends along the first direction, the orthographic projection of the third reset signal line on the base substrate covers the orthographic projection of the first active part on the base substrate, and a partial structure of the third reset signal line is used to form a second gate of the first transistor; the orthographic projection of the fourth reset signal line on the base substrate extends along the first direction, the orthographic projection of the fourth reset signal line on the base substrate covers the orthographic projection of the second active part on the base substrate, and a partial structure of the fourth reset signal line is used to form a second gate of the second transistor.

[0024] In an exemplary embodiment of the present disclosure, the orthographic projection of the first active portion on the substrate and the orthographic projection of the second active portion on the substrate are both located on a side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the first conductive portion on the substrate; the display panel further includes: a third conductive layer, the third conductive layer is located on a side of the second active layer away from the substrate, the third conductive layer includes a fifth reset signal line; wherein the orthographic projection of the fifth reset signal line on the substrate extends along the first direction, the orthographic projection of the fifth reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate and the orthographic projection of the second active portion on the substrate, a partial structure of the fifth reset signal line is used to form a first gate of the first transistor, and another partial structure of the fifth reset signal line is used to form a first gate of the second transistor.

[0025] In an exemplary embodiment of the present disclosure, the display panel further includes: a third conductive layer and a fourth conductive layer, the third conductive layer being located on a side of the second active layer away from the base substrate; the fourth conductive layer being located on a side of the third conductive layer away from the base substrate, the fourth conductive layer including the data line and the power line; wherein the orthographic projection of the data line on the base substrate and the orthographic projection of the power line on the base substrate extend along a second direction, the second direction intersects with the first direction, and the orthographic projection of the power line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first conductive portion on the base substrate.

[0026] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes the data line; in the first direction, the orthographic projection of the second active portion on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first active portion on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the display panel further includes: a third conductive layer and a fifth conductive layer, the third conductive layer being located on a side of the second active layer away from the base substrate; the fifth conductive layer being located on a side of the third conductive layer away from the base substrate, the fifth conductive layer including the initial signal line; and the square resistance of the fifth conductive layer being smaller than the square resistance of the third conductive layer.

[0028] In an exemplary embodiment of the present disclosure, an orthographic projection of the initial signal line on the base substrate covers an orthographic projection of the first active portion on the base substrate and an orthographic projection of the second active portion on the base substrate.

[0029] In an exemplary embodiment of the present disclosure, an orthographic projection of the initial signal line on the base substrate covers an orthographic projection of the first conductive portion on the base substrate.

[0030] In an exemplary embodiment of the present disclosure, the orthographic projection of the initial signal line on the substrate extends along a second direction, and the second direction intersects with the first direction; the fifth conductive layer also includes: a connecting portion, the orthographic projection of the connecting portion on the substrate extends along the first direction, and the connecting portion is connected between two adjacent initial signal lines.

[0031] In an exemplary embodiment of the present disclosure, the orthographic projection of the initial signal line on the substrate extends along a second direction, and the second direction intersects with the first direction; the third conductive layer includes a second reset signal line, and the orthographic projection of the second reset signal line on the substrate extends along the first direction, and the orthographic projection of the second reset signal line on the substrate covers the orthographic projection of the second active part on the substrate, and a partial structure of the second reset signal line is used to form a first gate of the second transistor; an opening is provided on the initial signal line, and the orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate.

[0032] In an exemplary embodiment of the present disclosure, the seventh active portion includes a first sub-active portion and a second sub-active portion, and the first active layer also includes a third sub-active portion connected between the first sub-active portion and the second sub-active portion; the orthographic projection of the initial signal line on the base substrate covers the orthographic projection of the third sub-active portion on the base substrate.

[0033] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 is a circuit structure schematic diagram of a pixel driving circuit in the related art;

[0037] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0038] Figure 3 A schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0039] Figure 4 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0040] Figure 5 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0041] Figure 6a for Figure 4 The timing diagram of each node of the pixel driving circuit;

[0042] Figure 6b for Figure 4 Simulation timing diagram of each node of the pixel driving circuit;

[0043] Figure 7 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0044] Figure 8 for Figure 7 The structural layout of the first active layer in FIG.

[0045] Fig. 9 for Figure 7 A structural layout of the first conductive layer;

[0046] Fig.10 for Figure 7 The structural layout of the second conductive layer;

[0047] Fig.11 for Figure 7 The structural layout of the second active layer;

[0048] Fig.12 for Figure 7 The structural layout of the third conductive layer;

[0049] Fig.13 for Figure 7 The structural layout of the fourth conductive layer;

[0050] Fig.14 for Figure 7 The structural layout of the fifth conductive layer;

[0051] Fig.15 for Figure 7 The structural layout of the anode layer;

[0052] Fig.16 for Figure 7 A structural layout of a first active layer and a first conductive layer;

[0053] Fig.17 for Figure 7 A structural layout of a first active layer, a first conductive layer, and a second conductive layer;

[0054] Fig.18 for Figure 7 A structural layout of a first active layer, a first conductive layer, a second conductive layer, and a second active layer;

[0055] Fig.19 for Figure 7 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer;

[0056] Fig. 20 for Figure 7 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0057] Fig.21 for Figure 7 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0058] Fig. 22 for Figure 7 A partial cross-sectional view along the dotted line AA;

[0059] Fig.23 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0060] Fig.24 for Fig.23 The structural layout of the first active layer in FIG.

[0061] Fig.25 for Fig.23 A structural layout of the first conductive layer;

[0062] Fig.26 for Fig.23 The structural layout of the second conductive layer;

[0063] Fig. 27 for Fig.23 The structural layout of the second active layer;

[0064] Fig.28 for Fig.23 The structural layout of the third conductive layer;

[0065] Fig.29 for Fig.23 The structural layout of the fourth conductive layer;

[0066] Fig.30 for Fig.23 The structural layout of the fifth conductive layer;

[0067] Fig.31 for Fig.23 The structural layout of the anode layer;

[0068] Fig.32 for Fig.23 A structural layout of a first active layer and a first conductive layer;

[0069] Fig.33 for Fig.23 A structural layout of a first active layer, a first conductive layer, and a second conductive layer;

[0070] Fig.34 for Fig.23 A structural layout of a first active layer, a first conductive layer, a second conductive layer, and a second active layer;

[0071] Fig.35 for Fig.23 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer;

[0072] Fig.36 for Fig.23 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0073] Fig.37 for Fig.23 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0074] Fig.38 for Fig.23 Partial cross-sectional view along dotted line AA. DETAILED DESCRIPTION

[0075] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0076] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0077] like Figure 1, which is a schematic diagram of a circuit structure of a pixel driving circuit in the related art. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED, used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistor has a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage. At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors, and the P-type low-temperature polycrystalline silicon transistor has a high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.

[0078] like Figure 2 As shown, Figure 1A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the gate driving signal terminal G1, G2 represents the timing of the gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the gate drive signal terminal G1 outputs a high-level signal, the gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Da outputs a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0079] However, using Figure 1 The display panel of the pixel driving circuit shown needs to be provided with two sets of gate driving circuits to provide gate driving signals to the N-type transistors (e.g., the first transistor T1, the second transistor T2) and the P-type transistors (e.g., the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7) in the pixel driving circuit respectively. Figure 1The driving current output by the pixel driving circuit is related to the voltage of the first power supply terminal Vdd, which is provided by a power supply line located on the display panel. However, due to the voltage drop (IR-drop) of the power supply line itself, the power supply lines at different positions on the display panel have different voltages, resulting in uneven display of the display panel at the same gray scale.

[0080] Based on this, this exemplary embodiment provides a pixel driving circuit, such as Figure 3 As shown, it is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. Among them, the pixel driving circuit may include: a driving circuit 1, a control circuit 2, a first reset circuit 3, a second reset circuit 4, and a coupling circuit 5. The driving circuit 1 can be connected to the first node N1, the second node N2, and the third node N3, and is used to input a driving current to the third node N3 through the second node N2 according to the signal of the first node N1. The control circuit 2 can be connected to the first power supply terminal VDD, the second node N2, the third node N3, the fourth node N4, and the enable signal terminal EM, and is used to respond to the signal of the enable signal terminal EM to connect the first power supply terminal VDD and the second node N2, and to respond to the signal of the enable signal terminal EM to connect the third node N3 and the fourth node N4. The first reset circuit 3 can be connected to the fourth node N4, the reset signal terminal Re, and the initial signal terminal Vinit, and is used to respond to the signal of the reset signal terminal Re to transmit the signal of the initial signal terminal Vinit to the fourth node N4. The second reset circuit 4 can be connected to the first node N1, the first power supply terminal VDD, and the reset signal terminal Re, and is used to transmit the signal of the first power supply terminal VDD to the first node N1 in response to the signal of the reset signal terminal Re. The coupling circuit 5 can be connected between the first node N1 and the fourth node N4; wherein the driving circuit 1, the control circuit 2, the first reset circuit 3, and the second reset circuit 4 can all include transistors, and the transistors in the driving circuit 1, the control circuit 2, the first reset circuit 3, and the second reset circuit 4 are all N-type transistors, and the transistors in the first reset circuit 3 are oxide transistors, and the transistors in the second reset circuit are oxide transistors. In this exemplary embodiment, Figure 3 As shown, the fourth node can be used to connect a light-emitting unit OLED, the other end of the light-emitting unit OLED can be connected to the second power supply terminal VSS, the pixel driving circuit can drive the light-emitting unit OLED to emit light, and the light-emitting unit can be a light-emitting diode.

[0081] In this exemplary embodiment, on the one hand, the transistors in the driving circuit 1, the control circuit 2, the first reset circuit 3, and the second reset circuit 4 are all N-type transistors, and the pixel driving circuit can provide a gate driving signal to the transistors in the pixel driving circuit through a group of gate driving circuits. On the other hand, the transistor in the first reset circuit 3 is an oxide transistor. For example, the material of the channel region of the oxide transistor can be indium gallium zinc oxide. The oxide transistor has a small leakage current, so that the leakage current of the fourth node N4 through the first reset circuit during the light-emitting stage can be reduced; the transistor in the second reset circuit is an oxide transistor. Similarly, this setting can reduce the leakage current of the first node N1 through the second reset circuit during the light-emitting stage. On the other hand, the pixel driving circuit can include a reset stage, a threshold compensation stage, and a light-emitting stage. Among them, in the reset stage: the first reset circuit 3 can respond to the signal of the reset signal end to transmit the initial signal of the initial signal end Vinit to the fourth node N4, wherein writing the initial signal to the fourth node N4 can eliminate the carriers that are not recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode. At the same time, the second reset circuit 4 can respond to the signal of the reset signal end to transmit the signal of the first power supply end VDD to the first node to reset the first node N1. In the threshold compensation stage, the data signal and the related amount of the threshold of the driving transistor T3 can be written to the first node N1. For example, in the threshold compensation stage, the compensation voltage Vdata+Vth can be written to the first node, wherein Vdata is the voltage of the data signal, and Vth is the voltage of the driving transistor T3. In the light-emitting stage, the control circuit can respond to the signal of the enable signal terminal to connect the first power supply terminal and the second node N2, the third node N3 and the fourth node N4, and the voltage of the fourth node N4 changes from Vinit to Voled, where Vinit is the voltage of the initial signal. Under the coupling action of the coupling circuit 5, the voltage of the first node N1 changes to Vdata+Vth+Voled-Vinit, thereby driving the output current of the transistor I=(μWCox / 2L)(Vdata+Vth+Voled-Vinit-Voled-Vth) 2 =(μWCox / 2L)(Vdata-Vinit) 2, that is, the output current of the pixel driving circuit is not related to the voltage of the first power supply terminal VDD, and the display panel using the pixel driving circuit will not have uneven display due to the voltage drop (IR-drop) of the power supply line itself. At the same time, in this exemplary embodiment, before the end of the reset phase, the initial signal terminal Vinit can have completed charging the capacitor C, that is, at the end of the reset phase, there is no current on the initial signal line used to provide the initial signal terminal, so that although the initial signal line itself has resistance, there is no current on the initial signal line after the initial signal terminal Vinit writes the voltage to the capacitor C, so there will be no voltage drop (IR-drop) on the initial signal line, that is, the voltage of the initial signal terminal at different positions of the display panel will not be different due to the resistance of the initial signal line itself.

[0082] It should be understood that the pixel driving circuit may also include other structures for writing a compensation voltage to the first node N1 during the threshold compensation phase. Figure 4 As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. In this exemplary embodiment, the pixel driving circuit may further include: a data writing circuit 6 and a threshold compensation circuit 7, wherein the data writing circuit 6 may be connected to the second node N2, the data signal terminal Vdata, and the gate driving signal terminal Gate, and is used to respond to the signal of the gate driving signal terminal Gate to transmit the signal of the data signal terminal Vdata to the second node N2; the threshold compensation circuit 7 may be connected to the third node N3, the first node N1, and the gate driving signal terminal Gate, and is used to respond to the signal of the gate driving signal terminal Gate to connect the first node N1 and the third node N3; wherein the data writing circuit 6 and the threshold compensation circuit 7 both include transistors, and the transistors in the data writing circuit 6 and the threshold compensation circuit 7 are all N-type transistors. The transistors in the data writing circuit 6 and the threshold compensation circuit 7 may share a set of gate driving circuits with the transistors in the control circuit 2, the first reset circuit 3, and the second reset circuit 4. In the threshold compensation stage, the data write circuit 6 can respond to the signal of the gate drive signal terminal Gate to transmit the signal of the data signal terminal Vdata to the second node N2, and the threshold compensation circuit 7 can respond to the signal of the gate drive signal terminal Gate to connect the first node N1 and the third node N3, so that the voltage Vdata+Vth can be written to the first node, where Vdata is the voltage of the data signal and Vth is the voltage of the driving transistor T3.

[0083] In this exemplary embodiment, Figure 3 , 4As shown, the driving circuit 1 may include: a driving transistor T3, the gate of the driving transistor T3 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. The control circuit 2 may include: a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode is connected to the first power supply terminal VDD, and the second electrode is connected to the second node N2, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode is connected to the third node N3, and the second electrode is connected to the fourth node N4. The first reset circuit 3 may include: a first transistor T1, the gate of the first transistor T1 is connected to the reset signal terminal Re, the first electrode is connected to the initial signal terminal Vinit, and the second electrode is connected to the fourth node N4. The second reset circuit 4 may include: a second transistor T2, the gate of the second transistor T2 is connected to the reset signal terminal Re, the first electrode is connected to the first power supply terminal VDD, and the second electrode is connected to the first node N1. The coupling circuit may include a capacitor C, and the capacitor C is connected between the first node and the fourth node. Among them, the driving transistor T3, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be N-type transistors, and the first transistor T1 and the second transistor T2 can be oxide transistors. For example, the material of the channel region of the oxide transistor can be indium gallium zinc oxide.

[0084] In this exemplary embodiment, Figure 4 As shown, the data writing circuit 6 may include: a fourth transistor T4, the gate of the fourth transistor T4 is connected to the gate drive signal terminal Gate, the first electrode is connected to the data signal terminal Vdata, and the second electrode is connected to the second node N2. The threshold compensation circuit 7 may include: a seventh transistor T7, the gate of the seventh transistor T7 is connected to the gate drive signal terminal Gate, the first electrode is connected to the first node N1, and the second electrode is connected to the third node N3. The fourth transistor T4 and the seventh transistor T7 may be N-type transistors.

[0085] In this exemplary embodiment, the transistors in the data writing circuit 6, the threshold compensation circuit 7, the control circuit 2, and the driving circuit 1 may be N-type low temperature polysilicon transistors. Figure 4As shown, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type low-temperature polysilicon transistors, which have high carrier mobility, thereby being conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. It should be noted that the first reset circuit 3 can also include an N-type low-temperature polysilicon transistor, for example, the N-type low-temperature polysilicon transistor can be arranged in series with the N-type oxide transistor in the first reset circuit 3. Similarly, the second reset circuit 4 can also include an N-type low-temperature polysilicon transistor arranged in series with the N-type oxide transistor therein.

[0086] It should be understood that in other exemplary embodiments, the pixel driving circuit may also write the compensation voltage to the first node N1 through other structures. Figure 5 As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may also include: a data writing circuit 6 and a threshold compensation circuit 7, wherein the data writing circuit 6 may be connected to the third node N3, the data signal terminal, and the gate driving signal terminal Gate, and is used to respond to the signal of the gate driving signal terminal Gate to transmit the signal of the data signal terminal to the third node N3; the threshold compensation circuit 7 is connected to the second node N2, the first node N1, and the gate driving signal terminal Gate, and is used to respond to the signal of the gate driving signal terminal Gate to connect the first node N1 and the second node N2; wherein the data writing circuit 6 and the threshold compensation circuit 7 both include transistors, and the transistors in the data writing circuit 6 and the threshold compensation circuit 7 are all N-type transistors. In the threshold compensation stage, the data write circuit 6 can respond to the signal of the gate drive signal terminal Gate to transmit the signal of the data signal terminal Vdata to the third node N3, and the threshold compensation circuit 7 can respond to the signal of the gate drive signal terminal Gate to connect the first node N1 and the second node N2, driving the transistor T3 to form a diode structure, so that the voltage Vdata+Vth can be written to the first node, where Vdata is the voltage of the data signal and Vth is the voltage of the driving transistor T3.

[0087] like Figure 6a As shown, Figure 4The timing diagram of each node of the pixel driving circuit is shown in the figure, wherein Gate is the timing of the gate driving signal terminal, EM is the timing of the enable signal terminal EM, and Re is the timing of the reset signal terminal. In this exemplary embodiment, the voltage of the first power supply terminal VDD can be a high-level voltage, and the voltage of the second power supply terminal VSS can be a low-level voltage. The driving method of the pixel driving circuit may include: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light-emitting stage t4. In the reset stage t1: the enable signal terminal EM and the gate driving signal terminal Gate output an invalid level (low level), the reset signal terminal Re outputs a valid level (high level), the first transistor T1 and the second transistor T2 are turned on, the high-level signal of the first power supply terminal VDD is transmitted to the first node N1, and the signal of the initial signal terminal Vinit is transmitted to the fourth node N4. In the threshold compensation stage t2: the enable signal terminal EM and the reset signal terminal Re output an invalid level (low level), the gate drive signal terminal Gate outputs a valid level (high level), the fourth transistor T4 and the seventh transistor T7 are turned on, and the data signal terminal Vdata writes the compensation voltage Vdata+Vth to the first node. In the buffer stage t3: the gate drive signal terminal Gate, the enable signal terminal EM, and the reset signal terminal Re output an invalid level (low level). In the light-emitting stage t4: the reset signal terminal Re and the gate drive signal terminal Gate output an invalid level (low level), the enable signal terminal EM outputs a valid level (high level), the fifth transistor T5 and the sixth transistor T6 are turned on, and the voltage of the fourth node N4 changes from Vinit to Voled, where Vinit is the voltage of the initial signal. Under the coupling effect of the capacitor C, the voltage of the first node N1 changes to Vdata+Vth+Voled-Vinit, thereby driving the output current I of the transistor = (μWCox / 2L)(Vdata+Vth+Voled-Vinit-Voled-Vth) 2 =(μWCox / 2L)(Vdata-Vinit) 2 , that is, the output current of the pixel driving circuit is not related to the voltage of the first power supply terminal VDD, so that the display panel using the pixel driving circuit will not have uneven display due to the voltage drop (IR-drop) of the power line itself. It should be understood that in other exemplary embodiments, the driving method of the pixel driving circuit may not include the buffer stage t3.

[0088] like Figure 6b As shown, Figure 4 In the simulation timing diagram of each node of the pixel driving circuit, Gate is the timing of the gate driving signal terminal, EM is the timing of the enable signal terminal EM, Re is the timing of the reset signal terminal, N1 is the timing of the first node, N2 is the timing of the second node, N3 is the timing of the third node, N4 is the timing of the fourth node, and I is the output current of the driving transistor. Figure 6b The timing diagrams of each node under three data signals are shown. The driving method of the pixel driving circuit may also include: a reset phase t1, a threshold compensation phase t2, a buffer phase t3, and a light emitting phase t4.

[0089] This exemplary embodiment further provides a pixel driving circuit driving method, which is used to drive the above-mentioned pixel driving circuit, wherein the driving method includes:

[0090] In the reset stage, a valid level is input to the reset signal terminal Re, and an invalid level is input to the enable signal terminal EM and the gate drive signal terminal Gate;

[0091] In the threshold compensation stage, a valid level is input to the gate drive signal terminal Gate, and an invalid level is input to the reset signal terminal Re and the enable signal terminal EM;

[0092] In the light emitting stage, an invalid level is input to the reset signal terminal Re and the gate driving signal terminal Gate, and a valid level is input to the enable signal terminal EM.

[0093] The pixel driving circuit driving method has been described in detail in the above content and will not be repeated here.

[0094] This exemplary embodiment also provides a display panel, wherein the display panel includes the above-mentioned pixel driving circuit.

[0095] The present exemplary embodiment also provides a display panel, which may include Figure 4 The pixel driving circuit shown in the figure, the display panel may also include a base substrate, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an anode layer stacked in sequence, and an insulating layer may be provided between the adjacent layers. Figure 7-Figure 21 As shown, Figure 7 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Figure 8 for Figure 7 The structural layout of the first active layer in Fig. 9 for Figure 7 The structural layout of the first conductive layer in Fig.10 for Figure 7 The structural layout of the second conductive layer in Fig.11 for Figure 7 The structural layout of the second active layer, Fig.12 for Figure 7 The structural layout of the third conductive layer, Fig.13 for Figure 7 The structural layout of the fourth conductive layer in Fig.14 for Figure 7 The structural layout of the fifth conductive layer, Fig.15 for Figure 7 The structural layout of the anode layer. Fig.16 for Figure 7 The structural layout of the first active layer and the first conductive layer, Fig.17 for Figure 7 The structural layout of the first active layer, the first conductive layer, and the second conductive layer, Fig.18 for Figure 7 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Fig.19 for Figure 7 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Fig. 20 for Figure 7 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer, Fig.21 for Figure 7 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer.

[0096] like Figure 7 , 8 16, the first active layer may include: a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67. The third active portion 63 is used to form a channel region of the driving transistor T3, the fourth active portion 64 is used to form a channel region of the fourth transistor T4, the fifth active portion 65 is used to form a channel region of the fifth transistor T5, the sixth active portion 66 is used to form a channel region of the sixth transistor T6, and the seventh active portion 67 is used to form a channel region of the seventh transistor T7. The first active layer may be formed of polysilicon, and accordingly, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be N-type low temperature polysilicon transistors.

[0097] like Figure 7 , 9As shown in Figures 1 and 16, the first conductive layer may include: a first conductive portion 11, a gate drive signal line Gate, and an enable signal line EM. The orthographic projection of the first conductive portion 11 on the base substrate covers the third active portion 63, and the first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The orthographic projection of the gate drive signal line Gate on the base substrate and the orthographic projection of the enable signal line EM on the base substrate can both extend along the first direction X. Among them, the orthographic projection of the gate drive signal line Gate on the base substrate covers the orthographic projection of the fourth active portion 64 on the base substrate and the orthographic projection of the seventh active portion 67 on the base substrate, and a partial structure of the gate drive signal line Gate can be used to form the gate of the fourth transistor, and another partial structure of the gate drive signal line Gate can be used to form the gate of the seventh transistor. The orthographic projection of the enable signal line EM on the substrate can cover the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The orthographic projection of the first conductive portion 11 on the substrate can be located between the orthographic projection of the gate drive signal line Gate on the substrate and the orthographic projection of the enable signal line EM on the substrate. In addition, the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer forms the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0098] like Figure 7 , 10 , 17, the second conductive layer may include a third reset signal line 2Re3, a fourth reset signal line 2Re4, and a second conductive portion 22. The orthographic projection of the second conductive portion 22 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 may form a second electrode of the capacitor C. The second conductive portion 22 may also be provided with an opening 221. The third reset signal line 2Re3 may be connected to the gate of the first transistor T1, and the fourth reset signal line 2Re4 may be connected to the gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re3 on the substrate and the orthographic projection of the fourth reset signal line 2Re4 on the substrate may both extend along the first direction X.

[0099] like Figure 7 , 11As shown in Figures 18, the second active layer may include a first active portion 71 and a second active portion 72. The first active portion 71 may be used to form a channel region of the first transistor T1, and the second active portion 72 may be used to form a channel region of the second transistor. The orthographic projection of the first active portion 71 on the substrate may be located on a side where the orthographic projection of the enable signal line EM on the substrate is away from the orthographic projection of the first conductive portion 11 on the substrate, and the orthographic projection of the second active portion 72 on the substrate may be located on a side where the orthographic projection of the gate drive signal line Gate on the substrate is away from the orthographic projection of the first conductive portion 11 on the substrate. Fig.18 As shown, the orthographic projection of the third reset signal line 2Re3 on the substrate covers the orthographic projection of the first active portion 71 on the substrate, and a portion of the structure of the third reset signal line 2Re3 can be used to form the bottom gate (second gate) of the first transistor T1, and the orthographic projection of the fourth reset signal line 2Re4 on the substrate covers the orthographic projection of the second active portion 72 on the substrate, and a portion of the structure of the fourth reset signal line 2Re4 can be used to form the bottom gate (second gate) of the second transistor. The second active layer can be formed of indium gallium zinc oxide, and accordingly, the first transistor and the second transistor can be N-type metal oxide transistors.

[0100] like Figure 7 , 12 As shown in , 19, the third conductive layer may include: a first reset signal line 3Re1 and a second reset signal line 3Re2. The orthographic projection of the first reset signal line 3Re1 on the base substrate may extend along the first direction X, the orthographic projection of the first reset signal line 3Re1 on the base substrate may cover the orthographic projection of the first active portion 71 on the base substrate, and a partial structure of the first reset signal line 3Re1 is used to form the top gate (first gate) of the first transistor T1. The orthographic projection of the second reset signal line 3Re2 on the base substrate may extend along the first direction X, the orthographic projection of the second reset signal line 3Re2 on the base substrate may cover the orthographic projection of the second active portion 72 on the base substrate, and a partial structure of the second reset signal line 3Re2 may be used to form the top gate (first gate) of the second transistor T2. The first reset signal line 3Re1 may be connected to the third reset signal line 2Re3 through a via hole, and the via hole may be located in the frame area of ​​the display panel; the second reset signal line 3Re2 may be connected to the fourth reset signal line 2Re4 through a via hole, and the via hole may be located in the frame area of ​​the display panel. The display panel can use the third conductive part as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer forms a channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0101] like Figure 7 , 13 As shown in FIG. 20 , the fourth conductive layer may include: a data line Vdata, a power line VDD, a bridge portion 41, a bridge portion 42, and a bridge portion 43. The data line Vdata is used to provide a data signal to Figure 4 The data signal terminal in the power line VDD is used to provide a voltage signal Figure 4 The orthographic projection of the data line Vdata on the substrate and the orthographic projection of the power line VDD on the substrate may extend along a second direction Y, and the second direction Y may intersect with the first direction X. For example, the second direction Y may be perpendicular to the first direction X. Fig. 20 As shown, the positive projection of the power line VDD on the substrate can be located between the positive projection of the data line Vdata on the substrate and the positive projection of the first conductive part 11 on the substrate, so that the power line VDD can shield the noise influence of the data line Vdata on the first conductive part 11, thereby improving the voltage stability of the gate of the driving transistor in the light-emitting stage. The bridge part 41 can be connected to the second active layer on one side of the first active part 71 through the via H3 to connect the first electrode of the first transistor T1, the bridge part 42 can be connected to the second conductive part 22 through the via H1, the first active layer on the side of the sixth active part 66 away from the third active part 63 through the via H2, and the second active layer on the other side of the first active part 71 through the via H4 to connect the second electrode of the capacitor C, the second electrode of the sixth transistor and the second electrode of the first transistor. The bridge portion 43 can be connected to the first active layer of the seventh active portion 67 away from the third active portion 63 through the via H8, connected to the second active layer on the side of the second active portion 72 through the via H10, and connected to the first conductive portion 11 through the via H9 to connect the first electrode of the seventh transistor, the gate of the driving transistor, and the second electrode of the second transistor. The positive projection of the via H9 on the substrate is located within the positive projection of the opening 221 on the substrate, so that the conductive structure in the via H9 is insulated from the second conductive portion 22. The power line VDD can be connected to the second active layer on the other side of the second active portion 72 through the via H7 to connect the first power supply terminal and the first electrode of the second transistor, and the power line VDD can be connected to the first active layer on the side of the fifth active portion away from the third active portion through the via H5 to connect the first power supply terminal and the first electrode of the fifth transistor. The data line Vdata can be connected to the first active layer on the side of the fourth active portion 64 away from the third active portion 63 through the via H6 to connect the first electrode of the fourth transistor and the data signal terminal.

[0102] like Figure 7 , 14As shown in FIG. 21 , the fifth conductive layer may include an initial signal line Vinit, a conductive portion 52, and a connecting portion 51, wherein the orthographic projection of the initial signal line Vinit on the substrate may extend along the second direction Y, and the initial signal line Vinit may be used to provide Figure 4The initial signal end in. The initial signal line Vinit can be connected to the bridge portion 41 through the via H12 to connect the first electrode of the first transistor T1 and the initial signal end. The conductive portion 52 can be connected to the bridge portion 42 through the via H11 to connect the second electrode of the sixth transistor. The positive projection of the connecting portion 51 on the base substrate can extend along the first direction X, and the connecting portion 51 can be connected between two adjacent initial signal lines Vinit, so that the initial signal line forms a grid structure, and the initial signal line of the grid structure can have a smaller resistance, so that the initial signal lines at different positions of the display panel have a smaller voltage difference. In addition, the square resistance of the fifth conductive layer can be smaller than the square resistance of any conductive layer of the first conductive layer, the second conductive layer, and the third conductive layer. In this exemplary embodiment, the initial signal line is set in the fifth conductive layer to further reduce the resistance of the initial signal line. The positive projection of the initial signal line Vinit on the base substrate can cover the positive projection of the first active portion 71 on the base substrate and the positive projection of the second active portion 72 on the base substrate. The initial signal line Vinit can shield the channel region of the first transistor T1 and the channel region of the second transistor T2, thereby preventing the first transistor and the second transistor from experiencing characteristic changes due to light exposure. In this exemplary embodiment, the orthographic projection of the initial signal line Vinit on the substrate can cover the orthographic projection of the first conductive portion 11 on the substrate. The initial signal line Vinit can form a parallel plate capacitor structure with the first conductive portion 11, and the voltage on the initial signal line Vinit can be a stable voltage. The initial signal line Vinit can stabilize the first conductive portion 11, thereby reducing the voltage fluctuation of the gate of the driving transistor during the light-emitting stage. The initial signal line Vinit may be provided with an opening 53, and the orthographic projection of the opening 53 on the substrate may at least partially overlap with the orthographic projection of the second reset signal line 3Re2 on the substrate, and the orthographic projection of the opening 53 on the substrate may at least partially overlap with the orthographic projection of the fourth reset signal line 2Re4 on the substrate. This arrangement may reduce the overlapping area between the initial signal line Vinit and the second reset signal line 3Re2, and may reduce the overlapping area between the initial signal line Vinit and the fourth reset signal line 2Re4, thereby reducing the parasitic capacitance on the second reset signal line 3Re2 and the fourth reset signal line 2Re4, and further increasing the charging speed of the second reset signal line 3Re2 and the fourth reset signal line 2Re4. The initial signal line Vinit may also be provided with an opening 54, and the conductive portion 52 may be located in the opening 54, and the orthographic projection of the opening 54 on the substrate may at least partially overlap with the orthographic projection of the enable signal line EM on the substrate, and this arrangement may also reduce the parasitic capacitance of the enable signal line EM, thereby increasing the charging speed of the enable signal line. Fig.14As shown, the openings 53 and 54 can be gaps located on the sides of the initial signal line Vinit, that is, the openings 53 and 54 are non-closed figures. It should be understood that in other exemplary embodiments, the openings 53 and 54 can also be located within the initial signal line Vinit, that is, the openings 53 and 54 can be closed figures.

[0103] like Figure 7 , 15 The anode layer may include an anode portion 81, and the anode portion 81 may be connected to the conductive portion 52 through the via hole H13. The anode portion 81 may be used to form an anode of the light emitting unit OLED.

[0104] like Fig. 22 As shown, Figure 7 Partial cross-sectional view along dotted line AA in FIG. The pixel driving circuit may also include a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a first dielectric layer 97, a second dielectric layer 98, a passivation layer 99, a first flat layer 910, and a second flat layer 911, wherein the substrate 91, the buffer layer 92, the first active layer, the first insulating layer 93, the first conductive layer, the second insulating layer 94, the second conductive layer, the third insulating layer 95, the second active layer, the fourth insulating layer 96, the third conductive layer, the first dielectric layer 97, the second dielectric layer 98, the fourth conductive layer, the passivation layer 99, the first flat layer 910, the fifth conductive layer, the second flat layer 911, and the anode layer are stacked in sequence. The buffer layer 92 may include at least one of a silicon oxide layer and a silicon nitride layer. The first insulating layer 93, the second insulating layer 94, the third insulating layer 95, and the fourth insulating layer 96 may include a silicon oxide layer. The first dielectric layer 97 and the second dielectric layer 98 may include a silicon nitride layer. The materials of the first planar layer 910 and the second planar layer 911 may include organic materials such as organic resins, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like. The material of the passivation layer 99 may include an organic insulating material or an inorganic insulating material. The anode layer may be formed of an indium tin oxide (ITO) material. The materials of the fourth conductive layer and the fifth conductive layer may include a metal material, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or a titanium / aluminum / titanium stack. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or the like.

[0105] This exemplary embodiment also provides another display panel, which may include Figure 4The pixel driving circuit shown in the figure, the display panel may also include a base substrate, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an anode layer stacked in sequence, and an insulating layer may be provided between the adjacent layers. Figure 23-37 As shown, Fig.23 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Fig.24 for Fig.23 The structural layout of the first active layer in Fig.25 for Fig.23 The structural layout of the first conductive layer in Fig.26 for Fig.23 The structural layout of the second conductive layer in Fig. 27 for Fig.23 The structural layout of the second active layer, Fig.28 for Fig.23 The structural layout of the third conductive layer, Fig.29 for Fig.23 The structural layout of the fourth conductive layer in Fig.30 for Fig.23 The structural layout of the fifth conductive layer, Fig.31 for Fig.23 The structural layout of the anode layer. Fig.32 for Fig.23 The structural layout of the first active layer and the first conductive layer, Fig.33 for Fig.23 The structural layout of the first active layer, the first conductive layer, and the second conductive layer, Fig.34 for Fig.23 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Fig.35 for Fig.23 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Fig.36 for Fig.23 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer, Fig.37 for Fig.23 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer.

[0106] like Fig.23 , 24, 32, the first active layer may include: a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67. The third active portion 63 is used to form a channel region of the driving transistor T3, the fourth active portion 64 is used to form a channel region of the fourth transistor T4, the fifth active portion 65 is used to form a channel region of the fifth transistor T5, and the sixth active portion 66 is used to form a channel region of the sixth transistor T6. The seventh active portion 67 may include a first sub-active portion 671 and a second sub-active portion 672. The first sub-active portion 671 may be used to form a first channel region of the seventh transistor, and the second sub-active portion 672 may be used to form a second channel region of the seventh transistor. The first active layer may further include a third sub-active portion 673 connected between the first sub-active portion 671 and the second sub-active portion 672. The first active layer may be formed of polysilicon, and accordingly, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be N-type low-temperature polysilicon transistors.

[0107] like Fig.23 , 25As shown in Figures 3 and 32, the first conductive layer may include: a first conductive portion 11, a gate drive signal line Gate, an enable signal line EM, and a protruding portion 12. The orthographic projection of the first conductive portion 11 on the base substrate covers the third active portion 63, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the gate drive signal line Gate on the base substrate and the orthographic projection of the enable signal line EM on the base substrate can both extend along the first direction X. Among them, the orthographic projection of the gate drive signal line Gate on the base substrate covers the orthographic projection of the fourth active portion 64 on the base substrate and the orthographic projection of the first sub-active portion 671 on the base substrate, and a partial structure of the gate drive signal line Gate can be used to form the gate of the fourth transistor, and another partial structure of the gate drive signal line Gate can be used to form the first gate of the seventh transistor. The orthographic projection of the enable signal line EM on the substrate can cover the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The orthographic projection of the first conductive portion 11 on the substrate can be located between the orthographic projection of the gate drive signal line Gate on the substrate and the orthographic projection of the enable signal line EM on the substrate. The raised portion 12 is connected to the gate drive signal line Gate, and the orthographic projection of the raised portion 12 on the substrate covers the orthographic projection of the second sub-active portion 672 on the substrate. Part of the structure of the raised portion 12 can be used to form the second gate of the seventh transistor. In addition, the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer forms the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0108] like Fig.23 , 26 As shown in Figures 3 and 33, the second conductive layer may include a sixth reset signal line 2Re6 and a second conductive portion 22. The orthographic projection of the second conductive portion 22 on the base substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 may form a second electrode of the capacitor C. The second conductive portion 22 may also be provided with an opening 221. The sixth reset signal line 2Re6 may be connected to the gate of the first transistor T1 and the gate of the second transistor T2. The orthographic projection of the sixth reset signal line 2Re6 on the base substrate may extend along the first direction X.

[0109] like Fig.23 , 27As shown in Figures 34, the second active layer may include a first active portion 71 and a second active portion 72. The first active portion 71 may be used to form a channel region of the first transistor T1, and the second active portion 72 may be used to form a channel region of the second transistor. The orthographic projection of the first active portion 71 on the substrate substrate and the orthographic projection of the second active portion 72 on the substrate substrate may be located on a side of the orthographic projection of the enable signal line EM on the substrate substrate away from the orthographic projection of the first conductive portion 11 on the substrate substrate. The orthographic projection of the sixth reset signal line 2Re6 on the substrate substrate may cover the orthographic projection of the first active portion 71 on the substrate substrate and the orthographic projection of the second active portion 72 on the substrate substrate. Part of the structure of the sixth reset signal line 2Re6 may be used to form the bottom gate (second gate) of the first transistor T1, and another part of the structure of the sixth reset signal line 2Re6 may be used to form the bottom gate (second gate) of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor and the second transistor may be N-type metal oxide transistors.

[0110] like Fig.23 , 28 As shown in , 35, the third conductive layer may include: a fifth reset signal line 3Re5, the orthographic projection of the fifth reset signal line 3Re5 on the substrate may extend along the first direction X, the orthographic projection of the fifth reset signal line 3Re5 on the substrate may cover the orthographic projection of the first active portion 71 on the substrate and the orthographic projection of the second active portion 72 on the substrate, and a partial structure of the fifth reset signal line 3Re5 is used to form the top gate (first gate) of the first transistor T1. Another partial structure of the fifth reset signal line 3Re5 may be used to form the top gate (first gate) of the second transistor T2. The fifth reset signal line 3Re5 may be connected to the sixth reset signal line 2Re6 through a via, and the via may be located in the frame area of ​​the display panel. The display panel may use the third conductive portion as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer forms the channel area of ​​the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0111] like Fig.23 , 29 As shown in FIG. 36 , the fourth conductive layer may include: a data line Vdata, a power line VDD, a bridge portion 41, a bridge portion 42, and a bridge portion 43. The data line Vdata is used to provide Figure 4 The data signal terminal, the power line VDD is used to provide Figure 4The orthographic projection of the data line Vdata on the substrate and the orthographic projection of the power line VDD on the substrate can extend along a second direction Y, and the second direction Y can intersect with the first direction X. For example, the second direction Y can be perpendicular to the first direction X. Fig.36 As shown, the orthographic projection of the power line VDD on the substrate can be located between the orthographic projection of the data line Vdata on the substrate and the orthographic projection of the first conductive part 11 on the substrate, so that the power line VDD can shield the noise influence of the data line Vdata on the first conductive part 11, thereby improving the voltage stability of the gate of the driving transistor in the light-emitting stage. The bridge portion 41 can be connected to the second active layer on one side of the first active portion 71 through the via H1 to connect the first electrode of the first transistor T1. The bridge portion 42 can be connected to the second conductive portion 22 through the via H5, connected to the first active layer on the side of the sixth active portion 66 away from the third active portion 63 through the via H6, and connected to the second active layer on the other side of the first active portion 71 through the via H7 to connect the second electrode of the capacitor C, the second electrode of the sixth transistor, and the second electrode of the first transistor. The bridge portion 43 can be connected to the first active layer of the seventh active portion 67 away from the third active portion 63 through the via H10, connected to the second active layer on the second active portion 72 through the via H4, and connected to the first conductive portion 11 through the via H8 to connect the first electrode of the seventh transistor, the gate of the driving transistor, and the second electrode of the second transistor. The positive projection of the via H8 on the substrate substrate is located within the positive projection of the opening 221 on the substrate substrate, so that the conductive structure in the via H8 is insulated from the second conductive portion 22. The power line VDD can be connected to the second active layer on the other side of the second active portion 72 through the via H2 to connect the first power supply terminal and the first electrode of the second transistor, and the power line VDD is connected to the first active layer on the side of the fifth active portion 65 away from the third active portion 63 through the via H3 to connect the first electrode of the fifth transistor and the first power supply terminal. The data line Vdata can be connected to the first active layer on the side of the fourth active portion 64 away from the third active portion 63 through the via H9 to connect the first electrode of the fourth transistor and the data signal terminal. In the first direction X, the orthographic projection of the second active portion 72 on the substrate can be located between the orthographic projection of the data line Vdata on the substrate and the orthographic projection of the first active portion 71 on the substrate. This arrangement can facilitate the connection between the first electrode of the second transistor and the gate of the driving transistor.

[0112] like Fig.23 , 30 As shown in FIG. 37 , the fifth conductive layer may include an initial signal line Vinit and a conductive portion 52 , wherein the orthographic projection of the initial signal line Vinit on the substrate may extend along the second direction Y, and the initial signal line Vinit may be used to provide Figure 4 The initial signal end in the circuit. The initial signal line Vinit can be connected to the bridge portion 41 through the via H12 to connect the first electrode of the first transistor T1 and the initial signal end. The conductive portion 52 can be connected to the bridge portion 42 through the via H11 to connect the second electrode of the sixth transistor. The square resistance of the fifth conductive layer can be smaller than the square resistance of any conductive layer among the first conductive layer, the second conductive layer, and the third conductive layer. In this exemplary embodiment, the initial signal line is set in the fifth conductive layer to reduce the resistance of the initial signal line. The orthographic projection of the initial signal line Vinit on the substrate substrate can cover the orthographic projection of the first active portion 71 on the substrate substrate and the orthographic projection of the second active portion 72 on the substrate substrate. The initial signal line Vinit can shield the channel region of the first transistor T1 and the channel region of the second transistor T2, thereby preventing the first transistor and the second transistor from having characteristics changes due to light exposure. In this exemplary embodiment, the orthographic projection of the initial signal line Vinit on the substrate substrate can cover the orthographic projection of the first conductive portion 11 on the substrate substrate. The initial signal line Vinit can form a parallel plate capacitor structure with the first conductive part 11, and the voltage on the initial signal line Vinit can be a stable voltage. The initial signal line Vinit can stabilize the voltage of the first conductive part 11, thereby reducing the voltage fluctuation of the gate of the driving transistor at the light-emitting node. The positive projection of the initial signal line Vinit on the substrate can also cover the positive projection of the third sub-active part 673 on the substrate, and the initial signal line Vinit can stabilize the voltage of the third sub-active part 673, thereby reducing the leakage current from the third sub-active part 673 to the source and drain of the seventh transistor caused by the voltage fluctuation of the third sub-active part 673.

[0113] like Fig.23 , 31 The anode layer may include an anode portion 81, and the anode portion 81 may be connected to the conductive portion 52 through the via hole H13. The anode portion 81 may be used as an anode of the light emitting unit OLED.

[0114] like Fig.38 As shown, Fig.23Partial cross-sectional view along dotted line AA in FIG. The pixel driving circuit may also include a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a first dielectric layer 97, a second dielectric layer 98, a passivation layer 99, a first flat layer 910, and a second flat layer 911, wherein the substrate 91, the buffer layer 92, the first active layer, the first insulating layer 93, the first conductive layer, the second insulating layer 94, the second conductive layer, the third insulating layer 95, the second active layer, the fourth insulating layer 96, the third conductive layer, the first dielectric layer 97, the second dielectric layer 98, the fourth conductive layer, the passivation layer 99, the first flat layer 910, the fifth conductive layer, the second flat layer 911, and the anode layer are stacked in sequence. The buffer layer 92 may include at least one of a silicon oxide layer and a silicon nitride layer. The first insulating layer 93, the second insulating layer 94, the third insulating layer 95, and the fourth insulating layer 96 may include a silicon oxide layer. The first dielectric layer 97 and the second dielectric layer 98 may include a silicon nitride layer. The materials of the first planar layer 910 and the second planar layer 911 may include organic materials such as organic resins, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like. The material of the passivation layer 99 may include an organic insulating material or an inorganic insulating material. The anode layer may be formed of an indium tin oxide (ITO) material. The materials of the fourth conductive layer and the fifth conductive layer may include a metal material, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or a titanium / aluminum / titanium stack. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or the like.

[0115] In this exemplary embodiment, the display panel may further include a light shielding layer, which may be located between the substrate and the first active layer. The orthographic projection of the light shielding layer on the substrate substrate may at least cover the orthographic projection of the channel region of the driving transistor T3 on the substrate substrate, and the light shielding layer may be used to reduce the characteristic changes caused by the channel region of the driving transistor being affected by light. In addition, the orthographic projection of the light shielding layer on the substrate substrate may also cover the orthographic projection of other transistor channel regions on the substrate substrate, for example, the orthographic projection of the light shielding layer on the substrate substrate may cover the orthographic projection of all transistor channel regions on the substrate substrate. The material of the light shielding layer may be a semiconductor material, a conductor material, etc. For example, the material of the light shielding layer may be amorphous silicon (a-Si), a metal material molybdenum (Mo), etc. The light shielding layer may be connected to a specific potential, for example, the light shielding layer may be connected to any one or more of the power line VDD and the initial signal line Vinit. This setting may not only form the light shielding layer into a shielding layer, but also reduce the self-resistance of the power line VDD and the initial signal line Vinit. The light shielding layer may include only a light shielding portion extending along the first direction, or only a light shielding portion extending along the second direction, or may include both a light shielding portion extending along the first direction and a light shielding portion extending along the second direction. When the light shielding layer includes both a light shielding portion extending along the first direction and a light shielding portion extending along the second direction, the light shielding layer may form a grid structure. When the light shielding layer includes only a light shielding portion extending along the same direction, the orthographic projection of the light shielding portion on the substrate substrate may form a grid structure with the orthographic projections of other stable signal lines on the substrate substrate, and the light shielding portion may be connected to the stable signal lines intersecting therewith through vias, and this arrangement may reduce the self-resistance of the stable signal line, thereby reducing the impedance load (IR loading) of the stable signal line, and the stable signal line may be a power line VDD or an initial signal line Vinit.

[0116] In addition, it should be noted that the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure.

[0117] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0119] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a light emitting unit and a pixel driving circuit for driving the light emitting unit, wherein the pixel driving circuit includes: Driver transistor; a first transistor, a first electrode of which is connected to the initial signal line, and a second electrode of which is connected to the first electrode of the light-emitting unit; a second transistor, a first electrode of which is connected to a power line, and a second electrode of which is connected to a gate of the driving transistor; a fifth transistor, a gate connected to the enable signal line, a first electrode connected to the power line, and a second electrode connected to the first electrode of the driving transistor; a sixth transistor, a gate connected to the enable signal line, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the first electrode of the light emitting unit; a fourth transistor, a gate connected to the gate driving signal line, a first electrode connected to the data line, and a second electrode connected to the first electrode of the driving transistor; a seventh transistor, a gate connected to the gate driving signal line, a first electrode connected to the gate of the driving transistor, and a second electrode connected to the second electrode of the driving transistor; A capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the second electrode of the sixth transistor Wherein, the driving transistor, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the fourth transistor, and the seventh transistor are N-type transistors, and the first transistor and the second transistor are oxide transistors; The display panel further includes: substrate substrate; A first active layer, located on one side of the base substrate, the first active layer comprising a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion; The third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; A first conductive layer, located on a side of the first active layer away from the base substrate, the first conductive layer comprising a first conductive portion, the gate drive signal line, and the enable signal line; The orthographic projection of the first conductive portion on the base substrate covers the third active portion, the first conductive portion is used to form the gate of the driving transistor, and the orthographic projection of the gate driving signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate extend along a first direction; The second active layer is located on a side of the first conductive layer away from the base substrate, and the second active layer includes a first active portion and a second active portion. The first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

2. The display panel according to claim 1, wherein: The first conductive layer is also used to form a first electrode of the capacitor, and the display panel further includes: A second conductive layer is located between the first conductive layer and the second active layer, the second conductive layer includes a second conductive portion, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the second conductive portion is used to form a second electrode of the capacitor.

3. The display panel according to claim 2, wherein: The orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the gate drive signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate; The orthographic projection of the first active portion on the base substrate is located on a side where the orthographic projection of the enable signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the second active portion on the base substrate is located on a side where the orthographic projection of the gate drive signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate; The display panel further includes: A third conductive layer, located on a side of the second active layer away from the substrate, the third conductive layer comprising a first reset signal line and a second reset signal line; The orthographic projection of the first reset signal line on the substrate extends along the first direction, the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and a partial structure of the first reset signal line is used to form a first gate of the first transistor; The orthographic projection of the second reset signal line on the base substrate extends along the first direction, the orthographic projection of the second reset signal line on the base substrate covers the orthographic projection of the second active portion on the base substrate, and a partial structure of the second reset signal line is used to form a first gate of the second transistor.

4. The display panel according to claim 3, wherein: The display panel further includes: a second conductive layer, located between the first conductive layer and the second active layer, the second conductive layer comprising a third reset signal line and a fourth reset signal line; The orthographic projection of the third reset signal line on the substrate extends along the first direction, the orthographic projection of the third reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and a partial structure of the third reset signal line is used to form a second gate of the first transistor; The orthographic projection of the fourth reset signal line on the base substrate extends along the first direction, the orthographic projection of the fourth reset signal line on the base substrate covers the orthographic projection of the second active portion on the base substrate, and a partial structure of the fourth reset signal line is used to form a second gate of the second transistor.

5. The display panel according to claim 1, wherein: The orthographic projection of the first active portion on the base substrate and the orthographic projection of the second active portion on the base substrate are both located on a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate; The display panel further includes: A third conductive layer, located on a side of the second active layer away from the substrate, the third conductive layer comprising a fifth reset signal line; Among them, the orthographic projection of the fifth reset signal line on the substrate extends along the first direction, the orthographic projection of the fifth reset signal line on the substrate covers the orthographic projection of the first active part on the substrate and the orthographic projection of the second active part on the substrate, a partial structure of the fifth reset signal line is used to form the first gate of the first transistor, and another partial structure of the fifth reset signal line is used to form the first gate of the second transistor.

6. The display panel according to claim 1, wherein: The display panel further includes: A third conductive layer is located on a side of the second active layer away from the substrate; a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising the data line and the power line; Among them, the orthographic projection of the data line on the base substrate and the orthographic projection of the power line on the base substrate extend along a second direction, the second direction intersects with the first direction, and the orthographic projection of the power line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first conductive part on the base substrate.

7. The display panel according to claim 5, wherein: The display panel further includes: a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising the data line; In the first direction, an orthographic projection of the second active portion on the base substrate is located between an orthographic projection of the data line on the base substrate and an orthographic projection of the first active portion on the base substrate.

8. The display panel according to claim 1, wherein: The display panel further includes: A third conductive layer is located on a side of the second active layer away from the substrate; a fifth conductive layer, located on a side of the third conductive layer away from the substrate, wherein the fifth conductive layer includes the initial signal line; The square resistance of the fifth conductive layer is smaller than the square resistance of the third conductive layer.

9. The display panel according to claim 8, wherein: The orthographic projection of the initial signal line on the base substrate covers the orthographic projection of the first active portion on the base substrate and the orthographic projection of the second active portion on the base substrate.

10. The display panel according to claim 8, wherein: The orthographic projection of the initial signal line on the base substrate covers the orthographic projection of the first conductive portion on the base substrate.

11. The display panel according to claim 8, wherein: The orthographic projection of the initial signal line on the base substrate extends along a second direction, and the second direction intersects with the first direction; The fifth conductive layer further comprises: The connecting portion has an orthographic projection on the base substrate extending along the first direction, and the connecting portion is connected between two adjacent initial signal lines.

12. The display panel according to claim 8, wherein: The orthographic projection of the initial signal line on the base substrate extends along a second direction, and the second direction intersects with the first direction; The third conductive layer includes a second reset signal line, the orthographic projection of the second reset signal line on the base substrate extends along the first direction, the orthographic projection of the second reset signal line on the base substrate covers the orthographic projection of the second active portion on the base substrate, and a partial structure of the second reset signal line is used to form a first gate of the second transistor; An opening is provided on the initial signal line, and an orthographic projection of the opening on the base substrate at least partially overlaps with an orthographic projection of the second reset signal line on the base substrate.

13. The display panel according to claim 8, wherein: The seventh active portion includes a first sub-active portion and a second sub-active portion, and the first active layer further includes a third sub-active portion connected between the first sub-active portion and the second sub-active portion; The orthographic projection of the initial signal line on the base substrate covers the orthographic projection of the third sub-active portion on the base substrate.

14. The display panel according to claim 1, wherein: The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the driving transistor are N-type low-temperature polysilicon transistors.

15. A display device, wherein: A display panel comprising any one of claims 1 to 14.

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