Test Circuit and Its Method

Abstract

The present disclosure provides a test circuit and a method thereof. The test circuit includes a data acquisition sub-circuit, which includes a communication interface configured to receive a register configuration instruction; wherein the register configuration instruction includes a plurality of memory addresses and a register status control instruction; a state machine sub-circuit electrically connected to the data acquisition sub-circuit and configured to configure the state of the state machine sub-circuit according to the register status control instruction; and a bus management sub-circuit electrically connected to the state machine sub-circuit and configured to send the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit according to the state of the state machine sub-circuit, so that the circuit under test reads a frame image corresponding to the current memory address.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display devices, and more particularly, to a test circuit and a method thereof. Background Art

[0002] A display system is an electronic system that provides visual information, including a video decoder, a storage unit (RAM), and a display device. The video decoder is configured to decode the received compressed data and store it in the storage unit, and the display device reads the decoded image data from the storage unit and displays it.

[0003] In the related art, during the communication between the video decoder and the display device, it is usually necessary for software (firmware) to configure the corresponding memory address (ddr address) for each frame of image data, so that the display device can sequentially read the image data corresponding to the ddr address. This way of verifying the function of the display device is not conducive to early discovery of problems in the circuit design process, resulting in a long circuit verification cycle. Summary of the Invention

[0004] The present disclosure provides a test circuit and a method thereof.

[0005] According to a first aspect of the present disclosure, a test circuit for a display device is provided, including a data acquisition sub-circuit, including a communication interface configured to receive a register configuration instruction; wherein the register configuration instruction includes a plurality of memory addresses and a register status control instruction; a state machine sub-circuit electrically connected to the data acquisition sub-circuit, configured to configure the state of the state machine sub-circuit according to the register status control instruction; a bus management sub-circuit electrically connected to the state machine sub-circuit, configured to send the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit according to the state of the state machine sub-circuit, so that the circuit under test reads a frame image corresponding to the current memory address.

[0006] For example, the register status control instruction includes one of a start instruction, a clear instruction, and a trigger instruction.

[0007] For example, the state machine sub-circuit is configured to, when the register configuration instruction includes a start instruction, switch the state of the state machine sub-circuit to a configuration state according to the start instruction, so that the state machine sub-circuit enters a working state.

[0008] For example, the state machine sub-circuit is configured to, when the register configuration instruction includes a clear instruction, switch the state of the state machine sub-circuit to an idle state according to the clear instruction.

[0009] For example, the register configuration instruction includes a trigger instruction, and the trigger instruction instructs that in the next processing cycle of the current processing cycle, the next memory address of the current memory address is sent to the circuit under test electrically connected to the test circuit.

[0010] For example, the state machine sub-circuit is further configured to, in response to the state of the state machine sub-circuit switching to the configuration state, the state machine sub-circuit controls the bus management sub-circuit to send the current memory address of multiple memory addresses to the circuit under test electrically connected to the test circuit, and configure the enable state of the circuit under test so that the circuit under test reads the frame image corresponding to the current memory address.

[0011] For example, the data acquisition sub-circuit is further configured to receive a flag signal from the circuit under test through the communication interface; wherein the flag signal is used to change the state of the state machine sub-circuit so that the test circuit periodically controls the circuit under test.

[0012] For example, the flag signal includes an image completion signal and an image preparation signal; wherein, the state machine sub-circuit is configured to set the state of the state machine sub-circuit to the configuration state or the waiting state according to the image completion signal and the image preparation signal.

[0013] For example, the image completion signal and the image preparation signal indicate whether the circuit under test has completed reading the frame image in the current processing cycle.

[0014] According to a second aspect of the embodiments of the present disclosure, there is provided a test method for a display device, including: receiving a register configuration instruction; wherein the register configuration instruction includes multiple memory addresses and a register status control instruction; configuring the state of the state machine sub-circuit according to the register status control instruction; and sending the current memory address of the multiple memory addresses to the circuit under test electrically connected to the test circuit according to the state of the state machine sub-circuit, so that the circuit under test reads the frame image corresponding to the current memory address.

[0015] According to a third aspect of the embodiments of the present disclosure, there is provided a test device, including at least one circuit under test; at least one test circuit provided by the first aspect of the present disclosure, electrically connected to the at least one circuit under test, and configured to perform a functional test on the at least one circuit under test.

[0016] According to the technical solution of the embodiments of the disclosure, there is provided a test circuit for a display device. This test circuit is used to replace traditional software to verify the function of the circuit under test, so that the function verification of the circuit under test can be completed in the early stage of hardware design, reducing the verification cycle and the verification cost. Description of the Drawings

[0017] Describing embodiments of the present disclosure in conjunction with the accompanying drawings below will make the above and other objects, features, and advantages of the embodiments of the present disclosure clearer. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the figures:

[0018] Figure 1 Shows a schematic structural diagram of a test circuit for a display device according to an embodiment of the present disclosure;

[0019] Figure 2 Shows a flowchart of state transitions of a state machine sub-circuit according to an embodiment of the present disclosure;

[0020] Figure 3 Shows a timing diagram of the working process of a test circuit according to an embodiment of the present disclosure;

[0021] Figure 4 Shows a flowchart of a test method for a display device according to an embodiment of the present disclosure;

[0022] Figure 5 Shows a schematic structural diagram of a test device according to an embodiment of the present disclosure. Detailed implementation manners

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as any limitation to the present disclosure, but only as examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0024] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be of the ordinary meaning understood by those skilled in the art. It should be noted that the terms used here should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] Some block diagrams and / or flowcharts are shown in the figure. It should be understood that some blocks or combinations of blocks in the block diagrams and / or flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when executed by the processor, these instructions can create a device for implementing the functions / operations illustrated in these block diagrams and / or flowcharts. The technology of the present disclosure can be implemented in the form of hardware and / or software (including firmware, microcode, etc.). Additionally, the technology of the present disclosure can take the form of a computer program product on a computer-readable storage medium storing instructions, which can be used by or in conjunction with an instruction execution system.

[0026] An embodiment of the present disclosure provides a test circuit, including a data acquisition sub-circuit, including a communication interface configured to receive register configuration instructions; wherein, the register configuration instructions include a plurality of memory addresses and register status control instructions; a state machine sub-circuit electrically connected to the data acquisition sub-circuit, configured to configure the state of the state machine sub-circuit according to the register status control instructions; a bus management sub-circuit electrically connected to the state machine sub-circuit, configured to send the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit according to the state of the state machine sub-circuit, so that the circuit under test reads a frame image corresponding to the current memory address.

[0027] A test circuit provided by an embodiment of the present disclosure. This test circuit is used to replace traditional software to verify the function of the circuit under test, so that the function verification of the circuit under test can be completed in the early stage of hardware design, reducing the verification cycle of the circuit under test and lowering the verification cost.

[0028] Figure 1 A schematic structural diagram of a test circuit according to an embodiment of the present disclosure is shown.

[0029] As Figure 1 shown, the test circuit 100 may include a data acquisition sub-circuit 110, a state machine sub-circuit 120, and a bus management sub-circuit 130.

[0030] The data acquisition sub-circuit 110 includes a communication interface. The communication interface is configured to receive register configuration instructions. The register configuration instructions include a plurality of memory addresses (double data rate, ddr) and register status control instructions.

[0031] The state machine sub-circuit 120 is electrically connected to the data acquisition sub-circuit 110. The state machine sub-circuit 120 is configured to configure the state of the state machine sub-circuit 120 according to the register status control instructions.

[0032] The bus management sub-circuit 130 is electrically connected to the state machine sub-circuit 120. The bus management sub-circuit 130 is configured to send the current memory addresses of multiple ddr addresses to the circuit under test electrically connected to the test circuit according to the state of the state machine sub-circuit 120, so that the circuit under test reads the frame image corresponding to the current memory address.

[0033] According to an embodiment of the present disclosure, the data acquisition sub-circuit 110 may be an Advanced Peripheral Bus dmux (APB dmux). The APB dmux may include an input interface and multiple output interfaces.

[0034] For example, the input port of the APB dmux is a communication interface for receiving at least one ddr address and a register status control instruction output by the user, and receiving a flag signal (Flag signal) output by the circuit under test. The input interface is also used to output the received input data to one or more of the multiple output interfaces.

[0035] For example, the at least one ddr address may be one or more. Each ddr address indicates the memory address for the circuit under test to read the frame image.

[0036] For example, each ddr address is different from each other and has uniqueness.

[0037] It can be understood that the ddr address may be represented in the form of 0x80000000, etc. The representation form of the ddr address is related to the circuit communication protocol, and the embodiments of the present disclosure do not limit this.

[0038] According to an embodiment of the present disclosure, the register status control instruction may include one of a start instruction (Start), a clear instruction (Clear), and a trigger instruction (Trig). The register status control instruction is used to configure the working state of the state machine sub-circuit 120.

[0039] For example, the state machine sub-circuit 120 is configured to, when the register configuration instruction includes the start instruction, according to the start instruction Start, switch the state of the state machine sub-circuit 120 to the configuration state (Config), so that the state machine sub-circuit 120 enters the working state. At this time, the state machine sub-circuit 120 configures the circuit under test through the bus management sub-circuit 130.

[0040] For example, the state machine sub-circuit 120 is configured to, when the register configuration instruction includes the clear instruction, according to the clear instruction Clear, switch the state of the state machine sub-circuit 120 to the idle state (IDLE). At this time, the state machine sub-circuit 120 is waiting to enter the Config state.

[0041] For example, the register configuration instruction includes a trigger instruction Trig. The trigger instruction Trig indicates that in the next processing cycle of the current processing cycle, the next memory address of the current memory address is sent to the circuit under test electrically connected to the test circuit, so that the circuit under test reads the frame image corresponding to the next memory address.

[0042] It can be understood that the current memory address in the embodiments of the present disclosure represents the memory address corresponding to the current processing cycle among multiple memory addresses in the current processing cycle.

[0043] For example, each memory address can be a data storage address.

[0044] For example, the multiple memory addresses can be data storage address 1, data storage address 2, data storage address 3,..., data storage address N respectively. N is an integer greater than or equal to 2.

[0045] For example, data storage address 2 is the next memory address of data storage address 1. Data storage address 3 is the next memory address of data storage address 2. And so on, data storage address N is the next memory address of data storage address N - 1. Data storage address 1 is the next memory address of data storage address N.

[0046] It can be understood that the bus management sub - circuit 130 can send each data storage address to the circuit under test electrically connected to the test circuit according to the register configuration instruction in the order of data storage address 1, data storage address 2, data storage address 3,..., data storage address N, data storage address 1, data storage address 2,....

[0047] For example, the current processing cycle can be the first processing cycle after circuit reset, the second processing cycle after circuit reset, the third processing cycle after circuit reset,....

[0048] For example, when the current processing cycle is the first processing cycle after circuit reset, the bus management sub - circuit 130 can send data storage address 1 to the circuit under test electrically connected to the test circuit.

[0049] For example, when the current processing cycle is the second processing cycle after circuit reset, the bus management sub - circuit 130 can send data storage address 1 or data storage address 2 to the circuit under test electrically connected to the test circuit.

[0050] For example, the bus management sub - circuit 130 can determine whether to send the next memory address corresponding to the current memory address to the circuit under test electrically connected to the test circuit in the next processing cycle according to whether there is a high level in the trigger instruction Trig in the current processing cycle.

[0051] For example, when there is a high level "1" in the trigger instruction Trig in the current processing cycle, in the next processing cycle, the bus management sub-circuit 130 sends the next memory address of the current memory address to the circuit under test electrically connected to the test circuit, so that the circuit under test reads the frame image corresponding to the next memory address.

[0052] For example, when there is no high level "1" in the trigger instruction Trig in the current processing cycle, in the next processing cycle, the bus management sub-circuit 130 continues to send the current memory address to the circuit under test electrically connected to the test circuit, so that the circuit under test continues to read the frame image corresponding to the current memory address.

[0053] For example, in the current processing cycle, the bus management sub-circuit 130 sends the data storage address 2 to the circuit under test electrically connected to the test circuit. When there is a high level "1" in the trigger instruction Trig in the current processing cycle, in the next processing cycle, the bus management sub-circuit 130 sends the data storage address 3 to the circuit under test electrically connected to the test circuit.

[0054] For example, in the current processing cycle, the bus management sub-circuit 130 sends the data storage address N to the circuit under test electrically connected to the test circuit. When there is a high level "1" in the trigger instruction Trig in the current processing cycle, in the next processing cycle, the bus management sub-circuit 130 sends the data storage address 1 to the circuit under test electrically connected to the test circuit.

[0055] For example, in the current processing cycle, the bus management sub-circuit 130 sends the data storage address 2 to the circuit under test electrically connected to the test circuit. When there is no high level "1" in the trigger instruction Trig in the current processing cycle, in the next processing cycle, the bus management sub-circuit 130 continues to send the data storage address 2 to the circuit under test electrically connected to the test circuit.

[0056] According to an embodiment of the present disclosure, the state machine sub-circuit 120 may include a state register and combinational logic circuitry, configured to perform state transitions according to control signals in accordance with a preset state.

[0057] For example, the states of the state machine sub-circuit 120 include but are not limited to the IDLE state, the Config state, the Config Doing state, and the Waiting state.

[0058] For example, after the state machine sub-circuit 120 receives a clear instruction Clear, a power-on instruction, or a reset instruction from the user, the state of the state machine sub-circuit 120 switches to the IDLE state.

[0059] For example, when the state machine sub - circuit 120 receives a start instruction Start from the user or a Flag signal from the circuit under test, the state of the state machine sub - circuit 120 switches to the Config state.

[0060] For example, after the state of the state machine sub - circuit 120 switches to the Config state, the state machine sub - circuit 120 configures the circuit under test through the bus management sub - circuit 130. At this time, the state of the state machine sub - circuit 120 switches to ConfigDoing.

[0061] For example, after the state of the state machine sub - circuit 120 switches to ConfigDoing, the state machine sub - circuit 120 completes the configuration of the circuit under test. At this time, the state of the state machine sub - circuit 120 switches to the Waiting state to enable the circuit under test to read the corresponding frame image according to the configured ddr address.

[0062] According to an embodiment of the present disclosure, the bus management sub - circuit 130 can be a bus write management sub - circuit (APBWrite). The bus management sub - circuit 130 is configured to implement communication between the test circuit 100 and the circuit under test according to the APB protocol.

[0063] For example, multiple ddr addresses can be set by the user according to the APB protocol to facilitate the test circuit 100 to perform register address configuration on the circuit under test and implement the reading of each frame image by the circuit under test.

[0064] According to an embodiment of the present disclosure, in the early stage of circuit design, the circuit under test is electrically connected to a test circuit. By setting the state of the state machine sub - circuit of the test circuit, the test circuit can perform periodic configuration on the circuit under test, enabling the circuit under test to read the frame images corresponding to each ddr address. This test circuit replaces the traditional software to verify the function of the circuit under test, enabling the function verification of the circuit under test to be completed in the early stage of hardware design, avoiding the problem in the prior art that the verification of the circuit under test can only start after the software is completed. This test circuit is beneficial to reducing the verification cycle, lowering the verification cost, and shortening the iteration cycle of the device.

[0065] Figure 2 Shows a flowchart of the state transition of the state machine sub - circuit according to an embodiment of the present disclosure.

[0066] As Figure 2 shown, the state transition process of the state machine sub - circuit includes steps S210 to S270.

[0067] In step S210, after the state machine sub-circuit receives the start instruction Start, power-on instruction, or reset instruction obtained from the data acquisition sub-circuit, the state of the state machine sub-circuit switches to the IDLE state. At this time, the state machine sub-circuit enters the waiting working state.

[0068] In step S220, the state machine sub-circuit determines whether the circuit under test is turned on (powered on).

[0069] In step S230, after the circuit under test is turned on, the state of the state machine sub-circuit switches from the IDLE state to the Config state at this time.

[0070] In step S240, in the Config state, the state machine sub-circuit issues a configuration instruction to the circuit under test through the bus management sub-circuit.

[0071] For example, the state machine sub-circuit sends the earliest ddr address among multiple ddr addresses to the circuit under test through the bus management sub-circuit to configure the register address of the circuit under test. This register address corresponds to the earliest ddr address so that the circuit under test can read the frame image corresponding to the earliest ddr address.

[0072] In the embodiment of the present disclosure, when the state machine sub-circuit has not completed the configuration of the circuit under test, return to step S230 at this time, and the state of the state machine sub-circuit switches to the Config state so that the state machine sub-circuit can complete the configuration of the circuit under test.

[0073] In step S250, after the state machine sub-circuit issues the configuration signal, the state of the state machine sub-circuit switches to ConfiDoing. At this time, the state machine sub-circuit controls the enable state (Enable) of the register of the circuit under test through the bus management sub-circuit so that the circuit under test enters the working state.

[0074] In step S260, after the circuit under test enters the working state, the circuit under test reads the corresponding frame image according to the configured register address. At this time, the state of the state machine sub-circuit switches to the Waiting state so that the circuit under test can complete reading the frame image.

[0075] In step S270, after the circuit under test completes reading the frame image, the circuit under test sends the Flag signal to the state machine sub-circuit through the bus management sub-circuit, causing the state of the state machine sub-circuit to switch to the Config state. At this time, the state machine sub-circuit starts the configuration process of the circuit under test for the next processing cycle.

[0076] In the embodiment of the present disclosure, when the circuit under test has not completed reading the frame image, return to step S260, and the state of the state machine sub-circuit switches to the Waiting state so that the circuit under test can complete reading the current frame image.

[0077] For example, the state transition process of the state machine sub-circuit can be controlled by a clock signal (Clock), and each state transition time is in the millisecond level.

[0078] In the embodiments of the present disclosure, the Flag signal includes a frame completion signal (Frame Done) and a frame ready signal (Frame vs).

[0079] For example, the state machine sub-circuit is configured to set the state of the state machine sub-circuit to the Config state or the Waiting state according to Frame Done and Frame vs.

[0080] According to the embodiments of the present disclosure, by testing multiple state transitions of the state machine sub-circuit of the test circuit, the address configuration and enable configuration of the circuit under test are realized by the state machine sub-circuit, so that the circuit under test can complete the reading of the frame image. This test circuit replaces the way of software intervention in the related art to realize the function verification of the circuit under test, shortens the verification cycle of the function of the circuit under test, and reduces the verification cost.

[0081] Figure 3 A timing diagram showing the working process of the test circuit according to an embodiment of the present disclosure is shown. As Figure 3 shown, the working process of the state machine sub-circuit can be divided into an initialization stage, a configuration stage, a data reading stage, and a configuration preparation stage for the next processing cycle.

[0082] In the embodiments of the present disclosure, the Vsync signal, the Hsync signal, the Vact signal, and the Den signal all represent frame image signals.

[0083] For example, the Vsync signal is a vertical synchronization signal, and the high level of the Vsync signal indicates that the circuit under test starts to read a frame of image.

[0084] For example, the time period between adjacent rising edges of the Vsync signal represents a processing cycle T1 of a frame of image.

[0085] For example, the processing cycle T1 can be the first processing cycle after the circuit is reset.

[0086] For example, the Hsync signal is a horizontal synchronization signal, and the high level of the Hsync signal indicates the start of scanning a line of data of the frame image.

[0087] For example, the Vact signal represents the interval of the longitudinal valid data of the frame image.

[0088] For example, the Vact signal includes a vertical back porch (Vbp) and a vertical front porch (Vfp). Vbp represents the number of invalid lines after the vertical synchronization signal Vsync at the start of a frame of image. Vfp represents the number of invalid lines before the vertical synchronization signal Vsync after a frame of image ends.

[0089] For example, as Figure 3 shown, when the state machine sub-circuit of the test circuit is in the Config state, it is determined that the effective time T2 set by the test circuit is less than the period corresponding to Vfp, so as to ensure that after the test circuit reads the current frame data in the current processing cycle, the state machine sub-circuit has reserved time to configure the circuit under test for the next processing cycle, so as to successfully complete the frame image reading of the next processing cycle. In the embodiments of the present disclosure, the effective time T2 represents the time from the completion of reading the current frame image in the current processing cycle to the start of reading the frame image in the next processing cycle.

[0090] For example, the Den signal represents valid line data. The value of Den can be expressed as 0 ≤ Den ≤ Hsync.

[0091] For example, when the Vact signal is at a high level and the Den is also at a high level, the line data corresponding to Den is valid at this time. In Figure 3 the example shown, the number of valid line data of this frame of image is 3.

[0092] In the embodiments of the present disclosure, the Frame Done signal and the Frame vs signal are Flag signals obtained by the test circuit from the circuit under test.

[0093] For example, the high level of the Frame Done signal indicates whether the frame image has been read completely. The high level of the Frame vs signal indicates the start of reading the current frame image.

[0094] For example, both the Frame Done signal and the Frame vs signal can be represented by binary signals, such as "0", "1", etc.

[0095] For example, when the obtained Frame Done signal is "0", it indicates that the frame image has not been read completely or the frame image is waiting to be read. When the obtained Frame Done signal is "1", it indicates that the frame image has been read completely.

[0096] For example, when the state machine sub-circuit detects the rising edge signal (0 to 1) of the Frame vs signal, it indicates that the circuit under test can start reading the frame image of the current processing cycle.

[0097] As Figure 3As shown, in the initialization phase, the state machine sub-circuit receives a Clear instruction, a power-on instruction, or a reset instruction from the user, and the state of the state machine sub-circuit is in the S1 state (IDLE state). At this time, the state machine sub-circuit and the circuit under test enter the waiting state to start working.

[0098] In the initialization phase, the level of the Frame Done signal is low. The Frame vs signal changes from low level to high level. The enable signal Enable is low. The ddr address is an invalid address.

[0099] In this embodiment, the enable signal Enable is active high (or inactive). Of course, it can also be active low.

[0100] After the state machine sub-circuit is powered on and starts, the state of the state machine sub-circuit switches to the S2 state (Config state), and the state machine sub-circuit enters the configuration phase. At this time, the state machine sub-circuit sends the current memory address ddr1 in multiple memory addresses to the circuit under test through the bus management sub-circuit to configure the register address of the circuit under test.

[0101] After the state machine sub-circuit completes the address configuration of the circuit under test, the state of the state machine sub-circuit switches to the S3 state (Config Doing). At this time, the state machine sub-circuit configures the register Enable state of the circuit under test through the bus management sub-circuit. After receiving the Enable signal, the circuit under test is turned on, and the circuit under test enters the working state, so that the circuit under test starts to read the frame image corresponding to addrl.

[0102] In the data reading phase, the state of the state machine sub-circuit switches to the S4 state (Waiting state), and the circuit under test reads the frame image.

[0103] It can be understood that when the state machine sub-circuit is in the Waiting state, the memory addresses sent by the state machine sub-circuit at this time are all invalid addresses xxx...xxx, that is, the register address configuration of the circuit under test is not performed.

[0104] After the circuit under test completes reading the frame image corresponding to addr1, the circuit under test sends a Flag signal to the state machine sub-circuit through the bus management sub-circuit. At this time, the level signal of the Frame Done signal is pulled high and input to the state machine sub-circuit. The state machine sub-circuit receives the Frame Done signal and switches the state from the Waiting state to the Config state, so that the state machine sub-circuit enters the configuration preparation phase of the next processing cycle.

[0105] As Figure 3As shown, in the current processing cycle, the Trig signal has a high level. The high level of the Trig signal indicates that the user inputs the Trig signal to instruct the state machine sub-circuit to change the ddr address sent to the circuit under test in the next processing cycle. Therefore, in the next processing cycle, the circuit under test reads the frame image corresponding to the addr2 address.

[0106] For example, in the current processing cycle, when the Trig signal does not have a high level, it means that the ddr address sent to the circuit under test is not changed in the next processing cycle. In this case, in the next processing cycle, the circuit under test continues to read the frame image corresponding to the addrl address.

[0107] According to an embodiment of the present disclosure, the data acquisition sub-circuit receives a Flag signal from the circuit under test through a communication interface. The Flag signal is used to change the state of the state machine sub-circuit so that the test circuit periodically verifies the circuit under test.

[0108] For example, according to the received Frame Done signal and Frame vs signal, the state of the state machine sub-circuit is set to the configuration state or the waiting state.

[0109] For example, the Frame Done signal and Frame vs signal indicate whether the circuit under test has completed reading the frame image in the current processing cycle.

[0110] In Figure 3 In the example shown, in the initialization stage, Frame Done is "0" and Frame vs is a rising edge (0 to 1), indicating that the circuit can process the current frame image.

[0111] For example, in the data reading stage, Frame Done is "0" and Frame vs is "0", indicating that the circuit under test is reading the current frame image.

[0112] For example, when Frame Done is "1" and Frame vs is "0", it means that the circuit under test has completed reading the current frame data.

[0113] It should be noted that the combined states and level values of the Frame Done signal and Frame vs signal in the embodiments of the present disclosure are only for exemplary illustration and do not constitute a limitation on the embodiments of the present disclosure.

[0114] According to an embodiment of the present disclosure, the test circuit obtains a control signal from the user or a flag signal of the circuit under test to switch the working state of the state machine sub-circuit of the test circuit, thereby realizing the configuration of the circuit under test by the test circuit and completing the functional verification of the circuit under test by the test circuit. This test circuit replaces software intervention to realize the functional verification of the circuit under test, improving the circuit verification efficiency.

[0115] Figure 4 shows a flowchart of a test method for a display device according to an embodiment of the present disclosure. As Figure 4 shown, the test method according to an embodiment of the present disclosure may include the following steps. It should be noted that the serial numbers of the respective steps in the following method are only for the representation of the steps for description and should not be regarded as indicating the execution order of the respective steps. Unless explicitly stated, the method does not need to be executed exactly in the order shown.

[0116] As Figure 4 shown, the test method 400, which is applied to a test circuit, includes steps S410 to S430. It can be understood that this method can be applied to a test circuit as Figure 1 shown. For the sake of simplicity, the present disclosure will not elaborate on the test circuit anymore.

[0117] In step S410, a register configuration instruction is received. Among them, the register configuration instruction includes a plurality of memory addresses and a register status control instruction.

[0118] It can be understood that step S410 can be executed by the Figure 1 data acquisition sub-circuit 110 shown. For the sake of simplicity, the present disclosure will not elaborate on the data acquisition sub-circuit 110 anymore.

[0119] In step S420, according to the register status control instruction, the state of the state machine sub-circuit is configured.

[0120] It can be understood that step S420 can be executed by the Figure 1 state machine sub-circuit 120 shown. For the sake of simplicity, the present disclosure will not elaborate on the state machine sub-circuit 120 anymore.

[0121] In step S430, according to the state of the state machine sub-circuit, the current memory address of the plurality of memory addresses is sent to the circuit under test electrically connected to the test circuit, so that the circuit under test reads the frame image corresponding to the current memory address.

[0122] It can be understood that step S430 can be executed by the Figure 1 bus management sub-circuit 130 shown. For the sake of simplicity, the present disclosure will not elaborate on the bus management sub-circuit 130 anymore.

[0123] Figure 5 shows a schematic structural diagram of a test device according to an embodiment of the present disclosure.

[0124] As Figure 5 shown, the test device 500 may include at least one circuit under test and at least one test circuit.

[0125] In the embodiments of the present disclosure, the number of circuits under test may be one or more. The number of test circuits may also be one or more.

[0126] For example, the number of circuits under test is the same as the number of test circuits.

[0127] For example, when the number of circuits under test is one, the number of test circuits is also one.

[0128] For example, when the number of circuits under test is multiple, the number of test circuits is also multiple. In this case, the circuits under test and the test circuits are electrically connected in one-to-one correspondence.

[0129] In Figure 5 In the example shown, the first circuit under test 511 is electrically connected to the first test circuit 512. The second circuit under test 521 is electrically connected to the second test circuit 522. And so on, the Nth circuit under test 5N1 is electrically connected to the Nth test circuit 5N2. N is a positive integer.

[0130] It can be understood that Figure 5 the test circuits 512, 522,..., 5N2 shown in Figure 1 have the same structure as the test circuit 100 shown in Figure 1 For the sake of simplicity, the present disclosure will not elaborate further. In addition, the difference between the test circuits 512, 522,..., 5N2 and

[0131] In the embodiments of the present disclosure, the circuit under test may be a certain functional module of the display device, which is used to read the frame image stored in the storage unit. The test circuit is configured to perform functional verification on the circuit under test that is electrically connected to the test circuit.

[0132] For example, the test circuit is used to configure the register address, enable state, and frame image reading of the circuit under test, etc., to achieve functional verification of the circuit under test.

[0133] For example, the test circuit configures the register address of the circuit under test in the Config state.

[0134] For example, the test circuit controls the enable state of the circuit under test in the Config Doing state, so that the circuit under test starts to enter the working state.

[0135] For example, in the Waiting state, the test circuit enables the circuit under test to read the frame image corresponding to the configured register address.

[0136] For example, the display device further includes an image processing module and an image display module.

[0137] For example, the circuit under test reads a frame image corresponding to the DDR address configured by the test circuit. The frame image can be sequentially output to the image processing module and the image display module, so that the image processing module performs image quality processing (HDR), motion compensation frame, etc. on the frame image. The image processing module outputs the processed frame image to the image display module for display.

[0138] According to an embodiment of the present disclosure, by externally connecting a test circuit to the circuit under test of the test device, the test circuit is used to verify the function of the circuit under test, so as to complete the function test of the circuit under test in the early stage of circuit design, improve the verification efficiency, and shorten the iteration cycle of the circuit.

[0139] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0140] Although the present disclosure has been shown and described with reference to specific exemplary embodiments of the present disclosure, those skilled in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. A test circuit for a display device, comprising: A data acquisition sub - circuit, including a communication interface configured to receive register configuration instructions; wherein, the register configuration instructions include a plurality of memory addresses and register status control instructions; A state machine sub - circuit, electrically connected to the data acquisition sub - circuit, configured to configure the state of the state machine sub - circuit according to the register status control instructions; A bus management sub - circuit, electrically connected to the state machine sub - circuit, configured to send the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit according to the state of the state machine sub - circuit, so that the circuit under test reads a frame image corresponding to the current memory address.

2. The circuit according to claim 1, wherein The register status control instructions include one of a start instruction, a clear instruction, and a trigger instruction.

3. The circuit according to claim 2, wherein, The state machine sub - circuit is configured to, when the register configuration instructions include a start instruction, switch the state of the state machine sub - circuit to a configuration state according to the start instruction, so that the state machine sub - circuit enters an operating state.

4. The circuit according to claim 2, wherein, The state machine sub - circuit is configured to, when the register configuration instructions include a clear instruction, switch the state of the state machine sub - circuit to an idle state according to the clear instruction.

5. The circuit according to claim 2, wherein The register configuration instructions include a trigger instruction, and the trigger instruction indicates that in the next processing cycle of the current processing cycle, the next memory address of the current memory address is sent to a circuit under test electrically connected to the test circuit.

6. The circuit according to claim 3, wherein, The state machine sub - circuit is further configured to: In response to the state of the state machine sub - circuit being switched to the configuration state, the state machine sub - circuit controls the bus management sub - circuit to send the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit, and configure the enable state of the circuit under test, so that the circuit under test reads a frame image corresponding to the current memory address.

7. The circuit according to claim 5, wherein, The data acquisition sub - circuit is further configured to: Receive a flag signal from the circuit under test through the communication interface; wherein, the flag signal is used to change the state of the state machine sub - circuit, so that the test circuit periodically controls the circuit under test.

8. The circuit according to claim 7, wherein, The flag signal includes an image completion signal and an image preparation signal; Wherein, the state machine sub - circuit is configured to set the state of the state machine sub - circuit to a configuration state or a waiting state according to the image completion signal and the image preparation signal.

9. The circuit according to claim 8, wherein, The image completion signal and the image preparation signal indicate whether the circuit under test has completed reading the frame image in the current processing cycle.

10. A test method for a display device, comprising: Receiving register configuration instructions; wherein, the register configuration instructions include a plurality of memory addresses and register status control instructions; Configuring the state of a state machine sub - circuit according to the register status control instructions; Sending the current memory address of the plurality of memory addresses to a circuit under test electrically connected to the test circuit according to the state of the state machine sub - circuit, so that the circuit under test reads a frame image corresponding to the current memory address.

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