Semiconductor device and method of forming the same

Abstract

Embodiments of the present application disclose a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, a pair of source / drain regions, a metal-containing layer and a gate structure. The substrate has a trench. The source / drain regions are disposed in the substrate on both sides of the trench. The metal-containing layer is disposed below the trench, and the metal-containing layer and the substrate on the opposite sidewalls of the trench jointly form a channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure comprises a gate dielectric layer disposed on the opposite sidewalls of the trench, a buffer layer disposed on the metal-containing layer, and a gate conductive layer disposed on the buffer layer and filling the trench. Embodiments of the present application can improve the driving current to improve the performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same. BACKGROUND

[0002] Dynamic random access memory (DRAM) is composed of a plurality of memory cells, each of which is generally composed of a transistor and a capacitor, and the memory cells are usually electrically connected to each other by word lines and bit lines. In order to improve the performance and integration of dynamic random access memory, dynamic random access memory with buried word lines has been developed to achieve light, thin, short, small and better performance of electronic products.

[0003] However, continuously improving the integration of semiconductor devices can lead to difficulties in improving the performance of dynamic random access memory, or make it difficult to maintain or even degrade its performance. Although the existing dynamic random access memory has generally met the needs, it is not satisfactory in all aspects. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device, comprising: a substrate, a pair of source / drain regions, a metal-containing layer, a gate structure, a gate dielectric layer, a buffer layer and a gate conductive layer. The substrate has a trench. The source / drain regions are disposed in the substrate on both sides of the trench. The metal-containing layer is disposed below the trench, and the metal-containing layer and the substrate on the opposite sidewalls of the trench together form a channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure includes: a gate dielectric layer disposed on the opposite sidewalls of the trench, a buffer layer disposed on the metal-containing layer, and a gate conductive layer disposed on the buffer layer and filling the trench.

[0005] Embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a doped region on a substrate; etching the substrate to form a trench passing through the doped region and extending into the substrate; forming a gate dielectric layer on the sidewalls of the trench; forming a metal-containing layer below the trench; forming a buffer layer on the metal-containing layer; and forming a gate conductive layer on the buffer layer and filling the trench. BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1A 、 FIG. 1B 、 FIG. 2 is a cross-sectional view of a semiconductor device according to some embodiments of the present application;

[0007] FIG. 3 is a cross-sectional view of a semiconductor device according to other embodiments of the present application;

[0008] FIGS. 4-13FIG. 1 is a cross-sectional view illustrating a process of forming a semiconductor device according to some embodiments of the present application;

[0009] FIGS. 14-15 FIG. 2 is a cross-sectional view illustrating a process of forming a semiconductor device according to other embodiments of the present application.

[0010] REFERENCE NUMERALS

[0011] 10, 20: semiconductor device

[0012] 100: substrate

[0013] 102: source / drain region

[0014] 103: trench

[0015] 104: first trench

[0016] 118: second trench

[0017] 105: gate structure

[0018] 106: gate dielectric layer

[0019] 108: metal layer

[0020] 110: metal-containing layer

[0021] 112: buffer layer

[0022] 114: barrier layer

[0023] 116: gate conductive layer

[0024] 120: isolation layer

[0025] 122: first connecting member

[0026] 124: second connecting member

[0027] 126: bit line

[0028] 128: capacitor

[0029] 130: isolation structure

[0030] DR1: first direction

[0031] DR2: second direction

[0032] L1, L2, L3, L4, L5, L6, L7: length DETAILED DESCRIPTION

[0033] The following disclosure provides numerous examples of different elements for implementing the subject matter. Specific examples of each element and its configuration are described below for simplification and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct or indirect contact; indirect contact, for example, includes an additional element formed between the first and second elements. Terms such as "connection" and "interconnection" can refer to two structures in direct or indirect contact.

[0034] The terms "about" or "approximately" in the text typically indicate a range within ±20% of a given value, preferably within ±10%, and even more preferably within ±5% or ±1%. Even without specific explanation of "about" or "approximately," the given numerical value may still imply the meaning of "about" or "approximately."

[0035] Current in a semiconductor device (e.g., conduction current (I)) ON The on-state current (or drive current) may decrease as semiconductor devices are miniaturized. For example, to overcome leakage current caused by semiconductor device miniaturization, the threshold voltage can be increased, provided that process margins and device design allow it. However, increasing the threshold voltage may reduce the on-state current or drive current of the semiconductor device, thereby affecting the performance of the semiconductor device. For dynamic random access memory (DRAM), a lower drive current may adversely affect the write recovery time (tWR) and / or retention time, leading to a decrease in DRAM performance.

[0036] This invention provides a semiconductor device and a method for forming the same, wherein using a metal-containing layer as part of the channel region of the semiconductor device can increase the drive current to improve the performance of the semiconductor device.

[0037] FIG. 1A A cross-sectional view of a semiconductor device 10 including a buried gate transistor is shown. The semiconductor device 10 includes: a substrate 100, a pair of source / drain regions 102, a metal layer 110, and a gate structure 105. FIG. 1AAs shown, the substrate 100 has a trench 103. The substrate 100 can include an elemental semiconductor including silicon or germanium; a compound semiconductor including gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor including a silicon-germanium (SiGe) alloy, a gallium-arsenic-phosphorus (GaAsP) alloy, an aluminum-indium-arsenide (AlInAs) alloy, an aluminum-gallium-arsenide (AlGaAs) alloy, a gallium-indium-arsenide (GaInAs) alloy, a gallium-indium-phosphorus (GaInP) alloy, and / or a gallium-indium-arsenide-phosphorus (GaInAsP) alloy, or a combination of the foregoing. The substrate 100 can also be a semiconductor on insulator (SOI). According to some embodiments of the present disclosure, the substrate 100 can be an undoped silicon substrate or a doped silicon substrate, where the doped silicon substrate can be an N-type doped silicon substrate or a P-type doped silicon substrate.

[0038] Referring to FIG. 1A The source / drain regions 102 are disposed in the substrate 100 on either side of the top of the trench 103. In some embodiments of the present disclosure, the source / drain regions 102 can be N-type doped, for example, with phosphorus, arsenic, or antimony, and the substrate 100 can be P-type doped, for example, with boron or indium. In other embodiments, the source / drain regions 102 can be P-type doped and the substrate 100 can be N-type doped.

[0039] The metal-containing layer 110 is disposed below the trench 103 and around the bottom of the trench 103. In some embodiments of the present disclosure, the metal-containing layer 110, together with the substrate 100 on opposite sidewalls of the trench 103 that are on top of the metal-containing layer 110, forms a channel region of the semiconductor device 10. In other words, the metal-containing layer 110 is part of the channel region of the semiconductor device 10. The metal-containing layer 110 can include a metal silicide layer, which can include a cobalt disilicide layer, a nickel silicide layer, a titanium silicide layer, other metal silicide layers, or a combination of the foregoing. In some embodiments, the metal-containing layer 110 extends laterally beyond the sidewalls of the trench 103. In some embodiments, the metal-containing layer 110 has a thickness of greater than or equal to 5 nm, for example, in a range from about 5 nm to about 9 nm, such as about 5 nm, about 7 nm, about 8 nm, or about 9 nm.

[0040] As FIG. 1AAs shown, a gate structure 105 is disposed in the trench 103. The gate structure 105 can be composed of a gate dielectric layer 106, a buffer layer 112, and a gate conductive layer 116. The gate dielectric layer 106 is disposed on opposite sidewalls of the trench 103. In some embodiments, a bottom of the gate dielectric layer 106 is connected to a top of the metal-containing layer 110. The material of the gate dielectric layer 106 can include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thickness of the gate dielectric layer 106 is less than the thickness of the metal-containing layer 110. For example, the thickness of the gate dielectric layer 106 can be about 4 nm to about 6 nm. In some embodiments, the metal-containing layer 110 laterally extends beyond the gate dielectric layer 106.

[0041] The buffer layer 112 is disposed on the metal-containing layer 110. In some embodiments, the buffer layer 112 is conformally disposed along the sidewalls of the gate dielectric layer 106 and the top surface of the metal-containing layer 110, forming a U-shaped profile of the buffer layer 112. The material of the buffer layer 112 can include silicon oxide, silicon nitride, silicon oxynitride, or a high-k (dielectric constant greater than 3.9) dielectric material. For example, the high-k dielectric material can include HfO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, Al2O3, or a combination thereof. In some embodiments, the buffer layer 112 is a single layer structure composed of silicon oxide. In other embodiments, the buffer layer 112 is a multi-layer structure including silicon oxide and a high-k dielectric material.

[0042] The gate conductive layer 116 is disposed on the buffer layer 112 and fills the trench 103. In some embodiments, the top surfaces of the buffer layer 112 and the gate conductive layer 116 are flush with each other. The gate conductive layer 116 can include a metal layer, a metal nitride layer, or a combination thereof. The material of the metal layer can include aluminum, copper, tungsten, titanium, tantalum, a metal alloy, other suitable materials, or a combination thereof. The material of the metal nitride layer can include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable materials, or a combination thereof. In some embodiments, the gate conductive layer 116 is a multi-layer structure including a metal nitride layer (e.g., titanium nitride) and a metal layer (e.g., tungsten) disposed on the metal nitride layer. In other embodiments, the gate conductive layer 116 is a single layer structure composed of a single metal nitride layer. In some embodiments, the metal-containing layer 110 is U-shaped and surrounds a portion of the gate conductive layer 116, as shown in FIG. 1A. In other embodiments, the metal-containing layer 110 is disposed on the gate conductive layer 116, as shown in FIG. 1B. FIG. 1AIn some embodiments, barrier layer 114 can be disposed between buffer layer 112 and gate conductive layer 116. For example, barrier layer 114 can include SiN, SiCN, SiOC, or SiOCN.

[0043] Still referring to FIG. 1A In some embodiments, semiconductor device 10 can include isolation layer 120. Isolation layer 120 is disposed on buffer layer 112 and gate conductive layer 116, and between source / drain regions 102. In some embodiments, isolation layer 120 fills the top of trench 103 and can be flush with the surface of substrate 100. The material of isolation layer 120 can be the same as or similar to the material of gate dielectric layer 106. For example, isolation layer 120 can include silicon nitride.

[0044] According to some embodiments of the present disclosure, the channel region of semiconductor device 10 is formed by metal-containing layer 110 and substrate 100 on the opposite sidewalls of trench 103. Metal-containing layer 110 in the channel region can reduce the resistance of the channel region, thereby increasing the mobility of the electrons to increase the on-current (or drive current) and improve the performance of the device. In embodiments of the present disclosure, metal-containing layer 110 is part of the channel region of semiconductor device 10, and metal-containing layer 110 is separated from source / drain regions 102 by substrate 100, i.e., metal-containing layer 110 does not directly contact source / drain regions 102. Therefore, metal-containing layer 110 does not cause shorting of source / drain regions 102.

[0045] Referring to FIG. 1A The solid circles drawn therein schematically represent electrons in an on state, in which the electrons flow from one of source / drain regions 102 through the channel region (metal-containing layer 110 and substrate 100 on the opposite sidewalls of trench 103) to the other source / drain region 102. Metal-containing layer 110 can increase the mobility of the electrons when the electrons flow through the channel region. As will be described below, the length of metal-containing layer 110 can be adjusted by the process of forming metal-containing layer 110. In some embodiments, referring to FIG. 1A The length of metal-containing layer 110 is the sum of lengths LI and L3 in the first direction DR1 and length L2 in the second direction DR2 (i.e., the length of metal-containing layer 110 is LI + L2 + L3). In some embodiments, the first direction DR1 is perpendicular to the second direction DR2. According to some embodiments, length LI and length L3 can each be about 5 nm to about 10 nm. According to some embodiments, length L2 can be about 20 nm to about 30 nm.

[0046] Referring to FIG. 1Bwherein the electrons (solid dots) and holes (open circles) are schematically depicted in the off state. Free electrons, if any, in the metal-containing layer 110 in the off state can recombine with the holes in the off state. Thus, employing a metal-containing layer as part of the channel region in a semiconductor device does not result in leakage or shorting.

[0047] Referring to FIG. 2 According to some embodiments of the present application, the semiconductor device 10 can be used in a dynamic random access memory application, wherein the gate structure 105 of the semiconductor device 10 serves as a buried word line of the dynamic random access memory, and the dynamic random access memory further comprises a first connection 122, a second connection 124, an isolation structure 130, a bit line 126, and a capacitor 128. It should be noted that the components in the figures can not be drawn to scale for the sake of ease of understanding. The first connection 122 and the second connection 124 are disposed on the source / drain regions 102, respectively. The material of the first connection 122 and the second connection 124 can comprise aluminum, copper, tungsten, other suitable materials, or combinations thereof. The isolation structure 130 is disposed between the first connection 122 and the second connection 124. In some embodiments, the material of the isolation structure 130 can comprise silicon oxide, silicon nitride, or silicon oxynitride. The bit line 126 is disposed on the first connection 122. In some embodiments, the bit line 126 can be constructed the same as or similar to the gate structure 105 serving as the buried word line. The capacitor 128 is disposed on the second connection 124. In some embodiments, the capacitor 128 is electrically connected to one of the source / drain regions 102 via the second connection 124, and the bit line 126 is electrically connected to the other source / drain region 102 via the first connection 122. In some embodiments, the metal-containing layer 110 is U-shaped and surrounds the bottom of the gate structure 105 serving as the buried word line.

[0048] As mentioned previously, lower drive current can adversely affect the write recovery time (tWR) and / or the retention time and degrade the performance of the dynamic random access memory. For example, at the on state, lower drive current requires a longer write time to charge the desired amount of charge into the capacitor, resulting in a longer write recovery time (i.e., slower write speed) and degrading the performance of the dynamic random access memory. On the other hand, at the same write time, lower drive current provides less amount of charge, and thus at the off state, less amount of charge remains in the capacitor, resulting in a shorter retention time and degrading the performance of the dynamic random access memory.

[0049] FIG. 2In the illustrated embodiment, the channel region of the dynamic random access memory (DRAM) is jointly formed by a metal layer 110 and a substrate 100 on opposite sidewalls of the trench 103. The metal layer 110 can improve electron mobility to increase the drive current. Therefore, the write recovery time can be reduced to improve the performance of the DRAM. Furthermore, in some embodiments, due to the increased drive current, more charge can be charged into the capacitor in the same write time, which can increase the retention time to improve the performance of the DRAM.

[0050] The metal layer 110 may have other shapes or different lengths. FIG. 3 This is a cross-sectional view of a semiconductor device 20 having a shorter metal layer 110, according to another embodiment of the present invention. For example, the length L4 of the metal layer 110 can be about 20 nm to about 30 nm. The metal layer 110 of the semiconductor device 20 is only disposed below the trench 103 and does not extend upward to the sidewall of the trench 103; therefore, its length L4 can be less than that described above. FIG. 1A The length (L1+L2+L3) of the metal-containing layer 110 of the semiconductor device 10. In these embodiments, a shorter metal-containing layer 110 can further provide flexibility in process and device design, and, as will be described below, can simplify the process and reduce process costs. In some embodiments, the metal-containing layer 110 of the semiconductor device 20 extends laterally beyond the sidewalls of the trench 103 and / or the sidewalls of the gate dielectric layer 106.

[0051] FIGS. 4-13 This is a cross-sectional view illustrating the process of forming the semiconductor device 10 according to some embodiments of the present invention. (Refer to...) FIG. 4 A blanket-doped substrate 100 is formed to create doped regions 102 on the substrate 100. Doping can be performed using ion implantation to implant a dopant into the substrate 100. In some embodiments, the dopant may include an N-type dopant, such as phosphorus, arsenic, antimony, or other N-type dopant. In other embodiments, the dopant may include a P-type dopant, such as boron, indium, or other P-type dopant.

[0052] Then as FIG. 5As shown, a patterning process is performed to form a first trench 104 through the doped region 102 and into the substrate 100. In some embodiments, the patterning process can include forming a photoresist layer (not shown) over the doped region 102, exposing the photoresist layer to a pattern, performing a post-exposure bake process, developing the photoresist layer to form a patterned mask layer, then using the patterned mask layer to etch the doped region 102 and the substrate 100 to form the first trench 104, and then removing the patterned mask layer. The etching process can include dry etching (e.g., reactive ion etching (RIE) or plasma etching), wet etching, and / or other suitable processes. After the patterning process, the doped region 102 on both sides of the first trench 104 can serve as source / drain regions for a subsequently formed semiconductor device.

[0053] Referring to FIG. 6 , a gate dielectric layer 106 is formed on the sidewalls of the first trench 104. In some embodiments, the material of the gate dielectric layer 106 can include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials, and can be formed by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, in situ steam generation (ISSG), or the like. According to some embodiments of the present disclosure, the gate dielectric layer 106 is formed by forming a silicon oxide layer on the sidewalls of the first trench 104 and on the substrate 100 using in situ steam generation (ISSG), and then removing the unwanted silicon oxide layer (e.g., the silicon oxide layer on the doped region 102 or the substrate 100) via a suitable etching process, thereby forming the gate dielectric layer 106 on the sidewalls of the first trench 104.

[0054] FIGS. 7-10 A process of forming a metal-containing layer 110 under the first trench 104 is shown. Although some embodiments are described in a sequential order, the steps in these embodiments can be performed in other logical orders, or some steps in certain embodiments can be omitted. First referring to FIG. 7 , the substrate 100 is etched along the first trench 104 to further extend the first trench 104, thereby forming an extended region 101 as shown by the dashed box in FIG. 7 . The process of extending the first trench 104 can be the same as or similar to the patterning process described above with respect to FIG. 5 .

[0055] Referring to FIG. 8 , a metal layer 108 is formed on the sidewalls of the gate dielectric layer 106 and on the bottom and sidewalls of the extended first trench 104. The material of the metal layer 108 can include cobalt, nickel, titanium, or other metals, and can be formed by physical vapor deposition (e.g., sputtering), atomic layer deposition, or other processes. Then referring to FIG. 9A heat treatment process is performed to silicide the metal layer 108 with the substrate 100 beneath the first trench 104 and the gate dielectric layer 106 to form a metal layer 110 (which may also be referred to as a metal silicide layer after silicide reaction). The heat treatment process may include an annealing process, such as rapid thermal annealing (RTA). In some embodiments, the thickness of the metal silicide layer may depend on the manner in which the annealing process is performed (e.g., one-stage or two-stage annealing) and / or parameters (e.g., annealing temperature). In some embodiments, the appropriate annealing temperature is selected according to the material of the selected metal layer 108. For example, the thickness of the metal silicide layer may be adjusted so that it extends laterally beyond the sidewalls of the gate dielectric layer 106. In some embodiments, the material composition of the metal silicide layer depends on the material of the metal layer 108. The metal silicide layer includes a cobalt disilicide layer, a nickel silicide layer, a titanium silicide layer, or a combination thereof. In some embodiments, reference is made to... FIG. 7 and FIG. 9 A metal layer 110 is formed below and around the extension region 101. Therefore, by adjusting the extension depth of the first trench 104 through the process of extending the first trench 104, the length L6 of the metal layer 110 along the bottom of the extended first trench 104 and / or the lengths L5 and L7 along the sidewalls of the extended first trench 104 can be controlled. According to some embodiments, the lengths L5 and L7 can each be about 5 nm to about 10 nm. According to some embodiments, the length L6 can be about 20 nm to about 30 nm. As described above, the metal layer 110 can serve as part of the channel region of the semiconductor device 10 to enhance the drive current. Therefore, the length of the metal layer 110 can be adjusted through the aforementioned process to achieve the desired drive current according to the design requirements of the device. Next, the unreacted metal layer 108 is removed, such as... FIG. 10 As shown. Unreacted metal layer 108 can be removed by an etching process. Although the above description relates to the formation of metal-containing layer 110 using a metal silicide process, this disclosure is not limited thereto. For example, in other embodiments, other methods may be used to form metal-containing layer 110, such as physical vapor deposition, metal-organic chemical vapor deposition, or other suitable processes.

[0056] Reference FIG. 11 A buffer layer 112 is compliantly formed on the metal-containing layer 110. In some embodiments, the buffer layer 112 is also formed on the sidewall of the gate dielectric layer 106. The material of the buffer layer 112 may include silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric material. The buffer layer 112 may be formed using chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, spin coating, one or more other suitable processes, or a combination thereof. The buffer layer 112 may be a single-layer structure or a multilayer structure formed of different materials.

[0057] Referring to FIG. 12 A gate conductive layer 116 is formed on the buffer layer 112 and fills the first trench 104. The gate conductive layer 116 can include a metal layer, a metal nitride layer, or a combination thereof. The gate conductive layer 116 can be formed by physical vapor deposition, atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, other suitable processes, or a combination thereof. In some embodiments, the gate conductive layer 116 can be a multi-layer structure including a metal nitride layer formed on the sidewalls and the bottom surface of the buffer layer 112 and a metal layer formed on the metal nitride layer and filling the first trench 104. In such embodiments, the metal nitride layer can have a barrier effect. In other embodiments, such as semiconductor devices with smaller trench width for further scaling, a single layer of gate conductive layer 116, such as a single layer of metal nitride layer, can be used due to the small trench width.

[0058] In some embodiments, an optional barrier layer 114 is formed along the sidewalls and / or the bottom surface of the buffer layer 112 before the gate conductive layer 116 is formed on the buffer layer 112. The material of the barrier layer 114 can include SiN, SiCN, SiOC, or SiOCN, and can be formed by chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0059] Referring to FIG. 13 The buffer layer 112, the barrier layer 114 (if formed), and the gate conductive layer 116 are etched back to form a second trench 118 exposing the gate dielectric layer 106. In some embodiments, the etching back is a back-etching process, which can include dry etching (e.g., reactive ion etching) or other etching processes. In some embodiments, after the etching back, the top surfaces of the buffer layer 112, the barrier layer 114 (if formed), and the gate conductive layer 116 are flush with each other. The isolation layer 120 is then filled into the second trench 118 to form the semiconductor device 10 as shown in FIG. 1A In some embodiments, the isolation material layer can be deposited into the second trench 118 by chemical vapor deposition or plasma-enhanced chemical vapor deposition, and then a planarization process (e.g., chemical mechanical polishing or back-etching) is used to remove the excess isolation material layer, thereby forming the isolation layer 120.

[0060] According to some embodiments of the present disclosure, after the semiconductor device 10 as shown in FIG. 1A is formed, a subsequent process can be performed to form the semiconductor device 10 as shown in FIG. 2The dynamic random access memory shown. Subsequent processes include, but are not limited to, forming first and second connections 122 and 124 on the source / drain regions 102, forming an isolation structure 130 between the first and second connections 122 and 124, forming a bit line 126 on the first connection 122, and forming a capacitor 128 on the second connection 124.

[0061] FIG. 14 and FIG. 15 According to other embodiments of the present application, cross-sectional views of processes for forming a semiconductor device 20 are shown. After forming a first trench 104 as shown in FIG. 6 the process of extending the trench shown in FIG. 7 may be omitted, and a metal layer 108 is formed on the sidewalls of the gate dielectric layer 106 and the bottom of the first trench 104 as shown in FIG. 14 A thermal process is then performed to cause the metal layer 108 to react with the substrate 100 underneath the first trench 104 and the gate dielectric layer 106 to form a metal silicide layer as shown in FIG. 15 Processes similar to those described above with respect to FIGS. 10-13 and filling the isolation layer 120 are then performed to form a semiconductor device 20 as shown in FIG. 3 FIG. 3 In these embodiments, the drive current can be increased to improve device performance as described above, and process cost and time can be reduced due to the omission of the process of extending the trench.

[0062] The semiconductor device and method of forming the same according to embodiments of the present application include forming a metal-containing layer as part of the channel region of the semiconductor device, which can increase the drive current to improve the performance of the semiconductor device. For example, write recovery time (tWR) can be reduced. In some embodiments, retention time can also be increased. Furthermore, the method of forming the semiconductor device according to embodiments of the present application can also adjust the length of the metal-containing layer to achieve a desired drive current and increase process margin as needed.

[0063] The foregoing summary of some embodiments is provided to better understand the various aspects of the present application. Those skilled in the art will readily recognize that the embodiments presented herein are merely illustrative of the principles of the present application. Those skilled in the art will readily recognize that other processes and materials can be used without departing from the spirit and scope of the present application. Accordingly, the present application is not to be limited as presented in this summary.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate having a trench; a pair of source / drain regions disposed in the substrate on opposite sides of the trench; a metal-containing layer disposed under the trench, wherein the metal-containing layer includes a metal silicide layer, the metal-containing layer and the substrate on opposite sidewalls of the trench collectively form a channel region of the semiconductor device, the metal-containing layer and the pair of source / drain regions are separated by the substrate; and a gate structure disposed in the trench, the gate structure includes: a gate dielectric layer disposed on opposite sidewalls of the trench; a buffer layer disposed on the metal-containing layer; and a gate conductive layer disposed on the buffer layer and filling the trench.

2. The semiconductor device according to claim 1, wherein The metal-containing layer laterally extends beyond the sidewalls of the trench.

3. The semiconductor device according to claim 1, wherein The metal-containing layer is U-shaped and surrounds a portion of the gate conductive layer.

4. The semiconductor device according to claim 1, wherein The metal silicide layer includes: a cobalt disilicide layer, a nickel silicide layer, a titanium silicide layer, or a combination thereof.

5. The semiconductor device according to claim 1, wherein Further comprising: a first contact and a second contact disposed on the pair of source / drain regions, respectively; an isolation structure disposed between the first contact and the second contact; a bit line disposed on the first contact; and a capacitor disposed on the second contact.

6. A method of forming a semiconductor device, characterized by, Comprising: forming a doped region on a substrate; etching the substrate to form a first trench through the doped region and extending into the substrate; forming a gate dielectric layer on sidewalls of the first trench; forming a metal-containing layer under the first trench, wherein the metal-containing layer includes a metal silicide layer, the metal-containing layer and the doped region are separated by the substrate; forming a buffer layer on the metal-containing layer; and forming a gate conductive layer on the buffer layer and filling the first trench.

7. The method for forming a semiconductor device according to Claim 6, wherein Before forming the metal-containing layer under the first trench, further comprising: etching the substrate along the first trench to form an extension region, and the metal-containing layer is formed under and around the extension region.

8. The method for forming a semiconductor device according to Claim 6, wherein Forming the metal-containing layer under the first trench includes: forming a metal layer on sidewalls of the gate dielectric layer and a bottom of the first trench; performing a heat treatment process to cause the metal layer to react with the substrate under the first trench and the gate dielectric layer to form the metal silicide layer; and removing unreacted metal layer.

9. The method for forming a semiconductor device according to Claim 8, wherein The metal silicide layer laterally extends beyond the sidewalls of the gate dielectric layer.

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