A multi-split channel decoding tracking device and display terminal

Abstract

This invention provides a multi-segment channel decoding and tracking device, comprising: a data sampling unit, a synchronization detection unit, a control signal generation unit, a reset generation unit, a channel tracking counting unit, a channel prediction unit, and a channel decision output unit. Through the coordinated operation of these units, multi-segment display of the image can be achieved. This device supports single-port multi-channel transmission, improving the utilization rate of ITU data transmission ports. It performs real-time channel decoding and tracking of ITU signals input to the port in hardware, solving the synchronization problem of signal channels during multi-channel transmission between the ITU receiver and input end. This reduces the software resource requirements for multi-channel display, improves the efficiency of decoding and tracking multiple camera input segmented display channels, and makes real-time multi-segment image display more accurate and stable.

Description

Technical Field

[0001] This invention relates to the field of digital image processing technology, and in particular to a multi-segment channel decoding and tracking device and a display terminal. Background Technology

[0002] In fields such as automotive driver assistance and video surveillance, in order to enable users to have a clearer and more unified grasp of the real-time situation, it is necessary to display the video footage input from multiple cameras on the same terminal, and realize the synchronous display of two-split, four-split, and six-split images. The application of multi-screen video display is becoming more and more widespread.

[0003] In current technical solutions, the front-end camera receives images via AHD input and outputs via ITU656 / 601. The back-end then fuses the ITU656 / 601 signals from multiple input channels and displays them synchronously on a single terminal. Traditionally, each input port corresponds to the transmission of one channel's ITU656 / 601 signal. To support simultaneous display of two-, four-, or six-segment images from multiple channels, multiple ITU656 / 601 signal ports are required for fusion. The more channels supported, the more pins are needed, which introduces significant inconvenience and costs in chip pin packaging and PCB routing. It may even require multiple chips to achieve the fused split-display function. Based on further requirements, a scheme for transmitting multiple channels through a set of ITU656 ports was proposed, namely, a one-port-multiple-channel transmission method. The existing method usually presets a low-speed clock according to the number of channels to directly downsample and decode the input ITU656 data, and then the software determines the channel information of the image and decides to divide and display it at the selected position on the screen. The problem with software judgment is that the response speed is slow, and even after each ITU receiver chip is powered on, the time for the screen to display the correct image is long, and it may even cause the image display position to be disordered.

[0004] Achieving efficient image rotation operations on a low-cost, single-display-chip small system is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the technical problem to be solved by the present invention is to provide a multi-segment channel decoding and tracking device and a display terminal to overcome the shortcomings of the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a multi-segment channel decoding and tracking device, comprising: a data sampling unit, a synchronization detection unit, a control signal generation unit, a reset generation unit, a channel tracking counting unit, a channel prediction unit, and a channel decision output unit;

[0008] The data sampling unit is used to sample the input ITU656 data according to the transition edge of the input clock to obtain sampled data; the transition edge includes rising edge and falling edge;

[0009] The synchronization detection unit is used to store the sampled data into a preset channel buffer according to the tracking count value of the channel tracking counting unit, and is also used to control whether to generate a synchronization signal according to the synchronization time base information.

[0010] The control signal generation unit is used to generate a synchronous decoding and tracking control signal based on the number of channels and single / dual edge mode of the input signal; it is also used to generate a main counting enable signal and a main judgment enable signal.

[0011] The reset generation unit is used to generate a reset signal for the channel tracking count based on the synchronization signal output by the synchronization detection unit, the control signal generated by the control signal generation unit, and the count value generated by the tracking count value of the channel tracking count unit.

[0012] The channel tracking and counting unit is used to generate tracking count values ​​so that the decoded channel information is completely synchronized with the channel information output by the front end;

[0013] The channel prediction unit is used to perform channel data prediction based on the tracking count value of the channel tracking counting unit, and to store the ITU656 input data in different channels according to the tracking count value.

[0014] The channel decision output unit is used to output the corresponding multi-segment channel decoding tracking signal according to the control signal generated by the control signal generation unit.

[0015] Furthermore, the data sampling unit includes a positive edge data sampling unit and a negative edge data sampling unit; the positive edge data sampling unit is responsible for receiving ITU656 data and sampling the input channel data using the rising edge of the input clock to obtain data sequences itu_data0 and itu_data1; the negative edge data sampling unit receives ITU656 data and samples the input channel data using the falling edge of the input clock to obtain data sequences n_itu_data0 and n_itu_data1.

[0016] Furthermore, the synchronization detection unit includes a positive edge synchronization detection unit and a negative edge synchronization detection unit;

[0017] The positive edge synchronization detection unit is responsible for receiving itu_data0 and storing itu_data0 into the pre-selected channel buffer according to the tracking count value of the positive edge channel tracking count unit, thus obtaining the pre-selected multi-level data buffers ch_d0, ch_d1, ch_d2, and ch_d3; the positive edge synchronization detection unit obtains the synchronization time base information, and when the data buffers ch_d1, ch_d2, and ch_d3 are equal to the synchronization time base information, it is determined that the synchronization signal syn_det has been detected;

[0018] The negative edge synchronization detection unit is responsible for receiving n_itu_data0 and storing n_itu_data0 into the pre-selected channel buffer according to the tracking count value of the negative edge channel tracking counting unit, thus obtaining the pre-selected multi-level data buffers n_ch_d0, n_ch_d1, n_ch_d2, and n_ch_d3. The negative edge synchronization detection unit obtains the synchronization time base information. When the data buffers n_ch_d1, n_ch_d2, and n_ch_d3 are equal to the time base information, it is determined that the synchronization signal n_syn_det has been detected.

[0019] Furthermore, the control signal generation unit includes a positive edge control signal generation unit and a negative edge control signal generation unit;

[0020] The positive edge control signal generation unit is responsible for generating the positive edge master count enable signal p_en and the positive edge master judgment enable signal p_judge_en. When the system is powered on, p_en defaults to 1 and p_judge_en defaults to 0. When a positive edge synchronous reset signal is received, the positive edge master count enable signal is generated as 1. When a negative edge synchronous reset signal is received, the positive edge master count enable signal is generated as 0. In the next cycle after receiving the negative edge synchronous reset signal, the positive edge master judgment enable signal p_judge_en is equal to the negative edge master judgment enable signal n_judge_en.

[0021] The negative edge control signal generation unit is responsible for generating the negative edge main count enable signal n_en and the negative edge main judgment enable signal n_judge_en. When the system is powered on, n_en and n_judge_en are both set to 0 by default. When a negative edge synchronous reset signal is received, the negative edge main count enable signal is set to 1. When a positive edge synchronous reset signal is received, the negative edge main count enable signal is set to 0. In the next cycle after receiving the positive edge synchronous reset signal, the negative edge main judgment enable signal n_judge_en is equal to the positive edge main judgment enable signal p_judge_en.

[0022] Furthermore, the control signal generation unit generates corresponding synchronous decoding and tracking control signals based on the dual-edge mode, dual-channel mode, and four-channel mode of the input signal. When the dual-edge mode is 0 and the four-channel mode is 1, the output control is effective for single-edge four-channel; when the dual-edge mode is 1 and the four-channel mode is 1, the output control is effective for dual-edge four-channel; when the dual-edge mode is 0 and the dual-channel mode is 1, the output control is effective for single-edge dual-channel; when the dual-edge mode is 1 and the dual-channel mode is 1, the output control is effective for dual-edge dual-channel; otherwise, the output control is effective for single-edge single-channel.

[0023] Furthermore, the reset generation unit includes a positive edge reset generation unit and a negative edge reset generation unit;

[0024] The positive edge reset generation unit receives the synchronization signal syn_det output by the positive edge synchronization detection unit, the control signal generated by the positive edge control signal generation unit, and the positive edge count value counter_p generated by the positive edge channel tracking count unit, and generates a reset signal for the positive edge channel tracking count. In single-edge four-channel mode, and counter_p equals 3, syn_det equals 1, and the data buffer ch_d0 is not equal to the preset channel identification code chid_set, a positive edge counter pre-reset signal counter_p_syn is generated. In dual-edge four-channel mode, and co If `ch_p` equals 2, `syn_det` equals 1, and the data buffer `ch_d0` is not equal to the preset channel identifier `chid_set`, then a positive edge counter pre-reset signal `counter_p_syn` is generated. In single-edge dual-channel mode, if `counter_p` equals 1, `syn_det` equals 1, and the data buffer `ch_d0` is not equal to the preset channel identifier `chid_set`, then a positive edge counter pre-reset signal `counter_p_syn` is generated. In dual-edge dual-channel mode, if `counter_p` equals 0 and `syn_det` equals 1... If the data buffer ch_d0 is not equal to the preset channel identification code chid_set, a positive edge counter pre-reset signal counter_p_syn is generated; the rising edge of counter_p_syn is detected, and a positive edge synchronization reset signal is generated when the rising edge occurs; the negative edge reset generation unit is used to receive the synchronization signal n_syn_det output by the negative edge synchronization detection unit, the control signal generated by the negative edge control signal generation unit, and the negative edge count value counter_n generated by the negative edge channel tracking count unit, and generate a reset signal for the negative edge channel tracking count; when it is a dual-edge four-channel mode, and c If counter_n equals 2, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, then a negative edge counter pre-reset signal counter_n_syn is generated; when it is a dual-edge dual-channel mode, and counter_n equals 0, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, then a negative edge counter pre-reset signal counter_n_syn is generated; the rising edge of counter_n_syn is detected, and a negative edge synchronous reset signal is generated when the rising edge occurs.

[0025] Furthermore, the channel tracking counting unit includes: a positive edge channel tracking counting unit and a negative edge channel tracking counting unit;

[0026] The positive edge channel tracking counter unit is used to generate the positive edge channel tracking count value counter_p, so that the decoded information can be completely synchronized with the information output by the front end. When the system is powered on, counter_p is set to 0; when a reset signal is received from the positive edge reset generation unit, counter_p is set to the value of ch_d0 to re-track the synchronized channel information; when the control signal is in single-edge four-channel mode, counter_p automatically increments by 1; when the control signal is in dual-edge four-channel mode, if the positive edge master count enable p_en is 1, counter_p automatically increments by 2, if... If the positive edge master count enable p_en is 0, then counter_p equals the negative edge channel tracking count value counter_n plus 1; when the control signal is in single-edge dual-channel mode, counter_p is limited to 1, and the least significant bit is automatically incremented by 1; when the control signal is in dual-edge dual-channel mode, if the positive edge master count enable p_en is 1, then counter_p is limited to 1, and counter_p equals counter_p; if the positive edge master count enable p_en is 0, then counter_p is limited to 1, and counter_p equals counter_n plus 1.

[0027] The negative edge channel tracking counter unit is used to generate the negative edge channel tracking counter value counter_n, so that the decoded information can be completely synchronized with the information output by the front end. When the system is powered on, counter_n is set to 1. When a reset signal is received from the negative edge reset generation unit, counter_n is set to the value of n_ch_d0 to re-track the synchronization channel information. When the control signal is in dual-edge four-channel mode, if the negative edge main count enable n_en is 1, counter_n is automatically incremented by 2. If the negative edge main count enable n_en is 0, counter_n is equal to the positive edge channel tracking counter value counter_p plus 1. When the control signal is in dual-edge dual-channel mode, if the negative edge main count enable n_en is 1, counter_n is limited to 1, and counter_n is equal to counter_n. If the negative edge main count enable n_en is 0, counter_n is limited to 1, and counter_n is equal to counter_p plus 1.

[0028] Furthermore, the channel prediction unit includes: a channel positive edge prediction unit and a channel negative edge prediction unit;

[0029] The channel positive edge prediction unit is used to make a positive edge channel data prediction based on the positive edge channel tracking count information; in the next cycle after the positive edge channel reset signal is generated, the sampled data of each positive edge channel is cleared to 0; when counter_p equals x, then chx_d0 equals itu_d0, where x is a natural number;

[0030] The channel negative edge prediction unit is used to make a prediction of the channel data of the negative edge based on the information of the negative edge channel tracking count; in the next cycle after the negative edge channel reset signal is generated, the sampled data of each negative edge channel is cleared to 0; when counter_n is equal to x, then n_chx_d0 is equal to itu_d0, and x is a natural number.

[0031] Furthermore, the channel decision output unit outputs the corresponding multi-segment channel decoding tracking signal based on the control signal generated by the control signal generation unit, specifically including:

[0032] When the control signal is in dual-edge four-channel mode, if p_judge_en equals 1, then the output data ch0_out of channel 0 equals n_ch0_d0, the output data ch1_out of channel 1 equals ch1_d0, the output data ch2_out of channel 2 equals n_ch2_d0, and the output data ch3_out of channel 3 equals ch3_d0. If p_judge_en equals 0, then the output data ch0_out of channel 0 equals ch0_d0, the output data ch1_out of channel 1 equals n_ch1_d0, the output data ch2_out of channel 2 equals ch2_d0, and the output data ch3_out of channel 3 equals n_ch3_d0.

[0033] When the control signal is in dual-edge, two-channel mode, if p_judge_en equals 1, then the output data ch0_out of channel 0 equals n_ch0_d0, and the output data ch1_out of channel 1 equals ch1_d0. If p_judge_en equals 0, then the output data ch0_out of channel 0 equals ch0_d0, and the output data ch1_out of channel 1 equals n_ch1_d0. In this mode, the outputs of channels 2 and 3 are 0.

[0034] When the control signal is in single-edge four-channel mode, the output data ch0_out of channel 0 is equal to ch0_d0, the output data ch1_out of channel 1 is equal to ch1_d0, the output data ch2_out of channel 2 is equal to ch2_d0, and the output data ch3_out of channel 3 is equal to ch3_d0.

[0035] When the control signal is in single-edge dual-channel mode, the output data ch0_out of channel 0 is equal to ch0_d0, the output data ch1_out of channel 1 is equal to ch1_d0, and the outputs of channels 2 and 3 are 0.

[0036] When the control signal is in single-channel mode, the output of strobe channel 0 is equal to itu_date1, and ordinary ITU decoding processing is performed; all other channels output 0.

[0037] This invention also provides a display device, including the multi-segment channel decoding and tracking device described above.

[0038] Compared with the prior art, the present invention has the following beneficial effects: The multi-segment channel decoding and tracking device provided by the present invention enables single-port multi-channel transmission in chips that support multi-segment display processing, improves the utilization rate of ITU data transmission ports, performs real-time channel decoding and tracking of ITU signals input to the port in hardware, solves the problem of signal channel synchronization when the ITU receiver and input end transmit multiple channels, reduces the software resource requirements of multi-channel display, improves the efficiency of decoding and tracking multiple camera input segmented display channels, and makes real-time multi-segment screen display more accurate and stable. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a structural diagram of a multi-segment channel decoding and tracking device according to the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] like Figure 1 The diagram shown is a structural diagram of a multi-segment channel decoding and tracking device according to an embodiment of the present invention. The device mainly includes: a positive edge data sampling unit, a channel positive edge prediction unit, a positive edge synchronization detection unit, a positive edge reset generation unit, a positive edge channel tracking and counting unit, a positive edge control signal generation unit, a negative edge data sampling unit, a channel negative edge prediction unit, a negative edge synchronization detection unit, a negative edge reset generation unit, a negative edge channel tracking and counting unit, a negative edge control signal generation unit, and a channel decision output unit.

[0043] The rising edge data sampling unit is responsible for receiving 8-bit data from ITU656. It samples the input channel data using the rising edge of the input clock to obtain itu_data0 and itu_data1.

[0044] The positive edge synchronization detection unit receives itu_data0 and, based on the tracking count value of the positive edge channel tracking counter unit, stores itu_data0 into pre-selected channel buffers, resulting in pre-selected data buffer levels ch_d0, ch_d1, ch_d2, and ch_d3. Specifically, when the tracking count value of the positive edge channel tracking counter unit is equal to 0, itu_data0 is stored in ch_d0, and ch_d0, ch_d1, and ch_d2 are stored in ch_d1, ch_d2, and ch_d3 respectively. Finally, the synchronization detection unit considers the synchronization signal syn_det detected when ch_d1, ch_d2, and ch_d3 equal the synchronization time base information.

[0045] The positive edge control signal generation unit generates a synchronous decoding and tracking control signal based on the input control signal, such as dual-edge mode, dual-channel mode, or quad-channel mode. When dual-edge mode is 0 and quad-channel mode is 1, the output control is effective for single-edge quad-channel; when dual-edge mode is 1 and quad-channel mode is 1, the output control is effective for dual-edge quad-channel; when dual-edge mode is 0 and dual-channel mode is 1, the output control is effective for single-edge dual-channel; when dual-edge mode is 1 and dual-channel mode is 1, the output control is effective for dual-edge dual-channel; otherwise, the output control is effective for single-edge single-channel.

[0046] In addition, this unit is responsible for generating the positive edge master count enable signal p_en and the positive edge master judgment enable signal p_judge_en. The specific process is as follows: 1. When the system is powered on, p_en defaults to 1 and p_judge_en defaults to 0; 2. When a positive edge synchronization reset signal is received, this unit generates a positive edge master count enable signal of 1; 3. When a negative edge synchronization reset signal is received, this unit generates a positive edge master count enable signal of 0; 4. In the next cycle after receiving the negative edge synchronization reset signal, the positive edge master judgment enable signal p_judge_en is equal to the negative edge master judgment enable signal n_judge_en (n_judge_en will be described in the subsequent negative edge processing section). By controlling the seamless switching between enabling and disabling the positive edge master count and between the positive edge master judgment signal and the negative edge master judgment signal, the device implemented in this invention can track the channel information of the input ITU port in real time to ensure the correct decoding of ITU signals.

[0047] The positive edge reset generation unit receives the syn_det signal output by the front-end detection module, the control signal generated by the positive edge control signal generation unit, and the positive edge count value counter_p generated by the positive edge channel tracking count unit. It then generates a reset signal for the positive edge channel tracking count to correctly track the channel data and achieve correct ITU signal decoding. In single-edge four-channel mode, if counter_p equals 3, syn_det equals 1, and ch_d0 is not equal to the preset channel identification code chid_set, then the positive edge counter pre-reset signal counter_p_syn is generated and is valid as 1. In dual-edge four-channel mode, if counter_p equals 2, syn_det equals 1, and ch_d0 is not equal to the preset channel identification code chid_set, then the positive edge counter pre-reset signal counter_p_syn is generated and is valid as 1. In single-edge dual-channel mode, if counter_p equals 1, syn_det equals 1, and ch_d0 is not equal to the preset channel identification code chid_set, then the positive edge counter pre-reset signal counter_p_syn is generated and is valid as 1. In dual-edge dual-channel mode, if counter_p equals 0, syn_det equals 1, and ch_d0 is not equal to the preset channel identification code chid_set, then the positive edge counter pre-reset signal counter_p_syn is generated and is valid as 1. After obtaining counter_p_syn, the rising edge of counter_p_syn is detected, and a positive edge synchronous reset signal is generated when the rising edge occurs.

[0048] The positive edge channel tracking counting unit generates a positive edge channel tracking count value counter_p, which ensures that the decoded channel information is completely synchronized with the channel information output from the front end. The specific workflow is as follows: 1. When the system powers on, counter_p is set to 0; 2. Upon receiving a reset signal from the positive edge reset generation unit, counter_p is set to the value of ch_d0 to re-track the synchronization channel information and correct the current counter_p; 3. If the control unit output is in single-edge four-channel mode, counter_p automatically increments by 1; 4. In dual-edge four-channel mode, if the positive edge main count enable p_en is 1, counter_p equals counter_p plus 2; if p_en is 0, counter_p equals the negative edge channel tracking count value counter_n plus 1; 5. In single-edge dual-channel mode, counter_p is limited to 1, and the least significant bit automatically increments by 1; 6. In dual-edge dual-channel mode, if the positive edge main count enable p_en is 1, the maximum limit of counter_p is 1, and counter_p equals counter_p. If p_en is 0, the maximum limit of counter_p is 1, and counter_p equals counter_n plus 1.

[0049] The channel positive edge prediction unit performs positive edge prediction based on the positive edge channel tracking count information. Specifically, in the next cycle after the positive edge channel reset signal is generated, the sampled data of each channel on the positive edge is cleared to 0, including the data ch0_d0 of channel 0, the data ch1_d0 of channel 1, the data ch2_d0 of channel 2, and the data ch3_d0 of channel 3. In other cases, the data input from the ITU is stored in different channels according to the positive edge count value. When counter_p equals x, then chx_d0 equals itu_d0, where x equals 0 to 3. For example, when counter_p equals 0, then ch0_d0 equals itu_d0, and so on for other channels.

[0050] The processing method for negative edge channel data is similar to that for positive edge data. The processing flows for both positive and negative edge channels are closely related. Only through the mutual control and connection between the positive edge path and the negative edge path can the channel decoding and tracking synchronization of this invention be correctly achieved. The negative edge channel data processing part is described in detail below.

[0051] The negative edge data sampling unit is responsible for receiving 8-bit data from ITU656 and sampling the input channel data using the falling edge of the input clock to obtain n_itu_data0 and n_itu_data1.

[0052] The negative edge synchronization detection unit receives n_itu_data0 and, based on the tracking count value of the negative edge channel tracking counter unit, stores n_itu_data0 into pre-selected channel buffers, resulting in pre-selected data buffer levels n_ch_d0, n_ch_d1, n_ch_d2, and n_ch_d3. Specifically, when the tracking count value of the negative edge channel tracking counter unit is equal to 0, n_itu_data0 is stored in n_ch_d0, and n_ch_d0, n_ch_d1, and n_ch_d2 are stored in n_ch_d1, n_ch_d2, and n_ch_d3 respectively. Finally, the synchronization detection unit considers the synchronization signal n_syn_det detected when n_ch_d1, n_ch_d2, and n_ch_d3 equal to the synchronization time base information.

[0053] The negative edge control signal generation unit generates a synchronous decoding and tracking control signal based on the input control signal, such as dual-edge mode, dual-channel mode, or quad-channel mode. When dual-edge mode is 0 and quad-channel mode is 1, the output control is effective for single-edge quad-channel; when dual-edge mode is 1 and quad-channel mode is 1, the output control is effective for dual-edge quad-channel; when dual-edge mode is 0 and dual-channel mode is 1, the output control is effective for single-edge dual-channel; when dual-edge mode is 1 and dual-channel mode is 1, the output control is effective for dual-edge dual-channel; otherwise, the output control is effective for single-edge single-channel.

[0054] In addition, this unit is responsible for generating the negative edge master count enable signal n_en and the negative edge master judgment enable signal n_judge_en. The specific process is as follows: 1. When the system is powered on, n_en and n_judge_en are both set to 0 by default; 2. Upon receiving a negative edge synchronization reset signal, this unit generates a negative edge master count enable signal of 1; 3. Upon receiving a positive edge synchronization reset signal, this unit generates a negative edge master count enable signal of 0; 4. In the next cycle after receiving a positive edge synchronization reset signal, the negative edge master judgment enable signal n_judge_en is equal to the positive edge master judgment enable signal p_judge_en. By accurately and efficiently switching between enabling and disabling the negative edge master count and between the negative edge master judgment signal and the positive edge master judgment signal, the device implemented in this invention can track the channel information of the input ITU port in real time to ensure the correct decoding of ITU signals.

[0055] The negative edge reset generation unit receives the n_syn_det signal output from the preceding detection module, the control signal generated by the negative edge control signal generation unit, and the negative edge count value counter_n generated by the negative edge channel tracking count unit. It then generates a reset signal for the negative edge channel tracking count to correctly track channel data and achieve correct subsequent ITU signal decoding. In dual-edge four-channel mode, if counter_n equals 2, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, a negative edge counter pre-reset signal counter_n_syn is generated and is valid as 1. In dual-edge dual-channel mode, if counter_n equals 0, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, a negative edge counter pre-reset signal counter_n_syn is generated and is valid as 1. After obtaining counter_n_syn, the rising edge of counter_n_syn is detected, and a negative edge synchronous reset signal is generated when the rising edge occurs. This unit does not generate a negative edge reset signal in other channel modes.

[0056] The negative edge channel tracking counter unit generates a negative edge channel tracking count value, counter_n, ensuring complete synchronization between the decoded channel information and the channel information output from the front end. The specific workflow is as follows: 1. When the system powers on, counter_n is set to 1; 2. Upon receiving a reset signal from the negative edge reset generation unit, counter_n is set to the value of n_ch_d0 to re-track and synchronize the channel information, correcting the current counter_n; 3. In dual-edge four-channel mode, if the negative edge master count enable n_en is 1, counter_n equals counter_n plus 2; if n_en is 0, counter_n equals the positive edge channel tracking count value, counter_p plus 1; 4. In dual-edge dual-channel mode, if the negative edge master count enable n_en is 1, the maximum limit of counter_n is 1, and counter_n equals counter_n. If n_en is 0, the maximum limit of counter_n is 1, and counter_n equals counter_p plus 1. In other single-edge channel modes, negative edge counting tracking can be disabled to save power. The negative edge channel tracking counter_n and the positive edge channel tracking counter_p are closely related. Depending on different control conditions such as p_en and n_en, they can achieve accurate reset and correction of the channel count in channel tracking. After the decision unit detects a change in the channel count, it can perform channel switching correction in real time, thereby achieving correct channel decoding and tracking so that the channel information can be completely synchronized with the information of the ITU transmitter.

[0057] The channel negative edge prediction unit performs a pre-judgment of channel data for negative edges based on the negative edge channel tracking count information. Specifically, in the next cycle after the negative edge channel reset signal is generated, the sampled data of each channel for the negative edge is cleared to 0, including the data n_ch0_d0 of negative edge channel 0, the data n_ch1_d0 of channel 1, the data n_ch2_d0 of channel 2, and the data n_ch3_d0 of channel 3. In other cases, according to the negative edge count value, the ITU input data is stored in different channels. When counter_n equals x, then n_chx_d0 equals itu_d0, where x equals 0 to 3. If counter_n equals 0, then n_ch0_d0 equals n_itu_d0, and so on for other channels.

[0058] After rigorous control processing, the positive edge channel data and negative edge channel data are finally output as relevant signals to the channel decision output unit for further processing. The decision output process is specifically described as follows, depending on the different channel operating modes output by the control unit:

[0059] In dual-edge four-channel mode, if p_judge_en equals 1, then the output data ch0_out of channel 0 equals n_ch0_d0, the output data ch1_out of channel 1 equals ch1_d0, the output data ch2_out of channel 2 equals n_ch2_d0, and the output data ch3_out of channel 3 equals ch3_d0. If p_judge_en equals 0, then the output data ch0_out of channel 0 equals ch0_d0, the output data ch1_out of channel 1 equals n_ch1_d0, the output data ch2_out of channel 2 equals ch2_d0, and the output data ch3_out of channel 3 equals n_ch3_d0.

[0060] In dual-edge, two-channel mode, if p_judge_en equals 1, then channel 0 output data ch0_out equals n_ch0_d0, and channel 1 output data ch1_out equals ch1_d0. If p_judge_en equals 0, then channel 0 output data ch0_out equals ch0_d0, and channel 1 output data ch1_out equals n_ch1_d0. In this mode, channels 2 and 3 output 0.

[0061] In single-edge four-channel mode, the output data ch0_out of channel 0 is equal to ch0_d0, the output data ch1_out of channel 1 is equal to ch1_d0, the output data ch2_out of channel 2 is equal to ch2_d0, and the output data ch3_out of channel 3 is equal to ch3_d0.

[0062] In single-edge dual-channel mode, channel 0 outputs data ch0_out equals ch0_d0, and channel 1 outputs data ch1_out equals ch1_d0. Channels 2 and 3 output 0.

[0063] In single-channel mode, the output of strobe channel 0 is equal to itu_date1, and normal ITU decoding processing is performed. All other channels output 0.

[0064] After the decoding and tracking processing of this invention, the multi-channel data of a port can be completely synchronized and matched with the ITU transmitter. Subsequent ITU processing only needs to process the channel signals of each decision output according to the number of channels of the port and the frequency division clock. The image content of the corresponding channel can be displayed on the terminal display screen at the expected position, realizing multi-segment display processing. This avoids the problem that the lack of fast channel data judgment will cause the asynchronous relationship between the ITU receiver and transmitter to result in the channel content display position not being fixed after power-on, or the slow time for the channel image content to reach stability due to software judgment.

[0065] This invention describes an example where a single port supports a maximum of four channels, meaning one port can achieve a four-way split display. In practice, this can be extended to support six or eight channels. Alternatively, in a system, two sets of ports can be superimposed to achieve a split-screen display effect with even more channels.

[0066] This invention also provides a display device, including the multi-segment channel decoding and tracking device described above.

[0067] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above.

[0068] The above-described preferred embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The scope of rights claimed by the present invention should be determined by the scope of the invention application, and not limited to the above-described embodiments.

Claims

1. A multi-segment channel decoding and tracking device, characterized in that, include: The system includes a data sampling unit, a synchronization detection unit, a control signal generation unit, a reset generation unit, a channel tracking and counting unit, a channel prediction unit, and a channel decision output unit. The data sampling unit is used to sample the input ITU656 data according to the transition edge of the input clock to obtain sampled data; the transition edge includes rising edge and falling edge; The synchronization detection unit is used to store the sampled data into a preset channel buffer according to the tracking count value of the channel tracking counting unit, and is also used to control whether to generate a synchronization signal according to the synchronization time base information. The control signal generation unit is used to generate a synchronous decoding and tracking control signal based on the number of channels and single / dual edge mode of the input signal; it is also used to generate a main counting enable signal and a main judgment enable signal. The reset generation unit is used to generate a reset signal for the channel tracking count based on the synchronization signal output by the synchronization detection unit, the control signal generated by the control signal generation unit, and the tracking count value of the channel tracking counting unit. The channel tracking and counting unit is used to generate tracking count values ​​so that the decoded channel information is completely synchronized with the channel information output by the front end; The channel prediction unit is used to perform channel data prediction based on the tracking count value of the channel tracking counting unit, and to store the ITU656 input data in different channels according to the tracking count value. The channel decision output unit is used to output the corresponding multi-segment channel decoding tracking signal according to the control signal generated by the control signal generation unit.

2. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The data sampling unit includes a positive edge data sampling unit and a negative edge data sampling unit. The positive edge data sampling unit is responsible for receiving ITU656 data and sampling the input channel data using the rising edge of the input clock to obtain the data sequences itu_data0 and itu_data1. The negative edge data sampling unit receives ITU656 data and samples the input channel data using the falling edge of the input clock to obtain the data sequences n_itu_data0 and n_itu_data1.

3. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The synchronization detection unit includes a positive edge synchronization detection unit and a negative edge synchronization detection unit; The positive edge synchronization detection unit is responsible for receiving itu_data0 and storing itu_data0 into the pre-selected channel buffer according to the tracking count value of the positive edge channel tracking count unit, thus obtaining the pre-selected multi-level data buffers ch_d0, ch_d1, ch_d2, and ch_d3; the positive edge synchronization detection unit obtains the synchronization time base information, and when the data buffers ch_d1, ch_d2, and ch_d3 are equal to the synchronization time base information, it is determined that the synchronization signal syn_det has been detected; The negative edge synchronization detection unit is responsible for receiving n_itu_data0 and storing n_itu_data0 into the pre-selected channel buffer according to the tracking count value of the negative edge channel tracking counting unit, thus obtaining the pre-selected multi-level data buffers n_ch_d0, n_ch_d1, n_ch_d2, and n_ch_d3. The negative edge synchronization detection unit obtains the synchronization time base information. When the data buffers n_ch_d1, n_ch_d2, and n_ch_d3 are equal to the time base information, it is determined that the synchronization signal n_syn_det has been detected.

4. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The control signal generation unit includes a positive edge control signal generation unit and a negative edge control signal generation unit; The positive edge control signal generation unit is responsible for generating the positive edge master count enable signal p_en and the positive edge master judgment enable signal p_judge_en. When the system is powered on, p_en defaults to 1 and p_judge_en defaults to 0. When a positive edge synchronous reset signal is received, the positive edge master count enable signal is generated as 1. When a negative edge synchronous reset signal is received, the positive edge master count enable signal is generated as 0. In the next cycle after receiving the negative edge synchronous reset signal, the positive edge master judgment enable signal p_judge_en is equal to the negative edge master judgment enable signal n_judge_en. The negative edge control signal generation unit is responsible for generating the negative edge main count enable signal n_en and the negative edge main judgment enable signal n_judge_en. When the system is powered on, n_en and n_judge_en are both set to 0 by default. When a negative edge synchronous reset signal is received, the negative edge main count enable signal is set to 1. When a positive edge synchronous reset signal is received, the negative edge main count enable signal is set to 0. In the next cycle after receiving the positive edge synchronous reset signal, the negative edge main judgment enable signal n_judge_en is equal to the positive edge main judgment enable signal p_judge_en.

5. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The control signal generation unit generates corresponding synchronous decoding and tracking control signals based on the dual-edge mode, dual-channel mode, and four-channel mode of the input signal. When the dual-edge mode is 0 and the four-channel mode is 1, the output control is effective for single-edge four-channel; when the dual-edge mode is 1 and the four-channel mode is 1, the output control is effective for dual-edge four-channel; when the dual-edge mode is 0 and the dual-channel mode is 1, the output control is effective for single-edge dual-channel; when the dual-edge mode is 1 and the dual-channel mode is 1, the output control is effective for dual-edge dual-channel; otherwise, the output control is effective for single-edge single-channel.

6. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The reset generation unit includes a positive edge reset generation unit and a negative edge reset generation unit; The positive edge reset generation unit receives the synchronization signal syn_det output by the positive edge synchronization detection unit, the control signal generated by the positive edge control signal generation unit, and the positive edge count value counter_p generated by the positive edge channel tracking count unit, and generates a reset signal for the positive edge channel tracking count. In single-edge four-channel mode, and counter_p equals 3, syn_det equals 1, and the data buffer ch_d0 is not equal to the preset channel identification code chid_set, a positive edge counter pre-reset signal counter_p_syn is generated. In dual-edge four-channel mode, and co If `ch_p` equals 2, `syn_det` equals 1, and the data buffer `ch_d0` is not equal to the preset channel identifier `chid_set`, then a positive edge counter pre-reset signal `counter_p_syn` is generated. In single-edge dual-channel mode, if `counter_p` equals 1, `syn_det` equals 1, and the data buffer `ch_d0` is not equal to the preset channel identifier `chid_set`, then a positive edge counter pre-reset signal `counter_p_syn` is generated. In dual-edge dual-channel mode, if `counter_p` equals 0 and `syn_det` equals 1... If the data buffer ch_d0 is not equal to the preset channel identification code chid_set, a positive edge counter pre-reset signal counter_p_syn is generated; the rising edge of counter_p_syn is detected, and a positive edge synchronization reset signal is generated when the rising edge occurs; the negative edge reset generation unit is used to receive the synchronization signal n_syn_det output by the negative edge synchronization detection unit, the control signal generated by the negative edge control signal generation unit, and the negative edge count value counter_n generated by the negative edge channel tracking count unit, and generate a reset signal for the negative edge channel tracking count; when it is a dual-edge four-channel mode, and c If counter_n equals 2, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, then a negative edge counter pre-reset signal counter_n_syn is generated; when it is a dual-edge dual-channel mode, and counter_n equals 0, n_syn_det equals 1, and n_ch_d0 is not equal to the preset channel identification code chid_set, then a negative edge counter pre-reset signal counter_n_syn is generated; the rising edge of counter_n_syn is detected, and a negative edge synchronous reset signal is generated when the rising edge occurs.

7. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The channel tracking counting unit includes: a positive edge channel tracking counting unit and a negative edge channel tracking counting unit; The positive edge channel tracking counter unit is used to generate a positive edge channel tracking count value, counter_p, so that the decoded information can be completely synchronized with the information output by the front end. When the system is powered on, counter_p is set to 0. When a reset signal is received from the positive edge reset generation unit, counter_p is set to the value of ch_d0 to re-track the synchronized channel information. When the control signal is in single-edge four-channel mode, counter_p automatically increments by 1. When the control signal is in dual-edge four-channel mode, if the positive edge master count enable p_en is 1, counter_p automatically increments by 2. If the positive edge master count enable p_en is 0, then counter_p equals the negative edge channel tracking count value counter_n plus 1; when the control signal is in single-edge dual-channel mode, counter_p is limited to 1, and the least significant bit is automatically incremented by 1; when the control signal is in dual-edge dual-channel mode, if the positive edge master count enable p_en is 1, then counter_p is limited to 1, and counter_p equals counter_p; if the positive edge master count enable p_en is 0, then counter_p is limited to 1, and counter_p equals counter_n plus 1. The negative edge channel tracking counter unit is used to generate the negative edge channel tracking counter value counter_n, so that the decoded information can be completely synchronized with the information output by the front end. When the system is powered on, counter_n is set to 1. When a reset signal is received from the negative edge reset generation unit, counter_n is set to the value of n_ch_d0 to re-track the synchronization channel information. When the control signal is in dual-edge four-channel mode, if the negative edge main count enable n_en is 1, counter_n is automatically incremented by 2. If the negative edge main count enable n_en is 0, counter_n is equal to the positive edge channel tracking counter value counter_p plus 1. When the control signal is in dual-edge dual-channel mode, if the negative edge main count enable n_en is 1, counter_n is limited to 1, and counter_n is equal to counter_n. If the negative edge main count enable n_en is 0, counter_n is limited to 1, and counter_n is equal to counter_p plus 1.

8. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The channel prediction unit includes: a channel positive edge prediction unit and a channel negative edge prediction unit; The channel positive edge prediction unit is used to make a positive edge channel data prediction based on the positive edge channel tracking count information; in the next cycle after the positive edge channel reset signal is generated, the sampled data of each positive edge channel is cleared to 0; when counter_p equals x, then chx_d0 equals itu_d0, where x takes the natural number 0-3; The channel negative edge prediction unit is used to make a prediction of the channel data of the negative edge based on the information of the negative edge channel tracking count; in the next cycle after the negative edge channel reset signal is generated, the sampled data of each negative edge channel is cleared to 0; when counter_n is equal to x, then n_chx_d0 is equal to n_itu_d0, and x takes the natural number 0-3.

9. The multi-segment channel decoding and tracking device according to claim 1, characterized in that, The channel decision output unit outputs the corresponding multi-segment channel decoding tracking signal based on the control signal generated by the control signal generation unit. Specifically, this includes: When the control signal is in dual-edge four-channel mode, if p_judge_en equals 1, then the output data ch0_out of channel 0 equals n_ch0_d0, the output data ch1_out of channel 1 equals ch1_d0, the output data ch2_out of channel 2 equals n_ch2_d0, and the output data ch3_out of channel 3 equals ch3_d0. If p_judge_en equals 0, then the output data ch0_out of channel 0 equals ch0_d0, the output data ch1_out of channel 1 equals n_ch1_d0, the output data ch2_out of channel 2 equals ch2_d0, and the output data ch3_out of channel 3 equals n_ch3_d0. When the control signal is in dual-edge, two-channel mode, if p_judge_en equals 1, then the output data ch0_out of channel 0 equals n_ch0_d0, and the output data ch1_out of channel 1 equals ch1_d0. If p_judge_en equals 0, then the output data ch0_out of channel 0 equals ch0_d0, and the output data ch1_out of channel 1 equals n_ch1_d0. In this mode, the outputs of channels 2 and 3 are 0. When the control signal is in single-edge four-channel mode, the output data ch0_out of channel 0 is equal to ch0_d0, the output data ch1_out of channel 1 is equal to ch1_d0, the output data ch2_out of channel 2 is equal to ch2_d0, and the output data ch3_out of channel 3 is equal to ch3_d0. When the control signal is in single-edge dual-channel mode, the output data ch0_out of channel 0 is equal to ch0_d0, the output data ch1_out of channel 1 is equal to ch1_d0, and the outputs of channels 2 and 3 are 0. When the control signal is in single-channel mode, the output of strobe channel 0 is equal to itu_date1, and ordinary ITU decoding processing is performed; all other channels output 0.

10. A display terminal, characterized in that, include: The multi-segment channel decoding and tracking device according to any one of claims 1-9.

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