Access method, device, chip, electronic equipment and storage medium

Abstract

An access method, device, chip, electronic equipment and storage medium. The access method comprises: in response to receiving a data processing task, generating a data access instruction, the data access instruction comprising a plurality of sub-access instructions corresponding to a plurality of target function modules in a plurality of function modules respectively, the physical addresses of the plurality of sub-access instructions corresponding to the plurality of target function modules respectively; obtaining distance information of a data processing module and the plurality of target function modules on an interconnection module; determining the priority of the plurality of sub-access instructions according to the distance information, wherein the priority of the plurality of sub-access instructions is used to determine the forwarding order of the plurality of sub-access instructions when a conflict occurs in the transmission of the data packets corresponding to the plurality of sub-access instructions in the interconnection module. The method can shorten the transmission time of the data packets corresponding to the distant sub-access instructions, thereby shortening the overall transmission time, reducing the bottleneck, and effectively shortening the delay.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an access method for a data processing module, an access method for a chip, an access device for a data processing module, a chip, an electronic device, and a computer-readable storage medium. Background Technology

[0002] A System-on-Chip (SoC) chip, also known as a system-level chip, is a circuit that implements the signal acquisition, storage, processing, and input / output (I / O) functions of a system on a single chip. An SoC chip may include a processor core, interconnect devices, memory, and input / output (I / O) interfaces. The interconnect devices are used to connect the various functional components within the SoC chip to enable data transfer between different functional components. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an access method for a data processing module, wherein the data processing module is interconnected with multiple functional modules via an interconnect module. The method includes: generating a data access instruction, wherein the data access instruction includes multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of the multiple sub-access instructions respectively correspond to the multiple target functional modules; obtaining distance information between the data processing module and the multiple target functional modules on the interconnect module; and determining the priority of the multiple sub-access instructions based on the distance information, wherein the priority of the multiple sub-access instructions is used to enable the interconnect module to determine the forwarding order when data packets corresponding to the multiple sub-access instructions collide during transmission in the interconnect module.

[0004] For example, obtaining the distance information between the data processing module and the plurality of target functional modules on the interconnect module includes: obtaining the plurality of target functional modules and their location information based on the correspondence between the physical addresses of the plurality of sub-access instructions and the plurality of target functional modules; and obtaining the distance information between the data processing module and the plurality of target functional modules on the interconnect module based on the location of the data processing module and the location information of the plurality of target functional modules.

[0005] For example, in an access method provided in an embodiment of this disclosure, the distance information between the data processing module and each of the target functional modules is determined based on the number of data transmission units on the transmission path between the data processing module and each of the target functional modules in the interconnection module, wherein the data transmission unit is at least used for buffering data packets.

[0006] For example, in an embodiment of the access method provided in this disclosure, the plurality of target functional modules include a first target functional module and a second target functional module. The distance between the data processing module and the first target functional module is a first distance, and the distance between the data processing module and the second target functional module is a second distance. The access of the data processing module to the first target functional module is a first sub-access instruction, and the access of the data processing module to the second target functional module is a second sub-access instruction. The priority of the plurality of sub-access instructions is determined according to the distance information, including: when the first distance is greater than the second distance, configuring the priority of the first sub-access instruction to be higher than the priority of the second sub-access instruction.

[0007] For example, in an access method provided in one embodiment of this disclosure, the priority includes a first priority and a second priority, wherein the first priority is higher than the second priority; determining the priority of the plurality of sub-access instructions based on the distance information includes: for each of the plurality of target functional modules, if the distance between the data processing module and the target functional module on the interconnect module is within a first distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the first priority; if the distance between the data processing module and the target functional module on the interconnect module is within a second distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the second priority, wherein the minimum distance included in the first distance range is greater than or equal to the maximum distance included in the second distance range.

[0008] At least one embodiment of this disclosure provides a method for accessing a chip, wherein the chip includes at least one data processing module, multiple functional modules, and an interconnect module. The at least one data processing module is interconnected with the multiple functional modules through the interconnect module. The method includes: each data processing module generating a data access instruction, wherein the data access instruction includes multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of the multiple sub-access instructions respectively correspond to the multiple target functional modules; for each data processing module, obtaining distance information between the data processing module and the multiple target functional modules on the interconnect module; for each data processing module, determining the priority of the multiple sub-access instructions generated by the data processing module based on the distance information; and the interconnect module determining the forwarding order when data packets corresponding to the multiple sub-access instructions collide during transmission in the interconnect module based on the priority of the multiple sub-access instructions.

[0009] For example, in an access method provided in one embodiment of this disclosure, the chip includes multiple data processing modules, which access the multiple functional modules through the interconnect module; the multiple functional modules include multiple storage modules.

[0010] For example, in an embodiment of the present disclosure, the method for obtaining distance information between the data processing module and the plurality of target functional modules on the interconnect module includes: obtaining the plurality of target functional modules and their location information based on the correspondence between the physical addresses of the plurality of sub-access instructions and the plurality of target functional modules; and obtaining distance information between the data processing module and the plurality of target functional modules on the interconnect module based on the location of the data processing module and the location information of the plurality of target functional modules.

[0011] For example, in an embodiment of the access method provided in this disclosure, the interconnect module includes a data transmission unit, which is at least used for buffering data packets; obtaining distance information between the data processing module and the plurality of target functional modules on the interconnect module includes: for each of the plurality of target functional modules, obtaining the number of data transmission units on the transmission path between the target functional module and the data processing module on the interconnect module; and determining the distance information between the target functional module and the data processing module based on the number of data transmission units.

[0012] For example, in an embodiment of the access method provided in this disclosure, the interconnection module further includes a plurality of forwarding units, each of which is used to forward data packets, and at least two adjacent forwarding units among the plurality of forwarding units are provided with the data transmission unit; the transmission path includes a first transmission path from the data processing module to the target functional module and a second transmission path from the target functional module to the data processing module, and the number of data transmission units on the transmission path includes the sum of the number of data transmission units between the first forwarding unit and the last forwarding unit on the first transmission path and the number of data transmission units between the first forwarding unit and the last forwarding unit on the second transmission path.

[0013] For example, in an access method provided in an embodiment of this disclosure, the plurality of target functional modules include a first target functional module and a second target functional module, the at least one data processing module includes a first data processing module, the distance between the first data processing module and the first target functional module is a first distance, and the distance between the first data processing module and the second target functional module is a second distance; the access of the first data processing module to the first target functional module is a first sub-access instruction, and the access of the first data processing module to the second target functional module is a second sub-access instruction; the priority of the plurality of sub-access instructions generated by the data processing module is determined according to the distance information, including: when the first distance is greater than the second distance, configuring the priority of the first sub-access instruction to be higher than the priority of the second sub-access instruction.

[0014] For example, in an access method provided in one embodiment of this disclosure, the priority includes a first priority and a second priority, wherein the first priority is higher than the second priority; determining the priority of the plurality of sub-access instructions generated by the data processing module according to the distance information includes: for each of the plurality of target functional modules, if the distance between the data processing module and the target functional module on the interconnection module is within a first distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the first priority; if the distance between the data processing module and the target functional module on the interconnection module is within a second distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the second priority, wherein the minimum distance included in the first distance range is greater than or equal to the maximum distance included in the second distance range.

[0015] For example, in an access method provided in an embodiment of this disclosure, determining the priority of the plurality of sub-access instructions generated by the data processing module based on the distance information includes: determining the priority of the plurality of sub-access instructions from a preset plurality of priorities based on the distance information; the method further includes: adjusting the number of the preset plurality of priorities based on the number of the at least one data processing module and / or the plurality of functional modules.

[0016] For example, in an access method provided in one embodiment of this disclosure, the number of the at least one data processing module and / or the plurality of functional modules is positively correlated with the number of the preset plurality of priorities.

[0017] For example, in an access method provided in an embodiment of this disclosure, the priority includes a first priority and a second priority, wherein the first priority is higher than the second priority; the plurality of sub-access instructions include a first sub-access instruction having the first priority and a second sub-access instruction having the second priority; the interconnection module includes a plurality of forwarding units, each of the forwarding units being used to forward data packets, and the plurality of forwarding units including a first forwarding unit; determining the forwarding order when data packets corresponding to the plurality of sub-access instructions conflict during transmission in the interconnection module based on the priority of the plurality of sub-access instructions includes: when the data packets to be forwarded by the first forwarding unit of the interconnection module include the data packets corresponding to the first sub-access instruction and the data packets corresponding to the second sub-access instruction, the first forwarding unit is made to prioritize forwarding the data packets corresponding to the first sub-access instruction.

[0018] At least one embodiment of this disclosure provides an access device for a data processing module, the data processing module being interconnected with multiple functional modules via an interconnection module. The access device includes an instruction generation unit, a distance acquisition unit, and a priority determination unit. The instruction generation unit is configured to generate data access instructions, wherein the data access instructions include multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of the multiple sub-access instructions respectively correspond to the multiple target functional modules. The distance acquisition unit is configured to acquire distance information between the data processing module and the multiple target functional modules on the interconnection module. The priority determination unit is configured to determine the priority of the multiple sub-access instructions based on the distance information, wherein the priority of the multiple sub-access instructions is used to enable the interconnection module to determine the forwarding order when data packets corresponding to the multiple sub-access instructions collide during transmission in the interconnection module.

[0019] At least one embodiment of this disclosure provides a chip, including: a plurality of functional modules, an interconnect module, and at least one data processing module. The at least one data processing module is configured to interconnect with the plurality of functional modules through the interconnect module. Each data processing module is configured to: generate a data access instruction, wherein the data access instruction includes a plurality of sub-access instructions corresponding to a plurality of target functional modules, and the physical addresses of the plurality of sub-access instructions respectively correspond to the plurality of target functional modules; obtain distance information between the data processing module and the plurality of target functional modules on the interconnect module; determine the priority of the plurality of sub-access instructions generated by the data processing module based on the distance information; and the interconnect module is configured to determine the forwarding order of data packets corresponding to the plurality of sub-access instructions during transmission in the interconnect module when conflicts occur, based on the priority of the plurality of sub-access instructions.

[0020] At least one embodiment of this disclosure provides an electronic device, including a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the access method provided in any embodiment of this disclosure.

[0021] At least one embodiment of this disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, can implement the access method provided in any embodiment of this disclosure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 A schematic diagram of a chip is shown;

[0024] Figure 2 A flowchart is shown illustrating an access method for a data processing module provided in at least one embodiment of this disclosure;

[0025] Figure 3 A flowchart illustrating the generation of data access instructions provided in at least one embodiment of this disclosure is shown;

[0026] Figure 4 A schematic diagram of a transmission path provided in at least one embodiment of this disclosure is shown;

[0027] Figure 5 A flowchart of a chip access method provided in at least one embodiment of the present disclosure is shown;

[0028] Figure 6 A schematic diagram of access using a mesh structure interconnection provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 7 A schematic block diagram of an access device for a data processing module provided in at least one embodiment of the present disclosure is shown;

[0030] Figure 8 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;

[0031] Figure 9 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown; and

[0032] Figure 10A schematic diagram of a computer-readable storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] Figure 1 A schematic diagram of a chip is shown, such as... Figure 1As shown, the chip may include processor cores C1 to C4 and storage modules (hereinafter also referred to as memory) D1 to D4. Processor cores may include, for example, CPU (Central Processing Unit) cores, GPU (Graphics Processing Unit) cores, etc. Storage modules may include, for example, DDR (Double Data Rate) memory, High Bandwidth Memory (HBM), Static Random-Access Memory (SRAM), and on-chip registers, etc. The chip may also include interconnect modules, such as NOC (Network On Chip). Processor cores C1-C4 and storage modules D1-D4 can be connected to the interconnect module. The interconnect module can include multiple forwarding units, such as units 101a, 101b, and 101c. Each forwarding unit can include a router. Processor cores C1-C4 and storage modules D1-D4 can be connected to the router within the forwarding unit. Access between processor cores C1-C4 and storage modules D1-D4 can be achieved through the forwarding operations of each forwarding unit. Each access processed by the interconnect device corresponds to an access initiator and an access responder. The access initiator can be called the master, and the access responder can be called the slave.

[0036] Chips can employ distributed memory. To fully utilize the total bandwidth of distributed memory, data can be evenly distributed and stored across multiple memory locations. When each processor core receives a data processing task, it needs to access multiple memory locations through the interconnect module to obtain the data to be processed or other data used to complete the data processing task. This significantly increases the load on the interconnect module, resulting in substantial latency.

[0037] At least one embodiment of this disclosure provides an access method for a data processing module, an access method for a chip, an access device for a data processing module, a chip, an electronic device, and a computer-readable storage medium. The data processing module is interconnected with multiple functional modules via an interconnect module. The access method for the data processing module includes: generating a data access instruction in response to receiving a data processing task; the data access instruction including multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, the physical addresses of the multiple sub-access instructions corresponding to the multiple target functional modules respectively; obtaining distance information between the data processing module and the multiple target functional modules on the interconnect module; and determining the priority of the multiple sub-access instructions based on the distance information, wherein the priority of the multiple sub-access instructions is used to enable the interconnect module to determine the forwarding order when data packets corresponding to the multiple sub-access instructions collide during transmission in the interconnect module.

[0038] Without using the access method provided in the embodiments of this disclosure, in a scenario where the data processing module accesses multiple target functional modules within the same time period, the greater the transmission distance between the data processing module and the target functional modules, the greater the transmission delay of the data packets transmitted between the data processing module and the target functional modules on the interconnect module. Although the data processing module will receive the data fed back by the nearby target functional modules earlier, for the overall transmission, the longer the time for the distant target functional modules to receive and send data will increase the overall time for the data processing module to acquire data.

[0039] The access method of this disclosure assigns priority to sub-access instructions based on the distance between the data processing module and the target functional module on the interconnection module. This allows the interconnection module to use distance as a reference condition for forwarding data packets of sub-access instructions when forwarding them, thus shortening the overall time for the data processing module to acquire data. For example, assigning a higher priority to sub-access instructions that are farther away can shorten the transmission time of the data packets corresponding to those instructions, thereby reducing the overall transmission time, mitigating bottlenecks, and effectively reducing latency.

[0040] In at least one embodiment of this disclosure, a data processing module is interconnected with multiple functional modules via an interconnection module. The data processing module may be a processor core, such as a CPU core or a GPU core. The functional modules may be storage modules, such as DDR memory. Furthermore, the functional modules may be other types of modules besides storage modules capable of data interaction with the data processing module. In some embodiments, the multiple functional modules may be modules with the same function, such as multiple DDR memories. In other embodiments, the multiple functional modules may be modules with different functions.

[0041] For example, the interconnect module can be an interconnect device with a structure such as a mesh or ring structure, such as an NOC, or other devices capable of interconnection.

[0042] Figure 2 A flowchart is shown of an access method for a data processing module provided in at least one embodiment of this disclosure.

[0043] like Figure 2 As shown, the method may include steps S210 to S230.

[0044] Step S210: Generate data access instructions. These data access instructions include multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of these multiple sub-access instructions correspond to the multiple target functional modules respectively.

[0045] Step S220: Obtain the distance information between the data processing module and multiple target functional modules on the interconnection module.

[0046] Step S230: Determine the priority of multiple sub-access instructions based on the distance information. The priority of these multiple sub-access instructions is used by the interconnect module to determine the forwarding order of data packets corresponding to each of the multiple sub-access instructions in case of conflicts during transmission within the interconnect module.

[0047] For example, in some of the following embodiments, the data processing module is a processor core, the functional module is a storage module (hereinafter also referred to as memory), and the interconnect device is a NOC.

[0048] For example, the access method used by the data processing module can be executed by the data processing module itself, or by other modules connected to the data processing module.

[0049] For example, in step S210, the data processing module can receive a data processing task and generate a data access instruction in response to receiving the data processing task. The data processing task can be, for example, an algorithm calculation task or a graphics processing task. After receiving the data processing task, it is necessary to first obtain the data to be processed or other data used to complete the data processing task, and then execute the data processing task based on the obtained data. Therefore, after the data processing module receives the data processing task, it can generate a data access instruction for accessing at least some of the multiple storage modules to read data from those modules.

[0050] For example, in other embodiments, after the data processing module completes the data processing task and obtains the processing result data, the data processing module may also generate a data access instruction. In this case, the generated data access instruction may be used to write the processing result data into at least some of the multiple storage modules.

[0051] For example, these multiple target functional modules are the functional modules corresponding to the physical addresses that the data processing module wants to access; that is, the physical addresses that the data processing module wants to access are included in the address range of these multiple target functional modules. These multiple target functional modules can be all or some of the multiple functional modules, depending on the physical addresses that the data processing module wants to access. Figure 1 As shown, the data processing module is, for example, Figure 1 The processor core C1 shown has multiple functional modules, such as... Figure 1 The storage modules D1 to D4 are shown. The physical addresses that the processor core C1 wants to access correspond to storage modules D1 and D2. For example, if the data that the processor core C1 wants to read is stored in storage modules D1 and D2, then storage modules D1 and D2 can be used as target functional modules.

[0052] For example, the data access instructions generated by the data processing module include multiple sub-access instructions corresponding to the multiple target functional modules, and the physical addresses of these multiple sub-access instructions are respectively located within the address range of the multiple target functional modules. Continuing with the above example, the data access instructions may include a first sub-access instruction corresponding to storage module D1 and a second sub-access instruction corresponding to storage module D2. The physical address of the first sub-access instruction is located within the address range of storage module D1, for accessing storage module D1. The physical address of the second sub-access instruction is located within the address range of storage module D2, for accessing storage module D2.

[0053] For example, in step S220, the distance information between the data processing module and each target functional module on the interconnection module can be obtained. This distance information is used to reflect the distance between the data processing module and the target functional module on the interconnection module.

[0054] For example, the data processing module can send the request data packets and their priority information corresponding to each sub-access instruction to the interconnecting device, so that the interconnecting device can forward the request data packets to the corresponding target functional module. For example, following the above example, the interconnecting device can forward the request data packet corresponding to the first sub-access instruction to the storage module D1, and forward the request data packet corresponding to the second sub-access instruction to the storage module D2. After receiving the request data packet corresponding to the first sub-access instruction, the storage module D1 can obtain the physical address to be accessed by parsing the data packet, read the data at the corresponding physical address, package the read data into a feedback data packet, and send the feedback data packet back to the data processing module through the interconnecting device. The storage module D2 does the same. In some other embodiments, if the first sub-access instruction sent by the data processing module is to store the processing result data in the storage module D1, the storage module D1 can obtain the processing result data and the storage address by parsing the data packet, write the processing result data to the corresponding storage address, and generate corresponding feedback information in the case of successful or failed writing. Based on the feedback information, a feedback data packet is formed and sent back to the data processing module through the interconnecting device to provide feedback on the result of the write operation to the data processing module.

[0055] For example, in step S230, the priorities of multiple sub-access instructions can be determined based on distance information. For instance, a higher priority can be set for sub-access instructions corresponding to target functional modules that are farther from the data processing module, and a lower priority can be set for sub-access instructions corresponding to target functional modules that are closer to the data processing module. Continuing with the above example, if the transmission distance between storage module D1 and processor core C1 on the interconnect device is greater than the transmission distance between storage module D2 and processor core C1 on the interconnect device, then the first sub-access instruction can have a higher priority than the second sub-access instruction. The priority of the sub-access instructions can be a QoS (Quality of Service) priority.

[0056] For example, based on the priority of multiple sub-access instructions, the interconnect module can determine the forwarding order when data packets corresponding to these sub-access instructions conflict during transmission within the interconnect module. A conflict between any two sub-access instructions during transmission within the interconnect module can be understood as a data packet to be forwarded by a forwarding unit in the interconnect module containing both sub-access instructions. For instance, data packets for two sub-access instructions might be input into the same forwarding unit through different input ports, and both sub-access instructions need to be processed by the same forwarding unit. The interconnect module can prioritize forwarding the data packet corresponding to the sub-access instruction with the higher priority. Continuing with the example above, if the first sub-access instruction has a higher priority than the second sub-access instruction, and a conflict occurs between the first and second sub-access instructions during transmission within the interconnect device, the data packet corresponding to the first sub-access instruction can be forwarded first, followed by the data packet corresponding to the second sub-access instruction.

[0057] For example, the data packet corresponding to the sub-access instruction may include a first data packet (such as the access data packet mentioned above) sent by the data processing module to the target functional module and / or a second data packet (such as the feedback data packet mentioned above) sent by the target functional module to the data processing module.

[0058] Without using the access method provided in the embodiments of this disclosure, in a scenario where the data processing module accesses multiple target functional modules simultaneously within the same time period, the greater the transmission distance between the data processing module and the target functional modules, the greater the transmission delay of the data packets transmitted between the data processing module and the target functional modules on the interconnect module. Although the data processing module will receive the data fed back by the nearby target functional modules earlier, for the overall transmission, the longer the time for the distant target functional modules to receive and send data will increase the overall time for the data processing module to acquire data.

[0059] The access method of this disclosure assigns priority to sub-access instructions based on the distance between the data processing module and the target functional module on the interconnect module. This allows the interconnect module to use distance as a reference condition for forwarding data packets of sub-access instructions when forwarding them, thus shortening the overall time for the data processing module to acquire data. For example, assigning a higher priority to sub-access instructions that are farther away can shorten the transmission time of the data packets corresponding to those instructions, thereby reducing the overall transmission time, mitigating bottlenecks, and effectively reducing latency.

[0060] Figure 3 A flowchart illustrating the generation of data access instructions provided in at least one embodiment of this disclosure is shown. For example... Figure 3 As shown, step S210 includes steps S211 to S213.

[0061] Step S211: Obtain the multiple virtual addresses to be accessed.

[0062] Step S212: Based on the pre-stored address translation information, convert multiple virtual addresses into multiple physical addresses corresponding to multiple target functional modules.

[0063] Step S213: Generate data access instructions based on multiple physical addresses.

[0064] For example, obtaining distance information between the data processing module and multiple target functional modules on the interconnect module includes: obtaining multiple target functional modules and their location information based on the correspondence between the physical addresses of multiple sub-access instructions and multiple target functional modules; and obtaining distance information between the data processing module and multiple target functional modules on the interconnect module based on the location information of the data processing module and the location information of the multiple target functional modules.

[0065] For example, when the functional module is memory (storage module), to fully utilize the distributed total memory bandwidth, data can be evenly distributed across various memory locations by means of hardware and software collaboration, distributing data corresponding to consecutive virtual addresses across multiple memory locations. This scenario can be called a UMA (unified memory access) scenario. In this scenario, the data processing module accesses virtual addresses, but since the data at consecutive virtual addresses is scattered across multiple memory locations, the data processing module actually needs to access multiple memory locations. General-purpose programmable processor architectures have hardware capable of mapping virtual addresses to physical addresses.

[0066] For example, address translation information can be pre-stored, recording the conversion relationship between virtual addresses and physical addresses. This virtual-to-physical address correspondence can be, for example, one-to-one. When generating data access instructions, the virtual address to be accessed can be determined first, and then converted to a physical address using the address translation information. Based on the physical address, the corresponding target functional module can be obtained, and then data access instructions for the target functional module can be generated based on the physical address to be accessed. Continuing with the above example, the virtual addresses to be accessed by processor core C1 are a1 to a100. The corresponding physical addresses are distributed across memory modules D1 and D2. For example, virtual addresses a1 to a100 correspond to physical addresses b1 to b50 and e1 to e50 in memory module D1. Through address translation, a first sub-access instruction and a second sub-access instruction for physical addresses b1 to b50 can be generated.

[0067] For example, in step S220, the distance information between the data processing module and the multiple target functional modules on the interconnect module can be obtained based on the location of the data processing module and the multiple physical addresses corresponding to the multiple target functional modules. For example, by performing coordinate calculations on the physical addresses corresponding to the multiple target functional modules and the location of the data processing module itself, the distance information between the data processing module and the multiple target functional modules can be obtained. This distance information is the physical distance on the interconnect module.

[0068] For example, the interconnect module includes multiple forwarding units, each of which is used to forward data packets. These forwarding units may include, for example, [missing information - likely related to data packet forwarding]. Figure 1 The forwarding units 101a, 101b, 101c, etc., are shown. For example, each forwarding unit 101 may include multiple sets of ports, some of which can be used to connect to functional devices such as computer cores and memory, while the rest can be used to connect to other forwarding units. For example, forwarding unit 101c may include at least three sets of ports, one set of which can be used to connect to memory module D1, another set of which can be used to connect to forwarding unit 101b, and yet another set of which can be used to connect to forwarding unit 101e. Furthermore, some ports of forwarding unit 101c can be used to connect to functional devices other than computer cores C1-C4 and memory modules D1-D4, while the remaining ports of forwarding unit 101b can be connected to forwarding units 101a, 101c, and 101d respectively. Each forwarding unit can receive data packets sent by the functional devices connected to it and forward the data packets to other forwarding units or other functional devices connected to it. Each forwarding unit can also receive data packets sent by other forwarding units connected to it and forward the data packets to other forwarding units or functional devices connected to it.

[0069] For example, the interconnect module may also include a data transmission unit, which can be a buffer, such as a pipeline buffer. The data transmission unit can be located between any two adjacent forwarding units, or between at least two adjacent forwarding units; for example, one or more data transmission units can be located between two adjacent forwarding units. The data transmission unit can be used as a buffer to buffer data packets to control the timing of data packets transmitted between two adjacent forwarding units. Furthermore, a data transmission unit can also be located between a forwarding unit and the functional devices connected to it.

[0070] For example, a forwarding unit may include an arbitrator, and arbitrators can be connected to each other via a data transmission unit. A NOC may include a node structure, but a node structure is not a necessary structure for an interconnection form. For example, a crossbar does not have a node structure. In interconnection modules without a node structure, arbitrators can be used to implement the node structure, such as in a mesh NOC.

[0071] For example, the distance information between the data processing module and each target functional module can be determined based on the number of data transmission units along the transmission path between the data processing module and each target functional module in the interconnection module. For example, refer to Figure 1 The transmission path between processor core C1 and memory module D1 on the interconnect module is, for example, forwarding unit 101a—forwarding unit 101b—forwarding unit 101c. Data transmission units can be configured between forwarding units 101a and 101b and / or between forwarding units 101b and 101c. These data transmission units can serve as data transmission units on the transmission path between processor core C1 and memory module D1 on the interconnect module. The distance information of the sub-access instructions between processor core C1 and memory module D1 can be determined based on the number of data transmission units on the transmission path between processor core C1 and memory module D1 on the interconnect module. Since data transmission units are used to buffer data packets and significantly affect data packet transmission latency, the distance information determined by the number of data transmission units on the transmission path can accurately reflect the distance.

[0072] For example, in some embodiments, the number of data transmission units may refer to the number of data transmission units, i.e., the number of each data transmission unit is counted as 1.

[0073] In other embodiments, the number of data transmission units may refer to the number of weights for each data transmission unit, i.e., the number after considering the delay weights of different data transmission units. For example, in some examples, if the delay of a certain data transmission unit (e.g., the first data transmission unit) is less than or equal to a delay threshold, then the weight of that data transmission unit can be counted as 1. If the delay of a certain data transmission unit (e.g., the second data transmission unit) is greater than the delay threshold, then the weight of that data transmission unit can be counted as a value greater than 1, such as 1, 1.5, or 2, etc. This value can be a preset fixed value or determined based on the degree to which the delay threshold is exceeded. In other examples, the weight of a data transmission unit can be determined based on the ratio of its delay to the delay threshold. For example, if the delay of the first data transmission unit is 0.8 times the delay threshold, then the weight of the second data transmission unit can be counted as 0.8. If the delay of the second data transmission unit is twice the delay threshold, then the weight of the second data transmission unit can be counted as 2.

[0074] For example, in other embodiments, in addition to determining the distance information by the number of data transmission units on the transmission path, the number of data transmission units can be combined with other parameters to jointly determine the distance information. Other parameters may include, for example, the number of forwarding units on the transmission path.

[0075] For example, the transmission path includes a first transmission path from the data processing module to the target functional module and a second transmission path from the target functional module to the data processing module. The distance between the data transmission module and the target functional module includes the sum of the distances corresponding to the first and second transmission paths. The number of data transmission units on the transmission path can include the sum of the number of data transmission units between the first and last forwarding units on the first transmission path and the number of data transmission units between the first and last forwarding units on the second transmission path. The multiple forwarding units traversed by the first and second transmission paths can be the same or different.

[0076] Figure 4 A schematic diagram of a transmission path provided by at least one embodiment of this disclosure is shown. For example... Figure 4 As shown, C1~CN represent N data processing modules (N is an integer greater than 1), D1 represents one of the multiple target function modules, "pipe" represents the data transmission unit (pipe is short for pipeline), and "others" can represent other modules besides the data processing modules that have an interactive relationship with the target function module D1.

[0077] Figure 4The example shown is for illustrative purposes only. There can be multiple target functional modules. The following explanation uses data processing module C1 and target functional module D1 as examples. In the interconnect module, the transmission path between data processing module C1 and target functional module D1 includes a request path (i.e., the first transmission path) from data processing module C1 to target functional module D1 and a feedback path (i.e., the second transmission path) from target functional module D1 to data processing module C1. The request path is used to send the request data packet corresponding to the sub-access instruction of data processing module C1 to target functional module D1, and the feedback path is used to send the feedback data packet of target functional module D1 to data processing module C1. The first transmission path may include multiple forwarding units and data transmission units. The first forwarding unit through which the request data packet passes is, for example, unit 301, and the last forwarding unit is, for example, unit 302. The number of data transmission units between unit 301 and unit 302 on the first transmission path is determined and denoted as the first number. Similarly, the number of data transmission units between the first and last forwarding units on the second transmission path is determined and denoted as the second number. The sum of the first and second numbers can be used as the number of data transmission units on the transmission path between the data processing module C1 and the target function module D1.

[0078] For example, each forwarding unit may include one or more arbitrators, which can be used to determine the forwarding order based on the priority of the packets to be forwarded, thus determining which packet is processed first. The number of data transmission units on the transmission path can also be the sum of the number of data transmission units between the first and last arbitrators on the first transmission path and the number of data transmission units between the first and last arbitrators on the second transmission path.

[0079] For example, multiple target functional modules include a first target functional module and a second target functional module. The distance between the data processing module and the first target functional module is a first distance, and the distance between the data processing module and the second target functional module is a second distance. Access to the first target functional module by the data processing module is a first sub-access instruction, and access to the second target functional module by the data processing module is a second sub-access instruction. If the first distance is greater than the second distance, the priority of the first sub-access instruction is determined to be higher than the priority of the second sub-access instruction.

[0080] For example, the data processing module is Figure 1 The processor core C1 shown has the following first target functional module: Figure 1 The storage module D1 shown, the second target function module is Figure 1The storage module D2 is shown. The number of data transmission units on the transmission path between processor core C1 and storage module D1 is m1, which is the first distance mentioned above. The number of data transmission units on the transmission path between processor core C1 and storage module D2 is m2, which is the second distance mentioned above. If m1 is greater than m2, the priority of the first sub-access instruction corresponding to storage module D1 can be higher than the priority of the second sub-access instruction corresponding to storage module D2. Based on this method, the transmission time of data packets corresponding to more distant sub-access instructions can be shortened, thereby shortening the overall transmission time, reducing bottlenecks, and effectively reducing latency.

[0081] For example, in some embodiments, different priorities can be set for multiple sub-access instructions issued by the data processing module. For instance, each sub-access instruction can be assigned a priority from high to low based on its distance from farthest to closest.

[0082] For example, in some embodiments, if the number of sub-access instructions is large, setting different priorities for each sub-access instruction would result in a large number of priorities, which would increase the workload of the interconnecting device to some extent and reduce efficiency. Therefore, a predetermined number of priorities can be set, for example, two priorities can be preset: a first priority and a second priority, with the first priority being higher than the second priority. Alternatively, three priorities can be preset: a first priority, a second priority, and a third priority (priority from high to low). In step S230, the priority of multiple sub-access instructions can be determined from the preset multiple priorities based on distance information. In this case, when the number of multiple sub-access instructions is greater than the number of priorities, some of the multiple sub-access instructions may have the same priority.

[0083] For example, when the priority includes the first priority and the second priority mentioned above, for each of the multiple target functional modules, if the distance between the data processing module and the target functional module on the interconnection module is within the first distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the first priority; if the distance between the data processing module and the target functional module on the interconnection module is within the second distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the second priority, wherein the minimum distance included in the first distance range is greater than or equal to the maximum distance included in the second distance range.

[0084] For example, the number of distance ranges can be the same as the number of priorities, and the boundary values ​​(e.g., maximum and minimum values) of the distance ranges (such as the first and second distance ranges mentioned above) can also be determined based on the distance information of multiple sub-access instructions. For example, taking two preset priorities as an example, two consecutive distance ranges can be set accordingly. The first distance range can be, for example, greater than or equal to a distance threshold, and the second distance range can be, for example, greater than 0 and less than the distance threshold. The distance threshold can be, for example, the average or median of multiple distances corresponding to multiple sub-access instructions. That is, if the distance corresponding to a sub-access instruction is less than the distance threshold, the priority of the sub-access instruction can be the lower second priority; if the distance corresponding to a sub-access instruction is greater than or equal to the distance threshold, the priority of the sub-access instruction can be the higher first priority. By grouping multiple sub-access instructions according to distance using distance ranges, and the sub-access instructions in each group have the same priority, priority allocation of sub-access instructions is achieved when the number of priorities is limited.

[0085] For example, in some examples, the number of preset priorities can be adjusted based on the number of the at least one data processing module and / or multiple functional modules. The number of the at least one data processing module and / or multiple functional modules can be positively correlated with the number of preset priorities. The number of the at least one data processing module and / or multiple functional modules can be the number of the at least one data processing module, the number of multiple functional modules, or the total number of data processing modules and multiple functional modules.

[0086] For example, the number of at least one data processing module and / or multiple functional modules affects bandwidth requirements. A larger number of these modules indicates a greater bandwidth demand and a higher number of data packets that the interconnect modules need to process. By adaptively adjusting the number of priority modules, a balance can be achieved between transmission efficiency and fine-grained processing to adapt to various scenarios. When the number of these modules is large, the number of priorities can be reduced, for example, from an initial three priorities to two, which can reduce the workload of the interconnect modules and improve efficiency to some extent. Conversely, when the number of these modules is small, the number of priorities can be increased, for example, from an initial three priorities to four priorities, which can achieve a more precise transmission order and further ensure that long-distance sub-access instructions are transmitted first.

[0087] This disclosure also provides a method for accessing a chip, the chip including at least one data processing module, multiple functional modules and an interconnect module, wherein the at least one data processing module is interconnected with the multiple functional modules through the interconnect module.

[0088] Figure 5 A flowchart of a chip access method provided by at least one embodiment of the present disclosure is shown.

[0089] like Figure 5 As shown, the method includes steps S410 to S440.

[0090] Step S410: Each data processing module generates a data access instruction. This data access instruction includes multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of these multiple sub-access instructions correspond to the multiple target functional modules respectively.

[0091] Step S420: For each data processing module, obtain the distance information between the data processing module and the plurality of target functional modules on the interconnection module.

[0092] Step S430: For each data processing module, determine the priority of the multiple sub-access instructions generated by the data processing module based on the distance information.

[0093] Step S440: The interconnect module determines the forwarding order of the data packets corresponding to the multiple sub-access instructions when conflicts occur during transmission in the interconnect module, based on the priority of the multiple sub-access instructions.

[0094] For example, the chip includes multiple data processing modules that access multiple functional modules through the interconnect module. These multiple functional modules include multiple storage modules.

[0095] For example, refer to Figure 1The chip includes processor cores C1 to C4, each of which can function as a data processing module. The chip also includes storage modules D1 to D4, each of which can function as a functional module. The chip may further include a task allocation unit, which can, for example, allocate data processing tasks to each of the processor cores C1 to C4. After receiving a data processing task, each of the processor cores C1 to C4 can execute the access method described above for the data processing module to obtain data from the corresponding target storage module (target functional module). Specifically, each of the processor cores C1 to C4 can perform operations such as generating data access instructions, obtaining distance information between the data processing module and multiple target functional modules on the interconnect module, and determining the priority of multiple sub-access instructions based on the distance information. For details, please refer to the above-described embodiments regarding the access method for the data processing module, which will not be repeated here. In other embodiments, after the data processing module completes its data processing task and obtains the processing result data, the above-described access method for the data processing module can also be executed to store the processing result data in the corresponding target storage module (target functional module).

[0096] For example, the physical addresses that each data processing module wants to access may be the same or different. Therefore, the target functional modules corresponding to each data processing module may be the same or different.

[0097] For example, in a UMA scenario, when multiple data processing modules access multiple corresponding target functional modules within the same time period, congestion can easily occur in the interconnection module if the access method provided in this embodiment is not used. The greater the transmission distance between the data processing module and the target functional module, the greater the transmission delay of data packets between the data processing module and the target functional module on the interconnection module. Although the data processing module will receive the data fed back by the nearby target functional module earlier, the overall transmission time will increase because the target functional module at a greater distance takes longer to receive and send data. The access method in this embodiment assigns priority to sub-access instructions for each data processing module based on the distance between the data processing module and the target functional module on the interconnection module. In this way, when the interconnection module forwards the data packets of the sub-access instructions, the distance is used as a reference condition for the forwarding order, which helps to shorten the overall time for each data processing module to obtain data. For example, if a higher priority is set for the sub-access instructions that are farther away, the transmission time of the data packets corresponding to the more distant sub-access instructions can be shortened, thereby shortening the overall transmission time, reducing bottlenecks, and effectively shortening the delay.

[0098] For example, in step S410, generating a data access instruction may include: obtaining multiple virtual addresses to be accessed; converting the multiple virtual addresses into multiple physical addresses corresponding to the multiple target functional modules based on pre-stored address translation information; and generating the data access instruction based on the multiple physical addresses. For example, each data processing module converts the virtual addresses it needs to access into corresponding physical addresses, and generates sub-access instructions corresponding to the multiple target functional modules based on the physical addresses. Obtaining the distance information between the data processing module and the multiple target functional modules on the interconnect module may include: obtaining the multiple target functional modules and their location information based on the correspondence between the physical addresses of the multiple sub-access instructions and the multiple target functional modules; and obtaining the distance information between the data processing module and the multiple target functional modules on the interconnect module based on the location information of the data processing module and the multiple target functional modules.

[0099] For example, the interconnect module includes a data transmission unit, which is at least used for buffering data packets to meet the timing requirements of long-distance transmission. In step S420, for each of the plurality of target functional modules, the number of data transmission units on the transmission path between the target functional module and the data processing module on the interconnect module is obtained; based on the number of data transmission units, the distance information between the target functional module and the data processing module is determined. The data transmission unit can be a buffer, such as a pipeline.

[0100] For example, the interconnect module also includes multiple forwarding units, each of which is used to forward data packets. At least two adjacent forwarding units are connected by the data transmission unit. The transmission path includes a first transmission path from the data processing module to the target functional module and a second transmission path from the target functional module to the data processing module. The number of data transmission units on the transmission path includes: the number of data transmission units between the first and last forwarding units on the first transmission path and / or the number of data transmission units between the first and last forwarding units on the second transmission path.

[0101] For example, the plurality of target functional modules may include a first target functional module and a second target functional module, and the at least one data processing module includes a first data processing module. The distance between the first data processing module and the first target functional module is a first distance, and the distance between the first data processing module and the second target functional module is a second distance. Access to the first target functional module by the first data processing module is a first sub-access instruction, and access to the second target functional module by the first data processing module is a second sub-access instruction. If the first distance is greater than the second distance, the priority of the first sub-access instruction is configured to be higher than the priority of the second sub-access instruction.

[0102] For example, the priority includes a first priority and a second priority, where the first priority is higher than the second priority. In step S440, for each of the plurality of target functional modules, if the distance between the data processing module and the target functional module on the interconnect module is within a first distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the first priority; if the distance between the data processing module and the target functional module on the interconnect module is within a second distance range, then the priority of the sub-access instruction corresponding to the target functional module is determined as the second priority, wherein the minimum distance included in the first distance range is greater than or equal to the maximum distance included in the second distance range.

[0103] For example, in step S430, the priority of the plurality of sub-access instructions is determined from a plurality of preset priorities based on the distance information. The method may further include adjusting the number of the plurality of preset priorities based on the load of the interconnect module.

[0104] For example, the load of the interconnect module is positively correlated with the number of preset priorities.

[0105] For example, the priority includes a first priority and a second priority, where the first priority is higher than the second priority; the multiple sub-access instructions include a first sub-access instruction with the first priority and a second sub-access instruction with the second priority. The interconnect module includes multiple forwarding units, each used to forward data packets, and the multiple forwarding units include a first forwarding unit. In step S440, when the data packets to be forwarded by the first forwarding unit include both the data packet corresponding to the first sub-access instruction and the data packet corresponding to the second sub-access instruction, the first forwarding unit prioritizes forwarding the data packet corresponding to the first sub-access instruction. That is, when the data packet corresponding to the first sub-access instruction and the data packet corresponding to the second sub-access instruction are both waiting for forwarding by the first forwarding unit, the data packet corresponding to the first sub-access instruction with the higher priority is forwarded first, and then the data packet corresponding to the second access instruction is forwarded.

[0106] The specific implementation and technical effects of this chip access method can be found in the above description of the access method for the data processing module, and will not be repeated here.

[0107] Figure 6 A schematic diagram of access using a Mesh structure interconnection provided by at least one embodiment of this disclosure is shown.

[0108] like Figure 6 As shown, each of C00, C10, C01, and C11 can be a data processing module, and each of D00, D10, D01, and D11 can be a functional module. Each forwarding unit can connect to one or more data processing modules and / or one or more functional modules. For example, forwarding unit node0 is connected to data processing modules C00 and C10 and functional modules D00 and D10, and forwarding unit node1 is connected to data processing modules C01 and C11 and functional modules D01 and D11. When a data processing module accesses a functional module connected to its unit through an interconnection module, the QoS (Quality of Service) priority of the sub-access instruction can be, for example, QoS0. When the access initiator accesses a functional module connected to another forwarding unit through an interconnection module, the priority level of the sub-access instruction can be, for example, QoS1, where QoS1 has a higher priority than QoS0. Figure 6 As shown in sections (a) and (b), when data processing module C00 accesses D00 or D10, the priority level of the sub-access instruction can be, for example, QoS0. Figure 6 As shown in sections (c) and (d), when the data processing module C00 accesses D01 or D11, the priority level of the sub-access instruction can be, for example, QoS1, which has a higher priority than QoS0.

[0109] In the access method of this disclosure embodiment, the data processing module identifies the distance between the target functional module represented by the physical address and its relative location, and adds a corresponding QoS priority to the sub-access instruction corresponding to the target functional module, so that access from a greater distance can obtain a higher routing priority, reduce the probability of being blocked by other traffic, and achieve the effects of bandwidth improvement, latency reduction, and reduction of bottlenecks.

[0110] In the access method of this embodiment, the data processing module, as the memory access initiator, is physically unequal to each distributed target functional module, and the path lengths on the interconnection modules are different. Accessing the remote end will incur more latency and arbitration costs. Considering the characteristics of UMA scenario access, the probability of memory access is the same regardless of distance. Therefore, a high-priority QoS is added to memory accesses that are farther away to increase the probability of successful arbitration with other data packets (e.g., low-priority data).

[0111] In the access method of this disclosure embodiment, the priority quantity can be dynamically adjusted according to the data traffic requirements of different application scenarios, so as to achieve a balance between transmission efficiency and fine processing, and adapt to the needs of various scenarios.

[0112] For example, as described above regarding the functions of the data processing module and the interconnection module, the interconnection module can use the priority in the data access command as the priority of its corresponding response to send the data or operation response back to the data processing module. If the priority setting of the interconnection module's response is the responsibility of the target functional module, then the operations described above regarding determining distance information and determining priority will be performed by the target functional module.

[0113] Figure 7 A schematic block diagram of an access device 500 for a data processing module provided in at least one embodiment of the present disclosure is shown.

[0114] For example, such as Figure 7 As shown, the access device 500 includes an instruction generation unit 510, a distance acquisition unit 520, and a priority determination unit 530. These components are interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, these modules can be implemented as hardware (e.g., circuit) modules, software modules, or any combination of both, as is the case in the following embodiments, and will not be repeated here. For example, these units can be implemented using a central processing unit (CPU), a graphics processing unit (GPU), a tensor processor (TPU), a field-programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, along with corresponding computer instructions. It should be noted that... Figure 7 The components and structure of the access device 500 shown are merely exemplary and not limiting; the access device 500 may also have other components and structures as needed.

[0115] The instruction generation unit 510 is configured to generate data access instructions, wherein the data access instructions include multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of the multiple sub-access instructions respectively correspond to the multiple target functional modules. The instruction generation unit 510 can, for example, execute... Figure 2 Step S210 is described.

[0116] The distance acquisition unit 520 is configured to acquire distance information between the data processing module and the plurality of target functional modules on the interconnection module. The instruction generation unit 520, for example, can execute... Figure 2 Step S220 is described.

[0117] The priority determination unit 530 is configured to determine the priority of the plurality of sub-access instructions based on the distance information. The priority of the plurality of sub-access instructions is used by the interconnect module to determine the forwarding order of data packets corresponding to the plurality of sub-access instructions in case of conflicts during transmission within the interconnect module. For example, the priority determination unit 530 can execute... Figure 2 Step S230 is described.

[0118] For example, the data processing module may also include an interconnection interface unit, which serves as an interface for interfacing with the interconnection module.

[0119] For example, the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 can be hardware, software, firmware, or any feasible combination thereof. For example, the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 can be dedicated or general-purpose circuits, chips, or devices, or they can be a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the above-mentioned units.

[0120] For example, the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 may include code and programs stored in memory; the processor may execute the code and programs to implement some or all of the functions of the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 as described above. For example, the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 may be dedicated hardware devices used to implement some or all of the functions of the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 as described above. For example, the instruction generation unit 510, the distance acquisition unit 520, and the priority determination unit 530 may be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In the embodiments of this disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) processor-executable firmware stored in memory.

[0121] It should be noted that in the embodiments of this disclosure, each unit of the access device 500 corresponds to each step of the aforementioned access method. For the specific functions of the access device 500, please refer to the relevant description of the access method, which will not be repeated here. Figure 7The components and structure of the access device 500 shown are exemplary and not limiting. The access device 500 may include other components and structures as needed. The access device 500 may include more or fewer circuits or units, and the connection relationships between the various circuits or units are not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited; it may be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0122] This disclosure also provides a chip comprising multiple functional modules, an interconnect module, and at least one data processing module. The at least one data processing module is configured to interconnect with the multiple functional modules via the interconnect module. Each data processing module is configured to: generate a data access instruction, wherein the data access instruction includes multiple sub-access instructions corresponding to multiple target functional modules among the multiple functional modules, and the physical addresses of the multiple sub-access instructions respectively correspond to the multiple target functional modules; obtain distance information between the data processing module and the multiple target functional modules on the interconnect module; and determine the priority of the multiple sub-access instructions generated by the data processing module based on the distance information. The interconnect module is configured to determine the forwarding order of data packets corresponding to the multiple sub-access instructions during transmission in the interconnect module in the event of a conflict, based on the priority of the multiple sub-access instructions.

[0123] For details on the technical implementation and effects of this chip, please refer to the above description of the access method, which will not be repeated here.

[0124] At least one embodiment of this disclosure also provides an electronic device including a processor and a memory, the memory storing one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the access methods described above.

[0125] Figure 8 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. For example... Figure 8 As shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 610 is used to execute the non-transitory computer-readable instructions, which, when executed by the processor 610, perform one or more steps of the access method described above. The memory 620 and the processor 610 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For specific implementations and explanations of the various steps of the access method, please refer to the embodiments of the access method described above; repetitions will not be repeated here.

[0126] It should be noted that Figure 8 The components of the electronic device 600 shown are merely exemplary and not limiting. The electronic device 600 may have other components as needed for the actual application.

[0127] For example, the processor 610 and the memory 620 can communicate with each other directly or indirectly.

[0128] For example, processor 610 and memory 620 can communicate via a network. The network may include a wired network. Processor 610 and memory 620 can also communicate with each other via a system bus; this disclosure is not limiting in this regard.

[0129] For example, the processor 610 and memory 620 can be located on the server side (or in the cloud).

[0130] For example, processor 610 can control other components in electronic device 600 to perform desired functions. For example, processor 610 can be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an x86 or ARM architecture. Processor 610 can be a general-purpose processor or a special-purpose processor, and can control other components in electronic device 600 to perform desired functions.

[0131] For example, memory 620 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or an on-chip register file. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 610 may run one or more computer program modules to implement various functions of electronic device 600. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0132] For example, in some embodiments, the electronic device 600 can be a mobile phone, tablet computer, electronic paper, television, monitor, laptop computer, digital photo frame, navigator, wearable electronic device, smart home device, etc.

[0133] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 600 can be referred to the description of the access method above, and will not be repeated here.

[0134] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 700 is, for example, suitable for implementing the access method provided in the embodiments of the present disclosure. The electronic device 700 may be a terminal device, etc. It should be noted that... Figure 9 The illustrated electronic device 700 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments of this disclosure.

[0135] like Figure 9 As shown, the electronic device 700 may include a processing unit (e.g., a central processing unit, a graphics processor, etc.) 710, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 720 or a program loaded from a storage device 780 into a random access memory (RAM) 730. The RAM 730 also stores various programs and data required for the operation of the electronic device 700. The processing unit 710, the ROM 720, and the RAM 730 are interconnected via a bus 740. An input / output (I / O) interface 750 is also connected to the bus 740.

[0136] Typically, the following devices can be connected to the I / O interface 750: input devices 760 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 770 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 780 including, for example, magnetic tape, hard disk, etc.; and communication devices 790. The communication device 790 allows the electronic device 700 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 9 An electronic device 700 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 700 may alternatively implement or have more or fewer devices.

[0137] For example, according to embodiments of this disclosure, the access method described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the access method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 790, or installed from a storage device 780, or installed from a ROM 720. When the computer program is executed by the processing device 710, the functions defined in the access method provided by embodiments of this disclosure can be implemented.

[0138] At least one embodiment of this disclosure also provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, enable the access method described above.

[0139] Figure 10 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 10 As shown, the storage medium 800 stores non-transitory computer-readable instructions 810. For example, when the non-transitory computer-readable instructions 810 are executed by a computer, one or more steps in the access method described above are performed.

[0140] For example, the storage medium 800 can be used in the aforementioned electronic device 600. For example, the storage medium 800 can be... Figure 8 The memory 620 in the illustrated electronic device 600. For example, a description of the storage medium 800 can be found here. Figure 8 The corresponding description of the memory 620 in the illustrated electronic device 600 will not be repeated here.

[0141] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0142] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0143] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0144] The following points should be noted regarding this disclosure:

[0145] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0146] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0147] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An access method for a data processing module, wherein, The data processing module is interconnected with a plurality of functional modules through an interconnection module, and the method comprises: generating a data access instruction, wherein the data access instruction comprises a plurality of sub-access instructions corresponding to a plurality of target functional modules in the plurality of functional modules respectively, and the physical addresses of the plurality of sub-access instructions correspond to the plurality of target functional modules respectively; obtaining distance information of the data processing module and the plurality of target functional modules on the interconnection module respectively; determining the priority of the plurality of sub-access instructions according to the distance information, wherein the priority of the plurality of sub-access instructions is used to make the interconnection module determine the forwarding order when a conflict occurs in the transmission of data packets corresponding to the plurality of sub-access instructions in the interconnection module, wherein the plurality of target functional modules at least include a first target functional module and a second target functional module, the plurality of sub-access instructions include a first sub-access instruction corresponding to the first target functional module and a second sub-access instruction corresponding to the second target functional module, the transmission distance of the data processing module and the first target functional module on the interconnection module is greater than the transmission distance of the data processing module and the second target functional module on the interconnection module, and the priority of the first sub-access instruction is higher than the priority of the second sub-access instruction.

2. The method of claim 1, wherein, Obtaining distance information of the data processing module and the plurality of target functional modules on the interconnection module respectively comprises: obtaining the plurality of target functional modules and the position information of the plurality of target functional modules according to the correspondence between the physical addresses of the plurality of sub-access instructions and the plurality of target functional modules; obtaining the distance information of the data processing module and the plurality of target functional modules on the interconnection module respectively according to the position of the data processing module and the position information of the plurality of target functional modules.

3. The method of claim 1, wherein the distance information of the data processing module and each of the target functional modules is determined according to the number of data transport units on the transmission path of the data processing module and each of the target functional modules in the interconnection module, wherein the data transport units are at least used for buffering the transported data packets.

4. The method according to any one of claims 1 to 3, wherein, Determining the priority of the plurality of sub-access instructions according to the distance information comprises: setting different priorities for the plurality of sub-access instructions respectively, wherein the priority of the sub-access instruction with a longer transmission distance is higher.

5. The method according to any one of claims 1-3, wherein, The priority includes a first priority and a second priority, and the first priority is higher than the second priority. Determining the priority of the plurality of sub-access instructions according to the distance information comprises, for each of the plurality of target functional modules, if the distance of the data processing module and the target functional module on the interconnection module belongs to a first distance range, the priority of the sub-access instruction corresponding to the target functional module is determined as the first priority. If the distance between the data processing module and the target function module on the interconnection module belongs to a second distance range, the priority of the sub-access instruction corresponding to the target function module is determined as the second priority, wherein the first distance range contains a minimum distance greater than or equal to a maximum distance contained in the second distance range.

6. An access method for a chip, wherein, The chip includes at least one data processing module, a plurality of function modules, and an interconnection module. The at least one data processing module is interconnected with the plurality of function modules through the interconnection module. The method includes: Each data processing module generates a data access instruction, wherein the data access instruction includes a plurality of sub-access instructions corresponding to a plurality of target function modules in the plurality of function modules, respectively, and the physical addresses of the plurality of sub-access instructions correspond to the plurality of target function modules, respectively. For each data processing module, distance information between the data processing module and the plurality of target function modules on the interconnection module is obtained. For each data processing module, the priority of the plurality of sub-access instructions generated by the data processing module is determined according to the distance information. The interconnection module determines the forwarding order when the plurality of sub-access instructions corresponding to the plurality of data packets respectively occur conflict in the process of transmission in the interconnection module based on the priority of the plurality of sub-access instructions, Wherein the plurality of target function modules at least include a first target function module and a second target function module, the plurality of sub-access instructions include a first sub-access instruction corresponding to the first target function module and a second sub-access instruction corresponding to the second target function module, the transmission distance between the data processing module and the first target function module on the interconnection module is greater than the transmission distance between the data processing module and the second target function module on the interconnection module, and the priority of the first sub-access instruction is higher than the priority of the second sub-access instruction.

7. The method of claim 6, wherein, The chip includes a plurality of data processing modules, and the plurality of data processing modules access the plurality of function modules through the interconnection module. The plurality of function modules include a plurality of storage modules.

8. The method of claim 6, wherein The distance information between the data processing module and the plurality of target function modules on the interconnection module is obtained, including: According to the correspondence between the physical addresses of the plurality of sub-access instructions and the plurality of target function modules, the plurality of target function modules and the position information of the plurality of target function modules are obtained. The distance information between the data processing module and the plurality of target function modules on the interconnection module is obtained according to the position of the data processing module and the position information of the plurality of target function modules, respectively.

9. The method of claim 6, wherein, The interconnection module includes a data delivery unit, and the data delivery unit is used at least for buffering data packets. The distance information between the data processing module and the plurality of target function modules on the interconnection module is obtained, including: for each of the plurality of target function modules, acquiring a quantity of data transport units on a transmission path of the target function module and the data processing module on the interconnection module; determining distance information of the target function module and the data processing module according to the quantity of data transport units.

10. The method of claim 9, wherein, The interconnection module further comprises a plurality of forwarding units, each of which is configured to forward a data packet, and at least two adjacent forwarding units in the plurality of forwarding units are provided with the data transport unit; The transmission path comprises a first transmission path from the data processing module to the target function module and a second transmission path from the target function module to the data processing module, The quantity of data transport units on the transmission path comprises the sum of the quantity of data transport units between the first forwarding unit and the last forwarding unit on the first transmission path and the quantity of data transport units between the first forwarding unit and the last forwarding unit on the second transmission path.

11. The method according to any one of claims 6-10, wherein, According to the distance information, the priority of the plurality of sub-access instructions is determined, comprising: different priorities are set for the plurality of sub-access instructions, wherein the priority of the sub-access instruction with a longer transmission distance is higher.

12. The method according to any one of claims 6-10, wherein, The priority comprises a first priority and a second priority, and the first priority is higher than the second priority. According to the distance information, the priority of the plurality of sub-access instructions generated by the data processing module is determined, comprising: if the distance between the data processing module and the target function module on the interconnection module belongs to a first distance range, the priority of the sub-access instruction corresponding to the target function module is determined as the first priority; if the distance between the data processing module and the target function module on the interconnection module belongs to a second distance range, the priority of the sub-access instruction corresponding to the target function module is determined as the second priority, wherein the minimum distance contained in the first distance range is greater than or equal to the maximum distance contained in the second distance range.

13. The method of any one of claims 6-10, wherein, According to the distance information, the priority of the plurality of sub-access instructions generated by the data processing module is determined, comprising: according to the distance information, determining the priority of the plurality of sub-access instructions from a plurality of preset priorities; The method further comprises: adjusting the quantity of the plurality of preset priorities according to the quantity of the at least one data processing module and / or the plurality of function modules.

14. The method of claim 13, wherein, The quantity of the at least one data processing module and / or the plurality of function modules is positively correlated with the quantity of the plurality of preset priorities.

15. The method according to any one of claims 6-10, wherein, The priority comprises a first priority and a second priority, and the first priority is higher than the second priority; the plurality of sub-access instructions comprises a first sub-access instruction with the first priority and a second sub-access instruction with the second priority; The interconnection module comprises a plurality of forwarding units, each of which is configured to forward a data packet, and the plurality of forwarding units comprises a first forwarding unit; The priority of the plurality of sub-access instructions is determined based on the priority of the plurality of sub-access instructions, and the forwarding order of the data packets corresponding to the plurality of sub-access instructions when a conflict occurs in the transmission of the data packets in the interconnection module is determined, including: in the case that the data packets to be forwarded by the first forwarding unit of the interconnection module include the data packet corresponding to the first sub-access instruction and the data packet corresponding to the second sub-access instruction, the first forwarding unit is caused to preferentially forward the data packet corresponding to the first sub-access instruction.

16. An access device for a data processing module, the data processing module being interconnected with a plurality of functional modules through an interconnection module, the access device comprising: an instruction generation unit configured to generate a data access instruction, wherein the data access instruction comprises a plurality of sub-access instructions corresponding to a plurality of target functional modules in the plurality of functional modules respectively, and physical addresses of the plurality of sub-access instructions correspond to the plurality of target functional modules respectively; a distance acquisition unit configured to acquire distance information of the data processing module and the plurality of target functional modules on the interconnection module respectively; a priority determination unit configured to determine priorities of the plurality of sub-access instructions according to the distance information, wherein the priorities of the plurality of sub-access instructions are used to cause the interconnection module to determine a forwarding order of data packets corresponding to the plurality of sub-access instructions when a conflict occurs in the transmission of the data packets in the interconnection module, wherein the plurality of target functional modules at least include a first target functional module and a second target functional module, the plurality of sub-access instructions include a first sub-access instruction corresponding to the first target functional module and a second sub-access instruction corresponding to the second target functional module, a transmission distance of the data processing module and the first target functional module on the interconnection module is greater than a transmission distance of the data processing module and the second target functional module on the interconnection module, and the priority of the first sub-access instruction is higher than the priority of the second sub-access instruction.

17. A chip, comprising: a plurality of functional modules; an interconnection module, and at least one data processing module configured to be interconnected with the plurality of functional modules through the interconnection module; wherein each of the data processing modules is configured to: generate a data access instruction, wherein the data access instruction comprises a plurality of sub-access instructions corresponding to a plurality of target functional modules in the plurality of functional modules respectively, and physical addresses of the plurality of sub-access instructions correspond to the plurality of target functional modules respectively; acquire distance information of the data processing module and the plurality of target functional modules on the interconnection module respectively; determine priorities of the plurality of sub-access instructions generated by the data processing module according to the distance information; the interconnection module is configured to determine a forwarding order of data packets corresponding to the plurality of sub-access instructions when a conflict occurs in the transmission of the data packets in the interconnection module based on the priorities of the plurality of sub-access instructions, The plurality of target function modules at least include a first target function module and a second target function module, the plurality of sub-access instructions include a first sub-access instruction corresponding to the first target function module and a second sub-access instruction corresponding to the second target function module, a transmission distance of the data processing module and the first target function module on the interconnection module is greater than a transmission distance of the data processing module and the second target function module on the interconnection module, and a priority of the first sub-access instruction is higher than a priority of the second sub-access instruction. 18.An electronic device, comprising: a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the access method of any one of claims 1-15. 19.A computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the access method of any one of claims 1-15.

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