Methods, systems, and computer program products for modifying a layout for an IC

Abstract

A method of modifying a layout for an integrated circuit (IC) includes selecting a circuit region to be scaled in the layout, setting a fixed region including a fixed component in the selected circuit region, and scaling the selected circuit region without scaling the fixed region including the fixed component to obtain a modified layout for the IC. Embodiments of the present application also relate to a system and a computer program product for modifying a layout for an IC.

Description

Technical Field

[0001] Embodiments of this application relate to methods, systems, and computer program products for modifying the layout of an IC. Background Technology

[0002] Integrated circuits (ICs) typically comprise many semiconductor devices represented in an IC layout (or layout). An IC layout is generated from an IC schematic, such as an electrical diagram of the IC. Throughout the various steps of the IC design process, from the IC schematic to the IC layout used for actual IC manufacturing, various checks, tests, and / or layout modifications are performed to ensure the IC can be manufactured as designed and will function optimally. Summary of the Invention

[0003] Some embodiments of this application provide a method for modifying the layout for an integrated circuit (IC), the method comprising: selecting a circuit region to be scaled in the layout; setting a fixed region including a fixed component in the selected circuit region; and scaling the selected circuit region without scaling the fixed region including the fixed component to obtain a modified layout for the IC.

[0004] Further embodiments of this application provide a system for modifying a layout for an integrated circuit (IC), the system comprising: a processor; and a non-transitory computer-readable storage medium connected to the processor, wherein the processor is configured to execute instructions stored on the computer-readable storage medium to: select a circuit region to be scaled along a first direction in the layout; disconnect a first conductive pattern extending in a second direction transverse to the first direction and across the boundary of the selected circuit region into an inner portion of the selected circuit region and an outer portion outside the selected circuit region; scale the selected circuit region along the first direction; and reconnect the inner and outer portions of the scaled circuit region in response to at least one of: a first determination that the inner and outer portions of the scaled circuit region are electrically disconnected from each other, or a second determination that at least one of the inner or outer portions of the scaled circuit region fails verification.

[0005] Other embodiments of this application provide a computer program product including a non-transitory, computer-readable medium containing instructions that, when executed by a processor, cause the processor to: select a circuit region to be scaled along a first direction in a layout for an integrated circuit (IC), wherein the selected circuit region includes: a device having a plurality of gate patterns arranged along the first direction at a first gate pattern spacing, a first conductive pattern extending along the first direction, a second conductive pattern extending along a second direction transverse to the first direction, and a via; scaling the selected circuit region along the first direction to obtain a modified layout without changing the gate pattern widths of the plurality of gate patterns, wherein the scaling includes: implementing a repositioning of the device having the plurality of gate patterns arranged along the first direction at a second gate pattern spacing, the second gate pattern spacing being different from the first gate pattern spacing; rearranging one or more of the second conductive pattern and the via along the first direction based on a scaling factor as a ratio of the second gate pattern spacing to the first gate pattern spacing; and adjusting the size of one or more of the first conductive patterns along the first direction based on the scaling factor. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 It is a functional flowchart of at least a portion of the IC design flow according to some embodiments.

[0008] Figure 2A This is a schematic diagram of an IC layout having various circuit regions according to some embodiments.

[0009] Figures 2B to 2C A schematic diagram of circuit regions of an IC layout at several stages of various scaling operations, according to some embodiments.

[0010] Figure 2D This is a schematic cross-sectional view of an IC according to some embodiments.

[0011] Figures 3A to 3B This includes schematic diagrams of the IC layout in various scaling operations with push areas according to some embodiments.

[0012] Figure 4 This includes a schematic diagram of the IC layout during scaling operations according to some embodiments.

[0013] Figure 5This includes schematic diagrams of IC layouts during disconnect, scaling, and reconnection operations according to some embodiments.

[0014] Figure 6 This includes schematic diagrams of IC layouts in scaling operations with fixed regions, according to some embodiments.

[0015] Figure 7 This is a schematic diagram of a circuit region of an IC layout in a disconnection operation with one or more fixed components, according to some embodiments.

[0016] Figures 8A to 8B These are flowcharts of various methods according to some embodiments.

[0017] Figure 9 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0018] Figure 10 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. Other components, values, operations, materials, arrangements, etc., are conceivable. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] In integrated circuit (IC) design, the IC design is provided by the circuit designer. The IC layout is generated based on the design, for example, through placement and routing operations. Various checks and / or simulations are performed on the generated layout. When one or more of the checks or simulations indicate one or more yield and / or performance issues, the layout is modified. In some cases, the layout is modified by enlarging (or expanding) or shrinking (or shrinking) one or more regions within the layout.

[0022] In at least one embodiment, the process of scaling up or down a region in an IC layout includes one or more operations before and / or after scaling the region. In some embodiments, a region associated with, within, or overlapping the region to be scaled is designated as a fixed region. Such a fixed region does not scale or move when the region is scaled. In some embodiments, a region associated with but outside the region to be scaled is designated as a push region. Such a push region will push or move a distance and / or push or move in a direction corresponding to the scaling operation. In some embodiments, one or more conductive patterns entering and / or leaving the region to be scaled (i.e., crossing the boundary of the region) are disconnected along the boundary of the region. After scaling, the disconnected conductive patterns are reconnected, for example, by a rerouting operation. In some embodiments, the rerouting operation includes adding additional wiring components (e.g., conductive patterns and / or vias) and / or modifying and / or rearranging one or more existing wiring components. In at least one embodiment, one or more of the described operations are omitted. In at least one embodiment, a combination of one or more of the described operations is performed in a layout modification process. In at least one embodiment, one or more or all of the described operations are automatically implemented by at least one processor.

[0023] In at least one embodiment, the described operation makes it possible to modify the IC layout by simultaneously scaling down another area of ​​the layout while enlarging one area and / or scaling down different areas of the layout by different scaling factors. Therefore, in one or more embodiments, it is possible to implement non-uniform scaling of the IC layout, whereby individual areas of the IC layout are scaled individually to provide a modified layout under which the IC can be manufactured as designed and will function optimally.

[0024] Figure 1 This is a functional flowchart of at least a portion of an IC design flow 100 according to some embodiments. Prior to IC fabrication, the design flow 100 utilizes one or more electronic design automation (EDA) tools for testing the IC design. In some embodiments, the EDA tool is a set of one or more executable instructions executed by a processor or controller or programming computer to implement the indicated functions. In at least one embodiment, the IC design flow 100 is described herein with respect to… Figures 9 to 10 The design room implementation of the IC manufacturing system is discussed.

[0025] In operation 110, the IC design is provided by a circuit designer. In some embodiments, the IC design includes an IC schematic, i.e., an electrical diagram of the IC. In some embodiments, the schematic is generated or provided in the form of a schematic netlist, such as a SPICE (Simulation Programming Interface) netlist with integrated circuit focus. Other data formats for describing the design are available in some embodiments.

[0026] In operation 120, a pre-layout simulation of the design is performed, for example, using an EDA tool, to determine whether the design meets predetermined specifications. If the design does not meet the predetermined specifications, the IC is redesigned. In some embodiments, SPICE simulation is performed on a SPICE netlist. In other embodiments, other simulation tools are available instead of or in addition to SPICE simulation.

[0027] In operation 130, a layout (or layout diagram) of the IC is generated based on the design. The IC layout diagram includes the physical locations of the individual circuit elements (or devices) of the IC and the physical locations of the individual networks and vias of the interconnecting circuit elements. In some embodiments, the layout is generated by an EDA tool in the form of a Graphical Design System (GDS) file. Other data formats used to describe the layout of the IC are within the scope of the various embodiments.

[0028] In some embodiments, the IC layout is generated in operation 130 by an EDA tool, such as an Automatic Place and Route (APR) tool. The APR tool receives the IC design in a netlist format as described herein and performs placement operations (or placement). For example, cells configured to provide predefined functionality and having a pre-designed layout are stored in one or more cell libraries. The APR tool accesses individual cells from one or more cell libraries and places the cells in an adjacency manner to generate an IC layout corresponding to the IC schematic. Exemplary cells include, but are not limited to, inverters, adders, multipliers, logic gates, phase-locked loops (PLLs), flip-flops, multiplexers, memory cells, etc. Exemplary logic gates include, but are not limited to, AND, OR, NAND, NOR, XOR, NOT, AND-OR-NOT (AOI), OR-NAND-NOT (OAI), multiplexers, flip-flops, buffers, latches, delays, clock cells, etc. In some embodiments, the cells include one or more active or passive circuit elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, and planar MOS transistors with raised source / drain electrodes. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0029] The APR tool then performs a routing operation (or wiring) to interconnect the various nets and vias of the placed circuit elements. Examples of nets include, but are not limited to, conductive pads, conductive patterns, and conductive redistribution layers. The routing operation is performed to ensure that the wiring interconnects satisfy a set of constraints. After the routing operation, the APR tool outputs an IC layout diagram including the placed circuit elements and the nets and vias of the wiring. Nets and vias are generally referred to herein as wiring components. The described APR tool is an example. Other arrangements are within the scope of the various embodiments. For example, in one or more embodiments, one or more of the described operations are omitted.

[0030] In one or more embodiments, a scaling process 135 for locally scaling one or more regions of a layout, as described herein, is implemented in operation 130. In some embodiments, the scaling process 135 is implemented by an APR tool or automatically by the APR tool based on user input.

[0031] In operation 140, a layout-to-schematic (LVS) check is performed. The LVS check ensures that the generated layout corresponds to the design. Specifically, the LVS check tool (i.e., an EDA tool) identifies electrical components and their connections from the pattern of the generated layout. The LVS check tool then generates a layout netlist representing the identified electrical components and connections. The layout netlist generated from the layout is compared by the LVS check tool with the schematic netlist of the design. If the two netlists match within the matching tolerance, the LVS check passes. Otherwise, at least one of the layout or design is corrected by returning the process to operation 110 and / or operation 130. In some embodiments, additional verification processes are available.

[0032] In operation 150, a design rule check (DRC) is performed on the GDS file representing the layout, for example, using an EDA tool, to ensure that the layout meets certain manufacturing design rules, i.e., to ensure the manufacturability of the IC. If one or more design rules are violated, at least one of the layout or design is corrected by returning the process to operation 110 and / or operation 130. Examples of design rules include, but are not limited to, width rules specifying the minimum width of a pattern in the layout, spacing rules specifying the minimum spacing between adjacent patterns in the layout, region rules specifying the minimum area of ​​a pattern in the layout, metal-to-via spacing rules specifying the minimum spacing between a metal pattern and an adjacent via, metal-to-metal spacing rules, polysilicon-to-oxide-defined (PO-to-OD) spacing rules, PO-to-PO spacing rules, etc. In some embodiments, other verification processes are available.

[0033] In operation 160, for example, resistance and capacitance (RC) extraction is performed using EDA tools to determine parasitic parameters of interconnects in the IC layout, such as parasitic resistance and capacitance, for timing simulation in subsequent operations. In some embodiments, other verification processes are available.

[0034] In operation 170, a post-layout simulation is performed by a simulation tool (i.e., an EDA tool) to determine whether the layout meets predetermined specifications, taking into account extracted parasitic parameters. If the simulation indicates that the layout does not meet predetermined specifications, for example, if parasitic parameters cause undesirable delays, at least one of the layout or design is corrected by returning the process to operations 110 and / or 130. Otherwise, the layout is passed to manufacturing or an additional validation process.

[0035] In some embodiments, one or more evaluations, checks, and / or simulations indicate one or more yield and / or performance issues and determine that the layout needs to be modified by scaling up or down one or more regions of the layout. In one example, a post-layout simulation in operation 170 indicates that a region of the layout will be scaled. In a further embodiment, the scaling of a region of the layout is indicated or determined by other operations in the IC design process, and / or by another automated system in the semiconductor device manufacturing process and / or equipment, and / or by the user. When a decision to locally scale at least one region of the layout is generated or received, scaling process 135 is implemented, for example, by an APR tool, to scale at least one region of the layout to obtain a modified layout. The modified layout undergoes one or more checks and / or simulations, for example, as described with respect to operations 140-170. When the modified layout does not meet one or more requirements in operations 140-170, the process returns to operation 130 for further layout modifications, followed by checks and verifications as described herein. In some embodiments, the layout prior to modification and / or the modified layout are stored in a non-transitory computer-readable medium.

[0036] In some embodiments, one or more of the described operations are omitted. In one example, in one or more embodiments, RC extraction in operation 160 and post-layout simulation in operation 170 are omitted. In a further example, in one or more embodiments, pre-layout simulation in operation 120 or post-layout simulation in operation 170 are omitted. In yet another example, initial layout generation in operations 110, 120, and 130 is omitted, and the existing IC layout is loaded into the APR tool and directly subjected to scaling process 135. Other arrangements are within the scope of the various embodiments.

[0037] For simplicity, the various operations and / or determinations herein are described as being implemented by an APR tool. However, in at least one embodiment, one or more of the described operations and / or determinations are implemented outside of the APR tool, for example, by one or more further automated systems, one or more processors, and / or one or more computer systems.

[0038] Figure 2A This is a schematic diagram of an IC layout 200 having various circuit regions according to some embodiments.

[0039] exist Figure 2A In the exemplary configuration, IC layout 200 includes multiple circuit regions 201, 202, 203, 204, and 205. For simplicity, Figure 2A One or more other circuit regions of IC layout 200 are omitted. For example, in one or more embodiments, one or more buffer regions (not shown) are arranged between adjacent circuit regions. Circuit regions 201-205 are arranged in IC layout 200 along the X and Y axes. The Y axis is transverse to the X axis. In some embodiments, the Y axis is perpendicular to the X axis. The X axis is in... Figure 2A The diagram schematically illustrates a direction with an X+ direction and an opposite X- direction. The Y-axis is... Figure 2A The diagram schematically illustrates a Y+ direction and an opposite Y- direction. The described number and / or arrangement of circuit regions in IC layout 200 are examples. Other numbers and / or arrangements of circuit regions in IC layout 200 are within the scope of various embodiments. In some embodiments, the IC corresponding to IC layout 200 includes circuitry corresponding to circuit regions 201-205 formed on the substrate, for example, as per [reference to...]. Figure 2D As described.

[0040] In some embodiments, at least one of circuit regions 201-205 includes cells or groups of cells read from one or more cell libraries, placed in IC layout 200 and routed as described herein. In some embodiments, at least one of circuit regions 201-205 includes intellectual property (IP) blocks. IP blocks include cells or combinations of cells developed by an IC designer (also referred to as an "IP provider"). In some cases, the IP designer is a fabless design studio or design company that designs but does not manufacture IC devices. In some cases, the IP designer is a foundry that designs and manufactures IC devices. IP designers develop individual IP blocks with correspondingly different functions and store the developed IP blocks in an IP library. Different IC designers develop different IP libraries. It is possible that the same component with the same function is developed by different IC designers and corresponds to different IP blocks. Users can reuse and select IP blocks to integrate selected IP blocks into IC devices. It is possible for users to select IP blocks from different IP designers or IP libraries to integrate into IC devices. In some embodiments, at least one of circuit regions 201-205 includes non-IP blocks. Non-IP blocks include cells or combinations of cells that are not retrieved from an IP library. For example, non-IP blocks are constructed from standard cells retrieved from a standard library and / or developed specifically for a particular IC device. Examples of IP blocks and / or non-IP blocks include, but are not limited to, memory, memory control logic, cache, resistor arrays, capacitor arrays, communication interfaces, application programming interfaces (APIs), analog-to-digital (A / D) converters, RF modulators, digital signal processors (DSPs), graphics processing units (GPUs), arithmetic logic units (ALUs), floating-point units (FPUs), central processing units (CPUs), etc. Circuit regions 201-205 are arranged along the X and Y axes in IC layout 200. The X-axis is... Figure 2A The diagram schematically illustrates a direction with an X+ direction and an opposite X- direction. The Y-axis is... Figure 2A The diagram is schematically shown as having a Y+ direction and an opposite Y- direction.

[0041] exist Figure 2A In the exemplary configuration, circuit regions 201 and 202 are determined to be enlarged, circuit regions 203 and 204 are determined to be reduced, and circuit region 205 is not determined to be enlarged or reduced. Figure 2AIn this embodiment, circuit regions 201 and 202 to be enlarged are designated as BLOW UP 1 and BLOW UP 2, circuit regions 203 and 204 to be reduced are designated as SRINK 1 and SRINK 2, and circuit region 205 is designated as UNSCALED. In one or more embodiments, the designations BLOW UP 1, BLOW UP 2, SRINK 1, SRINK 2, and UNSCALED are used for illustrative purposes and are not included in IC layout 200. Whether to enlarge or reduce circuit regions and by how much (e.g., scaling factor) is determined by an automated system and / or by a user (e.g., a layout engineer) based on one or more factors as described herein, including but not limited to evaluation, inspection, simulation of yield and / or performance issues. In some embodiments, at least one of circuit regions 201, 202, 203, and 204 is generated by an automated system, for example, by generating a device having a specific gate pattern pitch as described herein. In at least one embodiment, at least one of the circuit regions 201, 202, 203, 204 is generated by a user, such as a layout engineer, who uses a marker layer or a concrete layer to provide the circuit region.

[0042] Each of the circuit regions 201, 202, 203, and 204 will be scaled along at least one of the X-axis or Y-axis. An example of scaling the circuit region 201 along the X-axis includes keeping edge 206 of circuit region 201 fixed while stretching or moving opposite edge 207 of circuit region 201 along the X+ direction, where the X+ direction is the scaling direction in this example. Another example of scaling the circuit region 201 along the X-axis includes keeping opposite edge 207 of circuit region 201 fixed while stretching or moving edge 206 of circuit region 201 along the X direction, where the X direction is the scaling direction in this example. A further example of scaling the circuit region 201 along the X-axis includes keeping a predetermined reference line 208 of circuit region 201 fixed while correspondingly stretching or moving both edges 206 and 207 of circuit region 201 along the X+ and X- directions, where the X+ and X- directions are the scaling directions in this example.

[0043] In some embodiments, when the relative position of a component or circuit region with respect to a predetermined reference point of the IC layout containing the circuit region remains unchanged, the component or circuit region itself is considered fixed, even after a scaling operation. For example, when the relative position of a component or circuit region 201 with respect to a predetermined reference point 209 of the IC layout 200 remains unchanged, the component of circuit region 201 (e.g., edges 206, 207, or reference line 208, or any other component) or circuit region 201 itself is considered fixed, even after a scaling operation. In at least one embodiment, reference point 209 is the origin of the coordinate system associated with the IC layout 200. Figure 2A In the exemplary configuration, reference point 209 is a corner of IC layout 200, and reference line 208 is the X-axis center line that bisects the width of circuit region 201 along the X-axis. Other reference points and / or reference lines are arranged within the scope of various embodiments.

[0044] In at least one embodiment, circuit region 201 is enlarged along the Y-axis in one or more manners similar to those described regarding the enlargement of circuit region 201 along the X-axis. In at least one embodiment, circuit region 201 is enlarged along both the X-axis and Y-axis. Due to the scaling operation, the size of the circuit region changes. For example, when the circuit region is enlarged or reduced along the X-axis or Y-axis, the width of the circuit region along the X-axis or Y-axis increases or decreases accordingly. The ratio of the size or width of the circuit region after the scaling operation to the size or width of the circuit region before the scaling operation is sometimes referred to as the scaling factor of the scaling operation. Other scaling factors are defined within the scope of the various embodiments. In at least one embodiment, circuit region 201 is enlarged along both the X-axis and Y-axis with the same scaling factor. In at least one embodiment, circuit region 201 is enlarged along the X-axis and Y-axis with different scaling factors.

[0045] Circuit region 202 is scaled along the X-axis and / or Y-axis in one or more manners similar to those described with respect to circuit region 201. In some embodiments, circuit regions 201, 202 are scaled with the same scaling factor and / or scaling direction. In at least one embodiment, circuit regions 201, 202 are scaled with different scaling factors and / or different scaling directions.

[0046] An example of scaling operation for shrinking circuit region 203 along the X-axis includes keeping edge 206' of circuit region 203 fixed while shrinking or moving opposite edge 207' of circuit region 203 along the X- direction, where the X+ direction is the scaling direction in this example. Another example of scaling operation for shrinking circuit region 203 along the X-axis includes keeping opposite edge 207' of circuit region 203 fixed while shrinking or moving edge 206' of circuit region 203 along the X+ direction, where the X- direction is the scaling direction in this example. A further example of scaling operation for shrinking circuit region 203 along the X-axis includes keeping a predetermined reference line 208' (e.g., X-axis centerline) of circuit region 203 fixed while correspondingly shrinking or moving two edges 206', 207' of circuit region 203 along the X+ and X- directions, where the X+ and X- directions are the scaling directions in this example.

[0047] In at least one embodiment, circuit region 203 is scaled along the Y-axis in one or more manners similar to those described regarding scaling circuit region 203 along the X-axis. In at least one embodiment, circuit region 203 is scaled along both the X-axis and Y-axis with the same scaling factor. In at least one embodiment, circuit region 203 is scaled along both the X-axis and Y-axis with different scaling factors.

[0048] Circuit region 204 is scaled down along the X-axis and / or Y-axis in one or more ways similar to those described with respect to circuit region 203. In some embodiments, circuit regions 203 and 204 are scaled down with the same scaling factor and / or scaling direction. In at least one embodiment, circuit regions 203 and 204 are scaled down with different scaling factors and / or scaling directions.

[0049] As described herein, the size of each of circuit regions 201-204 changes after the corresponding scaling operation. Conversely, the size of the unscaled circuit region 205 remains unchanged despite the scaling operation of circuit regions 201-204. In at least one embodiment, the unscaled circuit region 205 remains fixed relative to reference point 209 despite the scaling operation of circuit regions 201-204, as described herein. In at least one embodiment, the unscaled circuit region 205 is moved or pushed along the scaling direction of a scaling operation of another circuit region.

[0050] In some embodiments, during a scaling process (e.g., scaling process 135), a user interface (e.g., a display device of an EDA tool or a screen on a monitor) is displayed to the user. The user interface displays the layout or portion of the layout undergoing the scaling process, while highlighting one or more circuit areas to be scaled. For example, the user interface displays something similar to... Figure 2AThe view is a view in which circuit regions 201-204 are visually presented in a format different from that of other unscaled circuit regions (including unscaled circuit region 205). In a non-limiting example, circuit regions 201 and 202 to be enlarged are displayed in a first color, circuit regions 203 and 204 to be reduced are displayed in a second color different from the first color, and other unscaled circuit regions including unscaled circuit region 205 are displayed in a third color different from the first and second colors. Thus, in one or more embodiments, a user (e.g., a layout engineer) can quickly and / or easily view circuit regions to be enlarged and / or reduced, and provide appropriate user input and / or corrections when prompted and / or requested by an automated system (e.g., an APR tool). The described color scheme as a way to highlight circuit regions to be scaled is an example. Any other schemes with visually different formats are within the scope of the various embodiments. For example, one or more of transparency, blinking or other animations, different shadows, different backgrounds or borders, other visual effects, etc., may be used to highlight and / or visually distinguish circuit regions to be scaled from unscaled circuit regions in the same layout.

[0051] Figure 2B This is a schematic diagram of a circuit region 210 including several stages of an IC layout in amplification operation along the X-axis according to some embodiments. In some embodiments, circuit region 210 corresponds to at least one of circuit regions 201, 202, and / or the IC layout corresponds to IC layout 200. Figure 2B In the top view, the circuit region 210 before scaling is shown; the middle view shows the intermediate circuit region 230 corresponding to the circuit region 210 after scaling and some wiring modifications; and the bottom view shows the modified circuit region 232 corresponding to the intermediate circuit region 230 after further wiring modifications.

[0052] Circuit region 210 includes one or more active regions extending along a first direction (e.g., the X-axis) and one or more gate patterns extending across the one or more active regions and along a second direction (e.g., the Y-axis) transverse to the first direction. For simplicity, in Figure 2BIn the exemplary configuration, circuit region 210 is shown as including an active region 211 and gate patterns 212, 213, 214 extending across the active region 211. The number of active regions and / or gate patterns described and / or shown is exemplary. Other numbers of active regions and / or gate patterns are within the scope of the various embodiments. Active regions are sometimes referred to as oxide-defined (OD) regions and are schematically shown in the figures using the designation "OD". The X-axis is sometimes referred to as the OD direction. Active region 211 in an IC fabricated corresponding to the layout includes P-type dopant and / or N-type dopant. Gate patterns 212-214 in an IC corresponding to the layout include conductive materials, such as polysilicon, and are schematically shown in the figures using the designation "PO". The Y-axis is sometimes referred to as the Poly direction. Other conductive materials (such as metals) used for gate patterns are within the scope of the various embodiments.

[0053] One or more active regions of circuit region 210 and one or more gate patterns together form one or more circuit elements. For simplicity, in Figure 2B In an exemplary configuration, circuit region 210 is shown as including a transistor configured by an active region 211 and a gate pattern 213. Gate pattern 213 corresponds to the gate of the transistor. A region of the active region 211 located on the opposite side of gate pattern 213 corresponds to the source / drain region (not numbered) of the transistor. In some embodiments, at least one of gate patterns 212, 214 corresponds to the gate terminal of another transistor in the layout. In at least one embodiment, at least one of gate patterns 212, 214 corresponds to a dummy gate pattern. Gate pattern 213 is an example of a "functional gate pattern" which, together with the underlying active region, configures the transistor and / or electrically couples it to one or more other circuit elements. Unlike functional gate patterns, dummy gate patterns or non-functional gate patterns are not configured to form a transistor together with the underlying active region, and / or one or more transistors formed by the dummy gate pattern together with the underlying active region are not electrically coupled to other circuit elements. In at least one embodiment, the dummy gate pattern comprises dielectric material in the manufactured IC.

[0054] In circuit region 210, gate patterns, including dummy gate patterns and functional gate patterns, are arranged with a regular gate pattern spacing CPP. The gate pattern spacing CPP is the center-to-center distance along the X-axis between adjacent gate patterns. For example, as... Figure 2BAs shown, the distance along the X-axis between the center line (unnumbered) of gate pattern 212 and the center line (unnumbered) of adjacent gate pattern 213 is the gate pattern pitch CPP. In some embodiments, the circuit region is enlarged by increasing the gate pattern pitch of the gate patterns in the circuit region, and the circuit region is reduced by decreasing the gate pattern pitch of the gate patterns in the circuit region, as described herein. Each gate pattern in circuit region 210 (including functional gate patterns and dummy gate patterns) has a gate pattern width wg, for example, as shown in the figure. Figure 2B The gate pattern 214 is shown in the figure.

[0055] Circuit region 210 also includes a contact structure located above and electrically contacting a corresponding source / drain region in the active region of circuit region 210. The contact structure is sometimes referred to as a metal-to-device structure and is schematically shown in the figures using the designation "MD". In the manufactured IC, the MD contact structure includes a conductive material formed above the corresponding source / drain region in the corresponding active region to define an electrical connection from one or more devices formed in the active region to other circuitry. Exemplary conductive materials for MD contact structures in the manufactured IC include metals. Other materials are within the scope of the various embodiments. Figure 2B In the exemplary configuration, MD contact structures 215 and 216 are located above and electrically contacted with the corresponding source / drain regions in the active region 211. MD contact structures 215 and 216 extend along the Y-axis. MD contact structures and gate patterns (including functional gate patterns and dummy gate patterns) are arranged alternately along the X-axis. The spacing between adjacent MD contact structures is the same as the gate pattern spacing CPP between adjacent gate patterns. For example, as... Figure 2B As shown, the distance along the X-axis between the center line (unnumbered) of the MD contact structure 215 and the center line (unnumbered) of the adjacent MD contact structure 215 is the same as the gate pattern spacing CPP.

[0056] Circuit region 210 also includes vias located above and electrically contacting the corresponding gate pattern or MD contact structure. Vias located above and electrically contacting the MD contact structure are sometimes referred to as via-to-device (VD). Vias located above and electrically contacting the gate pattern are sometimes referred to as via-to-gate (VG). Figure 2BIn an exemplary configuration, VG via 218 is located above and electrically contacts gate pattern 213, and VD vias 217 and 219 are correspondingly located above and electrically contacts MD contact structures 215 and 216. Exemplary materials for the VD and VG vias in the manufactured IC include metals. Other materials are within the scope of the various embodiments.

[0057] Circuit region 210 also includes one or more metal layers and via layers arranged sequentially and alternately above the VD and VG vias. The bottommost metal layer immediately above and electrically in contact with the VD and VG vias is the metal zero (M0) layer. In other words, the M0 layer is the bottommost metal layer above the active region or the metal layer closest to the active region. The next metal layer immediately above the M0 layer is the metal one (M1) layer, and so on. A via layer Vn is arranged between the Mn layer and the Mn+1 layer and electrically couples the Mn and Mn+1 layers, where n is an integer starting from zero. For example, the via zero (V0) layer is the bottommost via layer arranged between the M0 layer and the M1 layer and electrically couples the M0 and M1 layers. Other via layers are V1, V2, etc. Figure 2B In the exemplary configuration, M0 conductive patterns 227, 228, and 229 are shown as being included in circuit region 210. The M0 conductive patterns 227, 228, and 229 are correspondingly located above and electrically contacting vias 217, 218, and 219. The M0 conductive patterns 227, 228, and 229 extend along the X-axis and each has a metal width wm along the Y-axis. In another metal layer, for example, layer M1 ( Figure 2B (Not shown in the image), the conductive patterns extend along the Y-axis, and each conductive pattern has a metal width wm along the X-axis. In some embodiments, conductive patterns 227, 228, and 229 serve as examples of conductive patterns in even-numbered metal layers (e.g., M2, M4, etc.), and vias 217, 218, and 219 serve as examples of vias in odd-numbered via layers (e.g., V1, V3, etc.). In some embodiments, circuit region 210 includes conductive patterns and / or vias in other metal layers and / or via layers. For simplicity, in Figure 2B These are omitted here. The configurations described and shown for various components such as active regions, gate patterns, MD contact structures, conductive patterns, and vias are examples. Other configurations are within the scope of the various embodiments.

[0058] Circuit region 210 includes a boundary 220, within which various circuit elements and / or conductive patterns and / or vias are arranged. Figure 2BIn the exemplary configuration, boundary 220 is rectangular and includes edges 221, 222, 223, and 224. The shape and number of the described edges of boundary 220 are examples. Other configurations are within the scope of the various embodiments. In some embodiments, during placement and routing operations, such as operation 130 performed by the APR tools described herein, cells and / or circuit regions are placed in an IC layout adjacent to each other along their respective boundaries. For example, circuit region 210 may be placed adjacent to one or more other cells or circuit regions along the X-axis at one or more of edges 221, 223. Additionally or alternatively, circuit region 210 may be placed adjacent to one or more other cells or circuit regions along the Y-axis at one or more of edges 222, 224. In some embodiments, one or more of edges 221, 222, 223, and 224 are not placed adjacent to another cell or circuit region of the IC layout.

[0059] The dimensions of circuit region 210 are defined by boundary 220. For example, circuit region 210 has a width W along the X-axis as the distance between edges 221, 223 of boundary 220, and a height H along the Y-axis as the distance between edges 222, 224 of boundary 220. Figure 2B In the exemplary configuration, edges 221 and 223 correspond to the outer edges of gate patterns 212 and 214. Other configurations are within the scope of the various embodiments. For example, in at least one embodiment, edges 221 and 223 correspond to the center lines of gate patterns 212 and 214.

[0060] In some embodiments, the enlargement (or expansion) operation of the circuit region along the X-axis includes increasing the gate pattern spacing of the circuit region to a larger gate pattern spacing. For example, as Figure 2B As shown in the intermediate view, the gate pattern pitch CPP of circuit region 210 is increased to a new gate pattern pitch CPPb that is greater than the gate pattern pitch CPP. The scaling factor for the amplification operation is a ratio CPPb / CPP that is greater than 1. In this example, the circuit region is amplified by up to about 10%, resulting in a scaling factor in the range from greater than 1 to about 1.1. Figure 2B In the exemplary configuration, the scaling direction is the X+ direction, and the edge 223 of the boundary 220 of the circuit region 210 is fixed. However, other methods for amplifying the circuit region 210 are possible within the scope of the various embodiments, such as those relating to... Figure 2A As described.

[0061] In some embodiments, information corresponding to at least one of the new gate pattern pitch CPPb or scaling factor CPPb / CPP is automatically and / or manually input by the user from an automation system to the APR tool. Based on the input information, the APR tool obtains the new gate pattern pitch CPPb and repositions the circuit elements (or devices) of circuit region 210 along the X-axis at the new gate pattern pitch CPPb. During repositioning, the devices of circuit region 210 are placed in the IC layout, but arranged at the new gate pattern pitch CPPb. Therefore, the device size of the devices in circuit region 210 is increased, resulting in an intermediate circuit region 230. The intermediate circuit region 230 includes all the components and / or devices of circuit region 210 and is configured to implement the same function of circuit region 210 in the manufactured IC. Figure 2B In an exemplary configuration, intermediate circuit region 230 includes gate patterns 212, 213, 214 now arranged with a new gate pattern pitch CPPb, and MD contact structures 215, 216 now arranged with a new gate pattern pitch CPPb. In some embodiments, the gate pattern width wg of gate patterns 212, 213, 214 and / or the corresponding MD width (unnumbered) of MD contact structures 215, 216 in intermediate circuit region 230 are the same as in circuit region 210. In other words, gate patterns 212, 213, 214 and MD contact structures 215, 216 are redistributed in intermediate circuit region 230 with a new gate pattern pitch CPPb without changing their corresponding widths. In some embodiments, the gate pattern width of gate patterns 212, 213, 214 and / or the width of MD contact structures 215, 216 are scaled according to a scaling factor. In some embodiments, the width and length of each of the active region, gate pattern, and MD contact structure in the circuit region are scaled according to the same scaling factor.

[0062] The active region 211 of circuit region 210 is enlarged according to a scaling factor and becomes an enlarged active region 211b with a width (unnumbered) along the X-axis that is larger than that of active region 211. The enlarged active region 211b has the same height (unnumbered) along the Y-axis as active region 211. The size of circuit region 210 (e.g., width along the X-axis) is also increased. For example, intermediate circuit region 230 has a width Wb corresponding to the width W of circuit region 210 and a scaling factor CPPb / CPP. In at least one embodiment, Wb = W × CPPb / CPP. Other calculations of Wb are within the scope of the various embodiments. Due to the enlargement, the width change along the X-axis is ΔWb = Wb - W.

[0063] In some embodiments, after repositioning, the APR tool performs routing modifications to adjust at least one existing routing component in circuit region 210 and / or add at least one additional routing component. As described herein, routing components include conductive patterns and / or vias. Conductive patterns extending along the Y-axis are sometimes referred to as vertical routing, and conductive patterns extending along the X-axis are sometimes referred to as horizontal routing. Conductive patterns 227, 228, and 229 are examples of horizontal routing. Regarding Figures 4 to 6 Further examples of horizontal routing and vertical routing are described.

[0064] In some embodiments, adjusting existing wiring components after scaling the circuit region along the X-axis includes rearranging existing vias and vertical wiring in the circuit region according to a scaling factor. For example, vias 217, 218, and 219 are offset along the scaling direction (i.e., the X+ direction) in the X-axis of circuit region 210, becoming new positions for vias 217, 218, and 219 in intermediate circuit region 230. The offset distance of each of vias 217, 218, and 219 is proportional to the X-axis spacing between vias 217, 218, and 219 and the fixed edge 223, according to the scaling factor. Between circuit region 210 and intermediate circuit region 230, the position of via 217 is offset by a minimum distance in the X+ direction, the position of via 218 is offset by a greater distance than the distance of via 217, and the position of via 219 is offset by a greater distance than the distance of via 218. Vertical wiring is offset in a similar manner. In some embodiments, the size of the vias and / or the metal width of the vertical wiring remain unchanged by scaling the circuit region. The intermediate circuit region 230 is obtained by scaling and subsequent rearranging of the vias and vertical wiring present in the circuit region 210.

[0065] In some embodiments, adjusting the existing wiring components after scaling the circuit region along the X-axis further includes adjusting the dimensions of one or more existing horizontal wirings in the circuit region. For example, Figure 2B The intermediate view shows the existing horizontal wiring of circuit region 210 after scaling, namely, conductive patterns 227, 228, and 229. The dimensions of conductive patterns 227, 228, and 229 are adjusted according to the scaling factor to achieve the desired effect. Figure 2B The corresponding conductive patterns 227b, 228b, and 229b are obtained in the modified circuit region 232 in the bottom view. For example, the length of each of the conductive patterns 227, 228, and 229 in circuit region 210 is readjusted (e.g., by increasing the scaling factor) to obtain the length of the corresponding conductive patterns 227b, 228b, and 229b in the modified circuit region 232. The dimensions of further horizontal wirings, such as conductive patterns in one or more further even-numbered metal layers, are adjusted in a similar manner. In some embodiments, the metal width of the horizontal wiring remains unchanged by scaling the circuit region.

[0066] Except for the adjusted lengths of conductive patterns 227b, 228b, and 229b, the modified circuit region 232 is identical to the intermediate circuit region 230. The modified circuit region 232 is due to the amplification operation described for circuit region 210. The modified circuit region 232 is configured to perform the same function as circuit region 210. However, due to the amplification operation, the increased device size of the devices in the modified circuit region 232 provides one or more desired adjustments to the manufacturing yield and / or performance of ICs manufactured corresponding to the modified layout including the modified circuit region 232.

[0067] Figure 2C A schematic diagram of a circuit region 210 including an IC layout in several stages of a shrinking operation along the X-axis according to some embodiments. In some embodiments, Figure 2C The circuit region 210 corresponds to at least one of the circuit regions 203 and 204, and / or the IC layout corresponds to the IC layout 200. Figure 2C In the top view, the circuit region 210 before scaling is shown; the middle view shows the intermediate circuit region 234 corresponding to the circuit region 210 after scaling and some wiring modifications; and the bottom view shows the modified circuit region 236 corresponding to the intermediate circuit region 234 after further wiring modifications. Figure 2C Top view and Figure 2B The top view is the same as in the previous one, and the top view is omitted. Figure 2C A detailed description of the top view in the image.

[0068] In some embodiments, the shrinking (or contraction) operation of the circuit region along the X-axis includes reducing the gate pattern spacing of the circuit region to a smaller gate pattern spacing. For example, as Figure 2C As shown in the intermediate view, the gate pattern pitch CPP of circuit region 210 is reduced to a new gate pattern pitch CPPs smaller than the gate pattern pitch CPP. The scaling factor for the reduction operation is a ratio CPPs / CPP that is less than 1. In this example, the circuit region is reduced by up to about 10%, resulting in a scaling factor in the range from less than 1 to about 0.9. Figure 2C In the exemplary configuration, the scaling direction is the X+ direction, and the edge 223 of the boundary 220 of the circuit region 210 is fixed. However, other methods for scaling down the circuit region 210 are available in various embodiments, such as those relating to... Figure 2A As described.

[0069] In some embodiments, information corresponding to at least one of the new gate pattern pitch CPP or scaling factor CPP / CPP is automatically and / or manually input by the user from an automation system to the APR tool. Based on the input information, the APR tool obtains new gate pattern pitches CPPs and repositions the circuit elements (or devices) of circuit region 210 along the X-axis at the new gate pattern pitches CPPs. In the repositioning, the devices of circuit region 210 are placed in the IC layout, but arranged at the new gate pattern pitches CPPs. Therefore, the device size of the devices in circuit region 210 is reduced and an intermediate circuit region 234 is obtained. The intermediate circuit region 234 includes all the components and / or devices of circuit region 210 and is configured to implement the same function of circuit region 210 in the manufactured IC. Figure 2C In an exemplary configuration, intermediate circuit region 234 includes gate patterns 212, 213, 214 now arranged with a new gate pattern pitch CPPs, and MD contact structures 215, 216 now arranged with a new gate pattern pitch CPPs. In some embodiments, the gate pattern width wg of gate patterns 212, 213, 214 and / or the corresponding MD width (unnumbered) of MD contact structures 215, 216 in intermediate circuit region 234 are the same as in circuit region 210. In other words, gate patterns 212, 213, 214 and MD contact structures 215, 216 are redistributed in intermediate circuit region 234 with a new gate pattern pitch CPPs without changing their corresponding widths. In some embodiments, the gate pattern width of gate patterns 212, 213, 214 and / or the width of MD contact structures 215, 216 are scaled according to a scaling factor. In some embodiments, the width and length of each of the active region, gate pattern, and MD contact structure in the circuit region are scaled according to the same scaling factor.

[0070] The active region 211 of circuit region 210 is reduced according to a scaling factor and becomes a reduced active region 211s with a width (not numbered) smaller than that of active region 211 along the X-axis. The reduced active region 211s has the same height (not numbered) as active region 211 along the Y-axis. The size of circuit region 210 (e.g., width along the X-axis) is also reduced. For example, intermediate circuit region 234 has a width Ws corresponding to the width W of circuit region 210 and a scaling factor CPPs / CPP. In at least one embodiment, Ws = W × CPPs / CPP. Other calculations of Ws are within the scope of the various embodiments. Due to the reduction, the width change along the X-axis is ΔWs = W - Ws.

[0071] In some embodiments, after repositioning, the APR tool performs wiring modifications to adjust at least one existing wiring component in circuit region 210 and / or add at least one additional wiring component. In some embodiments, adjusting existing wiring components after scaling the circuit region along the X-axis includes rearranging existing vias and vertical wiring in the circuit region according to a scaling factor. For example, the positions of vias 217, 218, and 219 in circuit region 210 along the X-axis are offset in the X direction to become new positions of vias 217, 218, and 219 in intermediate circuit region 234. The offset distance of each of vias 217, 218, and 219 is proportional to the X-axis spacing between vias 217, 218, and 219 and fixed edge 223, according to the scaling factor. Between circuit region 210 and intermediate circuit region 234, the position of via 217 is offset by the smallest distance in the X direction, the position of via 218 is offset by a greater distance than the distance of via 217, and the position of via 219 is offset by a greater distance than the distance of via 218. Vertical wiring is offset in a similar manner. In some embodiments, the size of the vias and / or the metal width of the vertical wiring remain unchanged by scaling the circuit region. An intermediate circuit region 234 is obtained due to the scaling and subsequent rearrangement of the vias and vertical wiring present in circuit region 210.

[0072] In some embodiments, adjusting the existing wiring components after scaling the circuit region along the X-axis further includes adjusting the dimensions of one or more existing horizontal wirings in the circuit region. For example, Figure 2C The intermediate view shows the existing horizontal wiring of circuit region 210 after scaling, namely, conductive patterns 227, 228, and 229. The dimensions of conductive patterns 227, 228, and 229 are adjusted according to the scaling factor to achieve the desired effect. Figure 2C The corresponding conductive patterns 227s, 228s, and 229s are obtained in the modified circuit region 236 in the bottom view. For example, the length of each of the conductive patterns 227, 228, and 229 in the circuit region 210 is readjusted (e.g., reduced by a scaling factor) to obtain the length of the corresponding conductive patterns 227s, 228s, and 229s in the modified circuit region 236. The dimensions of further horizontal wirings, such as conductive patterns in one or more further even-numbered metal layers, are adjusted in a similar manner. In some embodiments, the metal width of the horizontal wiring remains unchanged by scaling the circuit region.

[0073] Except for the adjusted lengths of conductive patterns 227s, 228s, and 229s, the modified circuit region 236 is identical to the intermediate circuit region 234. The modified circuit region 236 is due to the shrinkage operation described for circuit region 210. The modified circuit region 236 is configured to perform the same function as circuit region 210. However, due to the shrinkage operation, the reduced device size of the devices in the modified circuit region 236 provides one or more desired adjustments to the manufacturing yield and / or performance of ICs manufactured corresponding to the modified layout including the modified circuit region 236.

[0074] about Figures 2B to 2C The scaling operation described is an exemplary scaling operation along the X-axis. In some embodiments, a scaling operation along the Y-axis or a scaling operation along both the X and Y axes is implemented in a similar manner. In at least one embodiment, the circuit region is scaled up or down along both the X and Y axes by the same scaling factor.

[0075] Figure 2D This is a schematic cross-sectional view of IC 250 according to some embodiments. In at least one embodiment, IC 250 corresponds to... Figures 2A to 2C and Figures 3A to 7 One or more IC layouts described in the document.

[0076] like Figure 2D As shown, the IC device 250 includes a substrate 252 on which circuit elements and structures corresponding to one or more circuit regions and / or layouts described herein are formed. The substrate 252 has a thickness direction along a Z-axis perpendicular to the X and Y axes. The Z-axis has a Z+ direction and an opposite Z- direction, as shown... Figure 2D As shown in the figure. In at least one embodiment, substrate 252 comprises silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor or dielectric material. In some embodiments, substrate 252 is a p-doped substrate. In some embodiments, substrate 252 is an n-doped substrate. In some embodiments, substrate 252 is a rigid crystalline material other than the semiconductor material on which the IC is fabricated (e.g., diamond, sapphire, aluminum oxide (Al2O3), etc.).

[0077] IC device 250 further includes N-type and P-type dopants added to substrate 252 to correspondingly form n-channel metal-oxide-semiconductor (NMOS) active regions and p-channel metal-oxide-semiconductor (PMOS) active regions. The NMOS and PMOS active regions form active regions. In some embodiments, an isolation structure is formed between adjacent active regions. For simplicity, from Figure 2D The isolation structure is omitted. In at least one embodiment, the active region of IC 250 corresponds to the area related to... Figures 2B to 2C One or more of the active regions described.

[0078] IC device 250 also includes various gate structures located above the active region. For example, the gate structure includes a gate portion 255 and a corresponding gate dielectric 256 located above the active region of substrate 252. Exemplary materials for the gate dielectric 256, comprising one or more layers, include HfO2, ZrO2, etc. Exemplary materials for the gate portion 255 include polysilicon, metal, etc. In some embodiments, the various gate structures of IC 250 correspond to one or more of gate patterns 212, 213, 214, as described above. Figures 2B to 2C As described. In at least one embodiment, the gate structure corresponding to the dummy gate pattern includes a dielectric material.

[0079] IC device 250 also includes MD contact structures for electrically coupling the lower source / drain terminals of individual transistors in the active region to other circuit elements. For example, MD contact structure 257 in Figure 2D As shown in the figure. In some embodiments, at least one of the MD contact structures 257 corresponds to one or more of the MD contact structures 215, 216, as shown in the figure. Figures 2B to 2C As described.

[0080] IC device 250 also includes VD vias and VG vias correspondingly located above and electrically in contact with the MD contact structure and gate structure. For example, as Figure 2D As shown, VG via 258 is located above and electrically contacts the gate portion 255 of one of the gate structures, and VD via 259 is located above and electrically contacts the MD contact structure 257. In some embodiments, VG via 258 corresponds to VG via 218, and / or VD via 259 corresponds to one or more of VD vias 217, 219, as per [reference to...]. Figures 2B to 2C As described.

[0081] IC device 250 also includes an interconnect structure 260 located above VD and VG vias, and includes a plurality of metal layers M0, M1, ... and a plurality of via layers V0, V1, ... arranged alternately in the thickness direction of substrate 252, i.e., along the Z-axis. Interconnect structure 260 also includes various interlayer dielectric (ILD) layers (not shown or numbered) embedded therein in the metal layers and via layers. The metal layers and via layers of interconnect structure 260 are configured to electrically couple the various components or circuits of IC device 250 to each other and / or to external circuitry. For simplicity, Figure 2D The metal layer and via layer above the M1 layer are omitted.

[0082] The MO layer includes MO conductive patterns 261 and 262 correspondingly located above and electrically contacting VG vias 258 and VD vias 259. In some embodiments, at least one of the MO conductive patterns 261 and 262 corresponds to one or more of conductive patterns 227, 228, and 229, as per [reference to...]. Figures 2B to 2C As described. The V0 layer includes V0 vias 263 and 264 correspondingly located above and electrically contacting the M0 conductive patterns 261 and 262. The M1 layer includes M1 conductive patterns 265 and 266 correspondingly located above and electrically contacting the V0 vias 263 and 264. The M0 conductive patterns, V0 vias, M1 conductive patterns, and / or further conductive patterns and vias of the interconnect structure 260 provide electrical connections to the various circuit elements of the IC 250 and / or to external circuitry.

[0083] In some embodiments, due to the implementation of various scaling operations on corresponding different circuit regions in the IC layout, the IC manufactured according to the IC layout includes corresponding different circuit regions with different gate pattern pitches. For example, when circuit regions 201 and 202 of IC layout 200 are scaled up with different scaling factors, the IC corresponding to the modified IC layout 200 includes corresponding circuit regions with different gate pattern pitches having a larger gate pattern pitch than that in other unscaled circuit regions. In a further example, when circuit regions 203 and 204 of IC layout 200 are scaled down with different scaling factors, the IC corresponding to the modified IC layout 200 includes corresponding circuit regions with different gate pattern pitches having a smaller gate pattern pitch than that in other unscaled circuit regions. In yet another example, when circuit regions 201 and 202 of IC layout 200 are scaled up with different scaling factors and circuit regions 203 and 204 of IC layout 200 are scaled down with different scaling factors, the IC corresponding to the modified IC layout 200 includes corresponding circuit regions with four different gate pattern pitches having a gate pattern pitch different from that in other unscaled circuit regions. Other configurations are within the scope of the various embodiments.

[0084] Figure 3A This is a schematic diagram of IC layout 300 in various scaling operations with a push area according to some embodiments.

[0085] IC layout 300 includes circuit regions 302, 303, 304 to be amplified and regions 312, 314. In some embodiments, one or more of the circuit regions 302, 303, 304 to be amplified correspond to one or more of the circuit regions 201, 202. In at least one embodiment, at least one of the regions 312, 314 includes one or more circuit regions to be amplified and / or one or more circuit regions to be scaled down and / or one or more unscaled circuit regions.

[0086] exist Figure 3A In the exemplary configuration, circuit regions 302, 303, and 304 are enlarged in the X+ direction. Region 312 is arranged relative to circuit regions 302 and 303 in the X+ direction and at least partially overlaps with each of circuit regions 302 and 303 along the X-axis. Region 314 is arranged relative to circuit region 304 in the X+ direction and at least partially overlaps with circuit region 304 along the X-axis. Circuit region 303 is arranged relative to circuit region 302 in the X+ direction and at least partially overlaps with circuit region 302 along the X-axis. Figure 3A ΔW1 indicates that the scaling operation height along the Y-axis increases due to scaling operations in one or more circuit regions.

[0087] Based on the scaling factor that will amplify circuit regions 302, 303, and 304 in the X+ direction, the corresponding width increases of circuit regions 302, 303, and 304 after amplification, ΔW2, ΔW3, and ΔW4, can be determined by APR tools. For example, based on the width of circuit regions 302, 303, and 304 before amplification and their corresponding scaling factors, such as regarding... Figure 2B As described. In some cases, there is a risk or concern that the increased width of one or more of the amplified circuit regions 302, 303, 304 may cause the gate pattern of the amplified circuit region to overlap with the gate pattern of one or more other circuit regions positioned adjacent to the amplified circuit region in the scaling direction. Gate pattern overlap violates one or more design rules and should be avoided.

[0088] In one or more embodiments, potential gate pattern overlap can be avoided after the amplification circuit region by causing the APR tool to further push or move one or more circuit regions in the scaling direction. For example, to avoid potential gate pattern overlap after amplifying circuit region 302 in the X+ direction due to a width increase W2, the APR tool pushes or moves the adjacent and overlapping circuit region 303 in the X+ direction by a distance corresponding to the width increase W2. Circuit region 303 itself has a width increase ΔW3 after amplification, resulting in a combined width increase ΔW2+ΔW3 caused by amplifying circuit regions 302, 304. To avoid potential gate pattern overlap after amplifying circuit regions 302, 303 in the X+ direction due to the combined width increase ΔW2+ΔW3, the APR tool pushes or moves the adjacent and overlapping region 312 (referred to herein as the "push region") in the X+ direction. Figure 3A The value specified as PUSHED 1) corresponds to an increase of ΔW2+ΔW3 in the combined width.

[0089] In some embodiments, the width of the combined push region 312 is increased by ΔW2 + ΔW3, even if region 312 does not overlap with circuit region 302 along the X+ direction. It is sufficient for region 312 to at least partially overlap with circuit region 303 along the X+ direction, while circuit region 303 at least partially overlaps with circuit region 302 along the X+ direction. In some embodiments, when region 312 at least partially overlaps with circuit region 302 but not with circuit region 303 along the X+ direction, the push region 312 corresponds to a width increase of ΔW2 after the amplified circuit region 302.

[0090] In some embodiments, to avoid potential gate pattern overlap after the amplification circuit region 304 in the X+ direction due to the width increase ΔW4, the APR tool pushes or moves in the X+ direction a region 314 (also referred to herein as the "push region") adjacent to and overlapping the circuit region 304. Figure 3A The value specified as PUSHED 2) corresponds to a distance that increases the width by ΔW4.

[0091] In some embodiments, the described pushing operation is applicable to amplification operations and to circuit regions or areas positioned in the scaling direction relative to the positive amplification circuit region. For example, when circuit region 304 shrinks, region 314 is not pushed. In another instance, circuit regions and / or areas positioned in the X-direction relative to circuit region 302 are not pushed (i.e., in...). Figure 3A (the left side of circuit region 302 in the middle), even if the circuit region and / or the region overlaps with circuit region 302 along the X-axis.

[0092] In some embodiments, the decision to push or move regions to avoid potential gate pattern overlap is implemented automatically and / or based on user input. For example, in one or more embodiments, the APR tool is configured to make a first determination, based on the position and / or height of the respective circuit regions and / or regions 302, 303, 312 along the Y-axis, whether region 312 overlaps with the circuit regions 302, 303 to be amplified along the X-axis. The APR tool is also configured to make a second determination, based on the position and / or width of the respective circuit regions and / or regions 302, 303, 312 along the X-axis, whether region 312 that overlaps with the circuit regions 302, 303 to be amplified along the X-axis is also positioned in a scaling direction (e.g., relative to the X+ direction of the circuit regions 302, 303 to be amplified). Upon reaching the conclusion that both the first and second determinations are affirmative, the APR tool sets the characteristics or attributes of region 312 to PUSH, i.e., to become a push region, and increases ΔW2 and ΔW3 using the calculated widths of circuit regions 302 and 303 to push or move region 312 in the scaling direction (e.g., the X+ direction) after amplifying circuit regions 302 and 303. In some embodiments, the region is set as the push region by a marker layer overlapping the push region. The marker layer is a virtual layer for handling layout and is not fabricated on the photomask and / or wafer.

[0093] In at least one embodiment, based on user input, the APR tool sets at least one of region 312 or region 314 as the push region. For example, in one or more embodiments, circuit regions to be scaled in the IC layout are highlighted to visually distinguish them from other, unscaled circuit regions, as described herein. Figure 2A As described. In Figure 3A In the exemplary configuration, circuit regions 302, 303, and 304 to be amplified are visually distinguished from other circuit regions or areas, for example, by the display device of the APR tool. Therefore, in one or more embodiments, a user can quickly recognize that region 312 overlaps with the circuit regions 302 and 303 to be amplified and is positioned in the scaling direction, i.e., the X+ direction, meaning that region 312 will be set as the push region. In at least one embodiment, the user provides user input indicating that region 312 will be set as the push region. In response to the user input, the APR tool sets a characteristic or attribute of region 312 to PUSH and increases ΔW2 and ΔW3 using the calculated widths of circuit regions 302 and 303 to push or move region 312 in the scaling direction (e.g., the X+ direction) after amplifying circuit regions 302 and 303.

[0094] In some embodiments, the APR tool and / or external computer system are configured to perform machine learning from instructional data, including past user input, in various situations, whether or not push regions are set. In some embodiments, the results of the machine learning include a machine learning model and / or a trained neural network. The APR tool and / or external computer system are configured to apply the machine learning model and / or the trained neural network to determine, in future situations, where one or more push regions will be set, in addition to or in place of user input. Other arrangements for setting one or more push regions are within the scope of the various embodiments.

[0095] Figure 3B This includes a schematic diagram of portions of the IC layout 320 in various scaling operations having a push area, according to some embodiments. Figure 3B In the diagram, from top to bottom, the first view shows the IC layout 320 without a push area, the second view shows the IC layout 320 without a push area when the amplifier circuit area is present, the third view shows the IC layout 320 with a push area present, and the fourth view shows the IC layout 320 with a push area present when the amplifier circuit area is present.

[0096] like Figure 3B As shown in the first view, the IC layout 320 includes an amplification circuit region 322 in the X+ direction and a capacitor region (in... Figure 3B The capacitor regions 323 and 324 (designated as Cap) and resistor regions 325 and 326 (designated as Resister) are specified in the embodiments. The number and / or arrangement of capacitor regions 323 and 324 and / or resistor regions 325 and 326 are examples. Other arrangements are within the scope of the various embodiments. Capacitor regions 323 and 324 and resistor regions 325 and 326 are examples of analog circuit regions that are not scaled to maintain their original size and unchanged performance. Further examples of unscaled circuit regions include high-speed digital circuits. Figure 3B The first view in the image shows the case when no push area is set for the circuit region 322 to be amplified.

[0097] like Figure 3B As shown in the second view, when the amplification circuit region 322 is in place, the amplification circuit region 322b is obtained. In some embodiments, the circuit region 322 is enlarged and the wiring is modified according to the new gate pattern spacing, as per [reference to...]. Figure 2BAs described. The dimension of amplifier circuit region 322b along the X-axis corresponds to an increase of ΔW in the dimension of circuit region 322 along the X-axis. This increased dimension causes amplifier circuit region 322b to contact capacitor regions 323, 324, or otherwise violate one or more design rules, as schematically shown in regions 333, 334. These problems are identified by the user or discovered through one or more checks when the modified layout 330, including amplifier circuit region 322b, is verified, as per [reference to...]. Figure 1 As described. For example, contacting one or more of the capacitor regions 323, 324 with an amplifier region 322b will cause the LVS check to fail. In another instance, not contacting but being too close to one or more of the capacitor regions 323, 324 with an amplifier region 322b (e.g., the distance between the amplifier region 322b and the capacitor regions 323, 324 is less than the critical dimension defined in the design rules) will cause the DRC to fail. Upon determining that a modified layout 330 has failed one or more verifications, the process automatically and / or based on user input returns to the initial IC layout 320 via APR tools for correction and / or adjustment.

[0098] like Figure 3B As shown in the third view, push region 335 is disposed in IC layout 320 to include capacitor regions 323, 324 and resistor regions 325, 326. Figure 3B In the exemplary configuration, although resistor regions 325, 326 are unlikely to contact or be too close to amplifier circuit region 322b, resistor regions 325, 326 are still included in push region 335. This is because there is vertical wiring (not shown) connecting resistor regions 325, 326 to the circuit region 322 to be amplified, and therefore, resistor regions 325, 326 are included in push region 335, which is to move with the amplifier circuit region. In some embodiments, resistor regions 325, 326 are not included in push region 335 and remain in the same position as circuit region 322 is amplified. In at least one embodiment, the decision of whether to include resistor regions 325, 326 in push region 335 is made by a user based on his / her expertise. In at least one embodiment, the decision of including resistor regions 325, 326 in push region 335 is made automatically by APR tools and / or another computer system, for example, through machine learning as described herein. Other arrangements are within the scope of the various embodiments.

[0099] like Figure 3BAs shown in the fourth view, since capacitor regions 323, 324 and resistor regions 325, 326 are included in the push-up region 335, when the circuit region 322 is enlarged in size and increased by ΔW, capacitor regions 323, 324 and resistor regions 325, 326 are pushed a distance corresponding to ΔW in the scaling direction (i.e., the X+ direction). The pushed circuit regions are designated as 323p, 324p, and the pushed resistor regions 325, 326 are designated as 325p, 326p. Before enlarging the circuit region 322 to the amplifier circuit region 322b, the physical and / or electrical relationships between the pushed capacitor regions 323p, 324p and the pushed resistor regions 325p, 326p remain the same as in the IC layout 320. The amplifier circuit region 322b no longer contacts or is too close to the pushed capacitor regions 323p, 324p. As a result, a modified layout 340 with the amplifier circuit region 322b and meeting various verifications is obtained.

[0100] Figure 4 This includes a schematic diagram of an IC layout 400 during scaling operations, according to some embodiments. Figure 4 In the top view, the IC layout 400 is shown before the circuit region 410 included in the scaled IC layout 400; the middle view shows the intermediate layout 440 with the circuit region 410 after scaling and some routing modifications; and the bottom view shows the layout 450 after further routing modifications.

[0101] like Figure 4 As shown in the top view, IC layout 400 includes a circuit region 410 having a boundary 420 with edges 421, 422, 423, 424. In some embodiments, circuit region 410 corresponds to circuit region 210, and / or the boundary 420 with edges 421, 422, 423, 424 corresponds to... Figure 2B The described boundary 220 has edges 221, 222, 223, and 224. Circuit region 410 includes one or more active regions, one or more gate patterns, and corresponding to... Figure 2B The description includes the active region, gate pattern, and one or more MD contact structures. For simplicity, Figure 4 The active region, gate pattern, and MD contact structure of circuit region 410 are omitted. Circuit region 410 also includes horizontal wiring, vertical wiring, and vias between the corresponding horizontal and vertical wirings. Figure 4In an exemplary configuration, exemplary horizontal wiring of circuit region 410 includes conductive patterns 407, 408, and 409 extending along the X-axis; exemplary vias include vias 417, 418, and 419 correspondingly located above and electrically contacting conductive patterns 407, 408, and 409; and exemplary vertical wiring includes conductive patterns 425, 431, and 434 extending along the Y-axis, correspondingly located above and electrically contacting vias 417, 418, and 419. In some embodiments, circuit region 410 further includes vertical and / or horizontal wiring in one or more metal layers other than the metal layers of conductive patterns 407, 408, 409, and 425, 431, and 434. Conductive patterns 425, 431, and 434 extend from within circuit region 410 to outside circuit region 410 for electrically coupling circuitry of circuit region 410 to other circuit regions. exist Figure 4 In the exemplary configuration, conductive patterns 425, 431, and 434 extend across the edge 424 of the boundary 420 of the circuit region 410. In some embodiments, one or more further vertical wirings extend across the opposite edge 422 of the boundary 420. The IC layout 400 also includes conductive patterns 426-430, 432-433, and 435 located in the same metal layer as the conductive patterns 425, 431, and 434, but located outside the circuit region 410 and do not form vertical wirings for the circuit region 410. The conductive patterns 425-435 are arranged along the X-axis with metal spacing corresponding to the metal layers.

[0102] like Figure 4 As shown in the intermediate view, circuit region 410 is enlarged along the X+ direction to create amplifier circuit region 410b. In some embodiments, circuit region 410 is enlarged and wiring modified according to a new gate pattern spacing, as per [reference to...]. Figure 2B As described. The dimension of the amplifier circuit region 410b along the X-axis corresponds to an increase of ΔW in the dimension of the circuit region 410 along the X-axis. When the circuit region 410 is magnified, the corresponding horizontal wiring is stretched along the X-axis, while the vias and vertical wiring are rearranged along the X-axis according to the scaling factor, for example, expanded, as described above. Figure 2B As described. For example, conductive patterns 407, 408, and 409 are stretched along the X-axis according to a scaling factor and become corresponding conductive patterns 407b, 408b, and 409b in the amplifier circuit region 410b. Vias 417, 418, and 419 and corresponding conductive patterns 425, 431, and 434 are rearranged along the X-axis and according to a scaling factor, for example, expanded, to serve as vias 417b, 418b, and 419b and conductive patterns 425b, 431b, and 434b in new positions. Figure 4In the intermediate view, the initial positions of conductive patterns 425, 431, and 434 are shown with dashed lines. Due to magnification and wiring modifications, an intermediate layout 440 is obtained, as shown... Figure 4 The middle view is shown in the image.

[0103] Conductive patterns 426-430, 432-433, and 435 are not associated with circuit region 410 and have not been rearranged due to the enlargement of circuit region 410. Therefore, the rearranged conductive patterns 425b, 431b, and 434b, as well as the conductive patterns 426-430, 432-433, and 435 remaining in the same location, may violate one or more design rules. For example, the metal-to-metal distance d1 between the rearranged conductive pattern 425b and the adjacent conductive pattern 426 may be less than a predetermined value (critical dimension) allowed by the design rules. In at least one embodiment, this problem is verified or discovered by a DRC check. In another example, the rearranged conductive patterns 431b and 434b correspondingly contact conductive patterns 432 and 435, as schematically shown at corresponding overlapping regions 441 and 444. In at least one embodiment, these problems correspond to short circuits and are verified or discovered by an LVS check. When it is determined that the modified layout 440 has failed one or more validations, the process automatically and / or based on user input returns to the APR tool for correction and / or adjustment.

[0104] like Figure 4 As shown in the bottom view, in one or more embodiments, the rearranged conductive patterns 425b, 431b, 434b and the corresponding rearranged vias 417b, 418b, 419b are moved back to the initial positions of the corresponding conductive patterns 425, 431, 434 and the corresponding vias 417, 418, 419. Furthermore, additional wiring components, such as conductive pattern 415, are added to conductive pattern 409b, or conductive pattern 409b extends in the X direction to pass under via 419 for electrical connection with conductive pattern 434. Thus, short-circuit and / or metal-to-metal distance problems are resolved, and a modified layout 450 with an amplification circuit region 410b and meeting various verification requirements is obtained. In some embodiments, the conductive patterns 425b, 431b, 434b and vias 417b, 418b, 419b are manually moved back and / or the additional conductive pattern 415 is added by the user or via an APR tool based on user input. In some embodiments, conductive patterns 425b, 431b, 434b and vias 417b, 418b, 419b are shifted back and / or additional conductive patterns 415 are automatically added by APR tools and / or another computer system, for example, through machine learning as described herein. Other arrangements are within the scope of the various embodiments.

[0105] Figure 5This includes schematic diagrams of IC layout 500 during disconnection, scaling, and reconnection operations according to some embodiments. In some embodiments, IC layout 500 corresponds to IC layout 400. Figure 4 The corresponding components in Figure 5 The components in the document are represented by the same reference numerals. Figure 5 In the top view, the IC layout 500 is shown in the disconnection operation before the circuit area 410 included in the scaled IC layout 500 is included. The middle view shows the intermediate layout 540 with the circuit area 410 after scaling and some wiring modifications. The bottom view shows the modified layout 550 after the reconnection operation.

[0106] like Figure 5 As shown in the top view, IC layout 500 includes circuit region 410, as per [the description of the IC layout]. Figure 4 As described. Figure 4 neutralization Figure 5 The difference between the top views in the images is that, Figure 5 For example, a disconnection operation is performed using an APR tool to disconnect each conductive pattern extending across the boundary 420 of the circuit region 410 into an inner portion within the circuit region 410 and an outer portion outside the circuit region 410. For example, conductive patterns 425, 431, and 434 extend from the outside into the circuit region 410 across the edge 424 of the boundary 420 and are disconnected along the edge 424, as schematically shown by arrow 504. Each of the conductive patterns 425, 431, and 434 is divided into an inner portion within the circuit region 410 and an outer portion outside the circuit region 410. For example, conductive pattern 425 is divided into an outer portion 525o and an inner portion 525i by the disconnection operation, conductive pattern 431 is divided into an outer portion 531o and an inner portion 531i, and conductive pattern 434 is divided into an outer portion 534o and an inner portion 534i.

[0107] In some embodiments, the disconnection operation is performed automatically by an APR tool. For example, the APR tool determines the boundary 420 of the circuit region 410 and the conductive patterns 425, 431, 434 that cross the edge of the boundary 420 from the IC layout 500. The APR tool automatically disconnects the conductive patterns 425, 431, 434 along the edge, which crosses, for example, edge 424. To later reconnect the disconnected inner and outer portions of the conductive patterns, the APR tool assigns pin pairs or anchors near edge 424 to the adjacent ends of the corresponding inner and outer portion pairs. For example, anchor pairs A1, A2 are assigned to the adjacent ends of the corresponding inner portion 525i and outer portion 525o pair, anchor pairs B1, B2 are assigned to the adjacent ends of the corresponding inner portion 531i and outer portion 531o pair, and anchor pairs C1, C2 are assigned to the adjacent ends of the corresponding inner portion 534i and outer portion 534o pair. In some embodiments, the assigned anchors A1, B1, C1 have the same coordinates along the X-axis as the corresponding anchors A2, B2, C2 (hereinafter referred to as X-axis coordinates). In at least one embodiment, the X-axis coordinate is determined relative to the origin of the coordinate system of the reference point or IC layout, such as regarding Figure 2A As described.

[0108] like Figure 5 As shown in the intermediate view, circuit region 410 is enlarged along the X+ direction to create amplifier circuit region 510b. In some embodiments, circuit region 410 is enlarged and wiring modified according to a new gate pattern spacing, as per [reference to...]. Figure 2B As described. The dimension of the amplifier circuit region 510b along the X-axis corresponds to an increase of ΔW in the dimension of the circuit region 410 along the X-axis. When the circuit region 410 is magnified, the corresponding horizontal wiring is stretched along the X-axis, while the vias and vertical wiring are rearranged along the X-axis according to the scaling factor, for example, expanded, as described above. Figure 2B As described.

[0109] exist Figure 4 In the embodiment, when the circuit region 410 is enlarged, the conductive patterns 425, 431, and 434 are not broken and are rearranged as a whole. Instead, in... Figure 5 In the embodiment, conductive patterns 425, 431, 434 are broken along edge 424, and therefore, when the circuit region 410 is enlarged, the inner portions 525i, 531i, 534i are rearranged, but the outer portions 525o, 531o, 534o remain unchanged. Therefore, regarding Figure 4 The potential design rule violations discussed in the embodiments are in Figure 5 This can be avoided in the embodiments described. In Figure 5In the intermediate view, the initial positions of the internal portions 525i, 531i, and 534i are shown with dashed lines. The internal portions 525i, 531i, and 534i are scaled according to a scaling factor, similar to the values ​​shown about... Figure 4 The described arrangement is rearranged, for example, expanded, and has new positions for the corresponding rearranged internal parts 525ib, 531ib, and 534ib. Due to disconnection, enlargement, and wiring modifications, an intermediate layout 540 is obtained, as shown... Figure 5 The middle view is shown in the image.

[0110] In some embodiments, the APR tool determines whether it is necessary to reconnect the corresponding internal and external portions that were disconnected from the initial conductive pattern through the disconnection operation described herein. In at least one embodiment, the APR tool makes the determination based on the X-axis coordinates of the paired anchors. In an example, the X-axis distance between anchors A1 and A2 can be determined based on the X-axis coordinates of anchors A1 and A2 correspondingly located on the rearranged internal portion 525ib and external portion 525o. If the X-axis distance between anchors A1 and A2 is greater than a predetermined value associated with the metal width of the rearranged internal portion 525ib and external portion 525o, the APR tool determines that the rearranged internal portion 525ib and external portion 525o are not properly electrically connected, and one or more additional wiring components will be added to connect the rearranged internal portion 525ib and external portion 525o. Similar determinations are made for other anchor pairs B1, B2 and C1, C2.

[0111] In some embodiments, the corresponding rearranged inner and outer portions are also determined to lack proper electrical connection, even when these portions are in contact with each other. For example, in intermediate layout 540, there is an electrical connection between the outer portion 525o and the rearranged inner portion 525ib, but its acceptability is to be verified. Figure 5Enlarged view 509 in the intermediate view shows the adjacent ends of the rearranged inner portion 525ib and outer portion 525o. The rearranged inner portion 525ib and outer portion 525o overlap on an overlap width Wo. In at least one embodiment, the overlap width Wo may be determined based on the X-axis distance between anchors A1, A2 (not shown in view 509) and the metal width of the rearranged inner portion 525ib and outer portion 525o. If the overlap width Wo is greater than a predetermined minimum metal width defined by design rules, the connection between the rearranged inner portion 525ib and outer portion 525o is acceptable in DRC verification. In this case, the APR tool will not attempt to reconnect the rearranged inner portion 525ib and outer portion 525o. Otherwise, at least one additional wiring component is added to meet the design rules. For example, when the overlap width Wo fails to pass DRC verification, the wiring modification performed by the APR tool extends one of the rearranged inner portion 525ib and outer portion 525o toward and above the other. Therefore, the overlap width Wo becomes greater than the metal width of the rearranged inner portion 525ib or outer portion 525o, and meets the design rules. Optionally or additionally, a jog value corresponding to the amount of overhang along the X-axis of one of the rearranged inner portion 525ib and outer portion 525o from the other can be used in the design rules for verifying the acceptability of the electrical connection from outer portion 525o to the rearranged inner portion 525ib.

[0112] like Figure 5 As shown in the bottom view, a reconnection operation is performed by the APR tool to reconnect the corresponding rearranged internal and external parts that were previously disconnected and separated from each other due to the amplifier circuit region 410. Figure 5In the exemplary configuration, the electrical connection between the rearranged internal portion 525ib and the external portion 525o satisfies DRC verification and requires no additional wiring components for reconnection. However, the rearranged internal portion 531ib and external portion 531o pair, as well as the rearranged internal portion 534ib and external portion 534o pair, require additional wiring components for reconnection. For example, to reconnect the rearranged internal portion 534ib and external portion 534o, the APR tool extends the external portion 534o into the amplifier circuit region 510b, adds a conductive pattern 546 overlapping the extended external portion 534o and the rearranged internal portion 534ib, and adds vias 547, 548 that correspondingly electrically couple the conductive pattern 546 to the extended external portion 534o and the rearranged internal portion 534ib. Thus, the external portion 534o is reconnected to the rearranged internal portion 534ib, and then connected to the corresponding conductive pattern 409b through via 419b. In at least one embodiment, the inner portion 531ib and the outer portion 531o are reconnected in a similar manner, and for simplicity, from Figure 5 The additional wiring components for reconnecting the internal portion 531ib and the external portion 531o are omitted. Upon completion of the reconnection operation, a modified layout 550 with an amplifier circuit area 510b and meeting various verification requirements is obtained.

[0113] Figure 6 This includes a schematic diagram of an IC layout 600 in a scaling operation with a fixed region according to some embodiments. In some embodiments, IC layout 600 corresponds to IC layout 400. Figure 4 The corresponding components in Figure 6 The components in the document are represented by the same reference numerals. Figure 6 In the top view, the IC layout 600 with a fixed region 603 is shown before the circuit region 410 included in the scaled IC layout 600. The middle view shows an intermediate layout 640 with the circuit region 410 after scaling and some routing modifications. The bottom view shows a modified layout 650 after further routing modifications.

[0114] like Figure 6 As shown in the top view, IC layout 600 includes circuit region 410, as described above. Figure 4 As described. Figure 4 neutralization Figure 6 The difference between the top views in the images is that, Figure 6In this configuration, the fixed region 603 is configured to include conductive patterns 425-435 adjacent to the circuit region 410, and includes conductive patterns 425, 431, and 434 extending from the outside into the circuit region 410. In some embodiments, the fixed region is set by the user. For example, a layout engineer uses a marker layer to cover the area to be set as a fixed region. Figure 6 In the exemplary configuration, the boundary of fixed region 603 corresponds to the marker layer. In some embodiments, power / ground networks or portions thereof in the layout are configured as one or more fixed regions.

[0115] In some embodiments, the fixed regions are automatically set by a processor, an APR tool, or an external computer system. For example, machine learning is used in one or more embodiments to learn from teaching data, including past user input, in various situations, with or without fixed regions set. In some embodiments, the results of machine learning include a machine learning model and / or a trained neural network. The APR tool and / or external computer system is configured to apply the machine learning model and / or trained neural network to determine, in future situations, where one or more fixed regions will be set, in addition to or in place of user input. Other arrangements for setting one or more fixed regions are within the scope of the various embodiments.

[0116] The fixed region indicates to the APR tool that it will not form a scaled area. Therefore, even though portions of the conductive patterns 425, 431, 434 and the corresponding vias 417, 418, 419 are included in the circuit region 410, the conductive patterns 425, 431, 434 and the corresponding vias 417, 418, 419 are unaffected by the scaling operation of the circuit region 410. In other words, the fixed region 603 in the memory device 600 does not scale or move, despite scaling operations on one or more circuit regions.

[0117] like Figure 6 As shown in the intermediate view, circuit region 410 is enlarged along the X+ direction to create amplifier circuit region 610b. In some embodiments, circuit region 410 is enlarged and wiring modified according to a new gate pattern spacing, as per [reference to...]. Figure 2B As described. The dimension of the amplifier circuit region 610b along the X-axis corresponds to an increase of ΔW in the dimension of the circuit region 410 along the X-axis. When the circuit region 410 is magnified, the corresponding horizontal wiring is stretched along the X-axis, while the vias and vertical wiring are rearranged along the X-axis according to the scaling factor, for example, expanded, as described above. Figure 2BAs described. However, because the vertical wiring and vias, i.e., the conductive patterns 425, 431, 434 and the corresponding vias 417, 418, 419, are included in the fixed region 603, the conductive patterns 425, 431, 434 and the corresponding vias 417, 418, 419 are not affected by the enlargement of the circuit region 410, and do not exhibit the characteristics described above. Figures 4 to 5 Rearrange or move as described, and maintain in accordance with Figure 6 In the same position as the top view in the image. Due to the setting of fixed area 603 and the enlargement of circuit area 410, intermediate layout 640 is obtained, as shown. Figure 6 The middle view is shown in the image.

[0118] The intermediate layout 640 is reviewed by users and / or undergoes various validations, such as DRC and LVS validations. Figure 6 In the exemplary configuration, DRC verification identifies that the distance d2 between edge 617 of conductive pattern 407b and adjacent edge 618 of conductive pattern 425 is less than the minimum distance allowed by the design rules. A similar DRC violation exists between edge 619 of conductive pattern 409b and adjacent edge 620 of conductive pattern 434. An open circuit exists between conductive patterns 409b and 434, which should be electrically connected to each other as in the initial circuit region 410. This problem is an LVS violation.

[0119] like Figure 6 As shown in the bottom view, the routing modifications, including reconnection operations, are implemented using APR tools to address DRC and / or LVS violations found in intermediate layout 640. For example, to address a DRC violation related to too small a distance d2, additional routing components, i.e., horizontal routing 627, are added to the edge 617 of conductive pattern 407b to extend conductive pattern 407b in the X direction. To address DRC and LVS violations related to an open circuit at edge 619, additional routing components, i.e., horizontal routing 629, are added to the edge 619 of conductive pattern 409b to extend conductive pattern 409b in the X direction to pass under via 419 for electrical connection with conductive pattern 434 to meet relevant LVS requirements, and also extend a sufficient distance beyond the relative edge 621 of conductive pattern 434 to meet relevant DRC rules. Upon completion of the routing modifications with reconnection operations, a modified layout 650 with an amplification circuit region 610b and meeting various verifications is obtained.

[0120] Figure 7 This is a schematic diagram of the circuit region of an IC layout 700 in a disconnection operation having one or more fixed components, according to some embodiments.

[0121] exist Figure 7In an exemplary configuration, IC layout 700 includes circuit regions 701, 702, 703, and 704 corresponding to circuit regions 201, 202, 203, and 204 in IC layout 200. IC layout 700 also includes individual conductive patterns extending into and out of circuit regions 701, 702, 703, and 704 across corresponding boundaries (unnumbered) of the circuit regions. (See also: Regarding...) Figure 5 As described, a disconnection operation is performed along the boundary of the circuit region before scaling the circuit region. For example, a disconnection operation is performed to disconnect conductive patterns 711 and 712 extending into circuit region 701, as schematically shown by arrow 713. A disconnection operation is performed to disconnect conductive patterns 721 and 722 extending into circuit region 702, as schematically shown by arrow 723. A disconnection operation is performed to disconnect conductive patterns 731 and 732 extending into circuit region 703, as schematically shown by arrow 733. A disconnection operation is performed to disconnect conductive patterns 731 and 741 extending into circuit region 704, as schematically shown by arrows 742 and 743.

[0122] IC layout 700 also includes a fixing component. In some embodiments, the fixing component is any component included in a fixing area or otherwise marked as fixing, such as regarding Figure 6 As described. Exemplary fixing components include, but are not limited to, conductive patterns, through-holes, circuit elements (devices), networks, cells, etc. Figure 7 In the exemplary configuration, the fixing component includes a conductive pattern 760 and corresponding vias (not shown) electrically coupling the conductive pattern to other devices and / or conductive patterns. The fixing conductive pattern 760 extends across the boundary of one or more circuit regions, such as circuit regions 701, 702, and 703. The fixing conductive pattern 760 is unaffected by the respective scaling operations in circuit regions 701, 702, and 703, and is also unaffected by disconnect operations along the boundary of the circuit region. For example, although the fixing conductive pattern 760 extends across the boundary of circuit regions 701, 702, and 703, the fixing conductive pattern 760 is not disconnected by the respective disconnect operations schematically shown by arrows 713, 723, and 733. In other words, the disconnect operation is performed along the boundary of the circuit region without disconnecting the fixing component.

[0123] After performing the disconnection operation without disconnecting the fixed components, various scaling operations are performed to enlarge circuit regions 701 and 702 and reduce circuit regions 703 and 704, for example, as per [reference to...]. Figures 2B to 2C As described. Due to the scaling operation, in addition to the fixed conductive pattern 760, the individual conductive patterns and vias in the circuit regions 701-704 are rearranged and / or resized, for example, as per [the description of the scaling operation]. Figures 2A to 2B , Figure 5 , Figure 6As described. Subsequently, various wiring modifications, including reconnection operations, are implemented to restore electrical connections between corresponding components in the fixed and scaled circuit areas and / or between broken portions of the initial conductive pattern, as per [the description of the wiring modifications]. Figures 5 to 6 As described, modified layouts can be obtained, with each circuit region individually scaled to achieve optimal yield and / or performance while meeting various design rules and requirements.

[0124] In some embodiments, the layout is modified by zooming in (or expanding) or shrinking (or contracting) one or more regions of the layout. For example, by assigning the properties PUSH and / or FIXED in the APR tool to correspondingly set the push and / or fixation regions. When a region is zoomed, the fixation region overlapping the region to be zoomed will not be zoomed or will be moved. Push or move a push region that is related to but outside the region to be zoomed by a certain distance and / or in the direction corresponding to the zoom operation. Before and after zooming, for example, the commands CHOP and RE-CONNECT are correspondingly implemented by the APR tool to provide various ways to implement local zooming. In one or more embodiments, regarding Figure 3A and Figure 3B This describes an instance of the PUSH attribute, regarding Figure 6 and Figure 7 An instance of the FIXED property is described, regarding Figure 5 and Figure 7 It describes instances of the command CHOP (i.e., disconnect), and about Figure 4 , Figure 5 and Figure 6 An instance of the RE-CONNECT command is described.

[0125] Figure 8A This is a flowchart of a method 800A for manufacturing a semiconductor device or IC according to some embodiments.

[0126] According to some embodiments, method 800A can, for example, use EDA system 900 ( Figure 9 (Discussed below) and integrated circuits (ICs), manufacturing systems 1000 ( Figure 10 (This will be discussed below) to achieve this. Examples of semiconductor devices that can be manufactured according to method 800 include... Figure 2D IC 250, ICs corresponding to various layouts disclosed herein, etc.

[0127] exist Figure 8A In method 800A, operations 802 and 804 are included. In operation 802, a layout diagram is generated, which (among other things) includes one or more layout diagrams disclosed herein. According to some embodiments, operation 802 may, for example, be performed using an EDA system 1000 ( Figure 10(This will be discussed below) to achieve this. In some embodiments, the generated layout includes at least one circuit region, individually or locally scaled, as described herein. From operation 802, the process proceeds to operation 804.

[0128] In operation 804, based on the layout diagram, (A) one or more photolithographic exposures are performed, or (B) one or more semiconductor masks are fabricated, or (C) at least one of one or more components in a semiconductor device layer are fabricated, as described below regarding... Figure 10 As described.

[0129] Figure 8B This is a flowchart of a layout generation method 800B according to some embodiments. More specifically, Figure 8B The flowchart illustrates a demonstration according to one or more embodiments. Figure 8A Additional operations of an instance of the process implemented in operation 802. In at least one embodiment, method 800B is implemented by an APR tool. Figure 8B In method 800B, operations 810-824 are included, wherein operation 818 includes operations 830-838.

[0130] In operation 810, the layout is loaded into, for example, an APR tool. In some embodiments, the layout is as follows: Figure 1 This is generated within the described IC design flow. In some embodiments, the layout is a pre-existing layout loaded from a non-transitory, computer-readable storage medium. From operation 810, the flow proceeds to operation 812.

[0131] In operation 812, one or more circuit regions in the layout are selected for scaling. In some embodiments, the circuit regions are selected automatically and / or based on user input. In at least one embodiment, the selected circuit regions are highlighted, for example, on the screen of the display device to help the user quickly and / or easily see the selected circuit regions to be scaled, whether the selected circuit regions are to be enlarged or reduced, and to provide appropriate user input and / or corrections when prompted and / or requested by an automated system (e.g., an APR tool). About Figures 2A to 2D and Figure 7 Examples of individual circuit regions selected for scaling in the layout are described. From operation 812, the flow proceeds to operation 814.

[0132] In operation 814, at least one fixed region and / or at least one push region are set. The fixed region or fixed component does not scale or disconnect, even if the fixed region or fixed component is within the scaling circuit region. The push region will push or offset a distance corresponding to the scaling factor of the scaling circuit region, even if the push region is outside the scaling circuit region. Regarding... Figures 3A to 3B This describes an instance of the push region. About Figures 6 to 7Examples of fixed areas and / or fixed components are described. In at least one embodiment, the fixed area and / or push area are set by the user. The fixed area and / or push area are automatically set by an automation system, APR tool, or computer system within the scope of the various embodiments, as described herein. In at least one embodiment, "push area" and "fixed area" are characteristics or flags set by the user or automatically to guide subsequent operations of an automation system (e.g., an APR tool). In at least one embodiment, the push area and / or fixed area are set by using one or more layers of markers arranged above the area to be pushed or fixed. In some embodiments, operation 814 is omitted. From operation 814, the process proceeds to operation 816.

[0133] In operation 816, one or more conductive patterns extending across the boundary of the selected circuit region are broken along the boundary without breaking the associated fixed area and / or one or more fixed components crossing the boundary. Regarding Figure 5 , Figure 7 An exemplary disconnect operation is described. In some embodiments, the user sets whether to perform a disconnect operation on a selected circuit region. As described herein, the disconnect operation may be performed automatically by an automation system, APR tool, or computer system within the scope of the various embodiments. In some embodiments, operation 816 is omitted. From operation 816, the flow proceeds to operation 818.

[0134] In operation 818, the selected circuit area is scaled, without scaling the associated fixed area and / or scaling one or more fixed components within the circuit area. About Figures 2B to 2C , Figures 3A to 6 This describes an exemplary scaling operation performed automatically by an automated system or APR tool. About Figure 6 An exemplary scaling operation without scaling a fixed region or fixed component is described. Operation 818 is described in further detail herein. From operation 818, the process proceeds to operation 820.

[0135] In operation 820, when the push area is set in operation 814, the scaling operation is a magnification operation, and the push area overlaps with the scaling circuit area along the scaling direction. The APR tool pushes or offsets the push area along the scaling direction by a distance corresponding to a scaling factor, for example, ΔW. In some embodiments, pushing the push area corresponds to the cumulative distance of the sum of the size increases of the various scaling circuit areas. Regarding... Figures 3A to 3B An exemplary push operation is described. In some embodiments, such as when a push area is not set in operation 814, operation 820 is omitted. From operation 820, the process proceeds to operation 822.

[0136] In operation 822, a reconnection operation is performed by the APR tool to reconnect conductive patterns previously disconnected in operation 816, and / or to reconnect fixed components to corresponding components in the scaling circuit area, and / or to reconnect components that were initially electrically coupled together but disconnected due to the scaling operation. In some embodiments, the reconnection operation is performed in response to verification results returned from DRC and / or LVS verification. In at least one embodiment, the reconnection operation includes adjusting existing wiring components and / or adding at least one additional wiring component. Regarding Figures 4 to 6 An exemplary reconnection operation is described. The modified layout obtained from operation 822 undergoes the following... Figure 1 One or more verifications are described, and a signature is made for manufacturing when the verifications are met.

[0137] The scaling operation in operation 818 includes operations 830-838. About Figures 2B to 2C , Figures 4 to 6 Describe an exemplary scaling operation.

[0138] In operation 830, a new gate pattern pitch CPP, different from the current gate pattern pitch CPP of the layout, is received. In some embodiments, the new CPP is user input. In at least one embodiment, the new CPP is automatically generated or determined. From operation 830, the process proceeds to operation 832.

[0139] In operation 832, the APR tool performs device repositioning based on the new CPP. From operation 832, the process proceeds to operation 834.

[0140] In operation 834, a scaling factor is determined. In some embodiments, the scaling factor is the ratio of the new CPP to the current CPP. Based on the scaling factor, the change in the size of the scaling circuit region can be determined. In at least one embodiment, when the scaling operation is a magnification operation, the size of the scaling circuit region increases by ΔW as a distance to further push the push region along the scaling direction, as described with respect to operation 820. From operation 834, the flow proceeds to operation 836.

[0141] In operation 836, based on the scaling factor, the APR tool rearranges via locations and conductive patterns in a direction transverse to the scaling direction. For example, when the scaling direction is along the X-axis, the via locations and vertical wiring (conductive patterns extending along the Y-axis) are rearranged along the X-axis. Regarding... Figures 2B to 2C , Figures 4 to 6 An exemplary rearrangement of through-holes and vertical wiring is described. From operation 836, the process proceeds to operation 838.

[0142] In operation 838, the APR tool adjusts the size of the conductive pattern elongated along the scaling direction (i.e., horizontal wiring) based on the scaling factor. Regarding Figures 2B to 2CAn example of size adjustment is described. From operation 838, the process returns to operation 818, or proceeds to operation 820. In some embodiments, one or more advantages described herein may be achieved through a modified layout obtained from method 800B or through a correspondingly manufactured IC.

[0143] The described methods include exemplary operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated within the spirit and scope of embodiments of the invention. Embodiments combining different components and / or different embodiments are within the scope of the invention and will be apparent to those skilled in the art after reading this invention.

[0144] In some embodiments, at least one method discussed herein is implemented, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system discussed below.

[0145] Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0146] In some embodiments, the EDA system 900 includes an automated placement and wiring (APR) system. According to one or more embodiments, the design layout method described herein represents wire routing arrangements, and according to some embodiments, the method may be implemented using the EDA system 900.

[0147] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory, computer-readable storage medium 904. Among other things, the storage medium 904 is encoded with, i.e., stores computer program code 906, i.e., a set of executable instructions. The hardware processor 902 executes the instructions 906 to represent (at least in part) some or all of the EDA tools that implement some or all of the methods described herein (hereinafter, the processes and / or methods mentioned) according to one or more embodiments.

[0148] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is configured to execute computer program code 906 encoded in computer-readable storage medium 904, such that system 900 can be used to implement some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0149] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 904 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0150] In one or more embodiments, storage medium 904 stores computer program code 906 configured such that system 900 (where such execution (at least partially) represents an EDA tool) can be used to implement some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 904 also stores some or all of information that facilitates the implementation of the mentioned processes and / or methods. In one or more embodiments, storage medium 904 stores a standard cell library 907 including standard cells as disclosed herein. In one or more embodiments, storage medium 904 stores one or more layout diagrams 909 corresponding to one or more layouts disclosed herein.

[0151] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 902.

[0152] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows system 900 to communicate with network 914, to which one or more other computer systems are connected. Network interface 912 includes: a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-2164. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 900.

[0153] System 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 902. The information is transmitted to processor 902 via bus 908. EDA system 900 is configured to receive UI-related information via I / O interface 910. This information is stored as a user interface (UI) 942 on computer-readable medium 904.

[0154] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 900. In some embodiments, methods such as those available from CADENCE DESIGNSYSTEMS, Inc. are used. Use tools or another suitable layout generation tool to generate layout diagrams that include standard cells.

[0155] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory cells, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROMs, RAMs, memory cards, etc.

[0156] Figure 10This is a block diagram of an integrated circuit (IC) manufacturing system 1000 and associated IC manufacturing processes according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer is manufactured using the manufacturing system 1000.

[0157] exist Figure 10 In this IC manufacturing system 1000, entities such as design room 1020, mask room 1030, and IC manufacturer / fab 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC 1060. The entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1020, mask room 1030, and IC fabrication plant 1050 are owned by a single, larger company. In some embodiments, two or more of design room 1020, mask room 1030, and IC fabrication plant 1050 coexist in a shared facility and use shared resources.

[0158] Design studio (or design team) 1020 generates IC design layout 1022. IC design layout 1022 includes various geometric patterns designed for IC 1060. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC 1060 to be manufactured. The various layers are combined to form the various IC parts. For example, portions of IC design layout 1022 include various IC parts (such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads) to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1020 implements appropriate design procedures to form IC design layout 1022. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1022 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1022 may be represented in GDSII file format or DFII file format.

[0159] Mask chamber 1030 includes data preparation 1032 and mask fabrication 1044. Mask chamber 1030 uses an IC design layout 1022 to fabricate one or more masks 1045 for fabricating various layers of IC 1060 according to the IC design layout 1022. Mask chamber 1030 implements mask data preparation 1032, in which the IC design layout 1022 is converted into a representative data file (RDF). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1050. Figure 10 In this diagram, mask data preparation 1032 and mask manufacturing 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0160] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 1022). In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as a reverse imaging problem.

[0161] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules, including certain geometric and / or connectivity constraints to ensure sufficient margin, to check the IC design layout 1022 already processed in the OPC to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for lithographic implementation effects during mask fabrication 1044, which can undo some modifications implemented by the OPC to satisfy the mask creation rules.

[0162] In some embodiments, mask data preparation 1032 includes a lithography process check (LPC), which simulates the process to be implemented by IC fabrication plant 1050 to manufacture IC 1060. The LPC simulates this process based on IC design layout 1022 to create a simulated manufacturing device, such as IC 1060. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after creating a simulated manufacturing device via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further improve IC design layout 1022.

[0163] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional components, such as logic operations (LOPs), to modify the IC design layout 1022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in various different sequences.

[0164] After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or mask set 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more photolithographic exposures based on the IC design layout 1022. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) 1045 using an electron beam (e-beam) or a plurality of e-beams mechanism based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, the mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV)) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and pass through the transparent regions. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1045 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1045, the individual components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be an attenuation-type PSM or an alternating-type PSM. The mask produced by mask fabrication 1044 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form individual doped regions in semiconductor wafer 1053, in etching processes to form individual etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0165] IC manufacturing plant 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility for providing other services to the foundry enterprise.

[0166] IC manufacturing plant 1050 includes manufacturing tools 1052 configured to perform various manufacturing operations on semiconductor wafers 1053 to manufacture ICs 1060 according to a mask (e.g., mask 1045). In various embodiments, manufacturing tools 1052 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0167] IC manufacturing plant 1050 uses a mask 1045, manufactured by mask chamber 1030, to manufacture IC 1060. Therefore, IC manufacturing plant 1050 uses IC design layout 1022 at least indirectly to manufacture IC 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturing plant 1050 using mask 1045 to form IC 1060. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0168] In some embodiments, a method for modifying the layout of an integrated circuit (IC) includes: selecting a circuit region to be scaled in the layout; setting a fixed region including a fixed component in the selected circuit region; and scaling the selected circuit region without scaling the fixed region including the fixed component to obtain a modified layout of the IC.

[0169] In some embodiments, a system for modifying the layout of an integrated circuit (IC) includes a processor and a non-transitory computer-readable storage medium connected to the processor, wherein the processor is configured to execute instructions stored on the computer-readable storage medium. The processor selects a circuit region in the layout to be scaled along a first direction and disconnects a first conductive pattern extending in a second direction transverse to the first direction and across the boundary of the selected circuit region to an inner portion of the selected circuit region and an outer portion outside the selected circuit region. The processor scales the selected circuit region along the first direction and, in response to at least one of the following: a first determination that the inner and outer portions of the scaled circuit region are electrically disconnected from each other, or a second determination that at least one of the inner or outer portions of the scaled circuit region fails verification.

[0170] In some embodiments, the computer program product includes a non-transitory, computer-readable medium containing instructions. The instructions (when executed) cause a processor to select a circuit region to be scaled along a first direction in a layout for an integrated circuit (IC). The selected circuit region includes: a device having a plurality of gate patterns arranged along the first direction at a first gate pattern spacing; a first conductive pattern extending along the first direction; a second conductive pattern extending along a second direction transverse to the first direction; and a via. The processor is further caused to scale the selected circuit region along the first direction to obtain a modified layout without changing the gate pattern widths of the plurality of gate patterns. The scaling includes: repositioning the device having a plurality of gate patterns arranged along the first direction at a second gate pattern spacing different from the first gate pattern spacing; rearranging one or more of the second conductive pattern and the via along the first direction based on a scaling factor that is a ratio of the second gate pattern spacing to the first gate pattern spacing; and adjusting the size of one or more of the first conductive patterns along the first direction based on the scaling factor.

[0171] Some embodiments of this application provide a method for modifying the layout of an integrated circuit (IC), the method comprising: selecting a circuit region to be scaled in the layout; setting a fixed region including a fixed component in the selected circuit region; and scaling the selected circuit region without scaling the fixed region including the fixed component to obtain a modified layout for the IC. In some embodiments, the scaling includes changing the gate pattern spacing between adjacent gate patterns among a plurality of gate patterns in the selected circuit region by a scaling factor. In some embodiments, the scaling includes changing the gate pattern spacing between adjacent gate patterns among a plurality of gate patterns in the selected circuit region by a scaling factor without changing the gate pattern width of the plurality of gate patterns. In some embodiments, the scaling includes enlarging the selected circuit region along a first direction by a scaling factor, the setting further comprising setting a region overlapping the selected circuit region along the first direction as a push region, and the method further comprising pushing the push region along the first direction by a distance corresponding to the width of the selected circuit region and the scaling factor. In some embodiments, the selection further includes selecting a further circuit region to be scaled in the layout, the scaling further includes enlarging the selected further circuit region along the first direction by a further scaling factor, the push region overlapping the selected circuit region and the further circuit region along the first direction, and the push includes pushing the push region along the first direction by a further distance corresponding to the width of the selected further circuit region and the further scaling factor. In some embodiments, the fixing component includes a conductive pattern extending across the boundary of the selected circuit region. In some embodiments, the method further includes: after the scaling, adding or modifying at least one wiring component to at least one of the following: restoring the electrical connection between the fixing component and the corresponding component in the scaled circuit region, or satisfying a design rule. In some embodiments, the selected circuit region includes: a device positioned along a first direction at a first gate pattern spacing, a first conductive pattern extending along the first direction, a second conductive pattern extending along a second direction transverse to the first direction, and a via, and the scaling includes: repositioning the device along the first direction at a second gate pattern spacing, the second gate pattern spacing being different from the first gate pattern spacing; rearranging one or more of the second conductive pattern and the via along the first direction based on a scaling factor that is a ratio of the second gate pattern spacing to the first gate pattern spacing; and adjusting the size of one or more of the first conductive patterns along the first direction based on the scaling factor.In some embodiments, the scaling includes scaling the selected circuit region along a first direction, the layout including a conductive pattern extending in a second direction transverse to the first direction and across the boundary of the selected circuit region, and the method further includes: prior to the scaling, breaking the conductive pattern into an inner portion within the selected circuit region and an outer portion outside the selected circuit region, and after the scaling, reconnecting the inner and outer portions within the scaled circuit region. In some embodiments, the reconnection includes at least one of: extending the outer portion into the scaled circuit region to overlap with the inner portion, or adding at least one wiring component.

[0172] Other embodiments of this application provide a system for modifying a layout for an integrated circuit (IC), the system comprising: a processor; and a non-transitory computer-readable storage medium connected to the processor, wherein the processor is configured to execute instructions stored on the computer-readable storage medium to: select a circuit region to be scaled along a first direction in the layout; disconnect a first conductive pattern extending in a second direction transverse to the first direction and across the boundary of the selected circuit region into an inner portion of the selected circuit region and an outer portion outside the selected circuit region; scale the selected circuit region along the first direction; and reconnect the inner and outer portions of the scaled circuit region in response to at least one of: a first determination that the inner and outer portions of the scaled circuit region are electrically disconnected from each other, or a second determination that at least one of the inner or outer portions of the scaled circuit region fails verification. In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: implement the verification, the verification including at least one of: a design rule check, or a layout-to-schematic (LVS) check. In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: in response to a third determination that the inner portion and the outer portion of the scaling circuit region overlap each other at a distance greater than a predetermined minimum conductive pattern width, not attempt to reconnect the inner portion and the outer portion of the scaling circuit region. In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: reconnect the inner portion and the outer portion of the scaling circuit region by at least one of: extending the outer portion into the scaling circuit region to overlap with the inner portion, or adding at least one wiring component. In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: set a first anchor on the inner portion and a second anchor on the outer portion before disconnecting the first conductive pattern; and after scaling the selected circuit region, make at least one of the first determination or the second determination based on a first coordinate of the first anchor on the inner portion of the scaling circuit region and a second coordinate of the second anchor on the outer portion. In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: in response to setting a fixed region in the layout, the fixed region including a second conductive pattern extending across the boundary of the selected circuit region in the second direction, without separating the second conductive pattern, and scaling the selected circuit region without scaling the fixed region.In some embodiments, the at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: in response to setting a push region in the layout, the push region overlapping the selected circuit region along the first direction, to magnify the selected circuit region by a scaling factor, and to push the push region along the first direction by a distance corresponding to the width of the selected circuit region and the scaling factor.

[0173] Further embodiments of this application provide a computer program product including a non-transitory, computer-readable medium containing instructions that, when executed by a processor, cause the processor to: select a circuit region to be scaled along a first direction in a layout for an integrated circuit (IC), wherein the selected circuit region includes: a device having a plurality of gate patterns arranged along the first direction at a first gate pattern spacing, a first conductive pattern extending along the first direction, a second conductive pattern extending along a second direction transverse to the first direction, and a via; scaling the selected circuit region along the first direction to obtain a modified layout without changing the gate pattern widths of the plurality of gate patterns, wherein the scaling includes: implementing a repositioning of the device having the plurality of gate patterns arranged along the first direction at a second gate pattern spacing, the second gate pattern spacing being different from the first gate pattern spacing; rearranging one or more of the second conductive pattern and the via along the first direction based on a scaling factor as a ratio of the second gate pattern spacing to the first gate pattern spacing; and adjusting the size of one or more of the first conductive patterns along the first direction based on the scaling factor. In some embodiments, at least one of the second conductive patterns extends across the boundary of the selected circuit region in the second direction, and the instruction, when executed by the processor, further causes the processor to: before the scaling, disconnect the at least one second conductive pattern into an inner portion within the selected circuit region and an outer portion outside the selected circuit region, and after the scaling, perform wiring to reconnect the inner portion and the outer portion in the scaled circuit region. In some embodiments, the instruction, when executed by the processor, further causes the processor to: in response to setting a fixed region in the layout, the fixed region including a fixed conductive pattern extending across the boundary of the selected circuit region in the second direction, disconnect the at least one second conductive pattern without disconnecting the fixed conductive pattern, and scale the selected circuit region without scaling the fixed region.

[0174] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for modifying the layout for an integrated circuit (IC), the method comprising: Select the circuit area to be scaled in the layout; A fixed area including fixed components is provided in the selected circuit area; as well as The selected circuit region is scaled, but the fixed region including the fixed component is not scaled, to obtain a modified layout for the IC. The scaling includes changing the gate pattern spacing between adjacent gate patterns among a plurality of gate patterns in the selected circuit region by means of a scaling factor, wherein the scaling factor is the ratio of the size or width of the selected circuit region after scaling to the size or width of the selected circuit region before scaling. in, The scaling includes scaling the selected circuit region along a first direction. The layout includes a conductive pattern extending in a second direction transverse to the first direction and across the boundary of the selected circuit region, and Prior to the scaling, the conductive pattern is broken into an inner portion within the selected circuit region and an outer portion outside the selected circuit region, and After the scaling, reconnecting the inner and outer portions of the scaling circuit region includes: Extend the external portion into the scaling circuit region; Add a conductive pattern that overlaps with the extended outer portion and the inner portion; Add vias to electrically couple the conductive pattern to the extended outer portion and the inner portion.

2. The method according to claim 1, wherein The selected circuit region is scaled along the first and second directions with the same or different scaling factors.

3. The method according to claim 1, wherein The scaling includes changing the gate pattern spacing between adjacent gate patterns among a plurality of gate patterns in the selected circuit region by means of the scaling factor, without changing the gate pattern width of the plurality of gate patterns.

4. The method according to claim 1, wherein The scaling includes magnifying the selected circuit region along a first direction using the scaling factor. The setting further includes defining the region overlapping the selected circuit region along the first direction as a push region, and The method further includes pushing the push area along the first direction at a distance corresponding to the width of the selected circuit area and the scaling factor.

5. The method according to claim 4, wherein The selection also includes choosing further circuit regions to scale within the layout. The scaling also includes magnifying the selected further circuit region along the first direction by a further scaling factor. The pushing region overlaps with the selected circuit region and the further circuit region along the first direction, and The push includes pushing the push area along the first direction at a distance corresponding to the width of the selected further circuit area and the further scaling factor.

6. The method according to claim 1, wherein The fixing component includes a conductive pattern extending across the boundary of the selected circuit region.

7. The method according to claim 1, further comprising: Following the scaling, at least one wiring component will be added to or modified to at least one of the following: Restore the electrical connection between the fixed component and the corresponding component in the scaling circuit area, or Meets design rules.

8. The method according to claim 1, wherein The selected circuit region includes: The device is placed along a first direction with a first gate pattern spacing. A first conductive pattern extends along the first direction. The second conductive pattern extends along a second direction transverse to the first direction, and Through holes, and The scaling includes: The device is repositioned along the first direction with a second gate pattern spacing, which is different from the first gate pattern spacing. Based on the scaling factor, which is the ratio of the second gate pattern pitch to the first gate pattern pitch, the second conductive pattern and one or more of the vias are rearranged along the first direction. Based on the scaling factor, the size of one or more of the first conductive patterns is adjusted along the first direction.

9. The method according to claim 1, further comprising: Perform validation on the modified layout, the validation including at least one of the following: Design rule check; Check the layout against the schematic diagram.

10. The method of claim 9, wherein The layout check compares the modified layout netlist generated with the designed schematic netlist.

11. A system for modifying the layout of an integrated circuit (IC), the system comprising: processor; as well as A non-transitory computer-readable storage medium is connected to the processor, wherein the processor is configured to execute instructions stored on the computer-readable storage medium to: Select the circuit area to be scaled along the first direction in the layout. The first conductive pattern, extending in a second direction transverse to the first direction and across the boundary of the selected circuit region, is broken into an inner portion within the selected circuit region and an outer portion outside the selected circuit region. Scaling the selected circuit region along the first direction, and In response to at least one of the following, the internal and external portions of the scaling circuit region are reconnected: a first determination that the internal and external portions of the scaling circuit region are electrically disconnected from each other, or a second determination that at least one of the internal or external portions of the scaling circuit region fails verification. The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: Reconnecting the inner portion and the outer portion in the scaling circuit region includes: extending the outer portion into the scaling circuit region; adding a conductive pattern that overlaps with the extended outer portion and the inner portion; and adding vias that correspondingly electrically couple the conductive pattern to the extended outer portion and the inner portion.

12. The system according to claim 11, wherein, The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: The verification is performed, and the verification includes at least one of the following: Design rule checks, or Layout check against schematic diagram (LVS).

13. The system according to claim 11, wherein, The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: In response to a third determination that the inner portion and the outer portion of the scaling circuit region overlap each other at a distance greater than a predetermined minimum conductive pattern width, no attempt is made to reconnect the inner portion and the outer portion of the scaling circuit region.

14. The system according to claim 12, wherein, The layout check compares the modified layout netlist generated with the designed schematic netlist.

15. The system according to claim 11, wherein, The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: Before disconnecting the first conductive pattern, a first anchor is provided on the inner portion, and a second anchor is provided on the outer portion. After scaling the selected circuit region, at least one of the first determination or the second determination is made based on the first coordinate of the inner portion of the first anchor in the scaled circuit region and the second coordinate of the second anchor on the outer portion.

16. The system according to claim 11, wherein, The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: In response to setting a fixed region in the layout, the fixed region comprising a second conductive pattern extending across the boundary of the selected circuit region in the second direction. Without breaking the second conductive pattern, and Scale the selected circuit region, but not the fixed region.

17. The system according to claim 11, wherein, The at least one processor is further configured to execute instructions stored on the computer-readable storage medium to: In response to setting a push area in the layout, the push area overlapping the selected circuit area along the first direction. The selected circuit region is magnified by a scaling factor, and The pushing area is pushed along the first direction, corresponding to the width of the selected circuit area and the distance of the scaling factor.

18. A computer program product comprising a non-transitory, computer-readable medium containing instructions that, when executed by a processor, cause the processor to perform: In the layout for integrated circuits (ICs), select the circuit region to be scaled along a first direction, where, The selected circuit region includes: a device having a plurality of gate patterns arranged along the first direction at a first gate pattern spacing; a first conductive pattern extending along the first direction; a second conductive pattern extending along a second direction transverse to the first direction; and a via. The selected circuit region is scaled along a first direction to obtain a modified layout without changing the gate pattern width of the plurality of gate patterns, wherein the scaling includes: repositioning a device having the plurality of gate patterns arranged along the first direction at a second gate pattern spacing different from the first gate pattern spacing; rearranging one or more of the second conductive patterns and the vias along the first direction based on a scaling factor that is a ratio of the second gate pattern spacing to the first gate pattern spacing; and adjusting the size of one or more of the first conductive patterns along the first direction based on the scaling factor. in, At least one of the second conductive patterns extends across the boundary of the selected circuit region in the second direction, and The instructions, when executed by the processor, further cause the processor to: Prior to the scaling, the at least one second conductive pattern is broken into an inner portion within the selected circuit region and an outer portion outside the selected circuit region. After scaling, wiring is performed to reconnect the inner portion and the outer portion in the scaling circuit region, including: extending the outer portion into the scaling circuit region; adding a conductive pattern that overlaps with the extended outer portion and the inner portion; and adding vias that electrically couple the conductive pattern to the extended outer portion and the inner portion accordingly.

19. The computer program product of claim 18, wherein the instructions, when executed by the processor, further cause the processor to: Perform validation on the modified layout, the validation including at least one of the following: Design rule check; Check the layout against the schematic diagram.

20. The computer program product according to claim 19, wherein, The instructions, when executed by the processor, further cause the processor to: In response to setting a fixed region in the layout, the fixed region comprising a fixed conductive pattern extending across the boundary of the selected circuit region in the second direction. The implementation involves disconnecting the at least one second conductive pattern without disconnecting the fixed conductive pattern, and The selected circuit region is scaled, but the fixed region is not scaled.

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