Display panel and display device

Abstract

This application discloses a display panel and a display device, belonging to the field of display technology. The display panel includes multiple pixel circuits, multiple gate lines, multiple data lines, multiple electrically controlled switches, a control circuit, and two row drive circuits. Each data line is connected to a pixel circuit located in the same column and to the control circuit. Each gate line is connected to a pixel circuit located in the same row, and both ends of each gate line are connected to a row drive circuit. At least one electrically controlled switch is disposed on each gate line. The control circuit is connected to each electrically controlled switch and each row drive circuit. The control circuit controls the opening and closing of the multiple electrically controlled switches and controls the two row drive circuits to output scanning signals at a first scanning frequency and a second scanning frequency, respectively. Using this application, the high refresh rate requirements of the application are met without requiring the entire display area of ​​the display panel to display at a high refresh rate, thus reducing display power consumption.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, display method, and display device. Background Technology

[0002] In recent years, with the rapid development of the display industry, display screens have been applied to various industries, such as mobile phones, wristbands, watches, automotive displays, laptops, televisions, and so on.

[0003] As industries such as gaming continue to develop and demand high refresh rates from display panels, consumers are placing increasingly higher demands on display panels, with high refresh rate and even ultra-high refresh rate display panels gradually becoming needed across various industries.

[0004] However, increasing the overall refresh rate of the display panel will lead to a significant increase in display power consumption. Summary of the Invention

[0005] This application provides a display panel and a display device that can solve the technical problems existing in related technologies. The technical solutions of the display panel and display device are as follows:

[0006] On one hand, embodiments of this application provide a display panel, which includes multiple pixel circuits, multiple gate lines, multiple data lines, multiple electronically controlled switches, a control circuit (also known as a control IC (Integrated Circuit)) and two row drive circuits;

[0007] Each data line is connected to a pixel circuit located in the same column and is also connected to the control circuit.

[0008] Each gate line is connected to a pixel circuit located in the same row, and each end of each gate line is connected to a row drive circuit. Each gate line is equipped with at least one electronically controlled switch.

[0009] The control circuit is connected to each electronically controlled switch and each row drive circuit. The control circuit is used to control the opening or closing of the plurality of electronically controlled switches and to control the two row drive circuits to output scanning signals at a first scanning frequency and a second scanning frequency, respectively.

[0010] In one possible implementation, the electronically controlled switch is a multiplexer (MUX).

[0011] In one possible implementation, each grid line is provided with an electronically controlled switch, and the plurality of electronically controlled switches are arranged in a straight line;

[0012] The control circuit is used to control all of the plurality of electronically controlled switches to be turned on, and the first scanning frequency is the same as the second scanning frequency; or, it is used to control all of the plurality of electronically controlled switches to be turned off, and the first scanning frequency is different from the second scanning frequency.

[0013] In one possible implementation, the line containing the plurality of electronically controlled switches is perpendicular to the extension direction of the grid line.

[0014] In one possible implementation, the plurality of electronically controlled switches are located in the middle of the display area of ​​the display panel.

[0015] In one possible implementation, the display panel further includes a first switch control line, which is connected to the control circuit and the plurality of electronically controlled switches respectively.

[0016] In one possible implementation, each grid line is provided with n electronically controlled switches, and the multiple electronically controlled switches are arranged in an m-row × n-column matrix, where n is an integer greater than 1 and m is the number of grid lines;

[0017] The control circuit is used to control all of the plurality of electronically controlled switches to be turned on, and the first scanning frequency is the same as the second scanning frequency; or, it is used to control the electronically controlled switch in the i-th column of the n columns to be turned off and the electronically controlled switches in the other columns to be turned on, and the first scanning frequency is different from the second scanning frequency.

[0018] In one possible implementation, the display panel further includes multiple second switch control lines, each of which is connected to an electronically controlled switch in a different column and to a control circuit.

[0019] In one possible implementation, for each gate line, in each pixel circuit on the gate line, the pixel circuits within the target distance range of the electrically controlled switch on the gate line are all display pixel circuits, and the pixel circuits outside the target distance range of the electrically controlled switch on the gate line include display pixel circuits and dummy pixel circuits.

[0020] In one possible implementation, for each gate line, the light-emitting elements in the plurality of display pixel circuits on the gate line are evenly arranged.

[0021] On the other hand, embodiments of this application provide a display device, the display device including a display panel as described in any of the preceding claims.

[0022] The technical solutions provided by the embodiments of this application have at least the following beneficial effects:

[0023] This application provides a display panel. When only a portion of the display area is used to display the interface of an application requiring a high refresh rate, the control circuit can divide the display area of ​​the display panel into at least two display partitions by controlling the opening or closing of multiple electronically controlled switches. The refresh rates of the two display partitions are independently controlled by controlling the first and second scanning frequencies of two row drive circuits. This achieves high refresh rate display for one display partition corresponding to the application and low refresh rate display for the other. While meeting the high refresh rate requirement of the application, it eliminates the need to control the entire display area of ​​the display panel to display at a high refresh rate, reducing power consumption and increasing the battery life of the display device.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a display panel shown in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the structure of an LTPS single-gate transistor shown in an embodiment of this application;

[0028] Figure 3 This is a circuit diagram of an LTPS single-gate transistor shown in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the structure of an LTPS dual-gate transistor shown in an embodiment of this application;

[0030] Figure 5 This is a circuit diagram of an LTPS dual-gate transistor shown in an embodiment of this application;

[0031] Figure 6 This is a schematic diagram of the structure of an IGZO transistor shown in an embodiment of this application;

[0032] Figure 7 This is a circuit diagram of an IGZO transistor shown in an embodiment of this application;

[0033] Figure 8This is a timing diagram illustrating the operation of a display panel according to an embodiment of this application;

[0034] Figure 9 This is a schematic diagram of the structure of a display panel shown in an embodiment of this application;

[0035] Figure 10 This is a schematic diagram of the structure of a display panel shown in an embodiment of this application;

[0036] Figure 11 This is a timing diagram illustrating the operation of a display panel according to an embodiment of this application;

[0037] Figure 12 This is a timing diagram illustrating the operation of a display panel according to an embodiment of this application;

[0038] Figure 13 This is a timing diagram illustrating the operation of a display panel according to an embodiment of this application;

[0039] Figure 14 This is a schematic diagram of the structure of a display panel shown in an embodiment of this application.

[0040] Legend

[0041] 1. Pixel circuit; 2. Gate line; 3. Data line; 4. Electronic switch; 5. Control circuit; 6. Horizontal drive circuit; 7. First switch control line; 8. Second switch control line;

[0042] 41. Active pattern; 42. Gate pattern; 43. First electrode; 44. Second electrode; 45. Oxide layer; 421. First gate pattern; 422. Second gate pattern. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application, such as... Figure 1 As shown, the display panel may include multiple pixel circuits 1, multiple gate lines 2, multiple data lines 3, multiple electronically controlled switches 4, control circuits 5, and two row drive circuits 6.

[0045] Among them, multiple pixel circuits 1 are arranged in a preset manner for displaying images on the display panel.

[0046] Each gate line 2 is connected to multiple pixel circuits 1 located in the same row. The two ends of each gate line 2 are connected to a row driving circuit 6 respectively. The gate line 2 is used to provide scanning signals to the switching transistors in the pixel circuit 1 to control the switching transistors to turn on and off.

[0047] Each data line 3 is connected to multiple pixel circuits 1 located in the same column and to the control circuit 5. The data line 3 is used to provide data signals to the pixel circuits 1 through switching transistors to enable the display of different images on the display panel.

[0048] At least one electronically controlled switch 4 is provided on each grid line 2. That is, only one electronically controlled switch 4 can be provided on each grid line 2, or multiple electronically controlled switches 4 can be provided. The number of electronically controlled switches 4 provided on each grid line 2 can be equal or unequal. This application embodiment does not limit this.

[0049] The control circuit 5 is connected to each electronic switch 4 and each row drive circuit 6. The control circuit 5 is used to control the opening or closing of multiple electronic switches 4 and to control the two row drive circuits 6 to output scanning signals at the first scanning frequency and the second scanning frequency, respectively.

[0050] When the electronically controlled switch 4 on a grid line 2 is turned on, the two row drive circuits 6 are connected. The control circuit 5 can control the first scanning frequency and the second scanning frequency of the two row drive circuits 6 to be the same, so as to output the same scanning signal. The two row drive circuits 6 jointly control the multiple pixel circuits 1 on the grid line 2, which can realize the synchronous display of the display panel. For example, it can realize the high refresh rate display or low refresh rate display of the entire display area on the display panel.

[0051] When one of the electronically controlled switches 4 on a grid line 2 is closed, the two row drive circuits 6 can be independently controlled. That is, the row drive circuit 6 located on the left side of the display panel can send scan signals to the multiple pixel circuits 1 located to the left of the electronically controlled switch 4 at a first scan frequency, but cannot send scan signals to the multiple pixel circuits 1 located to the right of the electronically controlled switch 4. Similarly, the row drive circuit 6 located on the right side of the display panel can send scan signals to the multiple pixel circuits 1 located to the right of the electronically controlled switch 4 at a second scan frequency, but cannot send scan signals to the multiple pixel circuits 1 located to the left of the electronically controlled switch 4.

[0052] When one electronic switch 4 on each grid line 2 is turned off simultaneously, the pixel circuit 1 of each row can be divided into left and right parts, thereby dividing the display area of ​​the display panel into two display zones, which are independently controlled by a row drive circuit 6.

[0053] When the display device is in operation, if only a portion of the display area shows applications requiring a high refresh rate, while other parts of the display area show applications that do not require a high refresh rate, the above control method can be used to achieve independent control of the left and right display partitions. The scanning frequency of the line drive circuit 6 corresponding to the display partition containing the application requiring a high refresh rate can be controlled to achieve a high refresh rate, while the scanning frequency of the line drive circuit 6 corresponding to the other display partition can be controlled to achieve a low refresh rate. This achieves frequency division display between the two display partitions. In this way, the high refresh rate requirement of the application can be met without setting the entire display area of ​​the display panel to a high refresh rate for that application, thereby reducing display power consumption and increasing the battery life of the display device.

[0054] In summary, this application provides a display panel where, when only a portion of the display area is used to display the interface of an application requiring a high refresh rate, the control circuit 5 can divide the display area into two display partitions by controlling the opening and closing of multiple electronic switches 4. Furthermore, by controlling the first and second scanning frequencies of the two row drive circuits 6, the refresh rates of the two display partitions can be independently controlled. This achieves high refresh rate display for the application's corresponding display partition and low refresh rate display for the other partition. While meeting the application's high refresh rate requirement, it eliminates the need to control the entire display area of ​​the display panel for high refresh rate display, reducing power consumption and increasing the display device's battery life.

[0055] In one possible implementation, the method for controlling the first and second scan frequencies of the two row driving circuits 6 to be the same or different is as follows: the control circuit 5 sends a first GSTV signal to the first row driving circuit 6 to cause it to send a scan signal at the first scan frequency to the pixel circuit 1, and sends a second GSTV signal to the second row driving circuit 6 to cause it to send a scan signal at the second scan frequency to the pixel circuit 1. When the first GSTV signal and the second GSTV signal are at the same frequency, the first scan frequency and the second scan frequency are the same; when the first GSTV signal and the second GSTV signal are not at the same frequency, the first scan frequency and the second scan frequency are different.

[0056] It is understandable that the frequency of the GSTV signal is the same as the frequency of the data signal sent by the data line 3 to the pixel circuit 1. The data signal received by the multiple pixel circuits 1 corresponding to the first GSTV signal is the first data signal, and the data signal received by the multiple pixel single-channel 1 corresponding to the second GSTV signal is the second data signal. Therefore, the first GSTV signal and the first data signal have the same frequency, and the second GSTV signal and the second data signal have the same frequency.

[0057] In one possible implementation, the display panel in this embodiment may further include multiple compensation units, which may include compensation capacitors or compensation resistors. Each compensation unit is connected to a gate line 2, and all compensation units are connected to the control circuit 5. When controlling the two display zones to perform frequency division display, the control circuit 5 can control these multiple compensation units to perform brightness compensation for multiple pixel circuits 1 in the two display zones, thereby improving the uniformity of brightness in the two display zones and improving the display performance of the display panel.

[0058] In one possible implementation, the electronic switch 4 can be any type of electronic switch capable of performing the above functions. In this embodiment, a multiplexer is used as the electronic switch 4.

[0059] In one possible implementation, the multiplexer can be any of an LTPS (Low Temperature Poly-silicon) single-gate transistor, an LTPS dual-gate transistor, and an IGZO (indium gallium zinc oxide) transistor.

[0060] like Figure 2 and Figure 3 As shown, when the multiplexer is an LTPS single-gate transistor, the electronically controlled switch 4 may include an active pattern 41, a gate pattern 42, a first electrode 43, and a second electrode 44. The active pattern 41 and the gate pattern 42 have an overlapping portion, thereby forming a gate. The active pattern 41 can be connected to the first electrode 43 and the second electrode 44 through vias, where the first electrode 43 and the second electrode 44 can be the source and the drain, respectively, or they can be the drain and the source, respectively. It should be noted that the source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In this embodiment, in order to distinguish the transistor, except for the gate, which serves as the control electrode, one of the source and drain is directly described as the first electrode, and the other is described as the second electrode. Therefore, in this embodiment, the first and second electrodes of all or part of the transistors can be interchanged as needed.

[0061] When the gate receives a high-frequency switching control signal, the LTPS single-gate transistor closes (opens); when the gate receives a low-frequency switching control signal, the LTPS single-gate transistor opens (closes).

[0062] like Figure 4 and Figure 5As shown, when the multiplexer is an LTPS dual-gate transistor, similarly to the above, the electronically controlled switch 4 includes an active pattern 41, a gate pattern 42, a first electrode 43, and a second electrode 44. The active pattern 41 may include two branches, both of which are connected to the gate pattern 42, thus forming a dual-gate structure. The two branches are also connected to the first electrode 43 and the second electrode 44 respectively through vias. The use of an LTPS dual-gate transistor can effectively improve the leakage protection effect of the electronically controlled switch 4.

[0063] The LTPS dual-gate transistor closes when the gate receives a high-frequency switching control signal, and turns off when the gate receives a low-frequency switching control signal.

[0064] like Figure 6 and Figure 7 As shown, when the multiplexer is an IGZO transistor, the electronically controlled switch 4 may include a gate pattern 42, a first electrode 43, a second electrode 44, and an oxide layer 45. The gate pattern 42 may include a first gate pattern 421 and a second gate pattern 422, which overlap with the oxide layer 45, thereby forming the top gate and bottom gate of the IGZO transistor. The oxide layer 45 can be connected to the first electrode 43 and the second electrode 44 through vias.

[0065] The IGZO transistor closes when the gate (including the top and bottom gates) receives a low-frequency switching control signal, and turns on when the gate transmits a high-frequency switching control signal.

[0066] In the embodiments of this application, the three types of transistors described above are merely examples. The multiplexer can also be any other reasonable type of transistor or combination of transistors, and the embodiments of this application do not limit this.

[0067] In this application embodiment, the electric control switch 4 can be configured in several ways. Two of these configurations are described in more detail below:

[0068] The first setting method of electric control switch 4

[0069] like Figure 1 As shown, each grid line 2 is equipped with an electronically controlled switch 4, and multiple electronically controlled switches 4 are arranged in a straight line.

[0070] These multiple electronic switches 4 can divide the multiple pixel circuits 1 of the display panel into two parts, the left side and the right side of the straight line. That is, the display area of ​​the display panel is divided into two display zones, left and right, with the straight line where the multiple electronic switches 4 are located as the boundary line.

[0071] When displaying on the display panel, the control circuit 5 can be used to control all of the multiple electronic switches 4 to be turned on, with the first scanning frequency being the same as the second scanning frequency, or to control all of the multiple electronic switches 4 to be turned off, with the first scanning frequency being different from the second scanning frequency.

[0072] When the control circuit 5 controls all the multiple electronic switches 4 to open, and the first scanning frequency is the same as the second scanning frequency, the entire display area of ​​the display panel can be displayed at the same frequency. The following describes two scenarios of display at the same frequency:

[0073] 1. When the display interface of an application requiring a high refresh rate overlaps with both left and right display zones, the control circuit 5 can control all the electronic switches 4 to open, thereby enabling joint control of the two horizontal drive circuits 6. The first and second scanning frequencies of the two horizontal drive circuits 6 are made the same and equal to the pre-stored scanning frequency corresponding to the application, thus achieving a high refresh rate display across the entire display area of ​​the display panel. For example, in... Figure 8 In the fourth frame, the switch control signal is a low-level signal (the switch control signal is the switch control signal of the electronic switch 4), that is, the control circuit 5 controls the electronic switch 4 to be in the open state. The control circuit 5 also sends high-frequency first GSTV signal and second GSTV signal to the two row drive circuits 6 respectively, and sends high-frequency first data signal and second data signal to the pixel circuit 1 through the data line 3, so as to realize the high refresh rate display of the entire display area of ​​the display panel.

[0074] Understandable, Figure 8 , Figure 11 , 12 The switch control signals in 13 are all illustrated using an N-type transistor as an example. When the electronic switch 4 is an N-type transistor, a low-level switch control signal can control the electronic switch 4 to open, and a high-level switch control signal can control the electronic switch 4 to close. This is just an example. In the embodiments of this application, the electronic switch 4 can also be a P-type transistor, that is, a high-level switch control signal can control the electronic switch 4 to open, and a low-level switch control signal can control the electronic switch 4 to close.

[0075] 2. When the display panel requires an application that does not require a high refresh rate to be displayed across the entire display area, the control circuit 5 can control all the electronic switches 4 to open, thereby enabling the joint control of the two horizontal drive circuits 6. The first and second scanning frequencies of the two horizontal drive circuits 6 are made the same and equal to the pre-stored scanning frequency corresponding to the application, thus achieving a low refresh rate display across the entire display area. For example, in... Figure 8In the first frame, the switch control signal is a low-level signal, that is, the control circuit 5 controls the electronic switch 4 to be in the open state. The control circuit 5 also sends low-frequency first GSTV signal and second GSTV signal to the two row drive circuits 6 respectively, and sends low-frequency first data signal and second data signal to the pixel circuit 1 through the data line 3, so as to realize the low refresh rate display of the entire display area of ​​the display panel.

[0076] When the control circuit 5 controls all the multiple electronic switches 4 to be turned off, and the first scanning frequency is different from the second scanning frequency, frequency division display of the two display zones of the display panel can be realized. The following is an introduction to the frequency division display scenario:

[0077] When the display interface of an application requiring a high refresh rate overlaps only with one display partition and not with the other, the control circuit can turn off all the electronic switches 4, thereby enabling independent control of the two line drive circuits 6. One line drive circuit 6 controls the first scan frequency in the left display partition, and the other line drive circuit 6 controls the second scan frequency of multiple pixel circuits 1 in the right display partition. The scan frequency of the line drive circuit 6 corresponding to the display partition where the application with a high refresh rate requirement is located is higher than the scan frequency of the other line drive circuit 6. This achieves a high refresh rate for the display partition where the application with a high refresh rate requirement is located and a low refresh rate for the other display partition. While meeting the high refresh rate requirement of the application, it is not necessary to set the high refresh rate of the entire display area of ​​the display panel, thereby reducing display power consumption and improving the battery life of the display device.

[0078] For example, in Figure 8 In the second frame, the switch control signal is a high-level signal, that is, the control circuit 5 controls the electronic switch 4 to be in the closed state. The control circuit 5 also sends a high-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition, and sends a high-frequency first data signal to the multiple data lines 3 corresponding to the left display partition, so as to realize the high refresh rate display of the left display partition of the display panel. The control circuit 5 also sends a low-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition, and sends a low-frequency second data signal to the multiple data lines 3 corresponding to the right display partition, so as to realize the low refresh rate display of the right display partition of the display panel.

[0079] Here's an example of an application scenario for the second frame described above: A user opens a game application on the terminal's display interface and shrinks the game application's display interface to the left-hand display partition. The area outside the game application's display interface is used to display applications that do not require a high refresh rate (e.g., novel readers, browsers, etc.). The terminal can pre-store the refresh rate requirements of each application, where the game application requires a high refresh rate.

[0080] For example, in Figure 8 In the third frame, the switch control signal is a high-level signal, meaning that the control circuit 5 controls the electronic switch 4 to be in the off state. The control circuit 5 also sends a low-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition, and sends a low-frequency first data signal to the multiple data lines 3 corresponding to the left display partition, so as to realize the low refresh rate display of the left display partition of the display panel. The control circuit 5 also sends a high-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition, and sends a high-frequency second data signal to the multiple data lines 3 corresponding to the right display partition, so as to realize the high refresh rate display of the right display partition of the display panel.

[0081] Here's an example of an application scenario for the third frame: A user opens a game application on the terminal's display interface and shrinks the game application's display interface to the right-hand display partition. The area outside the game application's display interface is used to display applications that do not require a high refresh rate. The terminal can pre-store the refresh rate requirements of each application, where the game application requires a high refresh rate.

[0082] In the above-listed application scenarios of same-frequency display and frequency division display, the method for determining whether the display panel performs same-frequency display or frequency division display, and the method for determining which side of the display partition achieves high refresh rate display when the display panel performs frequency division display, are determined based on the area range of the display interface of the application that the user requires a high refresh rate in the display area. The determination method listed above is only one of the determination methods, and other reasonable methods can also be used. This application embodiment does not limit this. For example, when the overlapping area of ​​the display interface of an application requiring a high refresh rate with the two display partitions is greater than or equal to a preset percentage threshold in each display partition, the display panel can be controlled to display applications with a high refresh rate at the same frequency. When the display panel displays applications that do not require a high refresh rate, or when the overlapping area of ​​the display interface of an application requiring a high refresh rate with the two display partitions is less than a preset percentage threshold in each display partition, the display panel can be controlled to display applications with a low refresh rate at the same frequency. When the overlapping area of ​​the display interface of an application requiring a high refresh rate with the first display partition is greater than or equal to a preset percentage threshold in the first display partition, and the overlapping area with the second display partition is less than a preset percentage threshold in the second display partition, the display panel can be controlled to perform frequency division display, with the first display partition displaying at a high refresh rate and the second display partition displaying at a low refresh rate. The preset percentage threshold can be any reasonable value. For example, its value range can be any value between [30%, 50%]. Of course, it can also be a value within other reasonable ranges. This application embodiment does not limit this.

[0083] Multiple electronically controlled switches 4 are arranged along a straight line. The position of this straight line determines the division of the two display zones. The position of the multiple electronically controlled switches 4 along the straight line can be set according to the actual needs of the display device to achieve local high refresh rate applications.

[0084] In one possible implementation, the straight line containing multiple electronically controlled switches 4 can be arbitrarily arranged in the display panel as needed. Typically, when displaying the content of multiple applications on a display device, the display area is regularly divided for user operation and viewing. Therefore, in this embodiment, the straight line containing multiple electronically controlled switches 4 can be set perpendicular to the extension direction of the grid line 2. In this way, the display area of ​​the display panel can be divided into two display partitions in the horizontal direction, which is more suitable for the user's regular operation and improves the applicability of the local high refresh rate display scheme.

[0085] Of course, the straight line containing multiple electronic switches 4 can also be set not perpendicular to the extension direction of the grid line 2. In this way, the display area of ​​the display panel can be irregularly divided. The specific division method can be set according to the requirements, and this application embodiment does not limit it.

[0086] In one possible implementation, when the line containing the electronic switch 4 is set perpendicular to the extension direction of the grid line 2, the position of the line in the display area can also be set according to actual needs.

[0087] For example, it can be like Figure 1 As shown, multiple electronically controlled switches 4 are positioned in the middle of the display area of ​​the display panel, which divides the display area into two display partitions, left and right, from the middle position. This makes it suitable for most partitioned display scenarios, allowing local high refresh rate displays to be applied in more usage scenarios, thereby minimizing display power consumption and improving the battery life of the display device.

[0088] Alternatively, multiple electronic switches 4 can be positioned in other locations. When applications requiring high refresh rates typically occupy a small or large portion of the display area, the multiple electronic switches 4 can be positioned slightly to the left or right. This divides the display panel into two partitions, one large and one small, thereby achieving localized high refresh rate display. For example, ... Figure 9 As shown, when an application requiring a high refresh rate needs to occupy a small portion of the display area on the left side of the display panel, multiple electronic switches 4 can be positioned on the left side of the display area. This divides the display area into a small display partition on the left and a large display partition on the right. When controlling the display of the application requiring a high refresh rate, all multiple electronic switches 4 can be turned off. Then, the row drive circuit 6 corresponding to the left display partition can be controlled to achieve a higher first scan frequency for the application, while the row drive circuit 6 corresponding to the right display partition can be controlled to achieve a lower second scan frequency, thereby achieving a localized high refresh rate display.

[0089] In one possible implementation, the display panel may further include a first switch control line 7, which is connected to the control circuit 5 and multiple electronic switches 4 respectively. This arrangement facilitates the control circuit 5 to synchronously control the opening or closing of multiple electronic switches 4, reducing resource waste and improving control accuracy compared to the scheme where the control circuit 5 controls multiple electronic switches 4 individually.

[0090] In one possible implementation, the multiple electronic switches 4 may not be arranged along the same straight line, but rather along two or even more straight lines. For example, the electronic switches 4 arranged on a predetermined number of grid lines 2 near the top of the display area are arranged along a first straight line, while the remaining electronic switches 4 arranged on the grid lines 2 near the bottom of the display area are arranged along a second straight line. Both the first and second straight lines are perpendicular to the extension direction of the grid lines 2, and the first and second straight lines are not collinear. In this way, the display area of ​​the display panel can be divided irregularly. For example, the first straight line may be located on the left side of the display area, and the second straight line may be located in the middle of the display area, and so on.

[0091] Here's an example of an application scenario for this partitioning method: When a display device needs to simultaneously display two applications with high refresh rate requirements on the left side of the display area, and the widths of the two applications' display interfaces are different, the two applications can be arranged vertically on the left side of the display area. Specifically, one application's display interface is placed near the top of the left side of the display area, and the other application's display interface is placed near the bottom. The first straight line is positioned at the right boundary of the application's display interface near the top, and the second straight line is positioned at the right boundary of the application's display interface near the bottom. During display, the control circuit 5 can control all multiple electronic switches 4 to be turned off, and control the first scanning frequency of the row drive circuit 6 corresponding to the left display partition to be higher than the second scanning frequency of the row drive circuit 6 corresponding to the right display partition, thereby achieving high refresh rate display for the two applications on the left side of the display area.

[0092] The second setting method for the electric control switch 4

[0093] Each grid line 2 is equipped with n electronically controlled switches 4. The multiple electronically controlled switches 4 are arranged in a matrix of m rows × n columns, where n is an integer greater than 1 and m is the number of grid lines 2.

[0094] In this array of m rows × n columns of electronically controlled switches 4, each column of switches 4 can divide the display area. Therefore, this array of m rows × n columns of electronically controlled switches 4 can divide the display area of ​​the display panel horizontally into n+1 sub-areas. For example, ... Figure 10 As shown, each grid line 2 is equipped with 3 electronic switches 4, arranged in an m x 3 matrix. These 3 columns of electronic switches 4 divide the display area into four sub-areas, which can be named A1, A2, A3 and A4 from left to right.

[0095] When the display panel is displaying, the control circuit 5 is used to control all of the multiple electronic switches 4 to be turned on, and the first scanning frequency is the same as the second scanning frequency. Alternatively, the control circuit 5 controls the i-th column of the n columns of electronic switches 4 to be turned off and the other columns of electronic switches 4 to be turned on, and the first scanning frequency is different from the second scanning frequency.

[0096] When the control circuit 5 controls all the multiple electronic switches 4 to open, and the first scanning frequency is the same as the second scanning frequency, the entire display area of ​​the display panel can be displayed at the same frequency. The following is an introduction to the scenario of displaying at the same frequency:

[0097] When the display interface of an application requiring a high refresh rate overlaps with each sub-area, the control circuit 5 can control all the electronic switches 4 to open, thereby achieving joint control of the two horizontal drive circuits 6. It also controls the first and second scanning frequencies of the two horizontal drive circuits 6 to be the same and equal to the pre-stored scanning frequency corresponding to the application, thus achieving a high refresh rate display across the entire display area of ​​the display panel. For example, Figure 11 The timing shown in the fourth frame, Figure 12 The timing shown in the fourth frame and Figure 13 The timing sequence shown in the fourth frame is as follows, where the switch control signal for M1 is... Figure 10 The switching control signals of multiple electrically controlled switches 4 located on line M1, and the switching control signal of M2 are... Figure 10 The switching control signals of multiple electrically controlled switches 4 located on line M2, and the switching control signal of M3 are... Figure 10 From the switching control signals of the multiple electrically controlled switches 4 located on line M3, it can be seen that... Figure 11 , Figure 12 and Figure 13 In the fourth frame, the switching control signals of all the electronic switches 4 on lines M1, M2 and M3 are low-level signals, that is, the control circuit 5 controls all the electronic switches 4 to be in the open state. The control circuit 5 also sends high-frequency first GSTV signal and second GSTV signal to the two line drive circuits 6 respectively, and sends high-frequency first data signal and second data signal to the pixel circuit 1 through data line 3, so as to realize high refresh rate display of the entire display area of ​​the display panel.

[0098] When the display panel requires an application that does not require a high refresh rate to be displayed across the entire display area, the control circuit 5 can control all the electronic switches 4 to open, thereby enabling joint control of the two horizontal drive circuits 6. The first and second scanning frequencies of the two horizontal drive circuits 6 are made the same and equal to the pre-stored scanning frequency corresponding to the application, thus achieving a low refresh rate display across the entire display area. For example, Figure 11 The timing shown in the first frame of the video, Figure 12 The timing shown in the first frame and Figure 7 As shown in the first frame timing diagram, it can be seen that the switching control signals of all the electronically controlled switches 4 on lines M1, M2 and M3 are low-level signals, that is, the control circuit 5 controls all the electronically controlled switches 4 to be in the on state. The control circuit 5 also sends low-frequency first GSTV signal and second GSTV signal to the two line drive circuits 6 respectively, and sends low-frequency first data signal and second data signal to the pixel circuit 1 through data line 3, so as to realize the low refresh rate display of the entire display area of ​​the display panel.

[0099] When the control circuit 5 controls any column of electronic switches 4 in the n columns to close, and the first scanning frequency is different from the second scanning frequency, the display area of ​​the display panel can be divided into two display zones to achieve frequency division display of the two display zones. The following is an introduction to the frequency division display scenario:

[0100] When the display interface of an application requiring a high refresh rate overlaps with the entire display area, but does not overlap with at least one sub-area located at the two edges of the display area (i.e., at least one sub-area on the far left and at least one sub-area on the far right), the control circuit 5 can divide these multiple sub-areas into two display partitions by controlling the opening or closing of the electronic control switch 4, and achieve frequency division display of the two display partitions by controlling the first scanning frequency and the second scanning frequency of the two line drive circuits 6.

[0101] Furthermore, the above-mentioned frequency division display method can be further divided into the following three cases:

[0102] In the first scenario: when the display interface of an application requiring a high refresh rate overlaps with at least one first sub-region located on the far left of the display area but does not overlap with at least one second sub-region located on the far right of the display area, the control circuit 5 can control the column of electronically controlled switches 4 between the first and second sub-regions to close and the other columns of electronically controlled switches 4 to open. This divides the multiple sub-regions of the display area into two display partitions. The left display partition includes the first sub-region that overlaps with the application's display interface, and the right display partition includes the second sub-region that does not overlap with the application's display interface. The control circuit 5 can also control the first scanning frequency of the row driving circuit 6 corresponding to the left display partition to be higher than the second scanning frequency of the row driving circuit 6 corresponding to the right display partition. This achieves a high refresh rate display for the left display partition and a low refresh rate display for the right display partition, eliminating the need to control the entire display area to display at a high refresh rate due to the application's high refresh rate requirement. This reduces display power consumption and increases the battery life of the display device.

[0103] by Figure 10 Taking the display panel as an example, Figure 10 The three columns of electronically controlled switches 4 divide the display area into four sub-areas, from left to right: A1, A2, A3, and A4.

[0104] Example 1: When the display interface of an application requiring a high refresh rate is located within sub-region A1 (i.e., the display interface of the application requiring a high refresh rate only overlaps with sub-region A1, and does not overlap with A2, A3, and A4), please refer to... Figure 11 The timing sequence shown in the second frame is used for control, namely: the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M1 line to control the electronically controlled switch 4 on the M1 line to close, thereby dividing these four sub-areas into two display partitions. The left display partition only includes the A1 sub-area, and the right display partition includes the three sub-areas A2, A3, and A4. The control circuit 5 also sends a high-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition, and sends a high-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a high refresh rate display of the left display partition, thereby achieving a high refresh rate display of the application's display interface. The control circuit 5 also sends a low-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition, and sends a low-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a low refresh rate display of the right display partition.

[0105] Second example: When the display interface of an application requiring a high refresh rate overlaps with sub-regions A1 and A2, but does not overlap with sub-regions A3 and A4, please refer to... Figure 12 The control circuit is implemented using the timing shown in the second frame of the image. Specifically, the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M2 line to close the switch, thereby dividing the four sub-areas into two display partitions. The left display partition includes sub-areas A1 and A2, and the right display partition includes sub-areas A3 and A4. The control circuit 5 also sends a high-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition and a high-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a high refresh rate display for the left display partition, thus enabling a high refresh rate display for the application's display interface. The control circuit 5 also sends a low-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition and a low-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a low refresh rate display for the right display partition.

[0106] Third example: When the display interface of an application requiring a high refresh rate overlaps with sub-regions A1, A2, and A3, but not with sub-region A4, please refer to... Figure 13 The timing sequence shown in the second frame is used for control. Specifically, the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M3 line to control the electronically controlled switch 4 on the M3 line to close, thereby dividing these four sub-areas into two display partitions. The left display partition includes sub-areas A1, A2, and A3, while the right display partition only includes sub-area A4. The control circuit 5 also sends a high-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition and a high-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a high refresh rate display for the left display partition, thus achieving a high refresh rate display for the application's display interface. The control circuit 5 also sends a low-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition and a low-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a low refresh rate display for the right display partition.

[0107] In the second scenario, when the display interface of an application requiring a high refresh rate overlaps with at least one third sub-region on the far right of the display area but does not overlap with at least one fourth sub-region on the far left of the display area, the control circuit 5 can control the column of electronic switches 4 between the third and fourth sub-regions to close and the other columns of electronic switches 4 to open. This divides the multiple sub-regions of the display area into two display partitions. The left display partition includes the aforementioned third sub-region that overlaps with the application's display interface, and the right display partition includes the aforementioned fourth sub-region that does not overlap with the application's display interface. The control circuit 5 can also control the first scanning frequency of the row driving circuit 6 corresponding to the left display partition to be lower than the second scanning frequency of the row driving circuit 6 corresponding to the right display partition. This achieves low refresh rate display in the left display partition and high refresh rate display in the right display partition, eliminating the need to control the entire display area to display at a high refresh rate due to the application's high refresh rate requirement. This reduces display power consumption and increases the battery life of the display device.

[0108] by Figure 10 Taking the display panel as an example, Figure 10 The three columns of electronically controlled switches 4 divide the display area into four sub-areas, from left to right: A1, A2, A3, and A4.

[0109] Example 1: When the display interface of an application requiring a high refresh rate overlaps with sub-regions A2, A3, and A4, but not with sub-region A1, please refer to... Figure 11The control is performed according to the timing shown in the third frame of the image. Specifically, the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M1 line to close the electronically controlled switch 4 on the M1 line, thereby dividing the four sub-areas into two display partitions. The left display partition only includes the A1 sub-area, and the right display partition includes the three sub-areas A2, A3, and A4. The control circuit 5 also sends a low-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition and a low-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a low refresh rate display in the left display partition. The control circuit 5 also sends a high-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition and a high-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a high refresh rate display in the right display partition, thereby achieving a high refresh rate display for the application's display interface.

[0110] Second example: When the display interface of an application requiring a high refresh rate overlaps with both sub-regions A3 and A4, but does not overlap with either sub-regions A1 or A2, please refer to... Figure 12 The control is performed according to the timing shown in the third frame of the image. Specifically, the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M2 line to close the electronically controlled switch 4 on the M2 line, thereby dividing the four sub-areas into two display partitions. The left display partition includes sub-areas A1 and A2, and the right display partition includes sub-areas A3 and A4. The control circuit 5 also sends a low-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition and a low-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a low refresh rate display in the left display partition. The control circuit 5 also sends a high-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition and a high-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a high refresh rate display in the right display partition, thereby achieving a high refresh rate display for the application's display interface.

[0111] Third example: When the display interface of an application requiring a high refresh rate is located within the A4 sub-area (i.e., the display interface of the application requiring a high refresh rate only overlaps with the A4 sub-area, and does not overlap with A1, A2, or A3), please refer to... Figure 13The timing sequence shown in the third frame is used for control. Specifically, the control circuit 5 sends a high-level signal to the electronically controlled switch 4 on the M3 line to control the electronically controlled switch 4 on the M3 line to close, thereby dividing these four sub-areas into two display partitions. The left display partition includes sub-areas A1, A2, and A3, while the right display partition only includes sub-area A4. The control circuit 5 also sends a low-frequency first GSTV signal to the row drive circuit 6 corresponding to the left display partition and a low-frequency first data signal to the multiple data lines 3 corresponding to the left display partition to achieve a low refresh rate display in the left display partition. The control circuit 5 also sends a high-frequency second GSTV signal to the row drive circuit 6 corresponding to the right display partition and a high-frequency second data signal to the multiple data lines 3 corresponding to the right display partition to achieve a high refresh rate display in the right display partition, thereby achieving a high refresh rate display for the application's display interface.

[0112] The third scenario: When the display interface of an application requiring a high refresh rate does not overlap with at least one fifth sub-region on the far left, at least one sixth sub-region on the far right, but overlaps with at least one seventh sub-region (the seventh sub-region is the sub-region between the fifth and sixth sub-regions), if the area of ​​the fifth sub-region is smaller than the area of ​​the sixth sub-region, the control circuit 5 can control the column of electronically controlled switches 4 between the sixth and seventh sub-regions to turn off, thereby dividing the multiple sub-regions of the display area into two display partitions. The left display partition includes the fifth and seventh sub-regions, and the right display partition includes the sixth sub-region. The control circuit 5 can also control the row drive corresponding to the left display partition. The first scanning frequency of path 6 is higher than the second scanning frequency of the row driving circuit 6 corresponding to the right display partition, thereby realizing high refresh rate display of the left display partition and low refresh rate display of the right display partition. It is not necessary to control the entire display area to display at a high refresh rate due to the application's high refresh rate requirements. Compared with other solutions (e.g., low refresh rate display of the fifth sub-region and high refresh rate display of the sixth and seventh sub-regions), this solution displays the larger sixth sub-region at a low refresh rate. While ensuring the application's high refresh rate display, it maximizes the area of ​​the low refresh rate display area, further reducing display power consumption and improving the display device's battery life.

[0113] by Figure 10 Taking the display panel as an example, Figure 10 The three rows of electronically controlled switches 4 in the middle divide the display area into four sub-areas, which are A1, A2, A3 and A4 from left to right. These four sub-areas have equal areas.

[0114] When the display interface of an application requiring a high refresh rate is located within sub-region A2 (i.e., the display interface of the application requiring a high refresh rate only overlaps with sub-region A2, and does not overlap with A1, A3, and A4), sub-region A1 is equivalent to the fifth sub-region mentioned above, sub-regions A3 and A4 are equivalent to the sixth sub-region mentioned above, and sub-region A2 is equivalent to the seventh sub-region mentioned above. Since the area of ​​the fifth sub-region is smaller than the area of ​​the sixth sub-region, this situation can be referred to... Figure 12 The timing is controlled according to the second frame shown in the image. The specific timing details have been described in detail above and will not be repeated here. This control allows sub-regions A1 and A2 to achieve high refresh rate display, while sub-regions A3 and A4 achieve low refresh rate display. While achieving high refresh rate display for the application, the area of ​​the low refresh rate display is maximized, reducing display power consumption and improving the battery life of the display device.

[0115] If the area of ​​the fifth sub-region is larger than the area of ​​the sixth sub-region, the control circuit 5 can control the column of electronically controlled switches 4 between the fifth and seventh sub-regions to turn off, thereby dividing the multiple sub-regions of the display area into two display partitions. The left display partition includes the fifth sub-region, and the right display partition includes the sixth and seventh sub-regions. The control circuit 5 can also control the first scanning frequency of the row driving circuit 6 corresponding to the left display partition to be lower than the second scanning frequency of the row driving circuit 6 corresponding to the right display partition, thereby realizing low refresh rate display of the left display partition and high refresh rate display of the right display partition. In this way, the fifth sub-region, which has a larger area, is displayed at a low refresh rate. While ensuring the high refresh rate display of the application, the area of ​​the low refresh rate display area is increased as much as possible, further reducing display power consumption and improving the battery life of the display device.

[0116] by Figure 10 Taking the display panel as an example, when the display interface of an application requiring a high refresh rate is located within the A3 sub-region (i.e., the display interface of the application requiring a high refresh rate only overlaps with the A3 sub-region, and does not overlap with A1, A2, and A4), the A1 and A2 sub-regions are equivalent to the fifth sub-region mentioned above, the A4 sub-region is equivalent to the sixth sub-region mentioned above, and the A3 sub-region is equivalent to the seventh sub-region mentioned above. Since the area of ​​the fifth sub-region is larger than the area of ​​the sixth sub-region, this situation can be referred to... Figure 12The timing is controlled according to the sequence shown in the third frame of the image. The specific timing details have been described in detail above and will not be repeated here. This control allows sub-regions A1 and A2 to achieve low refresh rate display, while sub-regions A3 and A4 achieve high refresh rate display. While achieving high refresh rate display for the application, it maximizes the area of ​​the low refresh rate display area, reduces display power consumption, and improves the battery life of the display device.

[0117] If the area of ​​the fifth sub-region is equal to the area of ​​the sixth sub-region, the control circuit 5 can select either the column of electronically controlled switches 4 between the fifth and seventh sub-regions to be turned off, or vice versa, thereby dividing the multiple sub-regions of the display area into two display partitions. It is understandable that since the areas of the fifth and sixth sub-regions are equal, both displaying the fifth and sixth sub-regions at a low refresh rate can achieve the goal of minimizing display power consumption.

[0118] When the area of ​​the fifth sub-region is equal to the area of ​​the sixth sub-region, it can be preset. The specific setting method can be any reasonable method, and this application embodiment does not limit it. For example, it can be preset that when the area of ​​the fifth sub-region is equal to the area of ​​the sixth sub-region, the control circuit 5 can control the column of electronically controlled switches 4 between the fifth and seventh sub-regions to be closed. Or, it can be preset that when the area of ​​the fifth sub-region is equal to the area of ​​the sixth sub-region, the column of electronically controlled switches 4 between the sixth and seventh sub-regions is controlled to be closed. Or, when the area of ​​the fifth sub-region is equal to the area of ​​the sixth sub-region, one of the above two columns of electronically controlled switches can be randomly selected to be closed, and so on.

[0119] In one possible implementation, the distance between any two adjacent columns of electronically controlled switches 4 in the display panel can be equal or unequal. When the distance between any two adjacent columns of electronically controlled switches 4 is equal, the n columns of electronically controlled switches 4 uniformly divide the display area of ​​the display panel. When the distance is unequal, the specific position of each column of electronically controlled switches 4 can be arbitrarily arranged according to actual needs, and this embodiment does not limit this arrangement.

[0120] In one possible implementation, the display panel further includes multiple second switch control lines 8, each second switch control line 8 being connected to a different column of electronically controlled switches 4 and also connected to the control circuit 5. This arrangement allows the control circuit 5 to synchronously control the opening or closing of any column of electronically controlled switches 4, reducing resource waste and improving control accuracy.

[0121] In this embodiment, if an electronically controlled switch 4 is to be connected to each gate line 2, the multiple pixel circuits 1 and electronically controlled switches 4 on the gate line 2 need to be arranged. This embodiment provides an arrangement method, namely: Figure 14 As shown, for each gate line 2, in each pixel circuit 1 on the gate line 2, the pixel circuit 1 within the target distance range of the electronically controlled switch 4 on the gate line 2 are all display pixel circuits, and the pixel circuit 1 outside the target distance range of the electronically controlled switch 4 on the gate line 2 includes display pixel circuits and dummy pixel circuits.

[0122] Typically, multiple pixel circuits 1 are arranged periodically on each gate line 2 according to preset rules and distances. The pixel circuits 1 connected on each gate line 2 may include display pixel circuits and dummy pixel circuits. The display pixel circuit includes a driving circuit and a light-emitting element. The driving circuit can drive the light-emitting element to emit light, while the dummy pixel circuit does not have a light-emitting element and cannot drive the light-emitting element to emit light.

[0123] On each gate line 2, the arrangement of the display pixel circuit and the dummy pixel circuit can be either four-in-one or eight-in-one. In the four-in-one arrangement, one dummy pixel circuit is connected after every four display pixel circuits. In the eight-in-one arrangement, one dummy pixel circuit is connected after every eight display pixel circuits.

[0124] In this embodiment, since setting the electronically controlled switch 4 in the circuit requires a certain area, after determining the target position of each grid line 2 where the electronically controlled switch 4 needs to be connected, the dummy pixel circuits in the multiple pixel circuits 1 on the grid line 2 that are within the target distance range from the target position can be removed. That is, the dummy pixel circuits in the multiple pixel circuits 1 located on the left and right sides of the target position within the target distance range are all removed, leaving only the display pixel circuits. Then, the multiple display pixel circuits located on the left side of the target position within the target distance range are moved to the left to fill the gap left after removing the dummy pixel circuits. Similarly, the multiple display pixel circuits located on the right side of the target position within the target distance range are moved to the right to fill the gap left after removing the dummy pixel circuits in the right area. In this way, a certain space can be left between the multiple display pixel circuits on the left and right sides of the target position, and the leftover space can be used to arrange the electronically controlled switch 4.

[0125] This configuration eliminates the need to occupy the space of the original display pixel circuit in the display panel to accommodate the electronic control switch 4, thereby improving the stability of the display panel.

[0126] For example, such as Figure 14In the display panel shown, the pixel circuits 1 within the target distance range of the electronic switch 4 are all display pixel circuits, while the pixel circuits 1 outside the target distance range of the electronic switch 4 are four-in-one display pixel circuits and dummy pixel circuits.

[0127] The target distance can be set according to the width of the electronically controlled switch 4, but this embodiment does not limit this.

[0128] In one possible implementation, for each gate line 2, the light-emitting elements in the multiple display pixel circuits on the gate line 2 are evenly arranged.

[0129] In implementation, after removing the dummy pixel circuits within the target distance range of each grid line 2 and moving the display pixel circuits to both sides to fill the original positions of the dummy pixel circuits, only the driving circuit of the display pixel circuit can be moved, while the position of the light-emitting element of the display pixel circuit remains unchanged. The positions of the light-emitting elements of all display pixel circuits on each grid line 2 are still evenly arranged according to the preset rules and distances. In this way, while arranging the electronic control switch 4, the display function of the display panel will not be affected, thus improving the stability of the display panel.

[0130] The technical solutions provided by the embodiments of this application have at least the following beneficial effects:

[0131] This application provides a display panel. When only a portion of the display area is used to display the interface of an application requiring a high refresh rate, the control circuit 5 can control the opening and closing of multiple electronic switches 4 to divide the display area of ​​the display panel into two display partitions. The refresh rates of the two display partitions can be independently controlled by controlling the first and second scanning frequencies of the two row drive circuits 6. This achieves high refresh rate display for one display partition corresponding to the application and low refresh rate display for the other display partition. While meeting the high refresh rate requirement of the application, it is not necessary to control the entire display area of ​​the display panel to display at a high refresh rate, thus reducing display power consumption and improving the battery life of the display device.

[0132] This application also provides a display device, which includes any of the above-described display panels.

[0133] Optionally, the display device can be an AMOLED (Active-Matrix Organic Light-Emitting Diode) display device, specifically, it can be a mobile phone, a smart bracelet, a watch, an in-vehicle display device, a laptop, a television, etc.

[0134] When a user wants to display applications requiring high refresh rates (e.g., games) in a specific display area of ​​the display device and applications not requiring high refresh rates (e.g., browsers, readers, etc.) in other display areas, the two horizontal drive circuits 6 can be independently controlled by opening or closing multiple electronically controlled switches 4 in the display panel. These circuits output scanning signals at different first and second scanning frequencies, respectively, to achieve high refresh rate display in the display area containing the application requiring high refresh rates and low refresh rate display in the other display area. This satisfies the high refresh rate requirements of the application while minimizing display power consumption and extending the display device's battery life.

[0135] In one possible implementation, the display device in this application embodiment may be a large-sized display device for displaying multiple parts of content. The content with high refresh rate requirements is displayed at a high refresh rate in a display partition on one side, while other content without high refresh rate requirements is displayed at a low refresh rate in a display partition on the other side.

[0136] In one possible implementation, the display device in this application embodiment can also be a flexible display device. In flexible display devices, the screen is often divided into two or more sub-regions by flexible bending. Each sub-region can display applications with different functions. In this case, the display area can be frequency-divided for display control according to demand, thereby achieving local high refresh rate display while minimizing display power consumption and improving the battery life of the display device.

[0137] In the embodiments of this application, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the description of the “open” operation of the electronic switch 4 may also be referred to as the “close” operation, and correspondingly, the “close” operation of the electronic switch 4 may also be referred to as the “disconnect” operation.

[0138] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0139] Spatial relative terms such as “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0140] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Specific features, structures, materials, or characteristics described in this specification may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of different embodiments or examples, without contradiction.

[0141] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel circuits, multiple gate lines, multiple data lines, multiple electronically controlled switches, multiple compensation units, control circuits, and two row drive circuits; Each data line is connected to a pixel circuit located in the same column and is also connected to the control circuit. Each gate line is connected to a pixel circuit located in the same row, and each end of each gate line is connected to a row drive circuit. Each gate line is equipped with at least one electronically controlled switch. The compensation unit includes a compensation capacitor or a compensation resistor, each compensation unit is connected to one of the gate lines, and all of the multiple compensation units are connected to the control circuit. The control circuit is connected to each electronically controlled switch and each row drive circuit. The control circuit is used to control the multiple compensation units to perform brightness compensation for the multiple pixel circuits when controlling the opening or closing of the multiple electronically controlled switches and controlling the two row drive circuits to output scanning signals at the first scanning frequency and the second scanning frequency, respectively. For each gate line, in each pixel circuit on the gate line, the pixel circuits within the target distance range of the electronically controlled switch on the gate line are all display pixel circuits, and the pixel circuits outside the target distance range of the electronically controlled switch on the gate line include display pixel circuits and dummy pixel circuits. For each gate line, the light-emitting elements in the multiple display pixel circuits on the gate line are evenly arranged.

2. The display panel according to claim 1, characterized in that, The electrical control switch is a multiplexer.

3. The display panel according to claim 1, characterized in that, Each grid line is provided with an electronically controlled switch, and the multiple electronically controlled switches are arranged in a straight line; The control circuit is used to control all of the plurality of electronically controlled switches to be turned on, and the first scanning frequency is the same as the second scanning frequency; or, it is used to control all of the plurality of electronically controlled switches to be turned off, and the first scanning frequency is different from the second scanning frequency.

4. The display panel according to claim 3, characterized in that, The straight line containing the plurality of electronically controlled switches is perpendicular to the extension direction of the grid line.

5. The display panel according to claim 4, characterized in that, The plurality of electronically controlled switches are located in the middle of the display area of ​​the display panel.

6. The display panel according to claim 3, characterized in that, The display panel also includes a first switch control line, which is connected to the control circuit and the plurality of electronically controlled switches respectively.

7. The display panel according to claim 1, characterized in that, Each grid line is equipped with n electronically controlled switches, and the multiple electronically controlled switches are arranged in an m-row × n-column matrix, where n is an integer greater than 1 and m is the number of grid lines; The control circuit is used to control all of the plurality of electronically controlled switches to be turned on, and the first scanning frequency is the same as the second scanning frequency; or, it is used to control the electronically controlled switch in the i-th column of the n columns to be turned off and the electronically controlled switches in the other columns to be turned on, and the first scanning frequency is different from the second scanning frequency.

8. The display panel according to claim 7, characterized in that, The display panel also includes multiple second switch control lines, each of which is connected to an electronically controlled switch in a different column and to a control circuit.

9. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-8.

Images