Array substrate, display panel and display device

Abstract

The present application discloses an array substrate, a display panel and a display device. The array substrate includes a display area and a peripheral area disposed around the display area. The peripheral area includes a straight area and a corner area. The array substrate includes a substrate and a driving circuit layer formed on one side of the substrate. The driving circuit layer includes a plurality of driving circuits located in the peripheral area. The plurality of driving circuits are arranged along the extending direction of the edge of the peripheral area. A stress relief channel is formed between at least some of the driving circuits located in the corner area. The stress relief channel includes stress relief holes and an organic material layer filled in the stress relief holes. The array substrate provided by the present application can effectively reduce the generation of wrinkles and reduce the probability of cracks caused by extrusion during the deformation process by providing the stress relief channel, thereby effectively improving the display quality.

Description

Technical Field

[0001] This application belongs to the technical field of display, and particularly relates to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, the requirement for the screen-to-body ratio of display devices is getting higher and higher. Flexible display panels have the advantages of being bendable, having good flexibility, being thin and light in volume, and having low power consumption. They can be attached to a cover plate with a curved surface to meet people's extreme pursuit of narrow-bezel or borderless displays. However, in related technologies, wrinkles and cracks are likely to occur at the arc angle positions of display devices, seriously affecting the display quality. Summary of the Invention

[0003] The embodiments of the present application provide a bonding device and a bonding method. By providing stress relief channels in the array substrate, the generation of wrinkles can be effectively reduced, and the probability of cracks caused by extrusion during the deformation process can be reduced, thereby effectively improving the display quality.

[0004] An embodiment of the first aspect of the embodiments of the present application provides an array substrate, including a display area and a peripheral area disposed around the display area. The peripheral area includes a straight area and a corner area. The array substrate includes:

[0005] A substrate;

[0006] A driving circuit layer formed on one side of the substrate, including a plurality of driving circuits located in the peripheral area. The plurality of driving circuits are arranged along the extending direction of the edge of the peripheral area. A stress relief channel is formed between at least some of the driving circuits located in the corner area. The stress relief channel includes a stress relief hole and an organic material layer filled in the stress relief hole.

[0007] An embodiment of the second aspect of the present application further provides a display panel, including the array substrate provided in the first aspect of the present application.

[0008] An embodiment of the third aspect of the present application further provides a display device, including the display panel provided in the second aspect of the present application.

[0009] The array substrate provided by the present application includes a plurality of driving circuits located in the peripheral region, and the plurality of driving circuits are arranged along the extending direction of the edge of the peripheral region. The array substrate further includes a plurality of pixel circuits located in the display region and light-emitting units connected to the pixel circuits. The driving circuits are connected to the pixel circuits and are used to provide electrical signals for the pixel circuits to drive the light-emitting units to emit light. At least part of the driving circuits in the corner region form the above-mentioned stress relief channels for stress relief. Specifically, when the display panel having the array substrate is attached to the curved cover plate, the display panel is prone to redundancy in the corner region when adapting to the shape of the curved cover plate, so that wrinkles appear in the corner region of the attached display panel. After forming the above-mentioned stress relief channels in the corner region of the array substrate, the deformed stress can be absorbed when the display panel adapts to the shape of the curved cover plate, thereby reducing the generation of wrinkles. The stress relief channel includes stress relief holes and an organic material layer filled in the stress relief holes. The stress relief holes provide space for the absorption of deformation. The organic material layer can fill the step difference brought by the stress relief holes. At the same time, since the organic material layer uses organic materials, the flexibility and bending performance of the organic materials are strong, and the absorption effect of deformation is good. Therefore, the bending resistance of the corner region can be improved, the generation of wrinkles can be effectively reduced, and the probability of cracks caused by extrusion during the deformation process can be reduced. Brief Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application;

[0012] Figure 2 is Figure 1 an enlarged view of the P region in

[0013] Figure 3 is Figure 2 a cross-sectional view along N-N' in

[0014] Figure 4 is Figure 1 an enlarged view of the Q region in

[0015] Figure 5 is Figure 2 another cross-sectional view along N-N' in

[0016] Figure 6 is Figure 2 another cross-sectional view along N-N' in

[0017] Figure 7 is Figure 2 Another cross-sectional view along N-N' in

[0018] Figure 8 is Figure 2 Another cross-sectional view along N-N' in

[0019] Figure 9 is Figure 1 Another enlarged view of region P in

[0020] Figure 10 is Figure 1 Another enlarged view of region P in

[0021] Figure 11 is Figure 1 Another enlarged view of region P in

[0022] Figure 12 It is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0023] Figure 13 It is a schematic structural diagram of a display device provided by an embodiment of the present application.

[0024] In the drawings:

[0025] 1 - Array substrate; AA - Display area; NA - Peripheral area; NA1 - Straight area; NA2 - Corner area; 10 - Substrate; 11 - Driving circuit layer; 111 - Driving circuit; 112 - Stress relief channel; 113 - Stress relief hole; 114 - Organic material layer; 115 - Gate insulating layer; 116 - First insulating layer; 117 - Second insulating layer; 118 - Third insulating layer; 119 - Fourth insulating layer; 120 - Fifth insulating layer; 121 - Buffer layer; 122 - First metal layer; 1221 - First connection line; 123 - Second metal layer; 1231 - Second connection line; 124 - Pixel circuit; 125 - Semiconductor layer; 126 - Gate metal layer; 127 - Capacitor metal layer; L1 - First edge; L2 - Second edge; L3 - Edge of the peripheral area; 2 - Display panel; 3 - Display device; 3 - Display device. Detailed implementation manners

[0026] Next, the features and exemplary embodiments of various aspects of the present application will be described in detail. In the following detailed description, many specific details are set forth in order to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0027] It should be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0028] The inventors have found through research that in a curved display device, due to redundancy at the arc angle position after the display panel is bent, wrinkles are likely to occur when it is attached to the curved cover plate, and cracks are likely to appear at the arc angle position of the display panel, resulting in display failure. Both the cracks and wrinkles seriously affect the display quality. Based on the research of the above problems, the inventors provide an array substrate, a display panel and a display device to improve the display quality.

[0029] For a better understanding of the present application, the following will be combined with Figures 1 to 13 The array substrate, display panel and display device according to the embodiments of the present application will be described in detail.

[0030] Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application; Figure 2 is Figure 1 an enlarged view of the P region in Figure 3 is Figure 2 a cross-sectional view along N-N' in

[0031] Please refer to Figure 1 、 Figure 2 and Figure 3 According to the embodiments of the present application, an array substrate 1 is provided, which includes a display area AA and a peripheral area NA arranged around the display area AA. The peripheral area NA includes a straight area NA1 and a corner area NA2. The array substrate 1 includes a substrate 10 and a driving circuit layer 11. The driving circuit layer 11 is formed on one side of the substrate 10 and includes a plurality of driving circuits 111 located in the peripheral area NA. The plurality of driving circuits 111 are arranged along the extending direction of the edge of the peripheral area NA. A stress relief channel 112 is formed between at least some of the driving circuits 111 located in the corner area NA2. The stress relief channel 112 includes a stress relief hole 113 and an organic material layer 114 filled in the stress relief hole 113.

[0032] In the array substrate 1 provided by the present application, as Figure 1As shown, the number of the corner regions NA2 can be four, which is not particularly limited in this application.

[0033] In the array substrate 1 provided by this application, the substrate 10 can be transparent, translucent or opaque, which is not particularly limited in this application. The substrate 10 can be a flexible substrate 10, and the specific material can be polyimide.

[0034] The array substrate 1 provided by this application includes a plurality of driving circuits 111 located in the peripheral region NA, and the plurality of driving circuits 111 are arranged along the extending direction of the edge of the peripheral region NA. The array substrate 1 further includes a plurality of pixel circuits 124 located in the display region AA and light-emitting units connected to the pixel circuits 124. The driving circuit 111 is connected to the pixel circuit 124 to provide an electrical signal for the pixel circuit 124 to drive the light-emitting unit to emit light. The above-mentioned stress relief channels 112 are formed between at least some of the driving circuits 111 in the corner region NA2 for stress relief. Specifically, when the display panel 2 having the array substrate 1 is attached to the curved cover plate, the display panel 2 is prone to redundancy in the corner region NA2 when adapting to the shape of the curved cover plate, so that wrinkles appear in the corner region NA2 of the display panel 2 after attachment. After the above-mentioned stress relief channels 112 are formed in the corner region NA2 of the array substrate 1, the deformed stress can be absorbed when the display panel 2 adapts to the shape of the curved cover plate, thereby reducing the generation of wrinkles. The stress relief channel 112 includes a stress relief hole 113 and an organic material layer 114 filled in the stress relief hole 113. The stress relief hole 113 provides space for the absorption of deformation. The organic material layer 114 can fill the step difference brought by the stress relief hole 113. At the same time, since the organic material layer 114 uses organic materials, the flexibility and bending performance of the organic materials are strong, and the absorption effect of deformation is good, so that the bending resistance of the corner region NA2 can be improved, the generation of wrinkles can be effectively reduced, and the probability of cracks caused by extrusion during the deformation process can be reduced.

[0035] In a feasible implementation manner, as Figure 4 shown, Figure 4 is Figure 1 an enlarged view of the Q region in

[0036] In the above embodiment, the driving circuit 111 is a scanning signal generating unit for generating a scanning signal. The driving circuit 111 is connected to the pixel circuit 124 through a scanning signal line to provide a scanning signal for the pixel circuit 124 and control the states of the transistors in the pixel circuit 124. Specifically, the pixel circuit 124 can be a 2T1C circuit, a 7T1C circuit, etc., which is not particularly limited in this application.

[0037] In the array substrate 1 provided by this application, the material of the organic material layer 114 can be selected as polyimide (PI), which is not particularly limited in this application.

[0038] In a feasible embodiment, as Figure 3 and 5 shown, Figure 5 is Figure 2 Another cross-sectional view along N-N' in, the driving circuit layer 11 includes multiple inorganic layers stacked on top of each other, and the stress relief holes 113 penetrate at least part of the multiple inorganic layers. Among them, the multiple inorganic layers include a gate insulating layer 115, a first insulating layer 116, a second insulating layer 117, a third insulating layer 118, a fourth insulating layer 119, and a fifth insulating layer 120 stacked in a direction away from the substrate 10.

[0039] In the above embodiment, the driving circuit layer 11 includes multiple inorganic layers stacked on top of each other. The inorganic layers have poor flexibility and bending performance, so their stress absorption performance is poor, and wrinkles and cracks are likely to occur after deformation. The stress relief holes 113 penetrate at least part of the multiple inorganic layers, and the stress relief holes 113 are filled with the organic material layer 114. The organic material has strong deformation absorption ability and bending ability, thereby improving the stress absorption ability of the corner region NA2 and the bending performance of the array substrate 1, and thus reducing the occurrence of defects such as wrinkles and cracks.

[0040] The driving circuit layer 11 includes devices such as transistors and capacitors, and the above devices are formed by stacking the film layers in the driving circuit layer 11. The multiple inorganic layers include a gate insulating layer 115, a first insulating layer 116, a second insulating layer 117, a third insulating layer 118, a fourth insulating layer 119, and a fifth insulating layer 120 stacked in a direction away from the substrate 10. The material of the gate insulating layer 115 can be selected as silicon oxide, the material of the first insulating layer 116 can be selected as silicon nitride, the material of the second insulating layer 117 can be selected as silicon nitride, the material of the third insulating layer 118 can be selected as silicon oxide, the material of the fourth insulating layer 119 can be selected as silicon oxide, and the material of the fifth insulating layer 120 can include silicon oxide and silicon oxide.

[0041] The driving circuit layer 11 may further include a semiconductor layer 125, which is located on the side of the gate insulating layer 115 facing the substrate 10 and is used to form the source region, drain region, and channel region of the transistor. The driving circuit layer 11 may further include a gate metal layer 126, which is located between the gate insulating layer 115 and the first insulating layer 116 and is used to form the gate of the transistor and the lower plate of the capacitor. The material of the gate metal layer 126 may be selected as molybdenum. The driving circuit layer 11 may further include a capacitor metal layer 127, which is used to form the upper plate of the capacitor. The capacitor metal layer 127 is formed between the second insulating layer 117 and the third insulating layer 118, and the material of the capacitor metal layer 127 may be selected as molybdenum.

[0042] In the above embodiment, the driving circuit 111 includes devices such as transistors and capacitors. There are multiple inorganic layers between adjacent driving circuits 111. When forming the stress relief holes 113 between adjacent driving circuits 111, some or all of the multiple inorganic layers may be penetrated. The more organic layers penetrated by the stress relief holes 113 and the deeper the depth of the stress relief holes 113, the stronger the stress relief effect.

[0043] In a feasible embodiment, as Figure 6 shown, Figure 6 is Figure 2 another cross-sectional view along N-N' in

[0044] In the above embodiment, the array substrate 1 further includes a buffer layer 121, which may include a stacked structure of multiple inorganic layers and organic layers to block the erosion of oxygen and moisture on the internal structure of the array substrate 1, prevent moisture or impurities from diffusing into the array substrate 1 through the substrate 10, and provide a flat surface on the upper surface of the substrate 10. Specifically, the material of the buffer layer 121 may include silicon oxide. The stress relief holes 113 may penetrate the multiple inorganic layers and the buffer layer 121 to increase the depth of the stress relief holes 113 and enhance their stress absorption effect. When the buffer layer 121 includes multiple stacked film layers, the stress relief holes 113 may penetrate some or all of the multiple film layers, and the present application does not make a special limitation.

[0045] In a feasible embodiment, as Figure 7 shown, Figure 7 is Figure 2 another cross-sectional view along N-N' in

[0046] In the above embodiment, the driving circuit layer 11 further includes a first metal layer 122. The first metal layer 122 is located on the side of the multi-layer inorganic layer away from the substrate 10. In the area of the stress relief hole 113, the first metal layer 122 is located on the side of the organic material layer 114 in the stress relief hole 113 away from the substrate 10. The first metal layer 122 is formed with a first connection line 1221, and adjacent driving circuits 111 are connected through the first connection line 1221, thereby realizing the electrical connection of adjacent driving circuits 111.

[0047] In a feasible embodiment, as Figure 8 shown, Figure 8 is Figure 2 Another cross-sectional view along N-N' in [reference], the driving circuit layer 11 further includes a second metal layer 123 located on the side of the first metal layer 122 away from the substrate 10. The first metal layer 122 and the second metal layer 123 are insulated by an insulating layer 128. The second metal layer 123 includes a second connection line 1231, and adjacent driving circuits 111 are electrically connected through the first connection line 1221 and / or the second connection line 1231.

[0048] In the above embodiment, the driving circuit layer 11 further includes a second metal layer 123. The second metal layer 123 is located on the side of the first metal layer 122 away from the substrate 10, and the second metal layer 123 is insulated from the first metal layer 122. Multiple signal lines are required to connect between adjacent driving circuits 111. The multiple signal lines include VGH, VGL, CK, STV signal lines, etc. When the peripheral area NA is made relatively narrow to meet the narrow bezel display requirement, when multiple signal lines are all arranged on the first metal layer 122, the first metal layer 122 has wiring difficulties due to its own space limitation. At this time, by setting the second connection line 1231 located on the second metal layer 123 to share the wiring pressure of the first metal layer 122, narrow bezel display can be better realized.

[0049] In a feasible embodiment, as Figure 9 shown, Figure 9 is Figure 1 Another enlarged view of the P region in [reference]. Among the stress relief hole 113 and the two driving circuits 111 on both sides of the stress relief hole 113, one driving circuit 111 includes a first edge L1 facing the stress relief hole 113, and the other driving circuit 111 includes a second edge L2 facing the stress relief hole 113. The stress relief hole 113 is formed between the circle with the intersection point of the extension lines of the first edge L1 and the second edge L2 as the center and the distance from the center to the midpoint of the first edge L1 as the radius and the edge of the peripheral area NA, and the shortest distance d between the stress relief hole 113 and the edge of the peripheral area NA is less than the shortest distance D between the driving circuit 111 and the edge of the peripheral area NA.

[0050] In the above embodiment, the shortest distance d between the stress relief hole 113 and the edge of the peripheral region NA is: the stress relief hole 113 includes a first edge close to the peripheral region NA, and the minimum distance between the intersection of the straight line segment perpendicular to the first edge with the edge of the peripheral region NA and the midpoint of the first edge, with the midpoint of the first edge as an endpoint.

[0051] The shortest distance D between the driving circuit 111 and the edge of the peripheral region NA is: the driving circuit 111 includes a second edge close to the peripheral region NA, and the minimum distance between the intersection of the straight line segment perpendicular to the second edge with the edge of the peripheral region NA and the midpoint of the second edge, with the midpoint of the second edge as an endpoint.

[0052] In the above embodiment, since the bending degree near the display area AA is relatively small and the spacing between adjacent driving circuits 111 near the display area AA is relatively small, the stress relief channel 112 may not be provided to prevent damage to adjacent driving circuits 111 and simplify the manufacturing process. The spacing between adjacent driving circuits 111 near the edge of the peripheral region NA is relatively large, the volume of the inorganic layer is large, so the bending resistance ability is poor. At the same time, the bending degree of this part is relatively large, and wrinkles and other defects are more likely to occur. Therefore, the stress relief channel 112 can be provided to improve the strain absorption ability and bending performance of this region, so as to reduce the probability of the occurrence of the above defects and improve the display effect.

[0053] In the above embodiment, the shortest distance between the stress relief hole 113 and the edge of the peripheral region NA is set to be less than the shortest distance between the driving circuit 111 and the edge of the peripheral region NA, so that the stress relief channel 112 can further absorb the deformation between the driving circuit 111 and the edge position of the peripheral region NA, and further reduce the probability of defects.

[0054] In a feasible embodiment, as Figure 9 shown, among the stress relief hole 113 and the two driving circuits 111 on both sides of the stress relief hole 113, one driving circuit 111 includes a first edge L1 facing the stress relief hole 113, and the other driving circuit 111 includes a second edge L2 facing the stress relief hole 113. The stress relief hole 113 includes a symmetry axis L, and the distances from any point on the symmetry axis L to the first edge L1 and the second edge L2 are equal.

[0055] In the above embodiment, the stress relief holes 113 are symmetric about the symmetry axis L. At the same time, the regions between the driving circuits 111 on both sides of the stress relief holes 113 and the stress relief holes 113 are symmetric about the symmetry axis L, so that the deformation absorption effects of the stress relief holes 113 on both sides are similar, which helps to maintain the overall structural stability of the array substrate 1 after deformation and reduce the occurrence of uneven stress caused by different deformations on both sides of the symmetry axis L.

[0056] In a feasible embodiment, the cross-sectional shape of the stress relief holes 113 in the direction perpendicular to the thickness of the driving circuit layer 11 is rectangular, as Figure 9 shown, or as Figure 10 shown. Figure 10 is Figure 1 another enlarged view of the P region in

[0057] In the above embodiment, the distance between adjacent driving circuits 111 gradually increases in the direction away from the display area AA from the side close to the display area AA, so that the space between adjacent driving circuits 111 gradually increases from the side close to the display area AA to the side away from the display area AA. Therefore, the cross-sectional shape of the stress relief holes 113 in the direction perpendicular to the thickness of the driving circuit layer 11 can be made fan-shaped to adapt to the space shape between adjacent driving circuits 111, so that the volume deformations of the inorganic layers in the regions between the stress relief holes 113 and the driving circuits 111 are similar, thereby reducing the generation of defects such as wrinkles. Specifically, the two straight edges of the fan shape can be made parallel to the edges of the adjacent driving circuits 111 to further reduce the difference in the inorganic layers on both sides of the stress relief holes 113, thereby further reducing the deformation difference on both sides of the stress relief holes 113 to reduce the overall deformation defects. Alternatively, the cross-sectional shape of the stress relief holes 113 in the direction perpendicular to the thickness of the driving circuit layer 11 can be made rectangular, and the stress relief holes 113 are located on one side close to the edge of the peripheral region NA between adjacent driving circuits 111, so that the deformations of the parts between adjacent driving circuits 111 close to the display area AA and away from the display area AA are similar, reducing the generation of defects such as wrinkles. At the same time, using stress relief holes 113 with a rectangular cross-section can simplify the manufacturing process.

[0058] In a feasible embodiment, as Figure 10 and Figure 11 shown. Figure 11 is Figure 1 another enlarged view of the P region in

[0059] In the above-described embodiment, the number of driving circuits 111 between adjacent stress relief channels 112 is the same, so that the stress relief channels 112 for absorbing deformation in the corner region NA2 of the entire array substrate 1 are evenly distributed, so as to evenly release the stress caused by the bending position in the corner region NA2, making the absorption of deformation in the corner region NA2 more uniform, and at the same time making the deformation in the corner region NA2 more uniform, improving the bending resistance of the corner region NA2.

[0060] Specifically, as shown in Figure 10 , the number of driving circuits 111 between adjacent stress relief channels 112 is 1, or, as shown in Figure 11 , the number of driving circuits 111 between adjacent stress relief channels 112 is 2. The present application does not make any special limitations.

[0061] In a feasible embodiment, the number of stress relief channels 112 between adjacent driving circuits 111 is the same.

[0062] In the above-described embodiment, the number of stress relief channels 112 between adjacent driving circuits 111 can be one or more. When there are multiple stress relief channels 112, the shapes, sizes, and arrangements of the multiple stress relief channels 112 between different adjacent driving circuits 111 are the same, so as to reduce the deformation difference of each part in the corner region NA2 and make the bending resistance of the corner region NA2 better.

[0063] The present application also provides a display panel 2, as shown in Figure 12 . Figure 12 It is a schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 2 includes any one of the array substrates 1 provided in the above-described embodiment of the present application.

[0064] The display panel 2 provided by the present application further includes a light-emitting device layer 21, a packaging layer 22, etc. located on the array substrate, and may further include a touch layer 23, etc. located on the side of the packaging layer 21 away from the light-emitting region device layer. The present application does not make any special limitations.

[0065] The display panel 2 provided by the present application is a flexible display panel 2, so as to be easily bent and attached to a curved cover plate to achieve curved display.

[0066] When the display panel 2 is attached to the curved cover plate, the areas opposite to the corner region NA2 and the flat region NA1 of the array substrate 1 need to be bent and profiled according to the shape of the curved cover plate. The deformations of the various parts after bending in the flat region NA1 are similar, so it is not easy to appear defects such as wrinkles and cracks. The corner region NA2 is located between the two flat regions NA1, and redundancy is likely to occur after bending, thus wrinkles are likely to appear. After setting the stress release channel 112 in the corner region NA2 of the array substrate 1, the inorganic layer can be replaced with the stress release hole 113 and the organic material layer 114 filled in the stress release hole 113. The organic material layer 114 has better deformation absorption ability and bending resistance ability. Therefore, it can absorb the stress generated by the redundancy after bending, improve the bending performance of the array substrate 1 and the display panel 2, and then improve the bonding yield of the display panel 2 and the curved cover plate, reduce the generation probability of defects such as wrinkles and cracks, and improve the final display effect.

[0067] The present application also provides a display device 3, such as Figure 13 shown, Figure 13 is a schematic structural diagram of a display device provided by an embodiment of the present application. The display device 3 includes any one of the display panels 2 provided in the above embodiments of the present application.

[0068] The display device 3 further includes a curved cover plate, and the display panel 2 is attached to the curved cover plate. In the display device 3 provided by the present application, the bonding effect at the corner of the display panel 2 and the curved cover plate is improved, so that it is not easy to appear defects such as wrinkles and cracks at the corner of the display device 3, thereby significantly improving the display quality and greatly enhancing the user experience.

[0069] The display device 3 can be a mobile terminal such as a mobile phone or a tablet, or a fixed terminal such as a monitor or a TV, or a wearable device such as a watch. The present application does not make a special limitation. The display device 3 is a curved display device 3, which improves the display area ratio, thereby making the user experience better.

[0070] According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, It includes a display area and a peripheral area arranged around the display area. The peripheral area includes a straight area and a corner area. The array substrate includes: a substrate; a driving circuit layer formed on one side of the substrate, including a plurality of driving circuits located in the peripheral area. The plurality of driving circuits are arranged along the extending direction of the edge of the peripheral area. A stress release channel is formed between at least some of the driving circuits located in the corner area. The stress release channel includes a stress release hole and an organic material layer filled in the stress release hole. Among the stress release hole and the two driving circuits on both sides of the stress release hole, one of the driving circuits includes a first edge facing the stress release hole, and the other driving circuit includes a second edge facing the stress release hole. The stress release hole is formed between the circle with the intersection point of the extension lines of the first edge and the second edge as the center and the distance from the center to the midpoint of the first edge as the radius and the edge of the peripheral area.

2. The array substrate according to claim 1, wherein The driving circuit layer includes multiple inorganic layers stacked. The stress release hole penetrates at least part of the multiple inorganic layers. Among them, the multiple inorganic layers include a gate insulating layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in a direction away from the substrate.

3. The array substrate according to claim 2, wherein, The array substrate further includes a buffer layer located between the substrate and the driving circuit layer. The stress release hole penetrates the buffer layer.

4. The array substrate according to claim 2, wherein The driving circuit layer includes a first metal layer located on the side of the multiple inorganic layers away from the substrate. The first metal layer includes a first connection line. Adjacent driving circuits are electrically connected through the first connection line.

5. The array substrate according to claim 4, wherein The driving circuit layer further includes a second metal layer located on the side of the first metal layer away from the substrate. The first metal layer and the second metal layer are insulated. The second metal layer includes a second connection line. Adjacent driving circuits are electrically connected through the first connection line and / or the second connection line.

6. The array substrate according to claim 1, wherein The shortest distance between the stress release hole and the edge of the peripheral area is less than the shortest distance between the driving circuit and the edge of the peripheral area.

7. The array substrate according to claim 1, wherein Among the stress release hole and the two driving circuits on both sides of the stress release hole, one of the driving circuits includes a first edge facing the stress release hole, and the other driving circuit includes a second edge facing the stress release hole. The stress release hole includes a symmetry axis. Any point on the symmetry axis is equidistant from the first edge and the second edge.

8. The array substrate according to claim 7, wherein The cross-sectional shape of the stress release hole along the direction perpendicular to the thickness direction of the driving circuit layer is rectangular or fan-shaped.

9. The array substrate according to claim 1, wherein The number of driving circuits between adjacent stress release channels is the same.

10. The array substrate according to claim 1, characterized in that, The driving circuit is a scan signal generation unit. The driving circuit layer further includes a plurality of pixel circuits located in the display area. The plurality of pixel circuits are arranged in rows and columns. Each scan signal generation unit is connected to one row of pixel circuits.

11. A display panel, characterized in that, An array substrate including any one of claims 1-10.

12. A display device, characterized in that, Including the display panel described in claim 11.

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