Calibration method and apparatus for carry chain delay

Abstract

This invention provides a method and apparatus for calibrating carry chain delay. The method includes: inputting a target signal into a frequency offset adjustment circuit; adjusting a first training clock signal generated by a reference crystal through the frequency offset adjustment circuit, wherein the frequency offset adjustment circuit is connected to the reference crystal; determining the period difference between the second period of the sampling clock signal of the carry chain generated by the master crystal and the first period of the first training clock signal; and calibrating the carry chain delay based on the period difference. This invention solves the problem of the inability to self-calibrate carry chain delay in related technologies, achieving the effect of self-calibrating carry chain delay.

Description

Technical Field

[0001] The present invention relates to the field of high-precision time measurement, and more specifically, to a calibration method and apparatus for carry chain delay. Background Technology

[0002] High-precision time measurement is one of the core technologies of LiDAR. To achieve centimeter-level ranging accuracy, LiDAR requires picosecond-level time measurement technology. The method of interpolating the clock cycle using a delay chain constructed from an additive carry chain is widely used. However, this method suffers from measurement errors; each delay unit is inconsistent, a limitation imposed by the FPGA manufacturing process. Therefore, the delay of each unit needs to be calibrated to improve measurement accuracy. However, related technologies suffer from the inability to self-calibrate the carry chain delay.

[0003] There is currently no effective solution to the aforementioned problems in the relevant technologies. Summary of the Invention

[0004] This invention provides a method and apparatus for calibrating carry chain delay, which at least solves the problem of the inability to self-calibrate carry chain delay in related technologies.

[0005] According to an embodiment of the present invention, a method for calibrating carry chain delay is provided, comprising: inputting a target signal into a frequency offset adjustment circuit, adjusting a first training clock signal generated by a reference crystal through the frequency offset adjustment circuit, wherein the frequency offset adjustment circuit is connected to the reference crystal; determining a period difference between a second period of a sampling clock signal of a carry chain generated by a master crystal and a first period of the first training clock signal; and calibrating the delay of the carry chain based on the period difference.

[0006] According to another embodiment of the present invention, a carry chain delay calibration apparatus is provided for running the carry chain delay calibration method in the above embodiment, comprising: a processing module for inputting a target signal into a frequency offset adjustment circuit; a frequency offset adjustment circuit connected to the output terminal of the processing module, the frequency offset adjustment circuit also connected to a reference crystal, for converting the target signal into a first voltage signal and then into a capacitance value; a reference crystal, the reference crystal also connected to the processing module, for generating a first training clock signal based on the capacitance value and sending the first training clock information to the processing module; a main crystal connected to the processing module for generating a carry chain sampling clock signal and sending the sampling clock signal to the processing module; the processing module is further configured to determine the period difference between the second period of the carry chain sampling clock signal output by the main crystal and the first period of the first training clock signal, and calibrate the carry chain delay based on the period difference.

[0007] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0008] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0009] This invention involves inputting a target signal into a frequency offset adjustment circuit connected to a reference crystal. The frequency offset adjustment circuit adjusts the first training clock signal generated by the reference crystal to determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal. The carry chain delay is then calibrated based on this period difference. Since the first training clock signal generated by the reference crystal can be adjusted by the frequency offset adjustment circuit, a difference in frequency (i.e., a period difference) is established between the first training clock signal generated by the reference crystal and the sampling clock signal generated by the main crystal. This period difference is used to perform carry chain calibration measurements without requiring an external random signal input. Therefore, this invention solves the problem of the inability to self-calibrate carry chain delay in related technologies, achieving the effect of self-calibrating carry chain delay. Attached Figure Description

[0010] Figure 1 This is a hardware structure block diagram of a mobile terminal for a carry chain delay calibration method according to an embodiment of the present invention.

[0011] Figure 2 This is a flowchart of a calibration method for carry chain delay according to an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of a calibration device for carry chain delay according to an embodiment of the present invention;

[0013] Figure 4 This is a waveform diagram of the first training clock signal, the sampling clock signal, the first signal, the second signal, and the third signal according to an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of delay calibration of the carry chain according to an embodiment of the present invention. Figure 1 ;

[0015] Figure 6 This is a schematic diagram of delay calibration of the carry chain according to an embodiment of the present invention. Figure 2 ;

[0016] Figure 7 This is a schematic diagram of a frequency offset adjustment circuit according to an embodiment of the present invention;

[0017] Figure 8 This is a circuit diagram of a frequency offset adjustment circuit according to an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a carry chain delay calibration method according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the carry chain delay calibration method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0023] This embodiment provides a method for calibrating carry chain delay. Figure 2 This is a flowchart of a carry chain delay calibration method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0024] Step S202: Input the target signal into the frequency offset adjustment circuit, and adjust the first training clock signal generated by the reference crystal through the frequency offset adjustment circuit, wherein the frequency offset adjustment circuit is connected to the reference crystal;

[0025] Step S204: Determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal;

[0026] Step S206: Calibrate the delay of the carry chain based on the period difference.

[0027] In the above embodiment, the target signal can be a PWM wave output by the processing module. The duty cycle of the target signal can be adjusted. By adjusting the duty cycle of the target signal, the output voltage of the frequency offset adjustment circuit can be changed, thereby changing the period of the first training clock signal generated by the reference crystal connected to the frequency offset adjustment circuit. The main crystal is also connected to the processing module. The main crystal can send the generated sampling clock signal to the processing module. The processing module can determine the period difference between the second period of the sampling clock signal and the first period of the first training clock signal, and calibrate the delay of the carry chain based on the period difference. The first training clock signal is a clock signal obtained by multiplying and dividing the reference crystal as the source clock, while the sampling clock signal is a clock signal obtained by multiplying and dividing the main crystal as the source clock.

[0028] The schematic diagram of the carry chain delay calibration device in the above embodiments can be found in the appendix. Figure 3 ,like Figure 3As shown, the carry chain delay calibration device uses two crystals as clock inputs, one of which is a reference crystal with a frequency offset adjustment circuit. This circuit can be implemented using a varactor diode and related circuitry. A small, adjustable frequency difference between the reference crystal and the master crystal can be achieved by fine-tuning the capacitor. After frequency multiplication by the processing module, the carry chain sampling clock signal MCLK and the first training clock signal RCLK are generated. By fine-tuning the adjustable capacitor, a small frequency difference is achieved between the generated RCLK and MCLK. Assuming the period of RCLK is T... R The period of MCLK is T M And T R Greater than T M The time difference generated during each MCLK cycle, i.e., the cycle difference, is ΔT = T. R -T M Among them, T M In a fixed clock, T R It is generated by adjusting the capacitor.

[0029] The entity executing the above steps can be a processing module, such as a processor, but is not limited to this.

[0030] This invention involves inputting a target signal into a frequency offset adjustment circuit connected to a reference crystal. The frequency offset adjustment circuit adjusts the first training clock signal generated by the reference crystal to determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal. The carry chain delay is then calibrated based on this period difference. Since the first training clock signal generated by the reference crystal can be adjusted by the frequency offset adjustment circuit, a difference in frequency (i.e., a period difference) is established between the first training clock signal generated by the reference crystal and the sampling clock signal generated by the main crystal. This period difference is used to perform carry chain calibration measurements without requiring an external random signal input. Therefore, this invention solves the problem of the inability to self-calibrate carry chain delay in related technologies, achieving the effect of self-calibrating carry chain delay.

[0031] In an exemplary embodiment, determining the period difference between the second period of the sampling clock signal of the carry chain generated by the master crystal and the first period of the first training clock signal includes: processing the first training clock signal and the sampling clock signal through an AND gate to obtain a first signal; filtering the first signal through a target filter to obtain a second signal; shaping the second signal to obtain a third signal; determining a first duration between two adjacent target edges included in the third signal; determining a first number of sampling clock signals generated by the master crystal within the first duration; and determining the ratio of the second period to the first number as the period difference. In this embodiment, waveform diagrams of the first training clock signal, the sampling clock signal, the first signal, the second signal, and the third signal can be found in the appendix. Figure 4 ,like Figure 4 As shown, RCLK represents the first training clock signal, MCLK represents the sampling clock signal, SOUT1 represents the first signal, SOUT2 represents the second signal, and SCLK represents the third signal. Vref is the waveform of the reference voltage sampled when the second signal is shaped.

[0032] In the above embodiments, the target filter can be a low-pass filter, and the second signal can be shaped using a comparator. The target edge can be a rising edge or a falling edge. MCLK and RCLK, after passing through an AND gate, can generate a SOUT1 waveform. This waveform, after passing through an LPF (low-pass filter), will form a SOUT2 waveform (this waveform can be a triangular wave or a sine wave, depending on the parameters of the LPF; the waveform itself does not affect subsequent calculations). SOUT2 is compared and shaped into a square wave with a reference voltage Vref. Taking any rising edge (or falling edge) of this square wave as the start signal and the next rising edge (or falling edge) as the end signal, the number of MCLKs during the period is counted, assuming it is m, then ΔT = T can be calculated. M / m.

[0033] In an exemplary embodiment, calibrating the delay of the carry chain based on the period difference includes: determining the sum of the latch point of the carry chain and the period difference; if the sum is within the current stage of the carry chain, controlling the carry chain to output a signal corresponding to the current stage; if the sum is at the next stage of the carry chain, controlling the carry chain to output a signal corresponding to the next stage. In this embodiment, since the relative positions of the rising edges of RCLK and MCLK are offset by ΔT each clock cycle, the time of the carry chain can be measured through this fixed phase change. The carry chain uses MCLK as the sampling latch clock, so the rising edge of RCLK is delayed by ΔT at each latch point. If the delay still falls within the current stage of the carry chain after each ΔT delay, the output of the carry chain remains unchanged, and a carry is generated when entering the next stage. For example, when the carry chain is a 4-stage carry chain, a schematic diagram of the carry chain delay calibration can be found in the appendix. Figure 5 and appendix Figure 6 ,like Figure 5 As shown, when the rising edge of RCLK is at the last solid arrow, the carry chain output is 1100, while when it is at the dashed arrow, the carry chain output jumps to 1110. Figure 6 As shown, after n MCLK clock cycles, the carry chain jumps from 1110 to 1111. The delay Td of this carry chain stage can then be calculated as n*ΔT. Similarly, calibration can be performed by continuously measuring the data of the entire carry chain, with a calibration accuracy of ΔT.

[0034] In an exemplary embodiment, the method further includes: determining the calibration accuracy of the carry chain; determining a second number of sampled clock signals generated within a second duration based on the calibration accuracy and the second period, wherein the second duration is the duration between two adjacent target edges included in the fourth signal, the fourth signal being obtained by: processing the second training clock signal and the sampled clock signal through an AND gate to obtain a fifth signal; filtering the fifth signal through a target filter to obtain a sixth signal; and shaping the sixth signal to obtain the fourth signal; adjusting the duty cycle of the target signal based on the calibration accuracy to obtain an adjustment signal; and inputting the adjustment signal to the frequency offset adjustment circuit to adjust the second training clock signal generated by the reference crystal. In this embodiment, for example, when the MCLK frequency is 200MHz, the clock period T... M The value is 4 ns. Assuming the required calibration accuracy of the carry chain is 1 ps, substituting into ΔT = T M The calculation yields m = 4000. This can be achieved by adjusting the adjustable capacitor in the frequency offset adjustment circuit to set m = 4000. Compared to the code density method, which often requires hundreds of thousands of data points, the calibration data acquisition is significantly reduced, requiring only 4000 × 4ns = 16us to complete, thus improving the speed and efficiency of calibration.

[0035] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0036] This embodiment also provides a carry chain delay calibration device, which is used to implement the above embodiments and preferred embodiments, and will not be repeated as already described. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0037] The calibration device for carry chain delay includes:

[0038] The processing module is used to input the target signal to the frequency offset adjustment circuit;

[0039] A frequency offset adjustment circuit is connected to the output terminal of the processing module. The frequency offset adjustment circuit is also connected to a reference crystal and is used to convert the target signal into a first voltage signal and convert the first voltage signal into a capacitance value.

[0040] The reference crystal is also connected to the processing module and is used to generate a first training clock signal based on the capacitance value and send the first training clock information to the processing module.

[0041] The main crystal, connected to the processing module, is used to generate a sampling clock signal for the carry chain and send the sampling clock signal to the processing module.

[0042] The processing module is further configured to determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal, and to calibrate the delay of the carry chain based on the period difference.

[0043] In the above embodiment, the target signal can be a PWM wave output by the processing module. The duty cycle of the target signal can be adjusted. By adjusting the duty cycle of the target signal, the output voltage of the frequency offset adjustment circuit can be changed, thereby changing the period of the first training clock signal generated by the reference crystal connected to the frequency offset adjustment circuit. The main crystal is also connected to the processing module. The main crystal can send the generated sampling clock signal to the processing module. The processing module can determine the period difference between the second period of the sampling clock signal and the first period of the first training clock signal, and calibrate the delay of the carry chain based on the period difference.

[0044] In the above embodiments, the carry chain delay calibration device can be found in the appendix. Figure 3 ,like Figure 3 As shown, the carry chain delay calibration device uses two crystals as clock inputs, one of which is a reference crystal with a frequency offset adjustment circuit. This circuit can be implemented using a varactor diode and related circuitry. A small, adjustable frequency difference between the reference crystal and the master crystal can be achieved by fine-tuning the capacitor. After frequency multiplication by the processing module, the carry chain sampling clock signal MCLK and the first training clock signal RCLK are generated. By fine-tuning the adjustable capacitor, a small frequency difference is achieved between the generated RCLK and MCLK. Assuming the period of RCLK is T... R The period of MCLK is T M And T R Greater than T M The time difference generated during each MCLK cycle, i.e., the cycle difference, is ΔT = T. R -T M Among them, T M In a fixed clock, T RIt is generated by adjusting the capacitor.

[0045] In this invention, the processing module inputs the target signal to a frequency offset adjustment circuit connected to a reference crystal. The frequency offset adjustment circuit converts the target signal into a first voltage signal, which is then input to the reference crystal to adjust the first training clock signal generated by the reference crystal. The reference crystal can send the first training clock signal to the processing module, and the main crystal can send its sampling clock signal to the processing module. The processing module determines the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal, and calibrates the carry chain delay based on this period difference. Since the first training clock signal generated by the reference crystal can be adjusted by the frequency offset adjustment circuit, a difference frequency clock (i.e., a period difference) exists between the first training clock signal output by the reference crystal and the sampling clock signal generated by the main crystal. This period difference is used to perform carry chain calibration measurement without requiring an external random signal input. Therefore, this invention solves the problem of the inability to self-calibrate carry chain delay in related technologies, achieving the effect of self-calibrating carry chain delay.

[0046] In an exemplary embodiment, the carry chain delay calibration device further includes an AND gate, which is connected to the processing module and is used to process the first training clock signal and the sampling clock signal sent by the processing module to obtain a first signal. In this embodiment, the carry chain delay calibration device further includes an AND gate, and MCLK and RCLK can generate a SOUT1 waveform, i.e., the first signal, after passing through an AND gate.

[0047] In an exemplary embodiment, the carry chain delay calibration device further includes a target filter connected to the AND gate, used to filter the first signal to obtain a second signal. In this embodiment, the target filter may be a low-pass filter (LPF). After the first signal passes through the LPF, it forms a SOUT2 waveform, which is the second signal.

[0048] In an exemplary embodiment, the carry chain delay calibration device further includes: a comparator, the input of which is connected to the target filter, and the output of which is connected to the processing module, for shaping the second signal to obtain a third signal, and sending the third signal to the processing module. The processing module is further configured to determine a first duration between two adjacent target edges included in the third signal, determine a first number of sampling clock signals generated by the main crystal within the first duration, and determine the ratio of the second period to the first number as the period difference. In this embodiment, the second signal SOUT2 is compared and shaped into a square wave with a reference voltage Vref. Any rising edge (or falling edge) of the square wave is taken as the start signal, and the next rising edge (or falling edge) is taken as the end signal. The number of MCLKs during the period is counted, assuming to be m, and then the period difference ΔT = T can be calculated. M / m.

[0049] In an exemplary embodiment, the frequency offset adjustment circuit includes: a low-pass filter connected to the processing module, used to adjust the target signal output by the processing module into a second voltage signal; a capacitor isolation module, the input terminal of which is connected to the output terminal of the low-pass filter, used to isolate the second voltage signal to obtain a third voltage signal; a varactor diode connected to the capacitor isolation module, the capacitance value of which changes with the third voltage; and a DC isolation module connected to the output terminal of the varactor diode, used to isolate a DC voltage to obtain the first voltage signal. The DC isolation module is also connected to the reference crystal, and the reference crystal generates the first training clock signal based on the capacitance value corresponding to the first voltage signal. In this embodiment, the frequency offset adjustment circuit is used to fine-tune the frequency offset of the reference crystal. A schematic diagram of the frequency offset adjustment circuit can be found in the attached diagram. Figure 7 ,like Figure 7 As shown, the frequency offset adjustment circuit includes a low-pass filter, a capacitor isolation module, a varactor diode, and a DC isolation module. The low-pass filter is connected to the processor (processing module), and the DC isolation module is connected to the reference crystal. The low-pass filter filters the target signal output from the processing module to obtain a second voltage signal. The capacitor isolation module isolates the second voltage signal to obtain a third voltage signal, thus reducing the influence of the capacitor on the reference crystal. The capacitance value of the varactor diode varies with the magnitude of the applied voltage, and the DC isolation module isolates the DC voltage, preventing it from affecting the crystal oscillation circuit.

[0050] In one exemplary embodiment, the low-pass filter includes a first resistor and a first capacitor. A first terminal of the first resistor is connected to the processing module, a second terminal of the first resistor is connected to a first terminal of the first capacitor, and a second terminal of the first capacitor is grounded. In this embodiment, the circuit diagram of the frequency offset adjustment circuit can be found in the appendix. Figure 8 ,like Figure 8 As shown, the processor outputs a PWM wave with an adjustable duty cycle. R1 and C1 form a low-pass filter, converting the PWM into a corresponding voltage signal. R21 and R22 act as isolation devices, reducing the influence of C1 on the crystal. D1 and D2 are varactor diodes, whose capacitance values ​​vary with the applied voltage. C21 and C22 isolate DC voltage, preventing it from affecting the crystal oscillation circuit.

[0051] In the above embodiments, the low-pass filter may include a first resistor R1 and a first capacitor C1. The first end of the first resistor is connected to the processor, i.e., the processing module, and the second end of the first resistor is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded.

[0052] In one exemplary embodiment, the capacitor isolation module includes a second resistor and a third resistor, with a first terminal of the second resistor connected to a second terminal of the first resistor, and a first terminal of the third resistor connected to a second terminal of the first resistor; the varactor diode includes a first varactor diode and a second varactor diode, with a first terminal of the first varactor diode connected to a second terminal of the second resistor and a second terminal of the first varactor diode grounded, and a first terminal of the second varactor diode connected to a second terminal of the third resistor and a second terminal of the second varactor diode grounded. In this embodiment, see further... Figure 8 The capacitor isolation module may include a second resistor R21 and a third resistor R22. The varactor diodes include a first varactor diode D1 and a second varactor diode D2. The first terminal of the second resistor R21 is connected to the second terminal of the first resistor R1, and the second terminal of the second resistor R21 is connected to the first terminal of the first varactor diode D1. The first terminal of the third resistor R22 is connected to the second terminal of the first resistor R1, and the second terminal of the third resistor R22 is connected to the second terminal of the second varactor diode D2. The second terminals of the first varactor diode D1 and the second terminal of the second varactor diode D2 are grounded.

[0053] In one exemplary embodiment, the DC isolation module includes a second capacitor and a third capacitor. A first terminal of the second capacitor is connected to a first terminal of the first varactor diode, and a second terminal of the second capacitor is connected to the reference crystal. A first terminal of the third capacitor is connected to a second terminal of the second varactor diode, and a second terminal of the third capacitor is connected to the reference crystal. In this embodiment, see also... Figure 8The DC isolation module may include a second capacitor C21 and a third capacitor C22. The first end of the second capacitor C21 is connected to the first end of the first varactor diode D1, and the second end of the second capacitor C21 is connected to the reference crystal X1. The first end of the third capacitor C22 is connected to the first end of the second varactor diode D2, and the second end of the second capacitor C22 is connected to the reference crystal X1.

[0054] In the aforementioned embodiments, the difference frequency clock is achieved by adjusting the crystal frequency offset. The phase change of the difference frequency clock is used to perform carry chain calibration measurements. Compared to the code density method, the amount of calibration data is extremely small, and no external random signal input is required, achieving self-calibration and real-time calibration. Utilizing the advantages of not requiring external calibration signals and high calibration speed, self-calibration is achieved during power-on and temperature changes. Calibration does not require a controllable delay unit with higher accuracy than the carry chain, making it more feasible, lower in cost, and simpler. The calibration accuracy is adjustable, and the delay of each unit can be directly measured, unaffected by the total delay accuracy of the carry chain.

[0055] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0056] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0057] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0058] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0059] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0060] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0061] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for calibrating carry chain delay, characterized in that, include: The target signal is input to the frequency offset adjustment circuit, and the first training clock signal generated by the reference crystal is adjusted by the frequency offset adjustment circuit, wherein the frequency offset adjustment circuit is connected to the reference crystal; Determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal; The delay of the carry chain is calibrated based on the period difference; The method further includes: determining the calibration accuracy of the carry chain; determining a second number of sampling clock signals generated within a second duration based on the calibration accuracy and the second period; adjusting the size of the adjustable capacitor of the frequency offset adjustment circuit based on the second number, wherein the second duration is the duration between two adjacent target edges included in the fourth signal, the fourth signal being obtained by: processing the second training clock signal and the sampling clock signal through an AND gate to obtain a fifth signal; filtering the fifth signal through a target filter to obtain a sixth signal; shaping the sixth signal to obtain the fourth signal; adjusting the duty cycle of the target signal based on the calibration accuracy to obtain an adjustment signal; and inputting the adjustment signal to the frequency offset adjustment circuit to adjust the second training clock signal generated by the reference crystal.

2. The method according to claim 1, characterized in that, The period difference between the second period of the sampling clock signal for the carry chain generated by the master crystal and the first period of the first training clock signal includes: The first signal is obtained by processing the first training clock signal and the sampling clock signal using an AND gate; The first signal is filtered by the target filter to obtain the second signal; The second signal is shaped to obtain the third signal; Determine the first duration between two adjacent target edges included in the third signal; Determine a first number of sampling clock signals generated by the main crystal within the first duration; The ratio of the second period to the first quantity is determined as the period difference.

3. The method according to claim 1, characterized in that, Calibrling the delay of the carry chain based on the period difference includes: Determine the sum of the latch point of the carry chain and the period difference; If the sum is within the current level of the carry chain, control the carry chain to output a signal corresponding to the current level; If the sum is at the next level of the current level of the carry chain, the carry chain is controlled to output a signal corresponding to the next level.

4. A calibration device for carry chain delay, characterized in that, For carrying out the method according to any one of claims 1 to 3, comprising: The processing module is used to input the target signal to the frequency offset adjustment circuit; A frequency offset adjustment circuit is connected to the output terminal of the processing module. The frequency offset adjustment circuit is also connected to a reference crystal and is used to convert the target signal into a first voltage signal and convert the first voltage signal into a capacitance value. The reference crystal is also connected to the processing module and is used to generate a first training clock signal based on the capacitance value and send the first training clock signal to the processing module. The main crystal, connected to the processing module, is used to generate a sampling clock signal for the carry chain and send the sampling clock signal to the processing module. The processing module is also used to determine the period difference between the second period of the sampling clock signal of the carry chain generated by the main crystal and the first period of the first training clock signal, and to calibrate the delay of the carry chain based on the period difference. The device is further configured to: determine the calibration accuracy of the carry chain; determine a second number of sampled clock signals generated within a second duration based on the calibration accuracy and the second period; adjust the size of the adjustable capacitor of the frequency offset adjustment circuit based on the second number, wherein the second duration is the duration between two adjacent target edges included in the fourth signal, the fourth signal being obtained by: processing the second training clock signal and the sampled clock signal through an AND gate to obtain a fifth signal; filtering the fifth signal through a target filter to obtain a sixth signal; shaping the sixth signal to obtain the fourth signal; adjusting the duty cycle of the target signal based on the calibration accuracy to obtain an adjustment signal; and inputting the adjustment signal to the frequency offset adjustment circuit to cause the frequency offset adjustment circuit to adjust the second training clock signal generated by the reference crystal.

5. The calibration device for carry chain delay according to claim 4, characterized in that, The carry chain delay calibration device further includes: An AND gate, connected to the processing module, is used to process the first training clock signal and the sampling clock signal sent by the processing module to obtain a first signal.

6. The calibration device for carry chain delay according to claim 5, characterized in that, The carry chain delay calibration device further includes: A target filter, connected to the AND gate, is used to filter the first signal to obtain a second signal.

7. The calibration device for carry chain delay according to claim 6, characterized in that, The carry chain delay calibration device further includes: A comparator, the input of which is connected to the target filter, and the output of which is connected to the processing module, is used to shape the second signal to obtain a third signal and send the third signal to the processing module. The processing module is also used to determine a first duration between two adjacent target edges included in the third signal, determine a first number of sampling clock signals generated by the main crystal within the first duration, and determine the ratio of the second period to the first number as the period difference.

8. The calibration device for carry chain delay according to claim 4, characterized in that, The frequency offset adjustment circuit includes: A low-pass filter, connected to the processing module, is used to adjust the target signal output by the processing module into a second voltage signal; A capacitor isolation module, the input terminal of which is connected to the output terminal of the low-pass filter, is used to isolate the second voltage signal and obtain a third voltage signal; A varactor diode is connected to the capacitor isolation module, and the capacitance value of the varactor diode changes with the change of the third voltage. A DC isolation module is connected to the output terminal of the varactor diode to isolate DC voltage and obtain the first voltage signal. The DC isolation module is also connected to the reference crystal, which generates the first training clock signal based on the capacitance value corresponding to the first voltage signal.

9. The calibration device for carry chain delay according to claim 8, characterized in that, The low-pass filter includes a first resistor and a first capacitor. The first end of the first resistor is connected to the processing module, the second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded.

10. The calibration device for carry chain delay according to claim 8, characterized in that, The capacitor isolation module includes a second resistor and a third resistor, wherein the first end of the second resistor is connected to the second end of the first resistor, and the first end of the third resistor is connected to the second end of the first resistor. The varactor diode includes a first varactor diode and a second varactor diode. The first terminal of the first varactor diode is connected to the second terminal of the second resistor, and the second terminal of the first varactor diode is grounded. The first terminal of the second varactor diode is connected to the second terminal of the third resistor, and the second terminal of the second varactor diode is grounded.

11. The calibration device for carry chain delay according to claim 10, characterized in that, The DC isolation module includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to the first terminal of the first varactor diode, and the second terminal of the second capacitor is connected to the reference crystal. The first terminal of the third capacitor is connected to the second terminal of the second varactor diode, and the second terminal of the third capacitor is connected to the reference crystal.

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