Processor chip performance testing method and testing device

Abstract

The present application relates to the technical field of hardware testing, and particularly relates to a processor chip performance testing method and testing device. The testing method comprises the following steps: firstly, a testing file for testing a processor chip is acquired, the testing file comprising a first header file and a first testing program; the first header file comprises breakpoint information for generating at least one snapshot file; then, the testing file is loaded onto a first testing platform to run the testing file, and at least one snapshot file is generated according to the breakpoint information; thus, multiple snapshot files can be generated at one time by running the testing file, and the compatibility problem of the snapshot files on different second testing platforms is overcome by converting the snapshot files; finally, the converted snapshot files are loaded onto an adapted second testing platform to run, and the testing result of the corresponding part is obtained, thereby improving the testing efficiency of the processor chip.

Description

Technical Field

[0001] This invention relates to the field of hardware testing technology, and in particular to a method and apparatus for testing the performance of a processor chip. Background Technology

[0002] In the design and verification process of processor chips, performance testing is required before tape-out to verify whether the processor chip's performance meets the expected requirements. If it does, tape-out production can proceed. If the performance prediction is not good, production may be suspended to avoid unnecessary economic losses. Therefore, it is very important to test the performance of processor chips before tape-out.

[0003] In current technologies, processor chip performance testing before tape-out primarily utilizes benchmark programs (such as SPEC CPU2006 / 2017) to perform performance tests. While benchmark programs are comprehensive testing programs, their large size means that testing on existing FPGA (Field Programmable Gate Array) platforms typically takes weeks or even months to complete one cycle. Running benchmark programs on RTL (Register Transfer Level) testing platforms requires even longer testing cycles, significantly slowing down the product development and tape-out timeline.

[0004] It is evident that existing performance testing methods for processor chips require long testing cycles, resulting in low testing efficiency. Summary of the Invention

[0005] This invention provides a method for testing the performance of processor chips, thereby solving the technical problem of low efficiency in the performance testing of processor chips in the prior art.

[0006] On one hand, the present invention provides a method for testing the performance of a processor chip, comprising:

[0007] Obtain a test file for testing a processor chip, the test file including a first header file and a first test program; wherein the first header file includes breakpoint information for generating at least one snapshot file;

[0008] The test file is loaded onto the first test platform to run the test file, and at least one snapshot file is generated based on the breakpoint information;

[0009] For each snapshot file, the snapshot file is transformed based on the attribute information corresponding to the second test platform used to load the snapshot file, resulting in a transformed snapshot file;

[0010] The converted snapshot file is loaded onto the second test platform and run to test the processor chip.

[0011] According to a processor chip performance testing method provided by the present invention, the step of loading the test file onto a first test platform to run the test file and generating at least one snapshot file based on the breakpoint information includes:

[0012] The test file is loaded onto the first test platform to run the test file;

[0013] During operation, intermediate state data of the processor chip is captured at different breakpoints;

[0014] Based on the intermediate state data and the attribute information of the first test platform, a second header file is generated;

[0015] The snapshot file is generated based on the second header file and the first test program.

[0016] According to a processor chip performance testing method provided by the present invention, the intermediate state data includes one or more of the following: integer register backup, floating-point register backup, control and status register backup, and program counter backup.

[0017] According to a processor chip performance testing method provided by the present invention, the step of converting the snapshot file based on attribute information corresponding to a second test platform used for loading the snapshot file to obtain a converted snapshot file includes:

[0018] Obtain the attribute information corresponding to the second test platform used to load the snapshot file;

[0019] Replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file;

[0020] The converted second header file and the first test program are packaged together to obtain the converted snapshot file.

[0021] According to a processor chip performance testing method provided by the present invention, the step of obtaining a test file for testing the processor chip includes:

[0022] Compile the first header file and set breakpoint information in the first header file to generate at least one snapshot file;

[0023] Compile the first test program;

[0024] The first header file and the first test program are packaged together to obtain the test file.

[0025] On the other hand, the present invention also provides a processor chip performance testing apparatus, comprising:

[0026] An acquisition unit is configured to acquire a test file for testing a processor chip, the test file including a first header file and a first test program; wherein, the first header file includes breakpoint information for generating at least one snapshot file;

[0027] A snapshot generation unit is used to load the test file onto a first test platform to run the test file and generate at least one snapshot file based on the breakpoint information;

[0028] The snapshot conversion unit is used to convert each snapshot file based on the attribute information corresponding to the second test platform used to load the snapshot file, so as to obtain the converted snapshot file.

[0029] The testing unit is used to load the converted snapshot file onto the second testing platform and run it to test the processor chip.

[0030] According to the processor chip performance testing apparatus provided by the present invention, the snapshot generation unit is specifically used for:

[0031] The test file is loaded onto the first test platform to run the test file;

[0032] During operation, intermediate state data of the processor chip is captured at different breakpoints;

[0033] Based on the intermediate state data and the attribute information of the first test platform, a second header file is generated;

[0034] The snapshot file is generated based on the intermediate state data and the first test program.

[0035] According to the processor chip performance testing apparatus provided by the present invention, the snapshot conversion unit is specifically used for:

[0036] Obtain the attribute information corresponding to the second test platform used to load the snapshot file;

[0037] Replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file;

[0038] The converted second header file and the corresponding second test program are packaged together to obtain the converted snapshot file.

[0039] On the other hand, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the processor chip performance testing method described above.

[0040] On the other hand, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the processor chip performance testing method as described above.

[0041] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the processor chip performance testing method as described above.

[0042] The processor chip performance testing method provided by this invention first obtains a test file for testing the processor chip, which includes a first header file and a first test program. The first header file includes breakpoint information for generating at least one snapshot file. Then, the test file is loaded onto a first test platform to run the test file, generating at least one snapshot file based on the breakpoint information. This allows multiple snapshot files to be generated at once by running the test file. Furthermore, by converting the snapshot files, the compatibility issues of snapshot files on different second test platforms are overcome. Finally, the converted snapshot files are loaded onto the adapted second test platform and run to obtain the corresponding test results, thus improving the testing efficiency of the processor chip. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a flowchart illustrating the processor chip performance testing method provided in an embodiment of the present invention.

[0045] Figure 2 A schematic diagram illustrating the composition of the first header file provided in an embodiment of the present invention;

[0046] Figure 3 This is one of the schematic diagrams of the process for generating snapshot files provided in an embodiment of the present invention;

[0047] Figure 4 This is the second schematic diagram of the process for generating snapshot files provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of test file loading provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the snapshot conversion process provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the snapshot text execution process provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of the processor chip performance testing device provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0054] In embodiments of the present invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone, where A and B can be singular or plural. In the textual description of the present invention, the character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0055] The technical solutions provided by the embodiments of this invention can be used in the field of hardware performance testing technology, especially in the field of processor chip performance testing. In the prior art, when testing the performance of processor chips before tape-out (i.e., the Pre-SI stage), testing is generally performed on an FPGA platform or an RTL platform. However, limited by the operating speed of the RTL platform and the clock frequency of the FPGA platform, only simple functional verification can be performed on the Pre-SI stage processor chip, making it difficult to comprehensively and effectively evaluate the processor chip's performance. This is especially true for high-performance CPUs (central processing units) with complex structures, where existing testing methods are insufficient for comprehensive performance testing.

[0056] Furthermore, current technologies primarily employ benchmark programs to test processor chip performance. However, benchmark programs are inherently large (i.e., they process a significant amount of data) and include separate test programs for multiple different test items. Running these test programs on the same platform can lead to incompatibility issues between the test program attributes and the test platform's data processing capabilities. For example, ISA (Industry Standard Architecture) test platforms, RTL (Register Transfer Level) and FPGA (Field Programmable Gate Array) test platforms have varying degrees of efficiency for different test items. Therefore, running the entire testing process on a single platform results in slower test program execution and reduced testing efficiency.

[0057] In this embodiment of the invention, a test file for testing the processor chip is first obtained. The test file includes a first header file and a first test program (i.e., test code). The first header file includes breakpoint information for generating at least one snapshot file. Then, the test file is loaded onto a first test platform to run the test file, thereby generating at least one snapshot file based on the breakpoint information. Then, based on the attribute information corresponding to the second test platform used to load the snapshot file, the snapshot file is converted to obtain a converted snapshot file. This ensures the compatibility of the snapshot file on the second test platform. Running the snapshot file on multiple second test platforms can yield multiple test results for different test items, improving the testing efficiency of the processor chip performance, shortening the testing cycle, and providing a more comprehensive test of the processor chip.

[0058] The abbreviations and full names of some technical terms involved in the embodiments of this invention are as follows:

[0059] Pre-si (Pre-silicon, referring to the pre-processor chip before it has been manufactured);

[0060] Post-si (Post-silicon, referring to the processor chip that has been manufactured after tape-out);

[0061] ISA (Instruction Set Architecture);

[0062] RTL (Register Transfer Level);

[0063] FPGA (Field Programmable Gate Array);

[0064] EDA (Electronic Design Automation);

[0065] CPT (checkpoint, snapshot);

[0066] CSR (Control Status Register);

[0067] GPR (General Purpose Register);

[0068] FPR (Floating Point Register).

[0069] The processor chip performance testing method provided by the present invention will be described in detail below through several specific embodiments. It is understood that these specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0070] Figure 1 This is a flowchart illustrating a processor chip performance testing method provided in an embodiment of the present invention. This processor chip performance testing method can be executed by software and / or hardware devices. For example, the hardware device can be an embedded device, a personal computer, or a server, etc. For further examples, please refer to... Figure 1 As shown, the processor chip performance testing method may include:

[0071] S101. Obtain a test file for testing the processor chip. The test file includes a first header file and a first test program. The first header file includes breakpoint information for generating at least one snapshot file.

[0072] For example, the test file includes a first header file and a first test program. The first header file mainly stores various control information and breakpoint information to control the entire execution process of the first test program, which is equivalent to the control header file in a complete program. The first test program is the test code. For example, in this embodiment, an existing benchmark program can be used as the first test program to test the performance of the processor chip to be tested.

[0073] The test files, including the first header file and the first test program, are binary files, and the content of these binary files does not depend on the test platform.

[0074] For example, when obtaining the test file for testing the processor chip, the storage space of the first test platform is first divided into a first header file storage area and a first test program storage area according to the size of the test file, so as to store the first header file and the first test program respectively.

[0075] Example, Figure 2 Please refer to the schematic diagram illustrating the composition of the first header file provided in this embodiment of the invention. Figure 2 The first header file may include boot1 (initialization information), boot2 (restoring the context and jumps), restore flag (flag bits), integer register backup, floating-point register backup, control and status register backup, program counter backup, and low-level code for external device drivers. The initialization information mainly includes information related to platform compatibility, the flag bits are mainly used to indicate whether to restore the context, and the low-level code for external device drivers generally refers to information related to platform compatibility.

[0076] For example, obtaining test files for testing processor chips specifically includes:

[0077] First, according to... Figure 2 Compile the first header file in the format shown, and set breakpoint information in the first header file to generate at least one snapshot file. The breakpoint information can be stored in boot2 and restore flag. Compile the first test program, and encapsulate the first header file and the first test program to obtain a complete test file.

[0078] It should be noted that the boot1 header file in this embodiment is used to store information related to platform compatibility. It can be replaced according to different platform attribute information to achieve cross-platform compatibility of the test file.

[0079] S102. Load the test file onto the first test platform to run the test file, and generate at least one snapshot file based on the breakpoint information.

[0080] If large software programs like SPEC CPU2006 / 2017 are used to test processor chips during the Pre-SI stage, cross-platform checkpoint recovery and binary program compatibility of the test files must be achieved. This embodiment solves the cross-platform checkpoint recovery and program compatibility issues of the test files by generating multiple snapshot files compatible with different test platforms.

[0081] Example, Figure 3 This is one of the schematic diagrams of the process for generating snapshot files provided in an embodiment of the present invention. Figure 4 This is a second schematic diagram of the process for generating snapshot files provided in an embodiment of the present invention, as shown below. Figure 3 and Figure 4 As shown, the test file is loaded onto the first test platform to run the test file, and at least one snapshot file is generated based on the breakpoint information, specifically including:

[0082] S301. Load the test file onto the first test platform to run the test file.

[0083] Figure 5 This is a schematic diagram of test file loading provided in an embodiment of the present invention. Please refer to it. Figure 5 First, based on the size of the test file, the storage space of the first test platform is divided into a first header file storage area and a first test program storage area, which are used to store the first header file and the first test program respectively. Then, the obtained first header file is stored in the first header file storage area, and the first test program is stored in the first test program storage area. The starting storage address of the first header file storage area is set to the program counter reset address to facilitate the search and retrieval of the first header file.

[0084] S302. During operation, capture intermediate state data of the processor chip at different breakpoints.

[0085] Breakpoint information can be understood as information at different points in the runtime. Therefore, breakpoints in breakpoint information can be understood as points in time. During the test program's execution, intermediate state data of the processor chip is captured at different breakpoints. This intermediate state data is the entire memory data from the first test platform.

[0086] For example, when capturing intermediate state data of a processor chip, the internal mechanism of the first test platform or the GDB (GNU debugger) method can be used to capture the intermediate state data.

[0087] S303. Generate the second header file based on the intermediate state data and the attribute information of the first test platform.

[0088] For example, the intermediate state data exported from the entire memory of the first test platform specifically includes: flag bits, integer register backups, floating-point register backups, control and status register backups, program counter backups, and other data.

[0089] For example, the attribute information of the first test platform includes platform initialization information, restoration of the context and jump, and the underlying code of the external device driver, etc. Among them, the platform initialization information is related to the platform's compatibility, that is, it includes compatibility information applicable to the first test platform, and the underlying code of the external device driver is also related to platform compatibility.

[0090] When generating the second header file, initialization is performed first to complete the initialization process of boot1. Then, the context restoration and jump procedures in boot2 are executed. When the snapshot file flag is reached, the data in various registers and memory is exported and arranged as follows: Figure 2 Store the file in the format shown to obtain the second header file.

[0091] The data types and structure of the second header file are similar to those of the first header file, and can be found by referring to [the first header file]. Figure 2 The format of the first header file is shown. The only difference between the first and second header files is the content of the specific data.

[0092] S304. Generate a snapshot file based on the second header file and the first test program.

[0093] For example, the snapshot file is obtained by encapsulating the second header file and the first test program.

[0094] Understandably, since the breakpoint information includes multiple breakpoints, during a single run of the test program, intermediate state data can be captured at different breakpoints, resulting in multiple snapshot files. Each snapshot file is itself an executable binary file containing data from the entire memory. Correspondingly, the second header file in the snapshot file controls its execution to complete the performance test of the processor chip under test. Understandably, the differences between different snapshot files lie only in the second header file; each snapshot file includes a complete first test program.

[0095] The first test platform includes the processor chip under test. It is understood that this embodiment loads the test file onto the first test platform and runs it, capturing multiple snapshot files during the process. These snapshot files can reflect the intermediate state information of the processor chip, and thus the performance test of the processor chip can be completed by running multiple snapshot files.

[0096] S103. For each snapshot file, based on the attribute information corresponding to the second test platform used to load the snapshot file, the snapshot file is converted to obtain the converted snapshot file.

[0097] For example, the conversion of the snapshot file can be completed before loading it onto the corresponding second test platform, or it can be completed after loading it onto the corresponding second test platform; generally, the conversion of the snapshot file can be completed before loading it onto the corresponding second test platform, and the snapshot file can be run after loading.

[0098] For example, based on the attribute information corresponding to the second test platform used to load the snapshot file, the snapshot file is transformed to obtain the transformed snapshot file, specifically including:

[0099] Obtain the attribute information corresponding to the second test platform used to load the snapshot file; replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file; encapsulate the converted second header file and the first test program to obtain the converted snapshot file. After loading the converted snapshot file into the pre-loaded test platform, the cross-platform restoration of the snapshot file is completed.

[0100] In particular, by converting the snapshot files, the converted snapshot files are made compatible with the second test platform, so that the snapshot files can be tested on the second test platform, thus improving the testing efficiency.

[0101] In this embodiment, based on the platform attribute information of the pre-loaded test platform, a preset format conversion tool is invoked to modify the second header file of the snapshot file, resulting in a converted snapshot file. The conversion tool modifies the attribute information of the first test platform in the snapshot file according to the platform attribute information used to load the test platform, replacing it with the attribute information of the second test platform. The first test program of the snapshot file remains unchanged to obtain the converted snapshot file. Then, the converted snapshot file is loaded onto the corresponding second test platform. After loading the snapshot file onto the second test platform used to load it, the cross-platform restoration of the snapshot file is completed.

[0102] Figure 6 This is a schematic diagram of the snapshot conversion process provided in an embodiment of the present invention; as shown below. Figure 6 As shown, when it is necessary to convert the first snapshot file into the second snapshot file, the content of boot3 in the second header file of the first snapshot file is modified to the content of boot4. The content stored in boot3 is the platform attribute information (i.e., platform compatibility related information). By modifying the content in boot3, the second snapshot file is obtained. The first test program included in the first snapshot file and the second snapshot file is the same.

[0103] S104. Load the converted snapshot file onto the second test platform and run it to test the processor chip.

[0104] In this embodiment, the second test platform can be understood as a simulator used to run snapshot files. Different simulators can perform tests on different test items to simulate the processor chip's ability to process various types of data. Specifically, the simulators used in this embodiment may include ISA simulators, RTL simulators, FPGA simulators, etc.

[0105] Example, Figure 7 This is a schematic diagram of the snapshot text execution flow provided in an embodiment of the present invention. First, the snapshot file is loaded. After initialization, the contents of the snapshot file are read on a second test platform to restore the snapshot file. Then, a first test program is called and runs from the counter execution position to complete the execution test process of the snapshot file. Each snapshot file runs on a compatible second test platform to simulate the testing of the corresponding functions of the processor chip, which can improve testing efficiency. Furthermore, by using multiple second test platforms to run multiple snapshot files, multiple test results for multiple processor chips can be obtained. Based on multiple test results, the performance of the processor chip can be determined, which can also improve testing efficiency and shorten the testing cycle.

[0106] As can be seen, this embodiment first obtains the test file for testing the processor chip, then loads the test file onto the first test platform to run the test file, and generates at least one snapshot file based on the breakpoint information; in this way, multiple snapshot files can be generated at once by running the test file, and by converting the snapshot files, the compatibility problem of snapshot files on different second test platforms is overcome. Finally, the converted snapshot files are loaded onto the adapted second test platform to run, and the corresponding test results can be obtained, thus improving the testing efficiency of the processor chip.

[0107] The processor chip performance testing apparatus provided by the present invention is described below. The processor chip performance testing apparatus described below can be referred to in correspondence with the processor chip performance testing method described above.

[0108] Figure 8 This is a schematic diagram of the processor chip performance testing device provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the processor chip performance testing device 80 includes:

[0109] The acquisition unit 801 is used to acquire a test file for testing the processor chip. The test file includes a first header file and a first test program. The first header file includes breakpoint information for generating at least one snapshot file.

[0110] The snapshot generation unit 802 is used to load the test file onto the first test platform to run the test file and generate at least one snapshot file based on the breakpoint information.

[0111] The snapshot conversion unit 803 is used to convert each snapshot file based on the attribute information corresponding to the second test platform used to load the snapshot file, so as to obtain the converted snapshot file.

[0112] Test unit 804 is used to load the converted snapshot file onto the second test platform and run it to test the processor chip.

[0113] Optionally, the acquisition unit 801 is specifically used for:

[0114] Compile the first header file and set breakpoint information in the first header file to generate at least one snapshot file; compile the first test program; encapsulate the first header file and the first test program to obtain the test file.

[0115] Optionally, the snapshot generation unit 802 is specifically used for:

[0116] Load the test file onto the first test platform to run the test file;

[0117] During operation, intermediate state data of the processor chip is captured at different breakpoints; based on the intermediate state data and the attribute information of the first test platform, a second header file is generated.

[0118] Generate a snapshot file based on the second header file and the first test program.

[0119] The intermediate state data includes one or more of the following: integer register backup, floating-point register backup, control and status register backup, and program counter backup.

[0120] Optionally, the snapshot conversion unit 803 is specifically used for:

[0121] Obtain the attribute information corresponding to the second test platform used to load the snapshot file;

[0122] Replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file;

[0123] The converted second header file and the first test program are packaged together to obtain the converted snapshot file.

[0124] Optionally, the snapshot conversion unit 803 is also used for:

[0125] The pre-defined format conversion tool is invoked to convert the snapshot file's format. This tool modifies the second header file of the snapshot file based on the platform attribute information of the pre-loaded test platform to obtain the converted snapshot file.

[0126] The processor chip performance testing device 80 provided in this embodiment of the invention can execute the technical solution of the processor chip performance testing method in any of the above embodiments. Its implementation principle and beneficial effects are similar to those of the processor chip performance testing method. Please refer to the implementation principle and beneficial effects of the processor chip performance testing method. It will not be repeated here.

[0127] Figure 9 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of the present invention, such as... Figure 8 As shown, the electronic device may include a processor 910, a communications interface 920, a memory 930, and a communication bus 940, wherein the processor 910, communications interface 920, and memory 930 communicate with each other via the communication bus 940. The processor 910 can call logical instructions in the memory 930 to execute a processor chip performance testing method. This method includes: acquiring a test file for testing the processor chip, the test file including a first header file and a first test program; wherein the first header file includes breakpoint information for generating at least one snapshot file; loading the test file onto a first test platform to run the test file, generating at least one snapshot file based on the breakpoint information; for each snapshot file, converting the snapshot file based on attribute information corresponding to a second test platform used to load the snapshot file, obtaining a converted snapshot file; loading the converted snapshot file onto the second test platform and running it to test the processor chip.

[0128] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the processor chip performance testing method provided by the above methods. The method includes: obtaining a test file for testing the processor chip, the test file including a first header file and a first test program; wherein the first header file includes breakpoint information for generating at least one snapshot file; loading the test file onto a first test platform to run the test file, and generating at least one snapshot file according to the breakpoint information; for each snapshot file, converting the snapshot file based on attribute information corresponding to a second test platform used to load the snapshot file, to obtain a converted snapshot file; loading the converted snapshot file onto the second test platform and running it to test the processor chip.

[0130] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the processor chip performance testing method provided by the above methods. The method includes: acquiring a test file for testing the processor chip, the test file including a first header file and a first test program; wherein the first header file includes breakpoint information for generating at least one snapshot file; loading the test file onto a first test platform to run the test file, and generating at least one snapshot file based on the breakpoint information; for each snapshot file, converting the snapshot file based on attribute information corresponding to a second test platform used to load the snapshot file, to obtain a converted snapshot file; loading the converted snapshot file onto the second test platform and running it to test the processor chip.

[0131] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0132] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing the performance of a processor chip, characterized in that, include: Obtain a test file for testing a processor chip, the test file including a first header file and a first test program; wherein the first header file includes breakpoint information for generating at least one snapshot file; The test file is loaded onto the first test platform to run the test file, and at least one snapshot file is generated based on the breakpoint information; The step of loading the test file onto the first test platform to run the test file, and generating at least one snapshot file based on the breakpoint information, includes: The test file is loaded onto the first test platform to run the test file; During operation, intermediate state data of the processor chip is captured at different breakpoints; Based on the intermediate state data and the attribute information of the first test platform, a second header file is generated; The snapshot file is generated based on the second header file and the first test program; For each snapshot file, the snapshot file is transformed based on the attribute information corresponding to the second test platform used to load the snapshot file, resulting in a transformed snapshot file; The converted snapshot file is loaded onto the second test platform and run to test the processor chip.

2. The processor chip performance testing method according to claim 1, characterized in that, The intermediate state data includes one or more of the following: integer register backup, floating-point register backup, control and status register backup, and program counter backup.

3. The processor chip performance testing method according to claim 1, characterized in that, The step of converting the snapshot file based on the attribute information corresponding to the second test platform used to load the snapshot file to obtain a converted snapshot file includes: Obtain the attribute information corresponding to the second test platform used to load the snapshot file; Replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file; The converted second header file and the first test program are packaged together to obtain the converted snapshot file.

4. The processor chip performance testing method according to any one of claims 1-3, characterized in that, The process of obtaining test files for testing the processor chip includes: Compile the first header file and set breakpoint information in the first header file to generate at least one snapshot file; Compile the first test program; The first header file and the first test program are packaged together to obtain the test file.

5. A processor chip performance testing device, characterized in that, include: An acquisition unit is configured to acquire a test file for testing a processor chip, the test file including a first header file and a first test program; wherein, the first header file includes breakpoint information for generating at least one snapshot file; A snapshot generation unit is configured to load the test file onto a first test platform to run the test file, and generate at least one snapshot file based on the breakpoint information; the step of loading the test file onto the first test platform to run the test file and generating at least one snapshot file based on the breakpoint information includes: loading the test file onto the first test platform to run the test file; capturing intermediate state data of the processor chip at different breakpoints during the operation; generating a second header file based on the intermediate state data and the attribute information of the first test platform; and generating the snapshot file based on the second header file and the first test program. The snapshot conversion unit is used to convert each snapshot file based on the attribute information corresponding to the second test platform used to load the snapshot file, so as to obtain the converted snapshot file. The testing unit is used to load the converted snapshot file onto the second testing platform and run it to test the processor chip.

6. The processor chip performance testing apparatus according to claim 5, characterized in that, The snapshot conversion unit is specifically used for: Obtain the attribute information corresponding to the second test platform used to load the snapshot file; Replace the attribute information of the first test platform in the second header file with the attribute information of the second test platform to obtain the converted second header file; The converted second header file and the corresponding second test program are packaged together to obtain the converted snapshot file.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the processor chip performance testing method as described in any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the processor chip performance testing method as described in any one of claims 1 to 4.

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