Pixel circuit and display panel

Abstract

Embodiments of the present application disclose a pixel circuit and a display panel, wherein the pixel circuit comprises a light-emitting time control circuit, a current size control circuit and a light-emitting module; a first voltage control module of the light-emitting time control circuit controls transmission of a first voltage to a control end of a first switch module according to a first control signal, and controls transmission of a second voltage to the control end of the first switch module according to a second control signal, a first data signal and a ramp signal; a second voltage control module controls writing of a second data signal to a control end of a driving module, and the driving module generates a driving current to drive the light-emitting module to emit light according to a voltage of a control end of the driving module when the second data signal is written to the control end of the driving module and the first switch module is turned on. According to the technical scheme, the duration of the first switch module being turned on can be relatively accurate, the size of the driving current generated by the driving module is also relatively accurate, and thus a good display effect is ensured.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display panel. Background Technology

[0002] With the development of display technology, pixel circuits driven by mixed-signal technology are being used more and more widely in display panels.

[0003] In the prior art, pixel circuits driven by mixed analog and digital signals typically include an analog control section and a digital control section, wherein the analog control section is used to control the brightness of the light-emitting module, and the digital control section is used to control the duration of light emission of the light-emitting module.

[0004] However, in existing mixed-signal driven pixel circuits, the analog control section and the digital control section are closely related, which results in a leakage path between the gates of the transistors in the analog control section that play a major role in controlling the light emission time and the transistors in the digital control section that control the current magnitude, leading to poor display effects. Summary of the Invention

[0005] This invention provides a pixel circuit and a display panel to eliminate leakage paths between the light emission timing control circuit and the control terminal of the driving module, thereby improving the display effect.

[0006] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a light emission time control circuit, a current magnitude control circuit, and a light emission module;

[0007] The light emission time control circuit includes a first switching module and a first voltage control module electrically connected to the control terminal of the first switching module. The current magnitude control circuit includes a driving module and a second voltage control module electrically connected to the control terminal of the driving module. The first switching module, the driving module, and the light emission module are connected in series between a first power supply voltage input terminal and a second power supply voltage input terminal. The first voltage control module is used to control the transmission of a first voltage to the control terminal of the first switching module according to a first control signal, and to control the transmission of a second voltage to the control terminal of the first switching module according to a second control signal, a first data signal, and a ramp signal, so as to control the conduction time of the first switching module.

[0008] The second voltage control module is used to control the writing of the second data signal to the control terminal of the driving module. The driving module is used to generate a driving current according to the voltage of its own control terminal to drive the light-emitting module to emit light after the second data signal is written to the control terminal of the driving module and the first switch module is turned on.

[0009] Secondly, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in the first aspect.

[0010] This invention provides a pixel circuit and a display panel. The pixel circuit includes a light-emitting time control circuit, a current magnitude control circuit, and a light-emitting module. The first voltage control module of the light-emitting time control circuit controls the transmission of a first voltage to the control terminal of a first switching module based on a first control signal, and controls the transmission of a second voltage to the control terminal of the first switching module based on a second control signal, a first data signal, and a ramp signal, thereby controlling the conduction time of the first switching module. The second voltage control module controls the writing of a second data signal to the control terminal of a driving module. After the second data signal is written to the control terminal of the driving module and the first switching module is turned on, the driving module generates a driving current based on the voltage of its own control terminal to drive the light-emitting module to emit light, thereby controlling the brightness of the light-emitting module. In this embodiment, the first voltage control module is electrically connected to the control terminal of the first switching module, and the second voltage control module is electrically connected to the control terminal of the driving module. The control terminal of the first switch module is not connected to the control terminal of the drive module, and the control terminal of the first voltage control module is also not connected to the control terminal of the drive transistor. Therefore, there is no leakage path between the control terminal of the first switch module and the control terminal of the drive module, and there is no leakage path between the control terminal of the first voltage control module and the control terminal of the drive transistor. This allows the conduction time of the first switch module to be relatively accurate, regardless of whether the transistor that plays a major role in controlling the light emission time in the light emission time control circuit is in the first switch module or the first voltage control module, and the magnitude of the drive current generated by the drive module is also relatively accurate, thereby ensuring a good display effect. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0012] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0015] Figure 5 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0016] Figure 6 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0017] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0019] As described in the background section, in existing mixed-signal driven pixel circuits, the analog control section and the digital control section are closely integrated. This results in a leakage path between the gates of the transistors in the digital control section, which play a major role in controlling the emission time, and the transistors in the analog control section, which control the current magnitude. This leads to poor display performance. The inventors have discovered that the reason for this problem is that in existing mixed-signal driven pixel circuits, the digital control section typically includes multiple transistors and at least one capacitor. Among these transistors is a transistor that plays a major role in controlling the emission time. By controlling the on / off state of this transistor, the emission time of the light-emitting device in the pixel circuit is directly or indirectly controlled. The analog control section also includes multiple transistors, among which is a transistor (driving transistor) that plays a major role in controlling the current magnitude. The driving transistor generates a driving current to drive the light-emitting device. Different driving current magnitudes result in different brightness levels of the light-emitting device. In existing mixed-signal driven pixel circuits, there is a leakage path between the transistor that plays a major role in the digital control section and the driving transistor in the analog control section. This causes the gate potential of the transistor that plays a major role in the digital control section to affect the gate potential of the driving transistor in the analog control section. As a result, the conduction time of the transistor that plays a major role in controlling the light emission time in the digital control section is affected, and the driving current generated by the driving transistor is also affected. This leads to inaccurate control of the light emission time by the digital control section and inaccurate driving current generated by the driving transistor, ultimately resulting in poor display effect.

[0020] For the reasons stated above, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 1 The pixel circuit includes a light emission timing control circuit 110, a current magnitude control circuit 120, and a light emission module 130.

[0021] The light emission timing control circuit 110 includes a first switch module 111 and a first voltage control module 112 electrically connected to the control terminal of the first switch module 111. The current magnitude control circuit 120 includes a drive module 121 and a second voltage control module 122 electrically connected to the control terminal of the drive module 121. The first switch module 111, the drive module 121, and the light emission module 130 are connected in series between the first power supply voltage input terminal VDD and the second power supply voltage input terminal VSS. The first voltage control module 112 is used to control the transmission of the first voltage V1 to the control terminal of the first switch module 111 according to the first control signal Ctrl1, and to control the transmission of the second voltage V2 to the control terminal of the first switch module 111 according to the second control signal Ctrl2, the first data signal Vdata1, and the ramp signal Sweep, so as to control the conduction time of the first switch module 111.

[0022] The second voltage control module 122 is used to control the writing of the second data signal Vdata2 to the control terminal of the drive module 121. The drive module 121 is used to generate a drive current according to the voltage of its own control terminal to drive the light-emitting module 130 to emit light after the second data signal Vdata2 is written to the control terminal of the drive module 121 and the first switch module 111 is turned on.

[0023] The control terminals of the light emission time control circuit 110 and the drive module 121 are not connected.

[0024] Specifically, in this embodiment, the light emission timing control circuit 110 is equivalent to the digital control part in the existing digital-analog hybrid drive pixel circuit, and the current magnitude control circuit 120 is equivalent to the analog control part in the existing digital-analog hybrid drive pixel circuit.

[0025] The operation of the light emission timing control circuit 110 is as follows: When the first control signal Ctrl1 is a valid potential signal, the first voltage control module 112 transmits the first voltage V1 to the control terminal of the first switch module 111. When the second control signal Ctrl2 is a valid potential signal, the first voltage control module 112 controls the second voltage V2 to prevent it from being transmitted to the control terminal of the first switch module 111 according to the first data signal Vdata1. Furthermore, when the second control signal Ctrl2 is an invalid potential signal, the first voltage control module 112 controls the transmission state of the second voltage V2 to the control terminal of the first switch module 111 according to the voltage change of the ramp signal Sweep. Specifically, after the second control signal Ctrl2 changes from a valid potential signal to an invalid potential signal, the voltage of the ramp signal Sweep begins to change. When the voltage of the ramp signal Sweep changes to a certain level, the first voltage control module 112 controls the second voltage V2 to be transmitted to the control terminal of the first switch module 111. In different frames, when the voltage of the first data signal Vdata1 is different, the voltage of the slope signal Sweep also needs to change to different values. Only then will the first voltage control module 112 control the transmission of the second voltage V2 to the control terminal of the first switch module 111, thereby controlling the time required for the voltage at the control terminal of the first switch module 111 to change from the first voltage V1 to the second voltage V2. Optionally, in this embodiment, the first switch module 111 responds to the first voltage V1 at its own control terminal to turn on, and responds to the second voltage V2 at its own control terminal to turn off. From the above analysis, it can be seen that the first voltage control module 112 can control the conduction time of the first switch module 111 by controlling the transmission state of the first voltage V1 and the second voltage V2 to the first switch module 111, thereby controlling the light emission time of the light-emitting module 130.

[0026] The current magnitude control circuit 120 operates as follows: the second voltage control module 122 controls the writing of the second data signal Vdata2 (which can be a voltage signal) to the control terminal of the drive module 121. This allows the drive module 121 to generate a drive current based on the voltage at its control terminal when the first switch module 111 of the light emission time control circuit 110 is turned on, thereby driving the light emission module 130 to emit light. Specifically, different voltage levels of the second data signal Vdata2 result in different drive currents generated by the drive module 121, and the light emission module 130 responds to these different drive currents with varying brightness. Optionally, the drive module 121 includes a drive transistor.

[0027] Optionally, the light-emitting module 130 may include organic light-emitting devices or inorganic light-emitting devices, and this embodiment does not specifically limit it.

[0028] In this embodiment, the first voltage control module 112 is electrically connected to the control terminal of the first switch module 111, and the first voltage control module 112 may include multiple transistors. The second voltage control module 122 is electrically connected to the control terminal of the drive module 121. Since the control terminals of the first switch module 111 and the drive module 121 are not connected, there is no leakage path between them, and the potentials of the control terminals of the first switch module 111 and the drive module 121 will not affect each other. Similarly, the first voltage control module 112 is not connected to the control terminals of the drive transistors, so there is no leakage path between the internal devices (which may be the gates of the transistors included in the first voltage control module 112) and the control terminals of the drive module 121. Therefore, the gate potentials of the transistors included in the first voltage control module 112 and the control terminal potentials of the drive module 121 will not affect each other. With the above settings, regardless of whether the transistor in the light-emitting time control circuit 110, which plays a major role in controlling the light-emitting time, is located in the first switch module 111 or the first voltage control module 112, there is no connection between the control terminal of the first switch module 111 and the control terminal of the drive module 121, nor between the control terminals of the first voltage control module 112 and the drive module 121. There is also no leakage path between the control terminals of the first voltage control module 112 and the drive module 121. Therefore, the potential of the control terminal of the first switch module 111 can be maintained stably, and the conduction time of the first switch module 111 can be relatively accurate. Similarly, the potential of the control terminal of the drive module 121 can also be maintained stably, resulting in a relatively accurate driving current generated by the drive module 121, thus ensuring a good display effect.

[0029] The pixel circuit provided in this embodiment includes a light emission time control circuit, a current magnitude control circuit, and a light emission module. The first voltage control module of the light emission time control circuit controls the transmission of a first voltage to the control terminal of the first switch module according to a first control signal, and controls the transmission of a second voltage to the control terminal of the first switch module according to a second control signal, a first data signal, and a ramp signal, thereby controlling the conduction time of the first switch module. The second voltage control module controls the writing of a second data signal to the control terminal of the drive module. After the second data signal is written to the control terminal of the drive module and the first switch module is turned on, the drive module generates a drive current based on the voltage of its own control terminal to drive the light emission module to emit light, thereby controlling the brightness of the light emission module. In this embodiment, the first voltage control module is electrically connected to the control terminal of the first switch module, and the second voltage control module is electrically connected to the control terminal of the drive module. The control terminal of the first switch module is not connected to the control terminal of the drive module, and the control terminal of the first voltage control module is also not connected to the control terminal of the drive transistor. Therefore, there is no leakage path between the control terminal of the first switch module and the control terminal of the drive module, and there is no leakage path between the control terminal of the first voltage control module and the control terminal of the drive transistor. This allows the conduction time of the first switch module to be relatively accurate, regardless of whether the transistor that plays a major role in controlling the light emission time in the light emission time control circuit is in the first switch module or the first voltage control module, and the magnitude of the drive current generated by the drive module is also relatively accurate, thereby ensuring a good display effect.

[0030] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 2 Optionally, the first voltage control module 112 includes a first control unit 1121 and a second control unit 1122. The first control unit 1121 is used to control the transmission of the first voltage V1 to the control terminal of the first switch module 111 according to the first control signal Ctrl1. The second control unit 1122 is used to control the transmission of the second voltage V2 to the control terminal of the first switch module 111 according to the second control signal Ctrl2, the first data signal Vdata1, and the ramp signal Sweep. The first switch module 111 is used to turn on according to the first voltage V1 at its own control terminal and turn off according to the second voltage V2 at its own control terminal.

[0031] The slope signal Sweep includes a first voltage leveling segment, a second voltage leveling segment, and a voltage slope change segment between the first and second voltage leveling segments. The initial point of the voltage slope change segment is after the effective potential signal of the first control signal Ctrl1 and after the effective potential signal of the second control signal Ctrl2.

[0032] Specifically, when the first control signal Ctrl1 is a valid potential signal, the first control unit 1121 is turned on, transmitting the first voltage V1 to the control terminal of the first switch module 111; when the first control signal Ctrl1 is an invalid potential signal, the first control unit 1121 is turned off. When the second control signal Ctrl2 is a valid potential signal, the second control unit 1122 controls the second voltage V2 to prevent it from being transmitted to the control terminal of the first switch module 111 according to the first data signal Vdata1. Furthermore, when the second control signal Ctrl2 is an invalid potential signal, the second control unit 1122 controls the transmission state of the second voltage V2 to the control terminal of the first switch module 111 according to the voltage change of the ramp signal Sweep. In this embodiment, the first switch module 111 can be turned on based on the first voltage at its control terminal and turned off based on the second voltage at its control terminal.

[0033] In this embodiment, within one frame, according to the chronological order, the Sweep signal includes a first voltage leveling segment, a voltage slope changing segment, and a second voltage leveling segment. The initial point of the voltage slope changing segment is after the effective potential signal of the first control signal Ctrl1 and after the effective potential signal of the second control signal Ctrl2. This allows the first control unit 1121 to turn on in response to the effective potential signal of the first control signal Ctrl1, transmitting the first voltage to the control terminal of the first switch module 111. The voltage of the Sweep signal only begins to change after the second control unit 1122 responds to the effective potential signal of the second control signal Ctrl2 and controls the second voltage to be prevented from being transmitted to the control terminal of the first switch module 111 according to the first data signal Vdata1. That is, before the voltage of the Sweep signal changes, the first switch module 111 can turn on according to the first voltage V1 written to its control terminal. As the slope voltage changes, when the slope voltage changes to a certain level, the second control unit 1122 controls the second voltage V2 to be transmitted to the control terminal of the first switch module 111, causing the first switch module 111 to turn off. Specifically, the value at which the voltage of the slope signal Sweep changes to trigger the second control unit 1122 to transmit the second voltage V2 to the control terminal of the first switch module 111 is related to the magnitude of the first data signal Vdata1. Therefore, by setting the slope signal Sweep to include a first voltage leveling segment, a second voltage leveling segment, and a voltage slope change segment between the first and second voltage leveling segments, with the initial point of the voltage slope change segment following the effective potential signal of the first control signal Ctrl1 and the effective potential signal of the second control signal Ctrl2, the timing of the change from the first voltage to the second voltage at the control terminal of the first switch module 111 can be controlled, thereby controlling the conduction time of the first switch module 111.

[0034] Continue to refer to Figure 2Optionally, the light emission time control circuit 110 also includes a first storage unit 113, which is used to store the voltage of the control terminal of the first switch module 111.

[0035] Continue to refer to Figure 2 Optionally, the first switching module 111 includes a first transistor T1, the gate of the first transistor T1 serves as the control terminal of the first switching module 111, the first terminal of the first transistor T1 is electrically connected to the first power supply voltage input terminal VDD, the second terminal of the first transistor T1 is electrically connected to the first terminal of the driving module 121, the second terminal of the driving module 121 is connected to the first terminal of the light-emitting module 130, the second terminal of the light-emitting module 130 is electrically connected to the second power supply voltage input terminal VSS, one end of the first storage unit 113 is connected to the gate of the first transistor T1, and the other end of the first storage unit 113 is connected to the first power supply voltage input terminal VDD.

[0036] Optionally, the driving module 121 includes a driving transistor DT, the gate of the driving transistor DT serves as the control terminal of the driving module 121, the first terminal of the driving transistor DT serves as the first terminal of the driving module 121, and the second terminal of the driving transistor DT serves as the second terminal of the driving module 121.

[0037] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 3 Optionally, the first control unit 1121 includes a second transistor T2, the gate of the second transistor T2 is connected to a first control signal Ctrl1, the first terminal of the second transistor T2 is connected to a first voltage V1, and the second terminal of the second transistor T2 is electrically connected to the control terminal of the first switching module 111.

[0038] The second transistor T2 can be either a P-type transistor or an N-type transistor. When the second transistor T2 is a P-type transistor, the effective potential signal of the first control signal Ctrl1 is a low potential signal; when the second transistor T2 is an N-type transistor, the effective potential signal of the first control signal Ctrl1 is a high potential signal. Optionally, the first storage cell 113 includes a first storage capacitor Cst1.

[0039] Continue to refer to Figure 3Optionally, the second control unit 1122 includes a data writing subunit 11221, a time control subunit 11222, and a coupling subunit 11223. The data writing subunit 11221 is used to write a first data signal Vdata1 to the control terminal of the time control subunit 11222 according to the second control signal Ctrl2. The coupling subunit 11223 is used to couple the change of the slope signal Sweep to the control terminal of the time control subunit 11222 according to the positive correlation. The time control subunit 11222 is used to control the transmission of the second voltage V2 to the control terminal of the first switch module 111 according to the voltage of its own control terminal.

[0040] In this embodiment, the time control subunit 11222 controls the transmission of low voltage to the control terminal of the first switch module 111 based on the voltage of its own control terminal, thereby controlling the first switch module 111 to change from an on state to an off state. Therefore, the time control subunit 11222 is the internal device in the first voltage control module 112 that plays a major role in controlling the light emission time. In this embodiment, there is no connection between the control terminal of the time control subunit 11222 and the control terminal of the drive module 121. Therefore, there is no leakage path between the control terminal of the time control subunit 11222 and the control terminal of the drive module 121, so that the control of the light emission duration by the light emission time control circuit 110 and the control of the drive current by the current magnitude control circuit 120 do not affect each other, thus ensuring a good display effect.

[0041] Specifically, when the second control signal Ctrl2 is a valid potential signal, the data writing subunit 11221 is turned on, transmitting the first data signal Vdata1 to the control terminal of the time control subunit 11222. After the first data signal Vdata1 is written to the control terminal of the time control subunit 11222, the time control subunit 11222 is turned off according to the first data signal Vdata1 at its own control terminal. After the first data signal Vdata1 is written to the control terminal of the time control subunit 11222, the voltage of the slope signal Sweep changes. The coupling subunit 11223 couples the voltage change of the slope signal Sweep to the control terminal of the time control subunit 11222 in a positive correlation, causing a change in the potential of the control terminal of the time control subunit 11222. When the voltage change of the slope signal Sweep is positively coupled to the control terminal of the time control subunit 11222, enabling the time control subunit 11222 to turn on, the second voltage V2 is transmitted to the control terminal of the first switch module 111 through the time control subunit 11222.

[0042] Continue to refer to Figure 3Optionally, the data writing subunit 11221 includes a third transistor T3, the time control subunit 11222 includes a fourth transistor T4, and the coupling subunit 11223 includes a first capacitor C1. The gate of the third transistor T3 is connected to a second control signal Ctrl2, the first terminal of the third transistor T3 is connected to a first data signal Vdata1, and the second terminal of the third transistor T3 is electrically connected to the gate of the fourth transistor T4. The first terminal of the first capacitor C1 is connected to a ramp signal Sweep, and the second terminal of the first capacitor C1 is electrically connected to the gate of the fourth transistor T4. The first terminal of the fourth transistor T4 is connected to a second voltage V2, and the second terminal of the fourth transistor T4 is electrically connected to the control terminal of the first switching module 111.

[0043] In this embodiment, both the third transistor T3 and the fourth transistor T4 can be either P-type or N-type transistors; no specific limitation is made here. When the third transistor T3 is a P-type transistor, the effective potential signal of the second control signal Ctrl2 is a low potential signal; when the third transistor T3 is an N-type transistor, the effective potential signal of the second control signal Ctrl2 is a high potential signal.

[0044] Optionally, the absolute value of the difference between the first data signal Vdata1 and the second voltage V2 is less than the absolute value of the threshold voltage of the fourth transistor T4.

[0045] Specifically, when the fourth transistor T4 is a P-type transistor, its threshold voltage is negative. The turn-on condition for T4 is that the difference between its gate voltage and source voltage is less than or equal to its threshold voltage. The corresponding turn-off condition is that the difference between its gate voltage and source voltage is greater than its threshold voltage. When the fourth transistor T4 is an N-type transistor, its threshold voltage is positive. The turn-on condition for T4 is that the difference between its gate voltage and source voltage is greater than or equal to its threshold voltage. The corresponding turn-off condition is that the difference between its gate voltage and source voltage is less than its threshold voltage. In this embodiment, by setting the absolute value of the difference between the first data signal Vdata1 and the second voltage to be less than the absolute value of the threshold voltage of the fourth transistor T4, the fourth transistor T4 can be turned off after the first data signal Vdata1 is written to the gate of the fourth transistor T4, regardless of whether the fourth transistor T4 is a P-type transistor or an N-type transistor.

[0046] Optionally, the absolute value of the difference between the first voltage V1 and the first power supply voltage input at the first power supply voltage input terminal VDD is greater than or equal to the absolute value of the threshold voltage of the first transistor T1.

[0047] Specifically, when the first transistor T1 is a P-type transistor, its threshold voltage is negative. The turn-on condition for the first transistor T1 is that the difference between its gate voltage and source voltage is less than or equal to its threshold voltage. The corresponding turn-off condition is that the difference between its gate voltage and source voltage is greater than its threshold voltage. When the first transistor T1 is an N-type transistor, its threshold voltage is positive. The turn-on condition for the first transistor T1 is that the difference between its gate voltage and source voltage is greater than or equal to its threshold voltage. The corresponding turn-off condition is that the difference between its gate voltage and source voltage is less than its threshold voltage. In this embodiment, by setting the absolute value of the difference between the first voltage V1 and the first power supply voltage input at the first power supply voltage input terminal VDD to be greater than or equal to the absolute value of the threshold voltage of the first transistor T1, the first transistor T1 can be turned on after the first voltage is written to the gate of the first transistor T1, regardless of whether the first transistor T1 is a P-type transistor or an N-type transistor.

[0048] Optionally, the first control signal Ctrl1 and the second control signal Ctrl2 can be the same control signal, meaning that the control terminal of the first control unit 1121 and the control terminal of the data writing subunit 11221 are connected to the same control signal. Correspondingly, the control terminals of the first control unit 1121 and the data writing subunit 11221 are connected to the same signal line, which reduces the number of signal lines in the display panel including the pixel circuit of this embodiment, thus simplifying the wiring structure. When the first control signal Ctrl1 and the second control signal Ctrl2 are the same control signal, the second transistor T2 and the third transistor T3 have the same channel type, so the second transistor T2 and the third transistor T3 are simultaneously turned on. In other optional embodiments, the first control signal Ctrl1 and the second control signal Ctrl2 can be different control signals, but it is necessary to ensure that the effective potential signal of the first control signal Ctrl1 and the effective potential signal of the second control signal Ctrl2 are before the light-emitting stage to control the conduction duration of the first switching module 111.

[0049] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 4Optionally, the second control unit 1122 further includes a compensation subunit 11224 and a write control subunit 11225. The compensation subunit 11224 is used to write information including the threshold voltage of the time control subunit 11222 to the control terminal of the time control subunit 11222 according to the second control signal Ctrl2. The write control subunit 11225 is used to turn off when the data write subunit 11221 is turned on, and to turn on after the data write subunit 11221 is turned off.

[0050] Optionally, the data writing subunit 11221 includes a third transistor T3, the time control subunit 11222 includes a fourth transistor T4, the coupling subunit 11223 includes a first capacitor C1, and the compensation subunit 11224 includes a fifth transistor T5; the gate of the third transistor T3 is connected to the second control signal Ctrl2, the first terminal of the third transistor T3 is connected to the first data signal Vdata1, and the second terminal of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4; the gate of the fifth transistor T5 is connected to the second control signal Ctrl2, and the first terminal of the fifth transistor T5 is electrically connected to the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5 is electrically connected to the gate of the fourth transistor T4; the first terminal of the fourth transistor T4 is connected to a second voltage through the write control subunit 11225, and the second terminal of the fourth transistor T4 is electrically connected to the control terminal of the first switch module 111; the first terminal of the first capacitor C1 is connected to the slope signal Sweep, and the second terminal of the first capacitor C1 is electrically connected to the gate of the fourth transistor T4; wherein, the effective potential signal of the first control signal Ctrl1 is after the effective potential signal of the second control signal Ctrl2.

[0051] Optionally, the write control subunit 11225 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to a second voltage to transmit the control signal Ctrl0, the first terminal of the sixth transistor T6 is connected to a second voltage V2, and the second terminal of the sixth transistor T6 is connected to the first terminal of the fourth transistor T4.

[0052] In this embodiment, the conduction states of the data writing subunit 11221 and the compensation subunit 11224 are controlled by the second control signal Ctrl2, and the conduction state of the first control unit 1121 is controlled by the first control signal Ctrl1. Since the effective potential signal of the first control signal Ctrl1 follows the effective potential signal of the second control signal Ctrl2, the first control unit 1121 conducts after the data writing subunit 11221 and the compensation subunit 11224 are turned on. That is, in this embodiment, when the effective potential signal of the second control signal Ctrl2 is received, the first data signal Vdata1 is first written to the control terminal of the time control subunit 11222 through the data writing subunit 11221, the time control subunit 11222, and the compensation subunit 11224, causing the time control subunit 11222 to turn off. Because the time control subunit 11222 conducts when the first data signal Vdata1 is written to its control terminal, the control terminal of the first switch module 111 will be written with the first data signal Vdata1. Then, the effective potential signal of the first control signal Ctrl1 writes the first voltage to the control terminal of the first switch module 111 through the first control unit 1121. This ensures that when entering the light emission stage, the first switch module 111 can be turned on according to the first voltage V1 of its own control terminal. As the voltage of the slope signal Sweep changes, the potential of the control terminal of the time control subunit 11222 is coupled and changes. When the potential of the control terminal of the time control subunit 11222 is coupled to meet the turn-on condition of the time control subunit 11222, the time control subunit 11222 is turned on, and the second voltage V2 is transmitted to the control terminal of the first switch module 111 through the writing control subunit 11225 and the time control subunit 11222, so that the first switch module 111 is turned off, thereby realizing the control of the light emission time.

[0053] In this embodiment, connecting the first terminal of the time control subunit 11222 to the write control subunit 11225 ensures that when the first data signal Vdata1 is written to the control terminal of the time control subunit 11222 (while the write control subunit 11225 is turned off), the second voltage will not be transmitted to the first terminal of the time control subunit 11222, thus guaranteeing the successful writing of the first data signal Vdata1. After writing the data signal to the control terminal of the time control subunit 11222, the write control subunit 11225 is turned on, so that when the time control subunit 11222 is turned on, the second voltage can be transmitted to the control terminal of the first switch module 111.

[0054] Optionally, the absolute value of the difference between the first data signal Vdata1 and the second voltage V2 is less than the absolute value of the threshold voltage of the fourth transistor T4.

[0055] Optionally, the absolute value of the difference between the first voltage V1 and the first power supply voltage input at the first power supply voltage input terminal VDD is greater than or equal to the absolute value of the threshold voltage of the first transistor T1.

[0056] Continue to refer to Figure 4 Optionally, the second control unit 1122 further includes an initialization subunit 11226, which is used to transmit the first initialization voltage Vint1 to the control terminal of the time control subunit 11222 before the data writing subunit 11221 writes the first data signal Vdata1 to the control terminal of the time control subunit 11222.

[0057] Optionally, the initialization subunit 11226 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the initialization control signal Ctrl3, the first terminal of the initialization subunit 11226 is connected to the first initialization voltage Vint1, and the second terminal of the initialization subunit 11226 is connected to the control terminal of the time control subunit 11222.

[0058] Specifically, before the data writing subunit 11221 writes the first data signal Vdata1 to the control terminal of the time control subunit 11222, the initialization subunit 11226 transmits the first initialization voltage Vint1 to the control terminal of the time control subunit 11222. For any first data signal Vdata1, the difference between the first initialization voltage Vint1 and the first data voltage satisfies the conduction condition of the time control subunit 11222, thereby ensuring that after the first initialization voltage Vint1 is written to the control terminal of the time control subunit 11222, the time control subunit 11222 can be turned on when writing the first data signal Vdata1 to the time control subunit 11222, thus ensuring the smooth writing of the first data signal Vdata1.

[0059] In this invention, the second voltage control module may include various structures. Figure 3 and Figure 4 Examples of two different structures for the second voltage control module are given respectively.

[0060] refer to Figure 3 Optionally, the second voltage control module 122 includes a data writing unit 1221 and a second storage unit 1222. The data writing unit 1221 is used to control the writing of the second data signal Vdata2 to the control terminal of the drive module 121 according to the third control signal SPAM. The second storage unit 1222 is used to store the voltage of the control terminal of the drive module 121.

[0061] Optionally, the control terminal of the data writing unit 1221 is connected to the third control signal SPAM, the first terminal of the data writing unit 1221 is connected to the second data signal Vdata2, and the second terminal of the data writing unit 1221 is electrically connected to the control terminal of the drive module 121.

[0062] refer to Figure 3 Optionally, the data writing unit 1221 includes an eighth transistor T8, the gate of which serves as the control terminal of the data writing unit 1221, the first terminal of which serves as the first terminal of the data writing unit 1221, and the second terminal of which serves as the second terminal of the data writing unit 1221. Optionally, the second storage unit 1222 includes a second storage capacitor Cst2.

[0063] Continue to refer to Figure 3 Optionally, the pixel circuit further includes an emissive control module 140. The first switch module 111, the drive module 121, the emissive control module 140, and the emissive module 130 are connected in series between the first power supply voltage input terminal VDD and the second power supply voltage input terminal VSS to form a drive branch. The emissive control module 140 is used to turn on during the emissive phase to turn on the drive branch. The effective potential signal of the emissive control signal EM is after the effective potential signal of the first control signal Ctrl1 and after the effective potential signal of the second control signal Ctrl2. The voltage ramp change segment of the ramp signal Sweep is located within the time period of the effective potential signal of the emissive control signal EM. The effective potential signal of the emissive control signal EM is after the effective potential signal of the third control signal SPAM.

[0064] Specifically, by setting a light-emitting control module 140 in the pixel circuit, and setting the effective potential signal of the light-emitting control signal EM connected to the control terminal of the light-emitting control module 140 (when the light-emitting control signal EM connected to the control terminal of the light-emitting control module 140 is an effective potential signal, the light-emitting control module 140 is turned on) after the effective potential signal of the first control signal Ctrl1 and after the effective potential signal of the second control signal Ctrl2, the voltage slope change segment of the slope signal Sweep is located within the time period of the effective potential signal of the light-emitting control signal EM; the effective potential signal of the light-emitting control signal EM is after the effective potential signal of the third control signal SPAM, so that before entering the light-emitting stage, the first data signal Vdata1 can be written to the gate of the fourth transistor T4, the first voltage V1 can be written to the gate of the first transistor T1, thereby realizing the control of the conduction time of the first transistor T1, and the second data signal Vdata2 can be written to the gate of the driving transistor DT, thereby realizing the control of the driving current magnitude during the light-emitting stage.

[0065] Continue to refer to Figure 3Optionally, the light-emitting control module 140 includes a ninth transistor T9, the gate of the ninth transistor T9 serving as the control terminal of the light-emitting control module 140, the first electrode of the ninth transistor T9 serving as the first terminal of the light-emitting control module 140, and the second electrode of the ninth transistor T9 serving as the second terminal of the light-emitting control module 140.

[0066] Optionally, the initial point of the voltage ramp transition segment coincides with the transition point where the light emission control signal EM changes from an invalid potential signal to an effective potential signal.

[0067] Specifically, if the initial point of the voltage ramp transition is before the transition point where the light-emitting control signal EM changes from an invalid potential signal to an effective potential signal, it may result in the fourth transistor T4 already being turned on when the light-emitting control signal EM changes from an invalid potential signal to an effective potential signal. This would allow the second voltage to be transmitted to the gate of the first transistor T1, causing the first transistor T1 to turn off. Consequently, when the light-emitting control signal EM is an effective potential signal, the first transistor T1 cannot be turned on, preventing the light-emitting module 130 from lighting up during the light-emitting stage. Conversely, if the initial point of the voltage ramp transition is after the transition point where the light-emitting control signal EM changes from an invalid potential signal to an effective potential signal, it may result in the fourth transistor T4 not being turned on during the entire light-emitting stage. This would prevent the second voltage from being transmitted to the gate of the first transistor T1, making it impossible to control the light-emitting time. In this embodiment, by setting the initial point of the voltage ramp change segment to coincide with the transition point where the light emission control signal EM jumps from an invalid potential signal to an effective potential signal, it is beneficial to ensure that the first transistor T1 can be turned on for at least a portion of the time period when the light emission control signal EM is an effective potential signal. On the other hand, it is beneficial to ensure that the fourth transistor T4 can be turned on during the time period when the light emission control signal EM is an effective potential signal, so that the second voltage can be transmitted to the gate of the first transistor T1, causing the first transistor T1 to turn off, thereby realizing the control of the light emission time.

[0068] Figure 5 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 3 The pixel circuit shown is for reference. Figure 3 and Figure 5 Taking a pixel circuit where all transistors are P-type transistors as an example, the working process of the pixel circuit includes a first data writing stage t1, a second data writing stage t2, and a light emission stage t3.

[0069] During the first data writing stage t1, the third control signal SPAM is at a low potential, the eighth transistor T8 is turned on, and the second data signal Vdata2 is written to the gate of the driving transistor DT through the eighth transistor T8.

[0070] During the second data writing stage t2, the first control signal Ctrl1 and the second control signal Ctrl2 are at low potentials, the second transistor T2 and the third transistor T3 are turned on, the first voltage V1 is transmitted to the gate of the first transistor T1 through the second transistor T2, and the first transistor T1 is turned on; the first data signal Vdata1 is transmitted to the gate of the fourth transistor T4 through the third transistor T3, causing the fourth transistor T4 to be turned off.

[0071] During the light-emitting stage t3, the light-emitting control signal EM is at a low potential, and the ninth transistor T9 is turned on. After the second data writing stage, the first voltage V1 is transmitted to the gate of the first transistor T1, turning it on and transmitting the first power supply voltage to the first terminal of the driving transistor DT. During the first data writing stage, the second data signal Vdata2 is transmitted to the gate of the driving transistor DT, turning it on. Therefore, the entire driving branch is turned on. The driving transistor DT generates a driving current based on the second data signal Vdata2 at its gate and the first power supply voltage at its first terminal, thus controlling the magnitude of the driving current. The light-emitting module 130 emits light according to the driving current generated by the driving transistor DT. As the voltage of the slope signal Sweep changes (where the voltage of the slope signal Sweep changes from high to low when the fourth transistor T4 is a P-type transistor), the gate voltage of the fourth transistor T4 gradually decreases from the first data voltage corresponding to the first data signal Vdata1. When the gate voltage of the fourth transistor T4 decreases to a value less than the threshold voltage of the fourth transistor T4 compared with the second voltage V2, the fourth transistor T4 turns on, transmitting the second voltage V2 to the gate of the first transistor T1, causing the first transistor T1 to turn off, thereby disconnecting the entire driving branch and stopping the light-emitting module 130 from emitting light, thus realizing the control of the light-emitting time of the light-emitting module 130.

[0072] Figure 4 Another structure of the second voltage control module 122 is shown in the figure, see reference. Figure 4Optionally, the second voltage control module 122 includes a data writing unit 1221 and a second storage unit 1222. The data writing unit 1221 is used to control the writing of the second data signal Vdata2 to the control terminal of the drive module 121 according to the third control signal SPAM. The second storage unit 1222 is used to store the voltage of the control terminal of the drive module 121. The second voltage control module 122 also includes a compensation unit 1223. The control terminal of the data writing unit 1221 is connected to the third control signal SPAM. The first terminal of the data writing unit 1221 is connected to the second data signal Vdata2. The second terminal of the data writing unit 1221 is electrically connected to the first terminal of the drive module 121. The control terminal of the compensation unit 1223 is connected to the third control signal SPAM. The first terminal of the compensation unit 1223 is electrically connected to the second terminal of the drive module 121. The second terminal of the compensation unit 1223 is electrically connected to the control terminal of the drive module 121.

[0073] refer to Figure 4 Optionally, the data writing unit 1221 includes an eighth transistor T8, the gate of which serves as the control terminal of the data writing unit 1221, the first terminal of which serves as the first terminal of the data writing unit 1221, and the second terminal of which serves as the second terminal of the data writing unit 1221. The compensation unit 1223 includes a tenth transistor T10, the gate of which serves as the control terminal of the compensation unit 1223, the first terminal of which serves as the first terminal of the compensation unit 1223, and the second terminal of which serves as the second terminal of the compensation unit 1223.

[0074] Continue to refer to Figure 4 Based on the above technical solution, the second voltage control module 122 further includes an initialization unit 1224, which is used to transmit a second initialization voltage Vint2 to the control terminal of the drive module 121 according to the fourth control signal VST, wherein the effective potential signal of the fourth control signal VST precedes the effective potential signal of the third control signal SPAM.

[0075] Optionally, the second initialization unit 1224 includes an eleventh transistor T11, the gate of the eleventh transistor T11 serving as the control terminal of the initialization unit 1224, the first terminal of the eleventh transistor T11 serving as the first terminal of the initialization unit 1224, and the second terminal of the eleventh transistor T11 serving as the second terminal of the second initialization unit 1224.

[0076] It should be noted that, in Figure 3 Based on the pixel circuit shown, the second voltage control module may also include an initialization unit. The structure and connection relationship of the initialization unit can be similar to those of the second voltage control module. Figure 4 The initialization units are the same, so they will not be repeated here.

[0077] Continue to refer to Figure 4 Optionally, the pixel circuit further includes an emissive control module 140. The first switch module 111, the drive module 121, the emissive control module 140, and the emissive module 130 are connected in series between the first power supply voltage input terminal VDD and the second power supply voltage input terminal VSS to form a drive branch. The emissive control module 140 is used to turn on during the emissive phase to turn on the drive branch. The effective potential signal of the emissive control signal EM is after the effective potential signal of the first control signal Ctrl1 and after the effective potential signal of the second control signal Ctrl2. The voltage ramp change segment of the ramp signal Sweep is located within the time period of the effective potential signal of the emissive control signal EM. The effective potential signal of the emissive control signal EM is after the effective potential signal of the third control signal SPAM.

[0078] Continue to refer to Figure 4 Optionally, the light-emitting control module 140 includes a ninth transistor T9. The gate of the ninth transistor T9 serves as the control terminal of the light-emitting control module 140, the first electrode of the ninth transistor T9 serves as the first terminal of the light-emitting control module 140, and the second electrode of the ninth transistor T9 serves as the second terminal of the light-emitting control module 140. Optionally, the initial point of the voltage ramp transition segment coincides with the transition point where the light-emitting control signal EM transitions from an invalid potential signal to an valid potential signal. In this embodiment, the light-emitting control module 140 and... Figure 3 The light emission control module 140 in the pixel circuit shown has the same function, and will not be described again here.

[0079] Figure 6 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 The pixel circuit shown is for reference. Figure 4 and Figure 6 Taking a pixel circuit where all transistors are P-type transistors as an example, the working process of the pixel circuit includes a first initialization stage t11, a first data writing stage t12, a second initialization stage t21, a second data writing stage t22, a first voltage writing stage t30, and a light emission stage t31.

[0080] In the first initialization phase t11, the fourth control signal VST is at a low potential, and the eleventh transistor T11 is turned on, transmitting the second initialization voltage Vint2 to the gate of the driving transistor DT, thereby initializing the gate potential of the driving transistor DT. This allows the driving transistor DT to be turned on during the first data writing phase t12, ensuring that the second data signal Vdata2 can be successfully written to the gate of the driving transistor DT during the first data writing phase t12.

[0081] During the first data writing stage t12, the third control signal SPAM is at a low potential, the eighth transistor T8 and the tenth transistor T10 are turned on, and the second data signal Vdata2 is written to the gate of the driving transistor DT through the eighth transistor T8, the driving transistor DT and the tenth transistor T10, thereby realizing the writing of the second data signal Vdata2 to the gate of the driving transistor DT and the compensation of the threshold voltage of the driving transistor DT.

[0082] In the second initialization phase t21, the initialization control signal Ctrl3 is at a low potential, the seventh transistor T7 is turned on, and the first initialization voltage Vint1 is transmitted to the gate of the fourth transistor T4 through the seventh transistor T7.

[0083] During the second data writing phase t22, the second control signal Ctrl2 is at a low level, and the second voltage transmission control signal Ctrl0 is at a high level. The third transistor T3 and the fifth transistor T5 are turned on, while the sixth transistor T6 is turned off. The first data signal Vdata1 is transmitted to the gate of the fourth transistor T4 through the third transistor T3, the fourth transistor T4, and the fifth transistor T5, thus writing the first data signal Vdata1 to the gate of the fourth transistor T4 and compensating for the threshold voltage of the fourth transistor T4. After the first data signal Vdata1 is written to the gate of the fourth transistor T4, the fourth transistor T4 is turned off.

[0084] During the first voltage writing phase t30, the first control signal Ctrl1 is at a low potential, the second transistor T2 is turned on, and the first voltage is transmitted to the gate of the first transistor T1, causing the first transistor T1 to turn on. Furthermore, during the first voltage writing phase t30, the second voltage transmission control signal Ctrl0 is at a low potential, the sixth transistor T6 is turned on, and the second voltage is transmitted to the first terminal of the fourth transistor T4.

[0085] During the light-emitting stage t31, the light-emitting control signal EM is at a low potential, and the ninth transistor T9 is turned on. After the first voltage writing stage t30, the first voltage V1 is transmitted to the gate of the first transistor T1, turning it on and transmitting the first power supply voltage to the first terminal of the driving transistor DT. During the first data writing stage t12, the second data signal Vdata2 is transmitted to the gate of the driving transistor DT, turning it on. Therefore, the entire driving branch is turned on. The driving transistor DT generates a driving current based on the second data signal Vdata2 at its gate and the first power supply voltage at its first terminal, thus controlling the magnitude of the driving current. The light-emitting module 130 emits light according to the driving current generated by the driving transistor DT. As the voltage of the slope signal Sweep changes (where the voltage of the slope signal Sweep changes from high to low when the fourth transistor T4 is a P-type transistor), the gate voltage of the fourth transistor T4 gradually decreases from the first data voltage corresponding to the first data signal Vdata1. When the gate voltage of the fourth transistor T4 decreases to a value less than the threshold voltage of the fourth transistor T4 compared with the second voltage V2, the fourth transistor T4 turns on, transmitting the second voltage to the gate of the first transistor T1, causing the first transistor T1 to turn off, thereby disconnecting the entire driving branch and stopping the light-emitting module 130 from emitting light, thus realizing the control of the light-emitting time of the light-emitting module 130.

[0086] This invention also provides a display panel. Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 7 The display panel 10 includes the pixel circuit 100 of any of the above embodiments of the present invention.

[0087] Continue to refer to Figure 7 Optionally, the display panel also includes light emission control signal lines (E1, E2, E3, E4...) and ramp signal lines (SW1, SW2, SW3, SW4...). Each light emission control signal line is connected to at least one row of pixel circuits, and each ramp signal line is connected to at least one row of pixel circuits. The light emission control signal lines are interconnected, and the ramp signal lines are interconnected.

[0088] Specifically, by interconnecting the light-emitting control signal lines and the ramp signal lines, each pixel circuit in the display panel can enter the light-emitting stage together after completing all stages before the light-emitting stage. Therefore, there is no need to set up a light-emitting control drive circuit with a multi-stage cascaded shift register structure, simplifying the circuit structure for providing the light-emitting control signals. Similarly, by interconnecting the ramp signal lines, the ramp signals transmitted by the ramp signal lines are identical, further simplifying the circuit structure for providing the ramp signals.

[0089] In other optional embodiments of the present invention, each light emission control signal line may be connected to at least one row of pixel circuits, each ramp signal line may be connected to at least one row of pixel circuits, and the light emission control signal lines and ramp signal lines may be disconnected. This embodiment is not specifically limited here.

[0090] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: Light emission timing control circuit, current magnitude control circuit, and light emission module; The light emission time control circuit includes a first switching module and a first voltage control module electrically connected to the control terminal of the first switching module. The current magnitude control circuit includes a driving module and a second voltage control module electrically connected to the control terminal of the driving module. The first switching module, the driving module, and the light emission module are connected in series between a first power supply voltage input terminal and a second power supply voltage input terminal. The first voltage control module is used to control the transmission of a first voltage to the control terminal of the first switching module according to a first control signal, and to control the transmission of a second voltage to the control terminal of the first switching module according to a second control signal, a first data signal, and a ramp signal, so as to control the conduction time of the first switching module. The second voltage control module is used to control the writing of the second data signal to the control terminal of the driving module. The driving module is used to generate a driving current according to the voltage of its own control terminal to drive the light-emitting module to emit light after the second data signal is written to the control terminal of the driving module and the first switch module is turned on. The first voltage control module includes a first control unit and a second control unit. The first control unit is used to control the transmission of the first voltage to the control terminal of the first switch module according to the first control signal. The second control unit is used to control the transmission of the second voltage to the control terminal of the first switching module according to the second control signal, the first data signal and the ramp signal; The ramp signal includes a first voltage leveling segment, a second voltage leveling segment, and a voltage ramp change segment between the first voltage leveling segment and the second voltage leveling segment. The initial point of the voltage ramp change segment is after the effective potential signal of the first control signal and after the effective potential signal of the second control signal. The second control unit includes a data writing subunit, a time control subunit, and a coupling subunit. The data writing subunit is used to write a first data signal to the control terminal of the time control subunit according to the second control signal. The coupling subunit is used to couple the change of the ramp signal to the control terminal of the time control subunit in a positive correlation. The time control subunit is used to control the transmission of the second voltage to the control terminal of the first switching module according to the voltage of its own control terminal. The first switch module is used to turn on according to the first voltage at its own control terminal and to turn off according to the second voltage at its own control terminal; When the second control signal is a valid potential signal, the data writing subunit is turned on, transmitting the first data signal to the control terminal of the time control subunit. After the first data signal is written to the control terminal of the time control subunit, the time control subunit turns off according to the first data signal at its own control terminal. After the first data signal is written to the control terminal of the time control subunit, the voltage of the ramp signal changes. The coupling subunit couples the voltage change of the ramp signal to the control terminal of the time control subunit in a positive correlation, causing the potential of the control terminal of the time control subunit to change. When the voltage change of the ramp signal is coupled to the control terminal of the time control subunit in a positive correlation, enabling the time control subunit to turn on, the second voltage is transmitted to the control terminal of the first switching module through the time control subunit.

2. The pixel circuit according to claim 1, characterized in that, The light emission time control circuit further includes a first storage unit, which is used to store the voltage at the control terminal of the first switch module.

3. The pixel circuit according to claim 2, characterized in that, The first switching module includes a first transistor, the gate of the first transistor serves as the control terminal of the first switching module, the first electrode of the first transistor is electrically connected to the first power supply voltage input terminal, the second electrode of the first transistor is electrically connected to the first terminal of the driving module, the second terminal of the driving module is connected to the first terminal of the light-emitting module, the second terminal of the light-emitting module is electrically connected to the second power supply voltage input terminal, one end of the first storage unit is connected to the gate of the first transistor, and the other end of the first storage unit is connected to the first power supply voltage input terminal.

4. The pixel circuit according to claim 1, characterized in that, The first control unit includes a second transistor, the gate of the second transistor is connected to the first control signal, the first terminal of the second transistor is connected to the first voltage, and the second terminal of the second transistor is electrically connected to the control terminal of the first switching module.

5. The pixel circuit according to claim 1, characterized in that, The data writing subunit includes a third transistor, the timing control subunit includes a fourth transistor, the coupling subunit includes a first capacitor, the gate of the third transistor is connected to the second control signal, the first terminal of the third transistor is connected to the first data signal, and the second terminal of the third transistor is electrically connected to the gate of the fourth transistor. The first terminal of the first capacitor is connected to the ramp signal, and the second terminal of the first capacitor is electrically connected to the gate of the fourth transistor. The first terminal of the fourth transistor is connected to the second voltage, and the second terminal of the fourth transistor is electrically connected to the control terminal of the first switching module.

6. The pixel circuit according to claim 5, characterized in that, The absolute value of the difference between the first data signal and the second voltage is less than the absolute value of the threshold voltage of the fourth transistor.

7. The pixel circuit according to claim 3, characterized in that, The absolute value of the difference between the first voltage and the first power supply voltage input at the first power supply voltage input terminal is greater than or equal to the absolute value of the threshold voltage of the first transistor.

8. The pixel circuit according to claim 5, characterized in that, The first control signal and the second control signal are the same control signal.

9. The pixel circuit according to claim 3, characterized in that, The second control unit further includes a compensation subunit and a write control subunit. The compensation subunit is used to write information including the threshold voltage of the time control subunit to the control terminal of the time control subunit according to the second control signal. The write control subunit is used to turn off when the data write subunit is turned on and turn on after the data write subunit is turned off.

10. The pixel circuit according to claim 9, characterized in that, The data writing subunit includes a third transistor, the time control subunit includes a fourth transistor, the coupling subunit includes a first capacitor, and the compensation subunit includes a fifth transistor; The gate of the third transistor is connected to the second control signal, the first terminal of the third transistor is connected to the first data signal, and the second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor. The gate of the fifth transistor is connected to the second control signal, the first terminal of the fifth transistor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is electrically connected to the gate of the fourth transistor. The first terminal of the fourth transistor is connected to the second voltage through the write control subunit, and the second terminal of the fourth transistor is electrically connected to the control terminal of the first switch module. The first terminal of the first capacitor is connected to the ramp signal, and the second terminal of the first capacitor is electrically connected to the gate of the fourth transistor. The effective potential signal of the first control signal follows the effective potential signal of the second control signal.

11. The pixel circuit according to claim 10, characterized in that, The absolute value of the difference between the first data signal and the second voltage is less than the absolute value of the threshold voltage of the fourth transistor.

12. The pixel circuit according to claim 9, characterized in that, The absolute value of the difference between the first voltage and the first power supply voltage input at the first power supply voltage input terminal is greater than or equal to the absolute value of the threshold voltage of the first transistor.

13. The pixel circuit according to claim 9, characterized in that, The second control unit further includes an initialization subunit, which is used to transmit a first initialization voltage to the control terminal of the time control subunit before the data writing subunit writes the first data signal to the control terminal of the time control subunit.

14. The pixel circuit according to any one of claims 1-13, characterized in that, The second voltage control module includes a data writing unit and a second storage unit. The data writing unit is used to control the writing of a second data signal to the control terminal of the drive module according to a third control signal. The second storage unit is used to store the voltage of the control terminal of the drive module.

15. The pixel circuit according to claim 14, characterized in that, The control terminal of the data writing unit is connected to the third control signal, the first terminal of the data writing unit is connected to the second data signal, and the second terminal of the data writing unit is electrically connected to the control terminal of the drive module. Alternatively, the second voltage control module may further include a compensation unit, wherein the control terminal of the data writing unit is connected to the third control signal, the first terminal of the data writing unit is connected to the second data signal, and the second terminal of the data writing unit is electrically connected to the first terminal of the drive module; the control terminal of the compensation unit is connected to the third control signal, the first terminal of the compensation unit is electrically connected to the second terminal of the drive module, and the second terminal of the compensation unit is electrically connected to the control terminal of the drive module.

16. The pixel circuit according to claim 14, characterized in that, The second voltage control module further includes an initialization unit, which is used to transmit a second initialization voltage to the control terminal of the drive module according to a fourth control signal, wherein the effective potential signal of the fourth control signal precedes the effective potential signal of the third control signal.

17. The pixel circuit according to claim 14, characterized in that, It also includes a light-emitting control module, the control terminal of which is connected to a light-emitting control signal. The first switch module, the drive module, the light-emitting control module, and the light-emitting module are connected in series between the first power supply voltage input terminal and the second power supply voltage input terminal to form a drive branch. The light-emitting control module is used to turn on during the light-emitting stage so that the drive branch is turned on. Wherein, the effective potential signal of the light emission control signal is after the effective potential signal of the first control signal and after the effective potential signal of the second control signal, and the voltage ramp change segment of the ramp signal is located within the time period of the effective potential signal of the light emission control signal; The effective potential signal of the light emission control signal follows the effective potential signal of the third control signal.

18. The pixel circuit according to claim 17, characterized in that, The initial point of the voltage ramp change segment coincides with the transition point where the light emission control signal changes from an invalid potential signal to an effective potential signal.

19. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-18.

20. The display panel according to claim 19, characterized in that, It also includes light emission control signal lines and ramp signal lines. Each light emission control signal line is connected to at least one row of the pixel circuit, and each ramp signal line is connected to at least one row of the pixel circuit. The light emission control signal lines are interconnected, and the ramp signal lines are interconnected.

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