Discharge protection circuit, display device and discharge protection method

Abstract

The present disclosure relates to the field of display, and discloses a discharge protection circuit, a display device and a discharge protection method. The discharge protection circuit comprises: a first discharge protection circuit is configured to be coupled to a power supply terminal related to a pixel in a display panel, and is configured to connect the power supply terminal related to the pixel with a ground terminal in response to a first signal of a first selection control terminal when the display panel is turned off, so that the charge on the power supply terminal related to the pixel is discharged; a second discharge protection circuit is configured to be coupled to a high potential transmission line, and is configured to delay the falling time of the voltage on the high potential transmission line in response to a second signal of a second selection control terminal when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged. The above-mentioned scheme of setting the first discharge protection circuit or the second discharge protection circuit, or setting the first discharge protection circuit and the second discharge protection circuit in the circuit at the same time, effectively solves the problem of incomplete charge discharge during the shutdown process.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology and provides a discharge protection circuit, a display device and a discharge protection method. Background Art

[0002] The display device generally includes a plurality of pixel units. Each pixel unit may include: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. By controlling the brightness corresponding to each sub-pixel, the desired color is mixed to display a color image. During the rapid power-on and power-off of the display panel, the charge in the display panel may not be released cleanly due to the short power-off time. Summary of the invention

[0003] Embodiments of the present disclosure provide a discharge protection circuit, a display device, and a discharge protection method, which are used to accelerate the discharge of charges of a display panel during a shutdown process.

[0004] The specific technical solutions provided by this disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a discharge protection circuit, comprising:

[0006] A first discharge protection circuit and / or a second discharge protection circuit;

[0007] The first discharge protection circuit is configured to be coupled to a pixel-related power supply terminal in the display panel, and is configured to connect the pixel-related power supply terminal to the ground terminal in response to a first signal from the first selection control terminal when the display panel is turned off, so as to discharge the charge on the pixel-related power supply terminal, wherein the pixel-related power supply terminal includes a common electrode and an analog power supply;

[0008] The second discharge protection circuit is configured to be coupled to the high potential transmission line, and is configured to delay the falling time of the voltage on the high potential transmission line in response to the second signal of the second selection control terminal when the display panel is turned off, so as to discharge the charge on the pixel electrode in the display panel; the high potential transmission line is configured to transmit the voltage of the effective potential of the gate scanning signal.

[0009] Optionally, the first discharge protection circuit includes: a first transistor and a discharge resistor;

[0010] A control terminal of the first transistor is coupled to a first selection control terminal, a first terminal of the first transistor is coupled to a pixel-related power supply terminal, and a second terminal of the first transistor is coupled to a first terminal of a discharge resistor;

[0011] The second terminal of the discharge resistor is coupled to the ground terminal.

[0012] Optionally, the first discharge protection circuit further includes: a first diode;

[0013] An anode of the first diode is coupled to the common voltage power supply, and a cathode of the first diode is coupled to the first end of the first transistor.

[0014] Optionally, the first discharge protection circuit further includes: a first resistor and a second resistor;

[0015] A first end of the first resistor is coupled to the anode of the first diode, and a second end of the first resistor is coupled to the first end of the second resistor;

[0016] The second end of the second resistor is coupled to the control end of the first transistor.

[0017] Optionally, the second discharge protection circuit is further configured to charge according to the voltage on the high potential transmission line in response to a third signal of the second enable control terminal after the display panel is powered on.

[0018] Optionally, the second discharge protection circuit includes: a gating control subcircuit, an indirect control subcircuit and a charge charging and discharging subcircuit;

[0019] The gating control subcircuit is configured to be coupled to the second gating control terminal, and is further configured to, after the display panel is powered on, respond to a third signal of the second gating control terminal to control the indirect control subcircuit to be turned on, so that the energy storage capacitor in the charge charging and discharging subcircuit is charged according to the voltage on the high potential transmission line, and is configured to, when the display panel is powered off, respond to a second signal of the second gating control terminal to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to discharge to the high potential transmission line, so as to delay the falling time of the voltage on the high potential transmission line, so that the charge on the pixel electrode in the display panel is discharged;

[0020] The indirect control subcircuit is configured to be coupled to the gating control subcircuit, and is further configured to charge the energy storage capacitor in the charge charging and discharging subcircuit with the voltage on the high potential transmission line after being turned on; and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to discharge to the high potential transmission line when the display panel is turned off;

[0021] The charge charging and discharging subcircuit is configured to use the voltage on the high potential transmission line for charging; it is also configured to delay the falling time of the voltage on the high potential transmission line through the load capacitor and at least one energy storage capacitor when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged.

[0022] Optionally, the gating control subcircuit includes: a third resistor, a first capacitor, a third transistor and a fourth resistor;

[0023] A first end of the third resistor is coupled to the second gate control end, and a second end of the third resistor is coupled to the control end of the third transistor;

[0024] A first terminal of the first capacitor is coupled to the control terminal of the third transistor, a second terminal of the first capacitor is grounded, and a first terminal of the third transistor is grounded;

[0025] The second end of the third transistor is coupled to the first end of the fourth resistor, and the second end of the fourth resistor is coupled to the charge charging and discharging sub-circuit.

[0026] Optionally, the indirect control subcircuit includes: a fifth resistor, a second capacitor, a fourth transistor, a second diode and a sixth resistor;

[0027] A first end of the fifth resistor is coupled to a first end of the fourth resistor, a second end of the fifth resistor is coupled to a first end of the second capacitor, and a second end of the second capacitor is grounded;

[0028] The control end of the fourth transistor is coupled to the first end of the second capacitor, the first end of the fourth transistor is coupled to the high potential transmission line, and the second end of the fourth transistor is coupled to the anode of the second diode;

[0029] The cathode of the second diode is coupled to the first end of the sixth resistor, and the second end of the sixth resistor is coupled to the charge charging and discharging sub-circuit.

[0030] Optionally, the charge charging and discharging sub-circuit includes: a fifth transistor, a seventh resistor, a third capacitor and a fourth capacitor;

[0031] The control terminal of the fifth transistor is coupled to the first terminal of the seventh resistor, the first terminal of the fifth transistor is coupled to the first terminal of the third capacitor, and the second terminal of the fifth transistor is coupled to the high potential transmission line;

[0032] The second end of the third capacitor is grounded, and the second end of the seventh resistor is coupled to the second end of the fourth resistor;

[0033] A first terminal of the fourth capacitor is coupled to the high potential transmission line, and a second terminal of the fourth capacitor is grounded.

[0034] Optionally, after the display panel is turned on, the second selection control terminal controls the third transistor and the fourth transistor to be turned on, and the high potential transmission line charges the third capacitor;

[0035] When the display panel is turned off, the potential of the high potential transmission line drops, the fifth transistor is turned on, and the charge in the high potential transmission line is discharged simultaneously through the third capacitor and the fourth capacitor.

[0036] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: a display panel and the above-mentioned discharge protection circuit;

[0037] The discharge protection circuit is coupled to the pixel-related power supply terminal in the display panel.

[0038] Optionally, it also includes: a timing controller and a power management circuit;

[0039] The power management circuit is configured to output a first signal to the first gate control terminal when detecting that the display panel is turned off;

[0040] The timing controller is configured to output a first signal to the first enable control terminal and a second signal to the second enable control terminal when detecting that the display panel is turned off; and output a third signal to the second enable control terminal after detecting that the display panel is turned on.

[0041] Optionally, when it is monitored that the running time of the clock control signal input to the display panel reaches a preset time, it is determined that the display panel is powered on completely.

[0042] In a third aspect, the present disclosure also provides a discharge protection method, including:

[0043] When the display panel is turned off, in response to a first signal from the first selection control terminal, the pixel-related power supply terminal is connected to the ground terminal to discharge the charge on the pixel-related power supply terminal;

[0044] and / or

[0045] When the display panel is turned off, in response to the second signal of the second gate control terminal, the falling time of the voltage on the high potential transmission line is delayed, so that the charge on the pixel electrode in the display panel is discharged.

[0046] The beneficial effects of the present disclosure are as follows:

[0047] In summary, in an embodiment of the present disclosure, a discharge protection circuit, a display device and a discharge protection method are provided. The discharge protection circuit includes: a first discharge protection circuit and / or a second discharge protection circuit. The first discharge protection circuit is configured to be coupled to a power supply terminal associated with a pixel in a display panel, and is configured to connect the power supply terminal associated with the pixel to the ground terminal in response to a first signal of a first selection control terminal when the display panel is turned off, so that the charge on the power supply terminal associated with the pixel is discharged. The second discharge protection circuit is configured to be coupled to a high potential transmission line, and is configured to delay the falling time of the voltage on the high potential transmission line in response to a second signal of a second selection control terminal when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged. The high potential transmission line is configured to transmit the voltage of the effective potential of the gate scanning signal. By setting the first discharge protection circuit or the second discharge protection circuit, or setting the first discharge protection circuit and the second discharge protection circuit in the circuit at the same time, the problem of incomplete charge discharge during the shutdown process is effectively solved.

[0048] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by practicing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0050] Figure 1 is a schematic diagram of the connection between the first discharge protection circuit and the common electrode in the embodiment of the present disclosure;

[0051] Figure 2 is a circuit connection diagram of a first type of first discharge protection circuit in an embodiment of the present disclosure;

[0052] Figure 3 is a circuit connection diagram of a second first discharge protection circuit in an embodiment of the present disclosure;

[0053] Figure 4 is a circuit connection diagram of a third first discharge protection circuit in an embodiment of the present disclosure;

[0054] Figure 5 is a circuit connection diagram of a fourth first discharge protection circuit in an embodiment of the present disclosure;

[0055] Figure 6 is a schematic diagram of the connection between the second discharge protection circuit and the display panel in an embodiment of the present disclosure;

[0056] Figure 7 is a circuit connection diagram of the first type of second discharge protection circuit in the embodiment of the present disclosure;

[0057] Figure 8 is a circuit connection diagram of a second type of second discharge protection circuit in an embodiment of the present disclosure;

[0058] Fig. 9 is a circuit connection diagram of a third second discharge protection circuit in an embodiment of the present disclosure;

[0059] Fig.10 is a first simulation waveform diagram of the second discharge protection circuit in the embodiment of the present disclosure;

[0060] Fig.11 is a second simulation waveform diagram of the second discharge protection circuit in the embodiment of the present disclosure;

[0061] Fig.12Schematic diagram of the connection between the first discharge protection circuit, the second discharge protection circuit and the pixel circuit in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the technical solution of the present disclosure, rather than all the embodiments. Based on the embodiments recorded in the present disclosure document, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present disclosure.

[0063] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented using sequences other than those illustrated or described herein.

[0064] In some embodiments of the present disclosure, the display device may include a display panel. The display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of multiple different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited here. The following is an example in which a pixel unit includes a red sub-pixel, a green sub-pixel and a blue sub-pixel.

[0065] In some embodiments of the present disclosure, the display panel may further include a plurality of gate lines and a plurality of data lines. A sub-pixel row may correspond to at least one gate line, the gate of the transistor may be coupled to the corresponding gate line, the source of the transistor may be coupled to the corresponding data line, and the drain of the transistor may be coupled to the pixel electrode. Exemplarily, a gate scan signal is loaded to each gate line respectively, and under the control of the effective potential of the gate scan signal, the transistor in the sub-pixel may be controlled to be turned on. Also, the data line inputs a data voltage, so that the voltage on the data line is input into the sub-pixel through the turned-on transistor to charge the sub-pixel, thereby charging each sub-pixel with the corresponding data voltage to realize the screen display function.

[0066] The display panel in the embodiment of the present disclosure may be a liquid crystal display panel. Exemplarily, the liquid crystal display panel generally includes an upper substrate and a lower substrate of a pair of boxes, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying a picture, due to the voltage difference between the data voltage loaded on the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode, the voltage difference can form an electric field, so that the liquid crystal molecules are deflected under the action of the electric field. Due to different intensities of electric fields, the deflection degree of the liquid crystal molecules is different, resulting in different transmittances of the sub-pixels, so that the sub-pixels can achieve different grayscale brightness, thereby realizing picture display.

[0067] Since the shutdown time is short, the above display panel often has the problem of unclean charge release. To address the above problem, the following method 1 or method 2 is often used in the related art to speed up the charge discharge during the shutdown process:

[0068] Method 1: When the display panel is turned off, the common electrode is discharged through an external discharge resistor. The disadvantage of this method is that the discharge resistor will inevitably generate power consumption when the display panel is turned on and during normal display, which increases heat loss and reduces the output efficiency of the power management circuit PMIC.

[0069] Method 2: During the shutdown process of the display panel, a storage capacitor is added to the high-potential transmission line to extend the voltage drop time of the effective potential on the gate line and extend the shutdown time of the transistor in the sub-pixel. However, the addition of the storage capacitor will affect the startup timing of the display panel, and in severe cases, it may even cause the display panel to fail to display.

[0070] Based on this, the present disclosure provides a discharge protection circuit, that is, the discharge speed of the charge of the display panel during the shutdown process is accelerated by the discharge protection circuit.

[0071] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0072] In the disclosed embodiment, the discharge protection circuit specifically includes: a first discharge protection circuit and / or a second discharge protection circuit.

[0073] In order to speed up the discharge of charge in the display panel during the shutdown process, the embodiments of the present application provide three solutions: Solution 1 is to set a first discharge protection circuit for the display panel, Solution 2 is to set a second discharge protection circuit for the display panel, and Solution 3 is to set the first discharge protection circuit and the second discharge protection circuit in the display panel at the same time.

[0074] During the implementation of Scheme 1, when the first discharge protection circuit is set, the charge on the pixel-related power supply terminal can be discharged when the display panel is turned off. The pixel-related power supply terminal includes a common electrode and an analog power supply, and the common electrode is configured to transmit a common electrode voltage.

[0075] Exemplarily, when the pixel-related power supply terminal is a common electrode, Figure 1 As shown, the first discharge protection circuit 20 is configured to be coupled to the common electrode VCOM 10 in the display panel, and is configured to connect the common electrode VCOM to the ground terminal in response to the first signal of the first selection control terminal CS1 when the display panel is turned off, so that the charge on the common electrode VCOM is discharged.

[0076] The first discharge protection circuit 20 is described below with reference to the circuit diagram.

[0077] See also Figure 2 As shown, the first discharge protection circuit 20 includes: a first transistor Q1 and a discharge resistor R.

[0078] The control terminal of the first transistor Q1 is coupled to the first selection control terminal CS1, the first terminal of the first transistor Q1 is coupled to the common electrode VCOM, the second terminal of the first transistor Q1 is coupled to the first terminal of the discharge resistor R, and the second terminal of the discharge resistor R is coupled to the ground terminal.

[0079] See also Figure 3 As shown, a common electrode voltage can also be input to the common electrode VCOM through a common voltage power supply VCOMIN. When the common electrode VCOM is controlled to discharge charges, in order to prevent the charges from flowing back during the discharge process, the first discharge protection circuit 20 further includes: a first diode D1. Exemplarily, the anode of the first diode D1 is coupled to the common voltage power supply VCOMIN, and the cathode of the first diode D1 is coupled to the common electrode VCOM.

[0080] In addition, for current limiting, see Figure 3 As shown, the first discharge protection circuit 20 further includes: a first resistor R1 and a second resistor R2.

[0081] Exemplarily, a first end of the first resistor R1 is coupled to the common voltage power source VCOMIN, a second end of the first resistor R1 is coupled to a first end of the second resistor R2, and a second end of the second resistor R2 is coupled to the control end of the first transistor Q1.

[0082] Exemplarily, when the pixel-related power supply terminal is an analog power supply, the first discharge protection circuit 20 is configured to be coupled to the analog power supply AVDD in the display panel 10. The above-mentioned analog power supply AVDD is used to provide voltage for the data line Data. The process of discharging the analog power supply AVDD through the first discharge protection circuit is similar to the above description and will not be repeated here.

[0083] Power management circuits are usually used to power related devices in display panels. Figure 4As shown, the display device further includes a power management circuit PMIC, which is coupled to a power supply signal VIN of the display panel. During implementation, when the display panel is turned off, the power supply signal VIN of the display panel is powered off. After the power management circuit PMIC detects that VIN is in a power-off state, it generates a first signal and provides the first signal to the first selection control terminal CS1. Since the first selection control terminal CS1 is coupled to the control terminal of the first transistor Q1, the first signal turns on the first transistor Q1, so that the discharge resistor R is connected to the second end of the first transistor Q1.

[0084] Exemplarily, when the display panel is in the power-on and displaying state, the power supply signal VIN of the display panel is in the power-on state, and the power management circuit PMIC turns off the first transistor Q1 after detecting that VIN is in the power-on state, that is, assuming that the common electrode VCOM is 7V, the B-pole voltage provided by the power management circuit PMIC to the first transistor Q1 is 7V, the E-pole voltage is 6.7V, and the conduction voltage drop of the first diode D1 is 0.3V, so the first transistor is turned off. Then the common electrode VCOM and the bleeder resistor R are in an open circuit state, so that when the display panel is in the power-on and displaying state, the power consumption generated by the bleeder resistor R is effectively avoided, the heat loss of the bleeder resistor R is reduced, and the output efficiency of the power management circuit PMIC is guaranteed.

[0085] During the implementation process, when the display panel is in the power-on and displaying state, the above-mentioned first diode D1 is turned on, and the charge on the common voltage power supply VCOMIN flows to the common electrode VCOM through the first diode D1, so that the common electrode VCOM is loaded with the common voltage; when the display panel is in the power-off state, due to the setting of the above-mentioned first diode D1, the charge in the common electrode VCOM cannot flow back to the common voltage power supply VCOMIN, thereby effectively avoiding current backflow.

[0086] It should be noted that the type of transistor in the first discharge protection circuit 20 can be a P-type transistor. In the embodiment of the present application, a P-type transistor is used for specific description. The P-type transistor is cut off under the action of a high potential signal and is turned on under the action of a low potential signal.

[0087] In other embodiments, the transistor may be an N-type transistor, which is turned on by a high potential signal and turned off by a low potential signal. When an N-type transistor is used to implement discharge protection, the process is similar and will not be described in detail here.

[0088] See also Figure 3 and Figure 4 As shown, in some embodiments, the first transistor may be a triode.

[0089] See also Figure 5 As shown, in some other embodiments, the first transistor in the first discharge protection circuit 20 may also be a MOS transistor, that is, Figure 5 The second transistor Q2 is a MOS tube.

[0090] In the implementation of the second solution, when the second discharge protection circuit is provided, the falling time of the voltage on the high potential transmission line can be delayed when the display panel is turned off, so that the charge on the pixel electrode in the display panel can be discharged.

[0091] For example, Figure 6 As shown, the second discharge protection circuit 30 is configured to be coupled to the high potential transmission line VGHL, and is configured to delay the falling time of the voltage on the high potential transmission line VGHL in response to the second signal of the second gate control terminal CS2 when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged. The above-mentioned high potential transmission line VGHL is configured to transmit the voltage of the effective potential of the gate scanning signal.

[0092] Exemplarily, the effective potential of the gate scan signal may be a high potential, and the corresponding voltage may be a positive voltage.

[0093] In summary, the first discharge protection circuit performs discharge protection on the common electrode VCOM or the analog power supply AVDD, while the second discharge protection circuit 30 in the embodiment of the present application discharges the charge on the high-potential transmission line through the load capacitor and the energy storage capacitor without affecting the power-on timing of the display panel. The second discharge protection circuit 30 is introduced below in conjunction with the circuit diagram.

[0094] See also Figure 7 As shown, the second discharge protection circuit 30 includes: a gating control subcircuit 301 , an indirect control subcircuit 302 and a charge charging and discharging subcircuit 303 .

[0095] The selection control subcircuit 301 is configured to be coupled to the second selection control terminal CS2, and is also configured to control the indirect control subcircuit 302 to be turned on in response to the third signal of the second selection control terminal CS2 after the display panel is turned on, so that the energy storage capacitor in the charge charging and discharging subcircuit 303 can be charged according to the voltage on the high potential transmission line VGHL, and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit 303 to discharge to the high potential transmission line VGHL in response to the second signal of the second selection control terminal CS2 when the display panel is turned off, so as to delay the falling time of the voltage on the high potential transmission line VGHL, so as to discharge the charge on the pixel electrode in the display panel.

[0096] Depend on Figure 7It can be known that the gating control subcircuit 301 includes: a third resistor R3, a first capacitor C1, a third transistor Q3 and a fourth resistor R4.

[0097] The connection relationship between the components in the gating control subcircuit 301 is as follows: the first end of the third resistor R3 is coupled to the second gating control terminal CS2, and the second end of the third resistor R3 is coupled to the control terminal of the third transistor Q3. The first end of the first capacitor C1 is coupled to the control terminal of the third transistor Q3, the second end of the first capacitor C1 is grounded, and the first end of the third transistor Q3 is grounded. The second end of the third transistor Q3 is coupled to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is coupled to the charge charging and discharging subcircuit 303.

[0098] It should be additionally explained that the third resistor R3, the first capacitor C1 and the fourth resistor R4 play the role of current limiting and filtering.

[0099] During the power-on process of the display panel, the second selection control terminal CS2 controls the third transistor Q3 to be cut off, and the high-potential transmission line VGHL will first charge the connected fourth capacitor C4, that is, the third capacitor C3 used for energy storage will not be charged during this process, so it will not affect the power-on process of the pixel unit.

[0100] The indirect control subcircuit 302 is configured to be coupled to the gate control subcircuit 301, and is also configured to charge the charge charging and discharging subcircuit 303 with the voltage on the high potential transmission line VGHL after being turned on. And it is also configured to control the charge charging and discharging subcircuit 303 to discharge to the ground end of the high potential transmission line VGHL when the display panel is turned off.

[0101] Depend on Figure 7 It can be known that the indirect control sub-circuit 302 includes: a fifth resistor R5, a second capacitor C2, a fourth transistor Q4, a second diode D2 and a sixth resistor R6.

[0102] The connection relationship between the components in the above-mentioned indirect control subcircuit 302 is as follows: the first end of the fifth resistor R5 is coupled to the first end of the fourth resistor R4, the second end of the fifth resistor R5 is coupled to the first end of the second capacitor C2, and the second end of the second capacitor C2 is grounded. The control end of the fourth transistor Q4 is coupled to the first end of the second capacitor C2, the first end of the fourth transistor Q4 is coupled to the high potential transmission line VGHL, and the second end of the fourth transistor Q4 is coupled to the positive electrode of the second diode D2. The negative electrode of the second diode D2 is coupled to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is coupled to the charge charging and discharging subcircuit.

[0103] During the power-on process of the display panel, after the third transistor Q3 is turned off under the control of the second enable control terminal CS2, the corresponding control-connected fourth transistor Q4 is also turned off, and the second diode D2 is also not turned on. This is equivalent to the enable control subcircuit 301 and the indirect control subcircuit 302 being in an open circuit state during the power-on process, and thus will not affect the power-on timing of the display panel.

[0104] After the display panel is turned on, the third transistor Q3 is turned on under the control of the third signal of the second selection control terminal CS2, thereby controlling the connected fourth transistor Q4 to be turned on, and the second diode D2 is also turned on, and the third capacitor C3 used for energy storage is charged, so that during the shutdown discharge process, the falling time of the voltage on the high potential transmission line VGHL is extended through the above-mentioned third capacitor C3 and fourth capacitor C4.

[0105] Exemplarily, the charge charging and discharging subcircuit 303 is configured to use the voltage on the high potential transmission line VGHL for charging; it is also configured to delay the falling time of the voltage on the high potential transmission line VGHL through a load capacitor and at least one energy storage capacitor when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged.

[0106] Depend on Figure 7 It can be known that the charge charging and discharging sub-circuit 303 includes: a fifth transistor Q5, a seventh resistor R7, a third capacitor C3 and a fourth capacitor C4. The control end of the fifth transistor Q5 is coupled to the first end of the seventh resistor R7, the first end of the fifth transistor Q5 is coupled to the first end of the third capacitor C3, and the second end of the fifth transistor Q5 is coupled to the high potential transmission line VGHL. The second end of the third capacitor C3 is grounded, and the second end of the seventh resistor R7 is coupled to the second end of the fourth resistor R4. The first end of the fourth capacitor C4 is coupled to the high potential transmission line VGHL, and the second end of the fourth capacitor C4 is grounded. Obviously, the third capacitor C3 is a storage capacitor, and the fourth capacitor C4 is a load capacitor.

[0107] Exemplarily, after the display panel is powered on, the second enable control terminal controls the third transistor and the fourth transistor to be turned on, and the high-potential transmission line charges the third capacitor; during the shutdown process of the display panel, the potential of the high-potential transmission line drops, the fifth transistor is turned on, and the charge in the high-potential transmission line is discharged through the third capacitor and the fourth capacitor at the same time. The following is a detailed description of the process from powering on the display panel, powering on completion to shutdown.

[0108] During the display panel startup process, since the second selection control terminal CS2 controls the third transistor Q3 and the fourth transistor Q4 to be turned off, the fourth capacitor C4 coupled to the high potential transmission line VGHL is charged under the control of the third signal of the second selection control terminal CS2.

[0109] After the display panel is powered on, the second selection control terminal CS2 controls the third transistor Q3 and the fourth transistor Q4 to be turned on, so that the high potential transmission line VGHL charges the third capacitor C3 for energy storage. Since the charging of the third capacitor C3 is performed after the display panel is powered on, the charging process will not affect the power-on timing of the display panel.

[0110] When the display panel is turned off, the potential of the high potential transmission line VGHL drops, the fifth transistor Q5 is turned on, and the charge in the high potential transmission line VGHL is discharged simultaneously through the third capacitor C3 and the fourth capacitor C4, thereby effectively extending the falling time of the voltage on the high potential transmission line VGHL. In this way, the pixel unit in the display panel can have more discharge time to discharge the charge when it is turned off.

[0111] In addition, see Figure 8 As shown, the display device further includes a timing controller TCON, which is coupled to the second discharge protection circuit 30. During implementation, when the display panel is turned off, the high potential transmission line VGHL is powered off, and the timing controller TCON generates a second signal after detecting that VGH is in a power-off state, and provides the second signal to the second gate control terminal CS2. Since the second gate control terminal CS2 is coupled to the control terminal of the third transistor Q3, the second signal of the second gate control terminal CS2 turns on the third transistor Q3.

[0112] Furthermore, when the display panel is turned on, the timing controller TCON generates a third signal after detecting a stable clock control signal CLK, and provides the third signal to the second gate control terminal CS2. Since the second gate control terminal CS2 is coupled to the control terminal of the third transistor Q3, the third signal of the second gate control terminal CS2 turns off the third transistor Q3.

[0113] To accelerate the discharge of charge, see Fig. 9 As shown, the second discharge protection circuit 30 in the embodiment of the present application may also include a plurality of third capacitors C3, and the plurality of third capacitors C3 are connected in parallel. Fig. 9 As shown in the capacitors C3-1, C3-2, C3-3 and C3-4, after the display panel is turned on, the high potential transmission line VGHL is charged through the above-mentioned capacitors C3-1, C3-2, C3-3 and C3-4. In this way, when the display panel is turned off, it can be discharged synchronously with the fourth capacitor C4 through the capacitors C3-1, C3-2, C3-3, C3-4 to delay the falling time of the voltage on the high potential transmission line VGHL, so that the charge on the pixel electrode in the display panel can be discharged. Fig. 9 The working process of each component in Figure 7 Similar, I will not go into details here.

[0114] When simulating the second discharge protection circuit 30, the following results are obtained: Fig.10 and Fig.11 As shown in the simulation waveform diagram. For example, when the power is turned on, Fig.10 As shown, the high potential transmission line VGHL first charges the fourth capacitor C4 to maintain the original power-on timing. After the clock control signal CLK output is stable, the timing controller TCON controls the base control signal of the third transistor Q3 to be pulled high, Q3 is turned on, and the gate voltage of the fourth transistor Q4 is pulled low to be turned on. The high potential transmission line VGHL can charge the third capacitor C3. At this time, the voltage of the high potential transmission line VGHL is stable and not affected. In this way, the load capacitor and the energy storage capacitor can be charged in batches without affecting the power-on timing.

[0115] When shutting down, Fig.11 As shown, as the voltage of the high-potential transmission line VGHL drops, UEB of the third transistor Q3 is greater than 0.7V, the third transistor Q3 is turned on, and the third capacitor C3 and the fourth capacitor C4 discharge the high-potential transmission line VGHL. It can be found that the addition of the third capacitor C3 can extend the power-off time of the high-potential transmission line VGHL, and the entire time period of the clock control signal CLK power-off is extended by 200ms to 600ms. When the system is shut down, the opening time of the gate in the screen is extended, so that the charge discharge time in the screen is also extended, which can effectively improve the problem of residual charge in the shutdown screen, and avoid the phenomenon of residual charge in the screen causing shutdown afterimage or picture flickering when the power is turned on again.

[0116] In the implementation process of the third scheme, when the first discharge protection circuit 20 and the second discharge protection circuit 30 are simultaneously provided for the display panel, the charge discharge to the ground can be realized through the resistor, and the charge discharge time can be effectively prolonged by providing multiple capacitors. In the specific implementation process, the first discharge protection circuit 20 and the second discharge protection circuit 30 work simultaneously. The working processes of the first discharge protection circuit 20 and the second discharge protection circuit 30 are the same as above, and will not be described one by one here.

[0117] Based on the same inventive concept, a discharge protection method is provided in an embodiment of the present disclosure, comprising:

[0118] When the display panel is turned off, in response to the first signal of the first selection control terminal, the pixel-related power supply terminal is connected to the ground terminal to discharge the charge on the pixel-related power supply terminal. And / or

[0119] During the implementation process, when the display panel is turned off and the charge on the pixel-related power supply terminal needs to be discharged, the first signal sent by the first selection control terminal CS1 turns on the transistor, thereby connecting the pixel-related power supply terminal to the discharge resistor, and the discharge resistor is connected to the ground terminal, so that the charge on the pixel-related power supply terminal can be quickly discharged to the ground.

[0120] Because, during the process of powering on and displaying the display panel, the power management circuit PMIC does not generate the first signal after detecting that VIN is in the power-on state, the first enable control terminal does not receive the first signal, the corresponding transistor is cut off, and the discharge resistor is in an open-circuit state, that is, the discharge resistor is not connected to the circuit, and the charge on the pixel-related power supply terminal is only supplied to the pixel unit, thereby avoiding the consumption of charge by the discharge resistor.

[0121] When the display panel is turned off, in response to the second signal of the second gate control terminal, the falling time of the voltage on the high potential transmission line is delayed, so that the charge on the pixel electrode in the display panel is discharged.

[0122] During the implementation process, when the display panel is turned off, the timing controller controls the charge charging and discharging sub-circuit to discharge to the high potential transmission line after providing the second signal to the second selection control terminal, that is, the charge is discharged through the third capacitor and the fourth capacitor at the same time, thereby effectively extending the falling time of the voltage on the high potential transmission line, so that the charge on the pixel electrode in the display panel is discharged more thoroughly.

[0123] Based on the same inventive concept, refer to Fig.12 As shown, a display device is provided in an embodiment of the present disclosure, including: a display panel 12 and the above-mentioned discharge protection circuit.

[0124] It should be noted that the first discharge protection circuit 20 is coupled to the pixel-related power supply terminal (common electrode VCOM or analog power supply AVDD), and the second discharge protection circuit 30 is coupled to the high potential transmission line VGHL, and the high potential transmission line VGHL is configured to transmit the voltage of the effective potential of the gate scanning signal Gate. The first discharge protection circuit 20 and the second discharge protection circuit 30 can be set in the circuit either one or both.

[0125] See also Fig.10 As shown, the connection relationship within a sub-pixel unit is used as an example to illustrate that one electrode plate of the capacitor CLC is a pixel electrode, the other electrode plate of the capacitor CLC is a common electrode, TFT represents a transistor connecting the pixel electrode and the data line, Gate represents a gate line, Data represents a data line, and VCOM represents a common electrode.

[0126] In addition, in order to effectively control the first discharge protection circuit 20 and / or the second discharge protection circuit 30 to work, the display device further includes: a timing controller TCON and a power management circuit PMIC.

[0127] The power management circuit PMIC is configured to output a first signal to the first enable control terminal when detecting that the display panel is turned off.

[0128] The timing controller TCON is configured to output a second signal to the second strobe control terminal when detecting that the display panel is turned off, and to output a third signal to the second strobe control terminal when detecting that the display panel is turned on.

[0129] Exemplarily, the power supply signal VIN of the display panel is connected to the power management circuit PMIC. When it is detected that the display panel is turned off, that is, the power management circuit PMIC detects that VIN is in a power-off state, it generates a first signal and provides the first signal to the first enable control terminal. After responding to the first signal, the first discharge protection circuit 20 quickly discharges the charge through the discharge resistor.

[0130] The timing controller TCON generates a second signal when detecting that the display panel is turned off, and also provides the second signal to the second selection control terminal through the I / O port. The second discharge protection circuit 30 performs corresponding work in response to the second signal.

[0131] Furthermore, the power management circuit PMIC generates a high potential VGH and outputs it to the timing conversion unit Level shift through the high potential transmission line VGHL, and the timing conversion unit Level shift forms the voltage of the effective potential of the gate driving signal.

[0132] In addition, the timing controller TCON generates a third signal after monitoring that the display panel is powered on, and provides the third signal to the second enable control terminal through the I / O port, so that the third capacitor in the second discharge protection circuit 30 continues to store energy and charge after the display panel is powered on.

[0133] It should also be noted that when it is monitored that the running time of the clock control signal input to the display panel reaches a preset time, that is, after it is monitored that the clock control signal CLK input to the display panel is stable, it is determined that the display panel is powered on. Optionally, the above preset time is 800ms.

[0134] It should be noted that the display device provided in the embodiment of the present disclosure is preferably a vehicle-mounted display device, an oversized product, a new smart display product, etc., which has strict requirements on the on / off response time, and can also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be elaborated here, nor should they be used as a limitation to the present disclosure.

[0135] In summary, the discharge protection circuit, display device and discharge protection method provided in the embodiments of the present disclosure include: a first discharge protection circuit and / or a second discharge protection circuit, the first discharge protection circuit is configured to be coupled to a common electrode in a display panel, and is configured to, when the display panel is turned off, in response to a first signal of a first selection control terminal, connect the common electrode to a ground terminal, so that the charge on the common electrode is discharged, and the common electrode is configured to transmit a common electrode voltage, the second discharge protection circuit is configured to be coupled to a high potential transmission line, and is configured to, when the display panel is turned off, in response to a second signal of a second selection control terminal, delay the falling time of the voltage on the high potential transmission line, so that the charge on the pixel electrode in the display panel is discharged, and the high potential transmission line is configured to transmit the voltage of the effective potential of a gate scanning signal, and by setting the first discharge protection circuit or the second discharge protection circuit, or by setting the first discharge protection circuit and the second discharge protection circuit in the circuit at the same time, the problem of incomplete charge discharge during the shutdown process is effectively solved.

[0136] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0137] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0140] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A discharge protection circuit, characterized in that: include: A first discharge protection circuit and / or a second discharge protection circuit; The first discharge protection circuit is configured to be coupled to a pixel-related power supply terminal in the display panel, and is configured to connect the pixel-related power supply terminal to the ground terminal in response to a first signal of a first selection control terminal when the display panel is turned off, so that the charge on the pixel-related power supply terminal is discharged, and the pixel-related power supply terminal includes a common electrode or an analog power supply. The first discharge protection circuit includes: a first transistor, a discharge resistor, a first diode, a first resistor, and a second resistor; The first end of the first transistor is coupled to the pixel-related power supply terminal, the second end of the first transistor is coupled to the first end of the discharge resistor, the second end of the discharge resistor is coupled to the ground terminal, the anode of the first diode is coupled to a common voltage power supply, and the cathode of the first diode is coupled to the common electrode; the first end of the first resistor is coupled to the anode of the first diode, the second end of the first resistor is coupled to the first end of the second resistor, and the second end of the second resistor is coupled to the control terminal of the first transistor; The second discharge protection circuit is configured to be coupled to the high potential transmission line, and is configured to delay the falling time of the voltage on the high potential transmission line in response to the second signal of the second gate control terminal when the display panel is turned off, so as to discharge the charge on the pixel electrode in the display panel; the high potential transmission line is configured to transmit the voltage of the effective potential of the gate scanning signal; The second discharge protection circuit is further configured to charge according to the voltage on the high potential transmission line in response to a third signal at the second strobe control terminal after the display panel is powered on, wherein the second discharge protection circuit comprises: a strobe control subcircuit, an indirect control subcircuit and a charge charging and discharging subcircuit; the strobe control subcircuit is configured to be coupled to the second strobe control terminal, and is further configured to control the indirect control subcircuit to be turned on in response to the third signal at the second strobe control terminal after the display panel is powered on, so that the energy storage capacitor in the charge charging and discharging subcircuit is charged according to the voltage on the high potential transmission line, and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to charge the high potential transmission line in response to the second signal at the second strobe control terminal when the display panel is powered off. The transmission line is discharged to delay the falling time of the voltage on the high potential transmission line, so that the charge on the pixel electrode in the display panel is discharged; the indirect control subcircuit is configured to be coupled with the selection control subcircuit, and is also configured to charge the energy storage capacitor in the charge charging and discharging subcircuit with the voltage on the high potential transmission line after being turned on; and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to discharge to the high potential transmission line when the display panel is turned off; the charge charging and discharging subcircuit is configured to charge using the voltage on the high potential transmission line; and is also configured to delay the falling time of the voltage on the high potential transmission line through the load capacitor and at least one energy storage capacitor when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged.

2. The discharge protection circuit according to claim 1, characterized in that: The gating control subcircuit comprises: a third resistor, a first capacitor, a third transistor and a fourth resistor; A first end of the third resistor is coupled to the second gate control end, and a second end of the third resistor is coupled to the control end of the third transistor; The first terminal of the first capacitor is coupled to the control terminal of the third transistor, the second terminal of the first capacitor is grounded, and the first terminal of the third transistor is grounded; The second end of the third transistor is coupled to the first end of the fourth resistor, and the second end of the fourth resistor is coupled to the charge charging and discharging sub-circuit.

3. The discharge protection circuit according to claim 1, characterized in that: The indirect control subcircuit comprises: a fifth resistor, a second capacitor, a fourth transistor, a second diode and a sixth resistor; The first end of the fifth resistor is coupled to the first end of the fourth resistor, the second end of the fifth resistor is coupled to the first end of the second capacitor, and the second end of the second capacitor is grounded; The control end of the fourth transistor is coupled to the first end of the second capacitor, the first end of the fourth transistor is coupled to the high potential transmission line, and the second end of the fourth transistor is coupled to the anode of the second diode; The cathode of the second diode is coupled to the first end of the sixth resistor, and the second end of the sixth resistor is coupled to the charge charging and discharging sub-circuit.

4. The discharge protection circuit according to claim 1, characterized in that: The charge charging and discharging subcircuit comprises: a fifth transistor, a seventh resistor, a third capacitor and a fourth capacitor; The control end of the fifth transistor is coupled to the first end of the seventh resistor, the first end of the fifth transistor is coupled to the first end of the third capacitor, and the second end of the fifth transistor is coupled to the high potential transmission line; The second end of the third capacitor is grounded, and the second end of the seventh resistor is coupled to the second end of the fourth resistor; A first end of the fourth capacitor is coupled to the high potential transmission line, and a second end of the fourth capacitor is grounded.

5. The discharge protection circuit according to claim 4, characterized in that: After the display panel is turned on, the second selection control terminal controls the third transistor and the fourth transistor to be turned on, and the high potential transmission line charges the third capacitor; When the display panel is turned off, the potential of the high potential transmission line drops, the fifth transistor is turned on, and the charge in the high potential transmission line is discharged simultaneously through the third capacitor and the fourth capacitor.

6. A display device, characterized in that: include: A display panel and a discharge protection circuit as claimed in any one of claims 1 to 5; The discharge protection circuit is coupled to the display panel.

7. The display device according to claim 6, wherein: Also includes: Timing controller and power management circuit; The power management circuit is configured to output a first signal to the first gate control terminal when detecting that the display panel is turned off; The timing controller is configured to output a second signal to the second strobe control terminal when detecting that the display panel is turned off; and output a third signal to the second strobe control terminal after detecting that the display panel is turned on.

8. The display device according to claim 6, wherein: When it is monitored that the running time of the clock control signal input to the display panel reaches a preset time, it is determined that the display panel is powered on completely.

9. A discharge protection method for a discharge protection circuit as claimed in any one of claims 1 to 5, characterized in that: include: When the display panel is turned off, the first discharge protection circuit, in response to the first signal of the first selection control terminal, conducts the pixel-related power supply terminal with the ground terminal, so that the charge on the pixel-related power supply terminal is discharged, and the first discharge protection circuit includes: a first transistor, a discharge resistor, a first diode, a first resistor, and a second resistor, wherein the first end of the first transistor is coupled to the pixel-related power supply terminal, the second end of the first transistor is coupled to the first end of the discharge resistor, the second end of the discharge resistor is coupled to the ground terminal, the anode of the first diode is coupled to the common voltage power supply, and the cathode of the first diode is coupled to the common electrode; the first end of the first resistor is coupled to the anode of the first diode, the second end of the first resistor is coupled to the first end of the second resistor, and the second end of the second resistor is coupled to the control terminal of the first transistor; and / or When the display panel is turned off, the second discharge protection circuit responds to the second signal of the second gate control terminal, delays the falling time of the voltage on the high potential transmission line, and discharges the charge on the pixel electrode in the display panel; After the display panel is powered on, the second discharge protection circuit responds to the third signal of the second gate control terminal and charges according to the voltage on the high potential transmission line, wherein the second discharge protection circuit includes: a gate control subcircuit, an indirect control subcircuit and a charge charging and discharging subcircuit; the gate control subcircuit is configured to be coupled to the second gate control terminal, and is also configured to control the indirect control subcircuit to be turned on in response to the third signal of the second gate control terminal after the display panel is powered on, so that the energy storage capacitor in the charge charging and discharging subcircuit is charged according to the voltage on the high potential transmission line, and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to discharge to the high potential transmission line in response to the second signal of the second gate control terminal when the display panel is powered off. , to delay the falling time of the voltage on the high potential transmission line, so that the charge on the pixel electrode in the display panel is discharged; the indirect control subcircuit is configured to be coupled with the selection control subcircuit, and is also configured to charge the energy storage capacitor in the charge charging and discharging subcircuit with the voltage on the high potential transmission line after being turned on; and is configured to control the load capacitor and at least one energy storage capacitor in the charge charging and discharging subcircuit to discharge to the high potential transmission line when the display panel is turned off; the charge charging and discharging subcircuit is configured to charge using the voltage on the high potential transmission line; and is also configured to delay the falling time of the voltage on the high potential transmission line through the load capacitor and at least one energy storage capacitor when the display panel is turned off, so that the charge on the pixel electrode in the display panel is discharged.

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