Signal processing method and receiving system for reducing bit width of nr system signal

Abstract

The present application relates to the technical field of mobile communication, in particular to a signal processing method and receiving system for reducing bit width of NR system signal, comprising: step S1: generating corresponding signal scaling factor according to signal power of each symbol in a to-be-processed signal; step S2: scaling signal amplitude of each symbol according to the signal scaling factor to obtain scaled symbol; step S3: intercepting bit width of the scaled symbol to obtain new to-be-processed signal. The beneficial effect lies in that, by adding the steps of scaling and bit intercepting processing for the reference signal after signal channel preprocessing, the memory required for signal storage is reduced by compressing signal amplitude and eliminating part of bit width, and the measurement error will not be caused for the reference signal, and the bit width required for the hardware accelerator is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of mobile communication technology, in particular to a signal processing method for reducing the bit width of signals in NR system and a receiving system. BACKGROUND

[0002] In the prior art, for various types of downlink signals received by user equipment, a radio frequency module is usually used for receiving, an analog-to-digital converter is used for sampling, and different channels are used for preprocessing, and then the corresponding decoding and measurement processes are entered. If a hardware accelerator or other processing chip needs to be called for processing, the preprocessed signal needs to be further stored in the memory for calling.

[0003] However, in the implementation process, the inventors found that since various types of downlink signals are sampled by the same analog-to-digital converter, the sampled signals all have corresponding bit widths, and the analog-to-digital converter itself is configured to have a relatively wide bit width. User equipment needs to process a large number of downlink signals, including downlink control signals and downlink shared signals, various types of reference signals, which leads to the fact that some reference signals, such as positioning reference signals (PRS) and channel state information reference signals (CSI-RS), need to be stored in a large amount of memory for offline processing, and the subsequent hardware accelerator also needs to be designed with a large accelerator area for the data with a wide bit width. SUMMARY

[0004] In view of the above problems in the prior art, the present application provides a signal processing method for reducing the bit width of signals in NR system. On the other hand, a signal receiving system applying the signal processing method is also provided.

[0005] The specific technical solutions are as follows:

[0006] A signal processing method for reducing the bit width of signals in NR system is suitable for user equipment to receive downlink reference signals, comprising:

[0007] Step S1: generating a corresponding signal scaling factor according to the signal power of each symbol in the to-be-processed signal;

[0008] Step S2: scaling the signal amplitude of each symbol according to the signal scaling factor to obtain a scaled symbol;

[0009] Step S3: truncating the bit width of the scaled symbol to obtain a new to-be-processed signal.

[0010] On the other hand, the step S1 comprises:

[0011] Step A11: truncating the cyclic prefix of each symbol of the to-be-processed signal respectively, and calculating a first power as the signal power according to the cyclic prefix.

[0012] Step A12: generating a target power of the symbol according to the signal power, a maximum output power and a measured power lower limit corresponding to the reference signal;

[0013] Step A13: generating the signal scaling factor corresponding to the symbol according to the target power.

[0014] In another aspect, the step S2 comprises:

[0015] Step A21: removing the cyclic prefix from each of the symbols to obtain a truncated signal, respectively;

[0016] Step A22: scaling the signal amplitude of each of the truncated signals by the signal scaling factor to obtain a scaled truncated signal;

[0017] Step A23: combining the scaled truncated signal with the corresponding cyclic prefix to obtain the scaled symbol corresponding to the symbol, respectively.

[0018] In another aspect, the step S1 comprises:

[0019] Step B11: calculating a second power of each symbol of the signal to be processed to obtain the signal power of the symbol;

[0020] Step B12: generating a target power of the symbol according to the signal power, a maximum output power and a measured power lower limit corresponding to the reference signal;

[0021] Step B13: generating the signal scaling factor corresponding to the scaled symbol according to the target power.

[0022] In another aspect, in the step S2, the scaled symbol is scaled by the signal scaling factor.

[0023] In another aspect, in the step S3, the bit width is truncated from the low bit of the scaled symbol, or the bit width is truncated from the high bit of the scaled symbol.

[0024] In another aspect, when the bit width is truncated from the high bit of the symbol, the target power is further corrected according to an input bit width and an output bit width of the signal to be processed in the step S2.

[0025] A signal receiving system for implementing the signal processing method described above, comprising:

[0026] A radio frequency module, an input end of the radio frequency module being connected to an antenna, the radio frequency module receiving a downlink signal;

[0027] an analog-to-digital converter, an input end of the analog-to-digital converter being connected to an output end of the radio frequency module, the analog-to-digital converter sampling the downlink signal;

[0028] at least one reference signal processing module, an input end of the reference signal processing module being connected to the analog-to-digital converter, the reference signal processing module processing the downlink signal by using the signal processing method and inputting the processed signal into a memory;

[0029] a hardware accelerator, the hardware accelerator obtaining the downlink signal from the memory and processing the downlink signal to obtain a processing result.

[0030] The above technical solution has the following advantages or beneficial effects:

[0031] In view of the problem in the prior art that the downlink reference signal processing process occupies more resources when being cached in the memory due to a large signal bit width and needs to use a hardware accelerator with a larger area for processing, the present application adds the steps of scaling and bit clipping processing for the reference signal after pre-processing in the signal path, reduces the memory required for signal storage by compressing the signal amplitude and eliminating part of the bit width, and the reference signal will not cause measurement error, reducing the bit width required by the hardware accelerator. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are used to more fully describe the embodiments of the present application. However, the accompanying drawings are only used for illustration and explanation, and do not constitute a limitation on the scope of the present application.

[0033] Figure 1 is a whole schematic diagram of the embodiment of the present application;

[0034] Figure 2 is a schematic diagram of step S1 in the embodiment one of the present application;

[0035] Figure 3 is a schematic diagram of step S2 in the embodiment one of the present application;

[0036] Figure 4 is a schematic diagram of step S1 in the embodiment two of the present application;

[0037] Figure 5 is a schematic diagram of the signal receiving system in the embodiment of the present application. DETAILED DESCRIPTION

[0038] With reference to the drawings and specific embodiments, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0039] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0040] The present application will be further described below in combination with the drawings and specific embodiments, but is not limited to the embodiments.

[0041] The present application includes:

[0042] A signal processing method for reducing the bit width of a signal in an NR system, suitable for a user equipment to receive a downlink reference signal, as shown in FIG. 1, comprising: Figure 1

[0043] Step S1: generating a corresponding signal scaling factor according to the signal power of each symbol in the to-be-processed signal;

[0044] Step S2: scaling the signal amplitude of each symbol according to the signal scaling factor to obtain a scaled symbol;

[0045] Step S3: truncating the bit width of each scaled symbol to obtain a new to-be-processed signal.

[0046] Specifically, for the downlink signal processing system in the prior art, because the bit width configured by the analog-to-digital sampler is large, the signal needs to occupy a large amount of space during the buffering process. In the present embodiment, for a plurality of reference signals on the downlink, the above method is used to scale the signal amplitude and truncate the bit width for each symbol in the to-be-processed signal. Since such signals are mainly used to obtain RSRP, SNR, time-frequency offset estimation and some information of the channel state, theoretically, too many data bit widths are not needed, only the signal power needs to be higher than the lower limit of the measured power to realize the measurement process, and a proper margin is added to adapt to different scenarios. Through the above setting, the resources needed by such signals in the subsequent storage and processing process can be reduced, and the use of memory space and the demand for hardware accelerator area are reduced.

[0047] ​In the implementation process, the above signal processing method is set in the corresponding signal processing system as a software embodiment, which is generally used for clipping processing of the signal before storing it into the memory after the path preprocessing of each reference signal. The signal to be processed refers to the reference signal received by the user equipment on the downlink, including timing reference signal (TRS), positioning reference signal (PRS), channel state information-reference signal (CSI-RS), etc. Symbol refers to the received sub-signal unit in each group of reference signals, which has a specific length.

[0048] In order to achieve better processing effect of the signal, the present scheme mainly has two implementation ways for the signal scaling part, including:

[0049] Embodiment one:

[0050] In this embodiment, as shown in Figure 2 Step S1 includes:

[0051] Step A11: The cyclic prefix of each symbol of the signal to be processed is cut off, and the first power calculated according to the cyclic prefix is taken as the signal power;

[0052] Step A12: The target power of the symbol is generated according to the maximum output power and the measured power lower limit corresponding to the reference signal;

[0053] Step A13: The signal scaling factor corresponding to the symbol is generated according to the signal power and the target power.

[0054] Specifically, in order to achieve better online processing effect, in this embodiment, for each symbol of the signal to be processed, the cyclic prefix (CP) thereof is cut off, and the power thereof is calculated as the signal power of the whole symbol, so as to achieve faster processing efficiency. In order to achieve better processing effect, the log2 domain power is generally selected for calculation. Subsequently, in order to adapt to the signal amplitude jitter, the target power is generated by the following formula:

[0055]

[0056] In the formula, P target is the target power, P outmax is the maximum output power, and P threshold is the measured power lower limit.

[0057] Then, the signal scaling factor of the symbol is easily calculated according to the current signal power of the signal to be processed and the target power calculated, including:

[0058]

[0059] In the formula, S factor is the signal scaling factor, P target is the target power, P cp is the signal power.

[0060] In the embodiment, as shown in Figure 3 , the step S2 includes:

[0061] Step A21: removing the cyclic prefix of each symbol respectively to obtain a truncated signal;

[0062] Step A22: scaling the signal amplitude of each truncated signal by using the signal scaling factor to obtain a scaled truncated signal;

[0063] Step A23: combining the scaled truncated signal with the corresponding cyclic prefix respectively to obtain a scaled symbol corresponding to the symbol.

[0064] Specifically, after the signal scaling factor is calculated, in order to achieve better online processing effect, in the embodiment, the signal scaling factor is further used to process the truncated signal behind the cyclic prefix, and the signal amplitude adjustment process of the truncated signal is realized. The process will make the signal amplitudes of the cyclic prefix part and the truncated signal part different, and the cyclic prefix needs to be removed in the subsequent processing process. Through the above process, the signal processing method can process each symbol in turn online, without buffering the complete symbol, calculating the signal scaling factor and then scaling, so as to improve the real-time performance.

[0065] Embodiment two

[0066] In the embodiment, as shown in Figure 4 , the step S1 includes:

[0067] Step B11: calculating the second power as the signal power of the symbol for each symbol of the signal to be processed;

[0068] Step B12: generating the target power of the symbol according to the maximum output power and the lower limit of the measured power corresponding to the reference signal;

[0069] Step B13: generating the signal scaling factor corresponding to the symbol according to the signal power and the target power.

[0070] Specifically, in order to achieve better calculation result, in the embodiment, the whole symbol is used to calculate the signal power after the complete reception and buffering of each symbol. Through the process, the calculation of the signal power of the whole symbol is more accurate, so that the relatively appropriate target scaling factor is selected. The specific calculation process is the same as that in Embodiment 1.

[0071] In the embodiment, in step S2, the scaled symbol is scaled by using the signal scaling factor.

[0072] Subsequently, after the signal scaling factor is calculated, in the embodiment, the signal scaling factor can be used to scale the whole symbol, and the bit width can be further compressed, which is suitable for offline processing.

[0073] In an embodiment, in step S3, the bit width is truncated from the low bit of the scaled symbol, or the bit width is truncated from the high bit of the scaled symbol.

[0074] In an embodiment, when the bit width is truncated from the high bit of the scaled symbol, in step S2, the target power is further corrected according to the input bit width and the output bit width of the to-be-processed signal.

[0075] After the amplitude of the to-be-processed signal is scaled and the bit is truncated by using the above method, the reference signal can be further selected to be truncated from the low bit or from the high bit. When it is determined that the bit width of the reference signal will be truncated from the high bit in step S3, since the step will right shift the signal by a specific bit, the target power needs to be further corrected to meet the measurement requirement. Specifically, the target power is corrected by using the following method: target P t ′ arget + 2 * (BITin-BITout) ;

[0076] In the formula, P target is the corrected target power, P t ′ arget is the uncorrected target power, BITin is the bit width of the original to-be-processed signal, and BITout is the bit width of the to-be-processed signal after the bit is truncated.

[0077] A signal receiving system for implementing the above signal processing method, as shown in FIG. 1, comprises: Figure 5

[0078] A radio frequency module 1, an input end of the radio frequency module 1 is connected to an antenna 11, and the radio frequency module 1 receives a downlink signal;

[0079] An analog-to-digital converter 2, an input end of the analog-to-digital converter 2 is connected to an output end of the radio frequency module 1, and the analog-to-digital converter samples the downlink signal;​

[0080] at least one reference signal processing module 3, an input end of the reference signal processing module 3 is connected to the analog-digital converter, and the reference signal processing module 3 processes the downlink signal by using the signal processing method and then inputs the downlink signal into the memory 31;

[0081] a hardware accelerator 4, which acquires the downlink signal from the memory 31 and processes the downlink signal to obtain a processing result.

[0082] Specifically, for the downlink signal processing system in the prior art, because the bit width configured by the analog-digital sampler is large, the signal needs to occupy a large amount of space in the process of buffering, in the embodiment, the reference signal processing module in the signal receiving system is improved, so that the signal processing method is used to further clip the processing in the process of pre-processing the downlink signal, thereby reducing the occupation of the memory space, and the subsequent measurement processing steps in the hardware accelerator are not affected.

[0083] In the actual implementation process, the signal receiving system is only a principle example, and other modules can be further added according to actual needs, for example, a preprocessing module for pre-processing according to different reference signals is added in the reference signal processing module 3, and related modules for processing and decoding other channels such as PDCCH and PDSCH signals are added after the analog-digital converter 2, which does not constitute a limitation on the actual scheme.

[0084] The above is only a preferred embodiment of the present application, and does not limit the implementation and protection scope of the present application. For those skilled in the art, it should be realized that any equivalent replacement and obvious changes made according to the content of the present application should be included in the protection scope of the present application.

Claims

1. A signal processing method for reducing NR system signal bit width, characterized in that, The application is suitable for receiving downlink reference signals by user equipment, comprising: Step S1: generating a signal scaling factor corresponding to each symbol in a to-be-processed signal according to signal power of each symbol in the to-be-processed signal; Step S2: scaling signal amplitude of each symbol according to the signal scaling factor to obtain a scaled symbol; Step S3: truncating bit width of each scaled symbol to obtain a new to-be-processed signal; The step S2 comprises: removing a cyclic prefix from each symbol to obtain a truncated signal; scaling the signal amplitude of each truncated signal by the signal scaling factor to obtain a scaled truncated signal; combining the scaled truncated signal with the corresponding cyclic prefix to obtain the scaled symbol corresponding to the symbol; When the bit width is truncated from the high bit of the scaled symbol, the target power is further corrected according to input bit width and output bit width of the to-be-processed signal in the step S2; The following method is used for correction: ; In the formula, is the target power after correction, is the target power before correction, is the bit width of the original signal to be processed, is the bit width of the signal to be processed after truncation.

2. The signal processing method of claim 1, wherein, The step S1 comprises: Step A11: removing a cyclic prefix from each symbol of the to-be-processed signal, and calculating a first power as the signal power according to the cyclic prefix; Step A12: generating a target power of the symbol according to a maximum output power and a lower limit of a measured power corresponding to the reference signal; Step A13: generating the signal scaling factor corresponding to the symbol according to the signal power and the target power; The target power is generated by the following formula: ； wherein Ptarget is the target power, Pmax is the maximum output power, Pmin is the measured power lower limit; The signal scaling factor is calculated by the following formula: ； wherein is a signal scaling factor, is a target power, is a signal power.

3. The signal processing method of claim 1, wherein, The step S1 comprises: Step B11: calculating each symbol of the to-be-processed signal to obtain a second power as the signal power of the symbol; Step B12: generating a target power of the symbol according to a maximum output power and a lower limit of a measured power corresponding to the reference signal; Step B13: generating the signal scaling factor corresponding to the symbol according to the signal power and the target power.

4. The signal processing method of claim 3, wherein, In the step S2, the scaled symbol is scaled by the signal scaling factor.

5. The signal processing method according to any one of claims 2 to 4, characterized by, In the step S3, the bit width is truncated from the low bit of the scaled symbol.

6. A signal receiving system characterized by comprising: A device for implementing the signal processing method according to any one of claims 1-5, comprising: a radio frequency module, an input end of the radio frequency module being connected with an antenna, the radio frequency module receiving a downlink signal; an analog-to-digital converter, an input end of the analog-to-digital converter being connected with an output end of the radio frequency module, the analog-to-digital converter sampling the downlink signal; at least one reference signal processing module, an input end of the reference signal processing module being connected with the analog-to-digital converter, the reference signal processing module processing the downlink signal by the signal processing method and inputting the downlink signal into a memory; a hardware accelerator, the hardware accelerator obtaining the downlink signal from the memory and processing the downlink signal to obtain a processing result.

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