Communication interface configuration method and communication interface

Abstract

The embodiment of the present invention discloses a configuration method of a communication interface and a communication interface. The configuration method of the communication interface includes: configuring the CSB signal of the communication interface as a low-effective signal so that the MCU reads and writes registers; configuring the FCSB signal of the communication interface as a low-effective signal so that the MCU reads and writes FIFOs; configuring the MOSI pin and the MISO pin of the communication interface to be combined into a secure digital input and output port so that the MCU and the wireless transceiver chip can perform data transmission. The solution provided by the present invention can realize the selection and switching of RF mode and FIFO mode by configuring the register of the MCU, replacing the communication mode of sending commands, and reducing the decoding work of the wireless transceiver chip and the technical effect of the internal state reaction time.

Description

Technical Field

[0001] The present invention relates to the field of chip technology applications, and in particular to a configuration method for a communication interface and a communication interface. Background Art

[0002] With the continuous development of the communication field, the application scenarios of wireless transceiver chips in daily life are becoming more and more extensive. The industry usually uses various interface protocols to realize the control of wireless transceiver chips by microcontroller units (MCUs). Among them, the serial peripheral interface (SPI) has become a commonly used interface protocol between many MCUs and wireless transceiver chips due to its high speed, full-duplex and synchronous characteristics. SPI enables MCU to configure various parameters and functions of wireless transceiver chips, thereby realizing applications in communication scenarios.

[0003] The SPI interface generally uses four wires: MOSI (master data output, slave data input, Master Input Slave Output), MISO (master data input, slave data output, Master Output Slave Input), SCLK (clock signal, generated by the master device, Serial Clock), and chip select signal CSB (slave chip select signal, sent by the master device, low bit 0 indicates valid, Chip Select).

[0004] When the existing MCU configures registers or reads and writes FIFOs to wireless transceiver chips, the host must send instructions for the corresponding operations, and the slave side needs to decode the instructions before data can be transmitted. The implementation of the decoding function increases the complexity of the wireless transceiver chip, and the decoding and switching of the internal states of the wireless transceiver chip take a certain amount of time, which reduces the efficiency of data transmission. At the same time, the switching between reading and writing slave registers and FIFOs can only be achieved by changing the type of instructions to be sent on the host side, and the switching method of reading and writing registers and FIFOs is not flexible enough. Moreover, this SPI docking method does not support continuous reading and writing of registers or FIFOs. If you want to read and write 32-bit registers, you need to perform 4 8-bit data transmissions or 2 16-bit data transmissions, which is not efficient enough.

[0005] Currently, no effective solution has been proposed to the problem of low data transmission efficiency caused by the high time spent in decoding and reading and writing when the MCU configures registers or reads and writes FIFOs of the wireless transceiver chip in the prior art. Summary of the invention

[0006] In order to solve the above technical problems, the embodiments of the present invention hope to provide a configuration method and a communication interface of a communication interface, so as to at least solve the problem of low data transmission efficiency caused by the fact that the MCU in the prior art consumes too much time in the decoding and reading and writing process when configuring registers or reading and writing FIFOs of the wireless transceiver chip.

[0007] The technical solution of the present invention is achieved in this way:

[0008] In a first aspect, an embodiment of the present invention provides a communication interface, including: the communication interface is connected to a wireless transceiver chip through a MOSI pin, a MISO pin, an SCLK pin and an NSS pin, wherein the MISO pin is a master device input / slave device output pin, used to send data in slave mode and receive data in master mode; the MOSI pin is a master device output / slave device input pin, used to send data in master mode and receive data in slave mode; the SCLK pin is a serial port clock, used for the output of the master device and the input of the slave device; the NSS pin is a master device or slave device selection pin, used to select the register of the wireless transceiver chip by setting NSS[0] as the CSB signal, and to select the FIFO of the wireless transceiver chip by setting NSS[1] as the FCSB signal; wherein the side that generates the clock is called the master device, and the other side is called the slave device; the communication interface is a single-line bidirectional mode, and the MOSI pin and the MISO pin are combined into a secure digital input and output port.

[0009] Optionally, the communication interface also includes: a sending buffer, a shift register, an STS register and a first CTRL register, wherein the sending buffer is used to write data to the sending buffer during a write operation; when a clock signal is received from the device and the first data bit appears on the MOSI pin, the data sending process starts, and the remaining digits in the data frame format are stored in the shift register; when the data in the sending buffer is transferred to the shift register, the TE flag of the SPI_STS register is set; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

[0010] Further, optionally, the communication interface also includes: a receiving buffer, wherein the receiving buffer is used to transfer the data in the shift register to the receiving buffer and set the RNE flag in the STS register when data reception is completed; if the RNEIE bit in the first CTRL register is set, an interrupt is generated; after the last sampling clock edge, the RNE bit is set to 1, and the data byte received in the shift register is transferred to the receiving buffer; when the DT register is read, the communication interface returns the value of the receiving buffer and clears the RNE bit.

[0011] Optionally, an RF_EN bit and a FIFO_MODE bit are added to the first CTRL register. The RF_EN bit is used by the MCU to configure the communication interface to enable the read and write register mode for the wireless transceiver chip; the FIFO_MODE bit is used by the MCU to configure the communication interface to enable the read and write FIFO mode for the wireless transceiver chip.

[0012] Further, optionally, the communication interface also includes: a main control circuit, wherein an NSS_SEL bit is added to the first CTRL register to enable NSS[0] and NSS[1] in the main control circuit; when the NSS_SEL bit is set to 0, NSS[0] is valid, and NSS[0] is used as a CSB signal to select the register chip in the wireless transceiver chip; when the NSS_SLE bit is set to 1, NSS[1] is valid, and NSS[1] is used as a FCSB signal to select the register chip in the wireless transceiver chip.

[0013] Optionally, the main control circuit includes: a timer using the bus clock as a reference clock, wherein the timer is used to start counting when the CSB signal is pulled low in the read and write register mode, and when the timer reaches the counting threshold, a first enable signal is sent to start data transmission.

[0014] Further, optionally, when the main control circuit detects that the data is transmitted to the preset data, the timer is started, and when the timer reaches the counting threshold, a second enable signal is generated to pull up the CSB signal.

[0015] Optionally, the communication interface also includes: a delay counter; wherein a TIM_CYCLE bit is added to the first CTRL register for configuring the delay time; a delay counter, used to count from the falling edge of the last SCLK, and when the delay counter times to the delay time, pull up the FCSB signal; when the delay counter times to a preset multiple of the delay time, if data is transmitted, pull down the FCSB signal; if no data is transmitted, keep the FCSB signal at a high level.

[0016] Optionally, the communication interface also includes: a second CTRL register, wherein the second CTRL register is used to detect address 0 sent by the MCU when the communication interface is configured to read register mode, and switch the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK to switch the IO port from output to input.

[0017] In a second aspect, an embodiment of the present invention provides a method for configuring a communication interface, which is applied to the above-mentioned communication interface, including: configuring the CSB signal of the communication interface to be a low-valid signal so that the MCU can read and write registers; configuring the FCSB signal of the communication interface to be a low-valid signal so that the MCU can read and write FIFOs; configuring the MOSI pin and the MISO pin of the communication interface to be combined into a secure digital input and output port so that the MCU can transmit data with the wireless transceiver chip.

[0018] Optionally, the method further includes: configuring the communication interface to be in single-line bidirectional mode, and setting the baud rate and data frame format; wherein, configuring the communication interface to be in single-line bidirectional mode, and setting the baud rate and data frame format includes: determining the serial clock baud rate through the MCLKP bit of the second CTRL register; determining the phase relationship between data transmission and the serial clock by configuring the CPOL and CPHA bits of the second CTRL register to be 0, wherein the phase relationship is: data is sent on the falling edge of the serial clock, and data is sampled on the rising edge of the serial clock; determining the data frame format to be 8 bits or 16 bits by configuring the DFF16 bit of the second CTRL register; determining the data frame format to be sent or received the most significant bit MSB first by configuring the LSBEN bit of the second CTRL register to be 0; if it is determined that the CSB pin is operating in input mode, in hardware mode, During data frame transmission, configure the level signal of the CSB pin to a high-level signal; in software mode, configure the SWANSSEN bit and ISS bit of the second CTRL register; if the CSB pin works in output mode, configure the NSSOE bit of the first CTRL register; by configuring the BDMODE bit of the second CTRL register, the communication interface enables single-line bidirectional mode, in which the SCLK pin is used as the clock, the master device uses the MOSI pin, and the slave device uses the MISO pin for data communication; the direction of transmission is controlled by the BDOE bit in the second CTRL register, when the BDOE bit is 1, data is output; when the BDOE bit is 0, data is input; by configuring the DT register, write the address of the wireless transceiver chip for reading and writing; by setting the MSTEN bit of the second CTRL register, configure the communication interface as a master device.

[0019] Optionally, the method also includes: configuring the communication interface to read and write wireless transceiver register mode; wherein, configuring the communication interface to read and write wireless transceiver register mode includes: configuring the NSS_SEL bit in the first CTRL register to 0, selecting to use the CSB signal as the chip select signal; configuring the RF_EN bit in the first CTRL register to 1, turning on the read and write wireless transceiver register mode; and enabling the communication interface by configuring the EN bit in the second CTRL register to 1.

[0020] Optionally, configuring the FCSB signal of the communication interface as a low-valid signal so that the MCU can read and write the FIFO includes: configuring the NSS_SEL bit in the first CTRL register to 1, selecting to use FCSB as the chip select signal; determining the delay time between consecutive read and write operations in FIFO mode by configuring the TIM_CYCLE bit in the first CTRL register; turning on the FIFO mode by configuring the FIFO_MODE bit in the first CTRL register to 1; and enabling the communication interface by configuring the SPI_EN bit in the second CTRL register to 1.

[0021] The embodiment of the present invention provides a configuration method and a communication interface of a communication interface. By configuring the CSB signal of the communication interface as a low effective signal, the MCU can read and write registers; by configuring the FCSB signal of the communication interface as a low effective signal, the MCU can read and write FIFOs; by configuring the MOSI pin and the MISO pin of the communication interface to be combined as a secure digital input and output port, the MCU can perform data transmission with a wireless transceiver chip, so that the selection and switching of the RF mode and the FIFO mode can be realized through the configuration of the register by the MCU, replacing the communication mode of sending commands, and reducing the decoding work of the wireless transceiver chip and the internal state reaction time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 A schematic diagram of a communication interface provided in Embodiment 1 of the present invention;

[0024] Figure 2 A flow chart of a method for configuring a communication interface provided in Embodiment 2 of the present invention;

[0025] Figure 3 A schematic diagram of the SPI read register timing in a communication interface configuration method provided in Embodiment 2 of the present invention;

[0026] Figure 4 A schematic diagram of the SPI write register timing in a communication interface configuration method provided in Embodiment 2 of the present invention;

[0027] Figure 5 A schematic diagram of an SPI read FIFO timing in a communication interface configuration method provided in Embodiment 2 of the present invention;

[0028] Figure 6A schematic diagram of the SPI write FIFO timing in a communication interface configuration method provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second" and the like in the specification, claims and drawings of the present invention are used to distinguish different objects rather than to limit a specific order.

[0031] It should also be noted that the following embodiments of the present invention may be executed separately, or in combination with each other, and the embodiments of the present invention do not impose specific limitations on this.

[0032] Technical terms involved in the embodiments of this application:

[0033] Microcontroller Unit: Microcontroller Unit; MCU for short;

[0034] Serial Peripheral Interface: Serial Peripheral Interface, referred to as SPI;

[0035] MOSI: Master device data output, slave device data input, Master Input Slave Output;

[0036] MISO: Master device data input, slave device data output, Master Output Slave Input;

[0037] SCLK: Clock signal, generated by the master device, Serial Clock;

[0038] Chip select signal CSB: Slave device chip select signal, sent by the master device, low bit (Below, low level is valid) 0 means valid, Chip Select Below;

[0039] SDIO: Secure Digital Input and Output, secure digital input and output;

[0040] MSB: Most Significant Bit;

[0041] RF: Radio Frequency.

[0042] Embodiment 1

[0043] In a first aspect, an embodiment of the present invention provides a communication interface. Figure 1 A schematic diagram of a communication interface provided in Embodiment 1 of the present invention; Figure 1 As shown, the communication interface provided in the embodiment of the present application includes:

[0044] The communication interface is connected to the wireless transceiver chip through the MOSI pin, MISO pin, SCLK pin and NSS pin, wherein the MISO pin is the master device input / slave device output pin, used to send data in slave mode and receive data in master mode; the MOSI pin is the master device output / slave device input pin, used to send data in master mode and receive data in slave mode; the SCLK pin is the serial port clock, used for the output of the master device and the input of the slave device; the NSS pin is the master device or slave device selection pin, used to select the register of the wireless transceiver chip by setting NSS[0] as the CSB signal, and to select the FIFO of the wireless transceiver chip by setting NSS[1] as the FCSB signal; wherein the side that generates the clock is called the master device, and the other side is called the slave device; the communication interface is a single-line bidirectional mode, and the MOSI pin and the MISO pin are combined into a secure digital input and output port.

[0045] Specifically, the communication interface provided in the embodiment of the present application can be a serial peripheral interface (referred to as SPI) in a preferred implementation scheme. In order to realize the control of MCU for CMT2300A (i.e., the wireless transceiver chip in the embodiment of the present application), it can work on a chip with ARM Cortex-M series as the core. It should be noted that the wireless transceiver chip provided in the embodiment of the present application is described by taking CMT2300A as an example, and is based on the realization of a communication interface provided in the embodiment of the present application, and is not specifically limited.

[0046] like Figure 1 As shown, MISO pin: master input / slave output pin. The MISO pin sends data in slave mode and receives data in master mode.

[0047] MOSI pin is used for master device output / slave device input pin. MOSI pin sends data in master mode and receives data in slave mode.

[0048] The SCLK pin is used for the serial port clock, which serves as the output of the master device and the input of the slave device.

[0049] NSS pin is used for slave device selection. This is an optional pin used to select the master / slave device. Its function is to be used as a "chip select pin" so that the master device can communicate with a specific slave device separately to avoid conflicts on the data line. NSS[0] and NSS[1] are used as CSB and FCSB signals respectively to select the register or FIFO of the wireless transceiver chip.

[0050] Since the SPI is configured as a single-wire bidirectional mode when the MCU communicates with the wireless transceiver chip, MISO and MOSI are both input and output at this time, and are merged into the same port SDIO (i.e., the secure digital input and output port in the embodiment of the present application).

[0051] Based on the above, the communication interface provided in the embodiment of the present application is configured as a single-line bidirectional communication mode, using only one SDIO data line for transmission, and data transmission is more intuitive.

[0052] Optionally, the communication interface provided in the embodiment of the present application also includes: a sending buffer, a shift register, an STS register and a first CTRL register, wherein the sending buffer is used to write data to the sending buffer during a write operation; when a clock signal is received from the device and the first data bit appears on the MOSI pin, the data sending process starts, and the remaining digits in the data frame format are stored in the shift register; when the data in the sending buffer is transferred to the shift register, the TE flag of the STS register is set; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

[0053] Specifically, Figure 1 As shown, during the data transmission process, in the write operation, the data is written to the transmit buffer. When the slave device receives the clock signal and the first data bit appears on the MOSI pin, the transmission process begins (wherein the first bit is sent out at this time). The remaining bits (for the 8-bit data frame format, there are 7 bits; for the 16-bit data frame format, there are 15 bits) are loaded into the shift register. When the data in the transmit buffer is transferred to the shift register, the TE flag of the SPI_STS register (i.e., the STS register in the embodiment of the present application) is set, and if the TEIE bit of the SPI_CTRL2 register (i.e., the first CTRL register in the embodiment of the present application) is set, an interrupt will be generated.

[0054] Further, optionally, the communication interface provided by the embodiment of the present application also includes: a receiving buffer, wherein the receiving buffer is used to transfer the data in the shift register to the receiving buffer and set the RNE flag in the STS register when data reception is completed; if the RNEIE bit in the first CTRL register is set, an interrupt is generated; after the last sampling clock edge, the RNE bit is set to 1, and the data byte received in the shift register is transferred to the receiving buffer; when the DT register is read, the communication interface returns the value of the receiving buffer and clears the RNE bit.

[0055] Specifically, Figure 1 As shown, during the data reception process: when data reception is completed: the data in the shift register is transferred to the receive buffer, and the RNE flag in the SPI_STS register is set. If the RNEIE bit in the SPI_CTRL2 register is set, an interrupt is generated. After the last sampling clock edge, the RNE bit is set to '1', and the data byte received in the shift register is transferred to the receive buffer. When reading the SPI_DT register (i.e., the DT register in the embodiment of the present application), the SPI device returns the value of this receive buffer. When reading the SPI_DT register, the RNE bit is cleared.

[0056] Optionally, an RF_EN bit and a FIFO_MODE bit are added to the first CTRL register. The RF_EN bit is used by the MCU to configure the communication interface to enable the read and write register mode for the wireless transceiver chip; the FIFO_MODE bit is used by the MCU to configure the communication interface to enable the read and write FIFO mode for the wireless transceiver chip.

[0057] Specifically, Figure 1 As shown in the figure, when the wireless transceiver chip is the CMT2300A chip, special improvements are made to the SPI for the CMT2300A chip: in order to replace the technology of MCU sending commands to switch the SPI transmission mode, the RF_EN and FIFO_MODE bits are added to the CTRL2 register, which are used by the MCU to configure the SPI to start the read and write register mode (RF mode) and read and write FIFO mode for CMT2300A.

[0058] Based on the above, the communication interface provided in the embodiment of the present application can realize the selection and switching of RF mode and FIFO mode through the configuration of registers by MCU, replacing the communication mode of sending commands, reducing the decoding work and internal state response time of the wireless transceiver chip.

[0059] Further, optionally, the communication interface provided in the embodiment of the present application also includes: a main control circuit, wherein an NSS_SEL bit is added to the first CTRL register to enable NSS[0] and NSS[1] in the main control circuit; when the NSS_SEL bit is set to 0, NSS[0] is valid, and NSS[0] is used as a CSB signal to select the register chip in the wireless transceiver chip; when the NSS_SLE bit is set to 1, NSS[1] is valid, and NSS[1] is used as a FCSB signal to select the register chip in the wireless transceiver chip.

[0060] Specifically, Figure 1 As shown in the figure, when the wireless transceiver chip is the CMT2300A chip, the SPI has made special improvements for the CMT2300A chip: the SPI_CTRL2 register adds the NSS_SEL bit, which is used to enable NSS[0] and NSS[1] in the main control circuit. When NSS_SEL is set to 0, NSS[0] is valid, and NSS[0] is used as the CSB signal to select the register chip in the CMT2300A. When NSS_SLE is set to 1, NSS[1] is valid, and NSS[1] is used as the FCSB signal to select the register chip in the CMT2300A.

[0061] Based on the above, the communication interface provided in the embodiment of the present application uses CSB and FCSB to distinguish and switch between register reading and writing and FIFO reading and writing, which is very flexible.

[0062] Optionally, the main control circuit includes: a timer using the bus clock as a reference clock, wherein the timer is used to start counting when the CSB signal is pulled low in the read and write register mode, and when the timer reaches the counting threshold, a first enable signal is sent to start data transmission.

[0063] Further, optionally, when the main control circuit detects that the data is transmitted to the preset data, the timer is started, and when the timer reaches the counting threshold, a second enable signal is generated to pull up the CSB signal.

[0064] Specifically, Figure 1 As shown in the figure, when the wireless transceiver chip is the CMT2300A chip, the SPI makes special improvements for the CMT2300A chip:

[0065] In order to meet the timing requirements of the CMT2300A chip at the beginning and end of data transmission (reading and writing registers requires 0.5SCLK cycle, and reading and writing FIFOs require 1SCLK cycle), a dedicated timer with the bus clock as the reference clock is designed in the main control circuit (that is, the timer with the bus clock as the reference clock in the embodiment of the present application). In the read-write register mode, the timer starts counting when CSB is pulled low, and the counting threshold is set in advance to be greater than half of the baud rate value (SCLK is the clock obtained by dividing the bus clock according to the baud rate).

[0066] When the timer reaches the counting threshold, an enable signal (i.e., the first enable signal in the embodiment of the present application) is sent to start data transmission, so that after the MCU pulls down CSB, the waiting time for data transmission is greater than the timing requirement of 0.5SCLK cycle. Similarly, after the main control circuit detects that the data is transmitted to data 7 (8-bit transmission) / data 15 (16-bit transmission) (i.e., the preset data in the embodiment of the present application), it starts the dedicated timer, and after the timer reaches the counting threshold, it generates an enable signal (i.e., the second enable signal in the embodiment of the present application), and CSB is pulled high.

[0067] Optionally, the communication interface provided in the embodiment of the present application also includes: a delay counter; wherein a TIM_CYCLE bit is added to the first CTRL register for configuring the delay time; a delay counter, used to count from the falling edge of the last SCLK, and when the delay counter times to the delay time, pull up the FCSB signal; when the delay counter times to a preset multiple of the delay time, if data is transmitted, pull down the FCSB signal; if no data is transmitted, keep the FCSB signal at a high level.

[0068] Specifically, Figure 1 As shown in the figure, when the wireless transceiver chip is the CMT2300A chip, the SPI makes special improvements for the CMT2300A chip:

[0069] Since it takes a certain amount of time to switch the internal state of CMT2300A in FIFO mode, the MCU will pull up FCSB after at least 2us after sending the last falling edge of SCLK. And between two consecutive read and write operations, FCSB must be pulled high for at least 4us. In order to implement this function, the TIM_CYCLE bit is added to the SPI_CTRL2 register to configure the delay time. There is a special delay counter inside the SPI (i.e., the delay counter in the embodiment of the present application). The delay counter starts counting from the falling edge of the last SCLK, and the counting unit is half a clock cycle of SCLK. The delay calculation formula is as follows:

[0070]

[0071] After the delay counter reaches the time defined by Delay (i.e., the delay time in the embodiment of the present application), FCSB is pulled high. In order to satisfy that the FCSB pull-up time is greater than 4us, when the delay counter reaches Delay*3 (i.e., the preset multiple of the delay time in the embodiment of the present application), a judgment is made based on whether the next data transmission is to be performed. If the data is to be transmitted, FCSB is pulled low, otherwise FCSB remains at a high level.

[0072] Based on the above, the communication interface provided in the embodiment of the present application can realize continuous transmission and reception of data, avoiding the tediousness caused by repeated configuration of repetitive single data transmission and the large amount of delay caused by repeated transmission.

[0073] Optionally, the communication interface provided in the embodiment of the present application also includes: a second CTRL register, wherein the second CTRL register is used to detect the address 0 sent by the MCU when the communication interface is configured to the read register mode, and to switch the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK to switch the IO port from output to input.

[0074] Specifically, Figure 1 As shown in the figure, when the wireless transceiver chip is the CMT2300A chip, the SPI makes special improvements for the CMT2300A chip:

[0075] An address 0 bit detection mechanism in the read register mode is designed in the SPI master control circuit. When the SPI is configured in the read register mode, it will detect the address 0 sent by the MCU, and before the falling edge of this SCLK, the BDOE bit in CTRL1 (i.e., the second CTRL register in the embodiment of the present application) will be switched from 1 to 0 to switch the IO port from output to input.

[0076] An embodiment of the present invention provides a communication interface. The communication interface is connected to the wireless transceiver chip through the MOSI pin, MISO pin, SCLK pin and NSS pin, wherein the MISO pin is a master device input / slave device output pin, used to send data in slave mode and receive data in master mode; the MOSI pin is a master device output / slave device input pin, used to send data in master mode and receive data in slave mode; the SCLK pin is a serial port clock, used for the output of the master device and the input of the slave device; the NSS pin is a master device or slave device selection pin, used to select the register of the wireless transceiver chip by setting NSS[0] as the CSB signal, and to select the FIFO of the wireless transceiver chip by setting NSS[1] as the FCSB signal; wherein the side generating the clock is called the master device, and the other side is called the slave device; the communication interface is a single-line bidirectional mode, and the MOSI pin and the MISO pin are combined into a secure digital input and output port, so that the selection and switching of the RF mode and the FIFO mode can be realized by configuring the register of the MCU, replacing the communication mode of sending commands, and reducing the decoding work of the wireless transceiver chip and the internal state reaction time.

[0077] Embodiment 2

[0078] In a second aspect, an embodiment of the present invention provides a method for configuring a communication interface, which is applied to the communication interface in the first embodiment above. Figure 2 A flow chart of a method for configuring a communication interface provided in Embodiment 2 of the present invention; Figure 2 As shown, the configuration method of the communication interface provided in the embodiment of the present application includes:

[0079] Step S202, configuring the CSB signal of the communication interface to be a low effective signal so that the MCU can read and write registers;

[0080] Step S204, configuring the FCSB signal of the communication interface to be a low effective signal so that the MCU reads and writes the FIFO;

[0081] Step S206, configuring the MOSI pin and the MISO pin of the communication interface to be combined into a secure digital input and output port, so that the MCU and the wireless transceiver chip can perform data transmission.

[0082] Specifically, the configuration method of the communication interface provided in the embodiment of the present application can be applied to the communication interface in the first embodiment. By using two slave device chip select signals CSB and FCSB, the register or FIFO of the infinite transceiver chip can be selected for reading and writing respectively, without sending command switching, which is very flexible. And the transmission mode can be changed by different configurations of the host to SPI without unnecessary processing on the slave side. The master-slave transmission and reception are carried out through a data line SDIO, which reduces the number of data transmission ports, and supports continuous reading and writing of data. Multiple beats of data can be transmitted at one time, which improves the transmission efficiency.

[0083] Among them, the low-effective CSB is the chip select signal for accessing the register, and the low-effective FCSB is the chip select signal for accessing the FIFO. Both cannot be set to low at the same time. SCLK is the serial port clock, and the fastest speed can reach 5MHz. Whether for the MCU itself or the external wireless transceiver chip, data is sent out on the falling edge of SCLK and data is collected on the rising edge. SDIO is a bidirectional pin used for input and output data. The address and data parts are transmitted starting from the MSB.

[0084] In summary, the configuration method of the communication interface provided in the embodiment of the present application configures the SPI in the read-write register and the read-write FIFO as follows:

[0085] 1. Configuration of read and write registers to SPI:

[0086] When accessing a register, CSB must be pulled low. Then a R / W bit is sent first, followed by a 7-bit register address. After the MCU pulls CSB low, it must wait for at least half an SCLK cycle before it can start sending the R / W bit. After the MCU sends the last falling edge of SCLK, it must wait for at least half an SCLK cycle before pulling CSB high.

[0087] for Figure 3 The read register operation, Figure 3 A schematic diagram of the SPI read register timing in a method for configuring a communication interface provided in Embodiment 2 of the present invention, in which both the MCU and CMT2300A (i.e., the wireless transceiver chip in the embodiment of the present application) will switch the IO (SDIO) port between address 0 and data 7. At this time, the CMT2300A will switch the IO port from input to output, and the MCU will switch the IO port from output to input. At the position of the middle dotted line, the MCU will switch the IO port to input before sending the falling edge of SCLK; the CMT2300A will switch the IO to output only after seeing the falling edge. This avoids the situation where both set SDIO to output at the same time, causing electrical conflicts. Figure 4 A schematic diagram of the SPI write register timing in a communication interface configuration method provided in Embodiment 2 of the present invention.

[0088] Optionally, the configuration method of the communication interface provided in the embodiment of the present application also includes: configuring the communication interface to a single-line bidirectional mode, and setting the baud rate and the data frame format; wherein, configuring the communication interface to a single-line bidirectional mode, and setting the baud rate and the data frame format includes: determining the serial clock baud rate through the MCLKP bit of the second CTRL register; determining the phase relationship between data transmission and the serial clock by configuring the CPOL and CPHA bits of the second CTRL register to 0, wherein the phase relationship is: data is sent on the falling edge of the serial clock, and data is sampled on the rising edge of the serial clock; determining the data frame format to be 8 bits or 16 bits by configuring the DFF16 bit of the second CTRL register; determining the data frame format to be 8 bits or 16 bits by configuring the LSBEN bit of the second CTRL register to be 0; if it is determined that the CSB pin is operating in input mode, In hardware mode, during data frame transmission, the level signal of the CSB pin is configured to be a high-level signal; in software mode, the SWANSSEN bit and ISS bit of the second CTRL register are configured; if the CSB pin works in output mode, the NSSOE bit of the first CTRL register is configured; by configuring the BDMODE bit of the second CTRL register, the communication interface enables a single-line bidirectional mode, in which the SCLK pin is used as the clock, the master device uses the MOSI pin, and the slave device uses the MISO pin for data communication; the direction of transmission is controlled by the BDOE bit in the second CTRL register, when the BDOE bit is 1, data is output; when the BDOE bit is 0, data is input; by configuring the DT register, the address of the wireless transceiver chip for reading and writing is written; by setting the MSTEN bit of the second CTRL register, the communication interface is configured as a master device.

[0089] Specifically, configure SPI to single-wire bidirectional mode and set the baud rate and data frame format including:

[0090] First, the serial clock baud rate is defined by the MCLKP[3:0] bit of the SPI_CTRL1 register (ie, the second CTRL register in the embodiment of the present application).

[0091] Second, configure the CPOL and CPHA bits of the SPI_CTRL1 register to 0 to define the phase relationship between data transmission and the serial clock (data is sent on the falling edge and data is sampled on the rising edge).

[0092] Third, configure the DFF16 bit of the SPI_CTRL1 register to define the 8-bit or 16-bit data frame format.

[0093] Fourth, configure the LSBEN bit of the SPI_CTRL1 register to 0, defining the frame format as sending / receiving MSB first.

[0094] Fifth, if the CSB pin is required to work in input mode, in hardware mode, the CSB pin should be connected to a high level during the entire data frame transmission; in software mode, the SWANSSEN bit and ISS bit of the SPI_CTRL1 register need to be set. If the CSB pin works in output mode, only the NSSOE bit needs to be set.

[0095] Sixth, set the BDMODE bit of the SPI_CTRL1 register to enable the single-line bidirectional mode. In this mode, the SCLK pin is used as the clock, the master device uses the MOSI pin and the slave device uses the MISO pin for data communication. The direction of transmission is controlled by the BDOE in the SPI_CTRL1 register. When this bit is '1', the data line is output, otherwise it is input. (BDOE is used to determine whether it is read or write).

[0096] Seventh, set the SPI_DT register and write the address of the wireless transceiver chip to be read or written.

[0097] Eighth, set MSTEN of the SPI_CTRL1 register to configure the SPI as a master device.

[0098] Optionally, the configuration method of the communication interface provided in the embodiment of the present application also includes: configuring the communication interface to a read-write wireless transceiver register mode; wherein, configuring the communication interface to a read-write wireless transceiver register mode includes: configuring the NSS_SEL bit in the first CTRL register to 0, and selecting to use the CSB signal as the chip select signal; configuring the RF_EN bit in the first CTRL register to 1, turning on the read-write wireless transceiver register mode; and enabling the communication interface by configuring the EN bit in the second CTRL register to 1.

[0099] Specifically, configuring SPI to RF mode includes:

[0100] First, configure NSS_SEL in SPI_CTRL2 (ie, the first CTRL register in the embodiment of the present application) to 0, and select CSB as the chip select signal.

[0101] Second, configure RF_EN in SPI_CTRL2 to 1 to enable RF mode (read and write wireless transceiver registers).

[0102] Third, configure SPI_EN (ie, the EN bit in the embodiment of the present application) in SPI_CTRL1 (ie, the second CTRL register in the embodiment of the present application) to 1 to enable the SPI device.

[0103] 2. Read and write FIFO configuration for SPI:

[0104] When the MCU needs to access the FIFO, it must first configure some registers to set the FIFO read / write mode. The timing diagram for reading and writing FIFO is as follows: Figure 5 and Figure 6 As shown, Figure 5 A schematic diagram of an SPI read FIFO timing in a communication interface configuration method provided in Embodiment 2 of the present invention; Figure 6 A schematic diagram of the SPI write FIFO timing in a configuration method of a communication interface provided in Example 2 of the present invention. It should be noted that the control of FCSB is slightly different from the control of CSB when accessing registers. When starting to access, FCSB must be pulled low for 1 clock cycle before sending out the rising edge of SCLK. After sending out the last falling edge of SCLK, it will take at least 2us before FCSB is pulled high. Between two consecutive read and write operations, FCSB must be pulled high for at least 4us. When writing to FIFO, the data of the first bit must be ready 0.5 clock cycles before the rising edge of the first SCLK is sent.

[0105] Among them, in the process of reading and writing FIFO, SPI is configured as a single-line bidirectional mode, and the baud rate and data frame format are set to be the same as the read / write register, which will not be repeated here.

[0106] Optionally, in step S204, the FCSB signal of the communication interface is configured as a low-valid signal so that the MCU reads and writes the FIFO, including: configuring the NSS_SEL bit in the first CTRL register to 1, selecting to use FCSB as the chip select signal; determining the delay time between consecutive read and write operations in FIFO mode by configuring the TIM_CYCLE bit in the first CTRL register; turning on the FIFO mode by configuring the FIFO_MODE bit in the first CTRL register to 1; and enabling the communication interface by configuring the EN bit in the second CTRL register to 1.

[0107] Specifically, configuring SPI to FIFO mode includes:

[0108] Configure NSS_SEL in SPI_CTRL2 to 1 and select FCSB as the chip select signal.

[0109] Configure TIM_CYCLE in SPI_CTRL2 to an appropriate value to meet the 2us and 4us delays between consecutive read and write operations in FIFO mode. The delay time starts counting from the falling edge of the last SCLK, and the counting unit is half a clock cycle of SCLK. The calculation formula for the delay time is as follows:

[0110]

[0111] Configure FIFO_MODE in SPI_CTRL2 to 1 to enable FIFO mode (read and write FIFO).

[0112] Configure SPI_EN in SPI_CTRL1 to 1 to enable the SPI device.

[0113] The embodiment of the present invention provides a configuration method of a communication interface. By configuring the CSB signal of the communication interface as a low-effective signal, the MCU can read and write registers; by configuring the FCSB signal of the communication interface as a low-effective signal, the MCU can read and write FIFOs; by configuring the MOSI pin and the MISO pin of the communication interface to be combined as a secure digital input and output port, the MCU can perform data transmission with a wireless transceiver chip, thereby enabling the selection and switching of the RF mode and the FIFO mode to be realized through the configuration of the register by the MCU, replacing the communication mode of sending commands, and reducing the decoding work of the wireless transceiver chip and the internal state reaction time.

[0114] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0115] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0116] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0117] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A communication interface, characterized in that: include: The communication interface is connected to the wireless transceiver chip through the MOSI pin, the MISO pin, the SCLK pin and the NSS pin, wherein: The MISO pin is a master device input / slave device output pin, used to send data in slave mode and receive data in master mode; The MOSI pin is a master device output / slave device input pin, used for sending data in the master mode and receiving data in the slave mode; The SCLK pin is a serial port clock, which is used for the output of the master device and the input of the slave device; The NSS pin is a master device or slave device selection pin, and is used to select the register of the wireless transceiver chip by setting NSS[0] as the CSB signal, and to select the FIFO of the wireless transceiver chip by setting NSS[1] as the FCSB signal; The side generating the clock is called the master device, and the other side is called the slave device; the communication interface is a single-line bidirectional mode, and the MOSI pin and the MISO pin are combined into a secure digital input and output port; The communication interface also includes: a main control circuit, wherein: Adding an NSS_SEL bit in the first CTRL register to enable NSS[0] and NSS[1] in the main control circuit; when the NSS_SEL bit is set to 0, NSS[0] is valid, and the NSS[0] is used as the CSB signal to select the register chip in the wireless transceiver chip; when the NSS_SLE bit is set to 1, NSS[1] is valid, and the NSS[1] is used as the FCSB signal to select the register chip in the wireless transceiver chip; The RF_EN bit and FIFO_MODE bit are added to the first CTRL register. The RF_EN bit is used by the MCU to configure the communication interface to enable the read and write register mode for the wireless transceiver chip; the FIFO_MODE bit is used by the MCU to configure the communication interface to enable the read and write FIFO mode for the wireless transceiver chip.

2. The communication interface according to claim 1, characterized in that: The communication interface further includes: a sending buffer, a shift register, an STS register and a first CTRL register, wherein: The sending buffer is used to write data to the sending buffer during a write operation; when the slave device receives a clock signal and the first data bit appears on the MOSI pin, the data sending process starts, and the remaining digits in the data frame format are stored in the shift register; when the data in the sending buffer is transferred to the shift register, the TE flag of the STS register is set; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

3. The communication interface according to claim 2, characterized in that: The communication interface further comprises: a receiving buffer, wherein: The receiving buffer is used to transfer the data in the shift register to the receiving buffer and set the RNE flag in the STS register when data reception is completed; if the RNEIE bit in the first CTRL register is set, an interrupt is generated; after the last sampling clock edge, the RNE bit is set to 1, and the data byte received in the shift register is transferred to the receiving buffer; when reading the DT register, the communication interface returns the value of the receiving buffer and clears the RNE bit.

4. The communication interface according to claim 1, characterized in that: The main control circuit includes: a timer using the bus clock as a reference clock, wherein the timer is used in a read-write register mode, the timer starts counting when the CSB signal is pulled low, and when the timer reaches a counting threshold, a first enable signal is sent to start data transmission.

5. The communication interface according to claim 4, characterized in that: When the main control circuit detects that the data is transmitted to the preset data, the timer is started, and when the timer reaches the counting threshold, a second enable signal is generated to pull up the CSB signal.

6. The communication interface according to claim 1, characterized in that: The communication interface also includes: a delay counter; wherein, A TIM_CYCLE bit is also added to the first CTRL register to configure the delay time; The delay counter is used to count from the falling edge of the last SCLK. When the delay counter times to the delay time, the FCSB signal is pulled high; when the delay counter times to a preset multiple of the delay time, if data is transmitted, the FCSB signal is pulled low; if the data is not transmitted, the FCSB signal is kept at a high level.

7. The communication interface according to claim 1, characterized in that: The communication interface also includes: a second CTRL register, wherein the second CTRL register is used to detect the address 0 sent by the MCU when the communication interface is configured as a read register mode, and to switch the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK to switch the IO port from output to input.

8. A method for configuring a communication interface, characterized in that: The communication interface as claimed in any one of claims 1 to 7, comprising: By configuring the CSB signal of the communication interface to be a low-effective signal, the MCU can read and write registers; By configuring the FCSB signal of the communication interface to be a low effective signal, the MCU is enabled to read and write the FIFO; The MOSI pin and the MISO pin of the communication interface are configured to be combined into a secure digital input and output port so that the MCU and the wireless transceiver chip can perform data transmission.

9. The method for configuring a communication interface according to claim 8, characterized in that: The method further comprises: Configuring the communication interface to a single-line bidirectional mode, and setting the baud rate and data frame format; wherein configuring the communication interface to a single-line bidirectional mode, and setting the baud rate and data frame format comprises: The serial clock baud rate is determined by the MCLKP bit of the second CTRL register; By configuring the CPOL and CPHA bits of the second CTRL register to be 0, a phase relationship between data transmission and the serial clock is determined, wherein the phase relationship is: data is sent at the falling edge of the serial clock, and data is sampled at the rising edge of the serial clock; Determine the data frame format to be 8 bits or 16 bits by configuring the DFF16 bit of the second CTRL register; By configuring the LSBEN bit of the second CTRL register to be 0, determining that the data frame format is to send or receive the most significant bit MSB first; If it is determined that the CSB pin works in input mode, in hardware mode, during data frame transmission, the level signal of the CSB pin is configured to be a high level signal; in software mode, the SWANSSEN bit and the ISS bit of the second CTRL register are configured; if the CSB pin works in output mode, the NSSOE bit of the first CTRL register is configured; By configuring the BDMODE bit of the second CTRL register, the communication interface enables a single-line bidirectional mode, wherein the SCLK pin is used as the clock, the master device uses the MOSI pin, and the slave device uses the MISO pin for data communication; the direction of transmission is controlled by the BDOE bit in the second CTRL register, when the BDOE bit is 1, the data is output; when the BDOE bit is 0, the data is input; By configuring the DT register, write the address of the wireless transceiver chip to read and write; By setting the MSTEN bit of the second CTRL register, the communication interface is configured as a master device.

10. The method for configuring a communication interface according to claim 9, characterized in that: The method further comprises: Configuring the communication interface to read and write wireless transceiver register RF mode; wherein configuring the communication interface to read and write wireless transceiver register mode includes: By configuring the NSS_SEL bit in the first CTRL register to be 0, the CSB signal is selected as the chip select signal; By configuring the RF_EN bit in the first CTRL register to 1, the read and write wireless transceiver register mode is enabled; By configuring the EN bit in the second CTRL register to be 1, the communication interface is enabled.

11. The method for configuring a communication interface according to claim 9, characterized in that: The configuring the FCSB signal of the communication interface to be a low effective signal so that the MCU reads and writes the FIFO includes: By configuring the NSS_SEL bit in the first CTRL register to be 1, FCSB is selected as the chip select signal; Determine the delay time between consecutive read and write operations in FIFO mode by configuring the TIM_CYCLE bit in the first CTRL register; Enable FIFO mode by configuring the FIFO_MODE bit in the first CTRL register to 1; By configuring the EN bit in the second CTRL register to be 1, the communication interface is enabled.

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