A display panel, a display device and a manufacturing method of a display panel

Abstract

The application discloses a display panel, a display device and a manufacturing method of the display panel, and aims at improving the problem that the pixel area of the prior art display panel is prone to dark spot defects. The display panel comprises a plurality of pixel areas on one side of a substrate and a blocking area on one side of at least part of the pixel areas; the pixel areas and the blocking area have an auxiliary electrode, a first electrode structure, a light-emitting layer and a second electrode structure on the one side of the substrate in sequence; the first electrode structure blocks the light-emitting layer in the blocking area, so that the second electrode structure is overlapped with the auxiliary electrode at the disconnection position of the light-emitting layer; and the thickness of the first electrode structure of the blocking area is greater than the thickness of the first electrode structure of the pixel area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a display panel, a display device and a manufacturing method of the display panel. BACKGROUND

[0002] Transparent organic light emitted diode (OLED) display products have both display and light transmission functions, and can be applied in subway windows and billboards. Figure 1 As shown, the OLED display product has a pixel area P and a light transmission area T, and the light transmission function is realized by sacrificing resolution.

[0003] However, the OLED product in the prior art has the problem that the pixel area is prone to dark spot defects. SUMMARY

[0004] The present application provides a display panel, a display device and a manufacturing method of the display panel to improve the problem that the pixel area in the prior art display panel is prone to dark spot defects.

[0005] The present application provides a display panel, a display device and a manufacturing method of the display panel to improve the problem that the pixel area in the prior art display panel is prone to dark spot defects.

[0006] In a possible implementation, the first electrode structure at least includes a reflective electrode and a first electrode located on the side of the reflective electrode away from the auxiliary electrode.

[0007] The film layer thickness of the reflective electrode of the blocking area is greater than the film layer thickness of the reflective electrode of the pixel area.

[0008] In a possible implementation, in the blocking area, the first electrode includes a first electrode part and a second electrode part located at the periphery of the first electrode part, wherein the orthographic projection of the first electrode part on the substrate and the orthographic projection of the reflective electrode on the substrate coincide with each other.

[0009] In the pixel area, the orthographic projection of the first electrode on the substrate and the orthographic projection of the reflective electrode on the substrate coincide with each other.

[0010] In a possible implementation, in the pixel area, the auxiliary electrode comprises a first crystallized indium tin oxide layer, and the first electrode comprises a second crystallized indium tin oxide layer and an induced crystallized indium tin oxide layer arranged in a stack.

[0011] In the blocking area, the auxiliary electrode comprises a first indium tin oxide layer, and the first electrode comprises a second indium tin oxide layer.

[0012] In a possible implementation, in the pixel area, the auxiliary electrode comprises a third indium tin oxide layer, and the first electrode comprises a fourth indium tin oxide layer and a fifth indium tin oxide layer arranged in a stack.

[0013] In the blocking area, the auxiliary electrode comprises a sixth indium tin oxide layer, and the first electrode comprises a seventh indium tin oxide layer.

[0014] In a possible implementation, the display panel further comprises a source-drain layer between the substrate and the auxiliary electrode, and a passivation layer between the source-drain layer and the auxiliary electrode; the source-drain layer comprises an auxiliary electrode lead.

[0015] The blocking area further comprises a via hole penetrating through the passivation layer, and the auxiliary electrode is electrically connected to the auxiliary electrode lead through the via hole.

[0016] The blocking area has the same auxiliary electrode and first electrode structure as the pixel area at a position of the via hole.

[0017] In a possible implementation, the display panel further comprises a plurality of transparent areas, and a projection of the transparent area on the substrate does not at least partially overlap with a projection of the blocking area on the substrate.

[0018] Embodiments of the present application also provide a display device comprising the display panel provided by the embodiments of the present application.

[0019] Embodiments of the present application also provide a manufacturing method of a display panel, comprising:

[0020] forming an auxiliary electrode and a first electrode structure in a pixel area and a blocking area on one side of a substrate, wherein the first electrode structure is located on a side of the auxiliary electrode away from the substrate, and a thickness of the first electrode structure in the blocking area is greater than a thickness of the first electrode structure in the pixel area;

[0021] forming a light-emitting layer on a side of the first electrode structure away from the auxiliary electrode, wherein the light-emitting layer is blocked by the first electrode structure in the blocking area;

[0022] A second electrode structure is formed on the side of the light emitting layer away from the first electrode structure, and the second electrode structure is overlapped with the auxiliary electrode at the break of the light emitting layer.

[0023] In one possible implementation, the blocking region includes a via; the pixel region and the blocking region on one side of the substrate form an auxiliary electrode and a first electrode structure, including:

[0024] A first sub-indium tin oxide layer, a copper / molybdenum / niobium stack, and a second sub-indium tin oxide layer are sequentially formed on one side of the substrate;

[0025] The first sub-indium tin oxide layer, the copper / molybdenum / niobium stack, and the second sub-indium tin oxide layer are removed from the regions other than the pixel region and the via region, and annealing is performed, and the first sub-indium tin oxide layer of the pixel region after annealing is taken as a first crystallized indium tin oxide layer, and the second sub-indium tin oxide layer is taken as a second crystallized indium tin oxide layer;

[0026] A third sub-indium tin oxide layer, a copper / molybdenum / niobium stack, and a fourth sub-indium tin oxide layer are sequentially formed on the side of the second crystallized indium tin oxide layer away from the first crystallized indium tin oxide layer;

[0027] A patterned first photoresist is formed only in the blocking region, the copper / molybdenum / niobium stack and the fourth sub-indium tin oxide layer in the pixel region and the via region are removed, the third sub-indium tin oxide layer in the blocking region is taken as a first indium tin oxide layer, the fourth sub-indium tin oxide layer is taken as a second indium tin oxide layer, and the third sub-indium tin oxide layer in the pixel region is taken as an induced crystallized indium tin oxide layer;

[0028] Alternatively, the pixel region and the blocking region on one side of the substrate form an auxiliary electrode and a first electrode structure, including:

[0029] A fifth sub-indium tin oxide layer, a copper / molybdenum / niobium stack, and a sixth sub-indium tin oxide layer are sequentially formed on one side of the substrate;

[0030] The fifth sub-indium tin oxide layer, the copper / molybdenum / niobium stack, and the sixth sub-indium tin oxide layer are removed from the regions other than the pixel region and the via region, and the fifth sub-indium tin oxide layer of the pixel region is taken as a third indium tin oxide layer, and the sixth sub-indium tin oxide layer is taken as a fourth crystallized indium tin oxide layer;

[0031] A seventh sub-indium tin oxide layer, a copper / molybdenum / niobium stack, and an eighth sub-indium tin oxide layer are sequentially formed on the side of the fourth crystallized indium tin oxide layer away from the third indium tin oxide layer;

[0032] Form a patterned second photoresist in the blocking area, the pixel area, and the via area, remove the copper / molybdenum / niobium stack outside the blocking area, and the eighth sub-ITO layer, take the seventh sub-ITO layer in the blocking area as a sixth ITO layer, and take the eighth sub-ITO layer as a seventh ITO layer.

[0033] The first electrode structure in the blocking area blocks the light-emitting layer, so that the second electrode structure is overlapped with the auxiliary electrode at the broken part of the light-emitting layer; the thickness of the first electrode structure in the blocking area is greater than the thickness of the first electrode structure in the pixel area, that is, the first electrode structure is thicker in the blocking area, which can block the light-emitting layer to realize the subsequent overlap of the second electrode structure and the auxiliary electrode; the first electrode structure is thinner in the pixel area, which can avoid more dark spots when the first electrode structure in the pixel area is thicker, and affect the normal display of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A top view of a display panel provided by the embodiment of the present application is shown;

[0035] Figure 2 A sectional view of a display panel provided by the embodiment of the present application is shown;

[0036] Figure 3a A sectional view of the related art when forming an auxiliary cathode 02 is shown;

[0037] Figure 3b A sectional view of the related art when forming a patterned auxiliary cathode 02 is shown;

[0038] Figure 3c A sectional view of the related art when forming a first electrode is shown;

[0039] Figure 3d A sectional view of the related art when forming a patterned reflective electrode and a first electrode is shown;

[0040] Figure 3e A sectional view of the related art when forming a patterned ITO layer is shown;

[0041] Figure 4 A sectional view of a display panel provided by the embodiment of the present application is shown;

[0042] Figure 5 A sectional view of a display panel provided by the embodiment of the present application is shown;

[0043] Figure 6 A flowchart of a manufacturing process of a display panel provided by the embodiment of the present application is shown;

[0044] Figure 7a A cross-sectional view of forming a first electrode structure precursor film layer of a pixel region in an embodiment of the present application;

[0045] Figure 7b A cross-sectional view of forming a first electrode structure of a pixel region in an embodiment of the present application;

[0046] Figure 7c A cross-sectional view of forming a first electrode structure precursor film layer of a blocking region in an embodiment of the present application;

[0047] Figure 7d A cross-sectional view of forming a first electrode structure of a blocking region in an embodiment of the present application;

[0048] Figure 8a A cross-sectional view of forming a first electrode structure precursor film layer of a pixel region in another embodiment of the present application;

[0049] Figure 8b A cross-sectional view of forming a first electrode structure of a pixel region in another embodiment of the present application;

[0050] Figure 8c A cross-sectional view of forming a first electrode structure precursor film layer of a blocking region in another embodiment of the present application;

[0051] Figure 8d A cross-sectional view of forming a first electrode structure of a blocking region in another embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort belong to the scope of protection of the present disclosure.

[0053] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms are used herein to distinguish one element from another, and are not necessarily used in a sequence or order, unless otherwise specified. The terms "comprises", "comprising", "includes", "including" and the like can be used herein to indicate that elements or objects encompassed by the terms can include, but not exclusively, those listed after the terms. The terms "connected", "coupled", and the like can be used herein to indicate either a direct connection or an indirect connection or an electrical connection, either directly or indirectly. The terms "upper", "lower", "left", "right", and the like are used herein merely to indicate relative positions, and can be changed when the absolute positions of the described objects are changed.

[0054] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art to be within the limits of the measurement and error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.

[0055] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0056] Referring to Figure 1 and Figure 2 as shown, wherein, Figure 2 is Figure 1 An enlarged cross-sectional schematic view of the via K in FIG. 4 shows that the panel can include a pixel region P and a blocking region R, wherein the blocking region R can block the light-emitting layer 4, achieving the overlap of the auxiliary electrode 2 and the second electrode structure 5 (which can be a cathode), thereby reducing the cathode impedance.

[0057] In the related art, in combination with Figures 3a-3eAs shown in the transparent reflective electrode (auxiliary cathode 02 and reflective anode 03) forming the pixel area P and the blocking area R, the manufacturing process includes: one, forming a first layer of indium tin oxide and annealing, forming a patterned crystalline indium tin oxide layer, which can be used as an auxiliary cathode 02 and the Arrat Test and maintenance processes, such as Figures 3a-3b As shown in the second, the buffer indium tin oxide layer 031 (the buffer indium tin oxide layer 031 can be formed when the crystalline indium tin oxide layer is deposited on the crystalline indium tin oxide layer, that is, the induced crystalline indium tin oxide layer), Cu / Mo / Nb layer 032 (which can be used as a reflective anode 03), and the top layer of indium tin oxide layer 033 are deposited on the patterned crystalline indium tin oxide layer formed in the first step, and the top layer of indium tin oxide layer 033 is etched, the Cu / Mo / Nb layer 032 is etched, and the buffer indium tin oxide layer 031 is etched, as shown in Figures 3c-3e ;

[0058] As shown in Figure 3e , in the related process, the thickness of the transparent reflective electrode (auxiliary cathode 02 and reflective anode 03) of the blocking area R (RIB area) and the pixel area P is the same, and the dark spots formed by the Cu Particle (PT) have a positive relationship with the thickness of the Cu / Mo / Nb layer. Therefore, when the transparent reflective electrode (auxiliary cathode 02 and reflective anode 03) of the pixel area P is thicker, the Cu Particle causes more dark spot defects, and when the Cu / Mo / Nb layer is etched, the Cu etchant can easily leak through the cracks in the indium tin oxide layer at the via K, causing the auxiliary electrode lead 6 (SD layer) below the passivation layer 7 to corrode, resulting in abnormal impedance of the via K.

[0059] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components is omitted.

[0060] Therefore, in combination with Figure 1 , Figure 2 , Figure 4 , Figure 5 As shown in the present application, a display panel is provided, which includes a plurality of pixel areas P located on one side of a substrate 1, and a blocking area R located on one side of at least part of the pixel area P; the pixel area P and the blocking area R have an auxiliary electrode 2, a first electrode structure 3, a light-emitting layer 4, and a second electrode structure 5 located on one side of the substrate 1 in sequence; wherein the first electrode structure 3 blocks the light-emitting layer 4 in the blocking area R, so that the second electrode structure 5 is connected with the auxiliary electrode 2 at the broken part of the light-emitting layer 4; the thickness d1 of the first electrode structure 3 of the blocking area R is greater than the thickness d2 of the first electrode structure 3 of the pixel area P.

[0061] In the embodiment of the present application, the first electrode structure 3 blocks the light-emitting layer 4 in the blocking area R, so that the second electrode structure 5 is overlapped with the auxiliary electrode 2 at the position where the light-emitting layer 4 is broken; the thickness d1 of the first electrode structure 3 in the blocking area R is greater than the thickness d2 of the first electrode structure 3 in the pixel area P, that is, the first electrode structure 3 is thicker in the blocking area R, which can block the light-emitting layer 4 to realize the subsequent overlap of the second electrode structure 5 and the auxiliary electrode 2; the first electrode structure 3 is thinner in the pixel area P, which can avoid more dark spots when the first electrode structure 3 in the pixel area P is thicker, thereby affecting the normal display of the display panel.

[0062] It should be noted that, Figure 4 and Figure 5 In order to more clearly show the contrast of the film layers at the pixel area P, the blocking area R and the via K, only part of the pixel area P, the blocking area R and the via K are compared and described, and the positional relationship of the pixel area P, the blocking area R and the via K in the specific implementation can not be limited thereto.

[0063] Specifically, as shown in Figure 1 The display panel provided by the embodiment of the present application can be a transparent display panel, that is, the display panel further comprises a plurality of transparent areas T, and the orthogonal projection of the transparent area T on the substrate substrate 1 and the orthogonal projection of the blocking area R on the substrate substrate 1 at least partially do not overlap. Specifically, the orthogonal projection of the transparent area T on the substrate substrate 1 and the orthogonal projection of the blocking area R on the substrate substrate 1 can completely mutually overlap.

[0064] Specifically, as shown in Figure 2 The display panel further comprises a buffer layer 81, an interlayer dielectric layer 82, a source-drain electrode layer 6, a passivation layer 7 and a planarization layer 83 arranged in sequence between the substrate electrode plate 1 and the auxiliary electrode 2; and a pixel definition layer 84 can also be arranged between the auxiliary electrode 2 and the light-emitting layer 4.

[0065] In a possible implementation, as shown in Figure 4 or Figure 5 The first electrode structure 3 at least comprises a reflective electrode 31 and a first electrode 32 located on the side of the reflective electrode 31 away from the auxiliary electrode; the film layer thickness d3 of the reflective electrode 31 in the blocking area R is greater than the film layer thickness d4 of the reflective electrode 31 in the pixel area P.

[0066] Specifically, in the blocking area R, the thickness d3 of the reflective electrode 31 can be greater than and less than In the pixel area P, the thickness d4 of the reflective electrode 31 can be greater than and less than Specifically, the thickness d4 of the reflective electrode 31 can be The light emitting layer 4 is blocked by the reflective electrode 31 in the blocking area R. Specifically, in the blocking area R, the thickness d3 of the reflective electrode 31 can be greater than the thickness of the auxiliary electrode 2, and the thickness d3 of the reflective electrode 31 can also be greater than the thickness of the first electrode 32; in the pixel area P, the thickness d4 of the reflective electrode 31 can be substantially equal to the thickness of the auxiliary electrode 2, and the thickness d3 of the reflective electrode 31 can also be substantially equal to the thickness of the first electrode 32.

[0067] Specifically, the first electrode 32 can be an anode. Specifically, the second electrode structure 5 can include a second electrode, and the second electrode can be a cathode.

[0068] Specifically, the reflective electrode 31 can include copper / molybdenum / niobium or aluminum / molybdenum which are sequentially stacked on the side of the auxiliary electrode 2 away from the substrate 1.

[0069] In a possible implementation, referring to Figure 4 As shown in the figure, in the blocking area R, the first electrode 32 includes a first electrode part Z1 and a second electrode part Z2 located at the periphery of the first electrode part Z1, wherein the orthographic projection of the first electrode part Z1 on the substrate 1 and the orthographic projection of the reflective electrode 31 on the substrate 1 overlap each other, so as to realize the blocking of the light emitting layer 4 by the difference in structure; in the pixel area P, the orthographic projection of the first electrode 32 on the substrate 1 and the orthographic projection of the reflective electrode 31 on the substrate 1 overlap each other, that is, different from the prior art, the first electrode 32 and the reflective electrode 31 in the pixel area P can be formed by different process procedures than the first electrode 32 and the reflective electrode 31 in the blocking area R, and thus the size relationship of the first electrode 32 and the reflective electrode 31 in the pixel area P can be different from the size relationship of the first electrode 32 and the reflective electrode 31 in the blocking area R.

[0070] In a possible implementation, referring to Figure 4 As shown in the figure, in the pixel area P, the auxiliary electrode 2 includes a first crystallized indium tin oxide layer 22, and the first electrode 32 includes a second crystallized indium tin oxide layer 322 and an induced crystallized indium tin oxide layer 323 which are sequentially stacked; in the blocking area R, the auxiliary electrode 2 includes a first indium tin oxide layer 21, and the first electrode 32 includes a second indium tin oxide layer 321. In the embodiment of the application, when the auxiliary electrode 2 and the first electrode structure 3 in the pixel area P and the blocking area R are formed, the first electrode structure 3 in the pixel area P can be formed first, and then the first electrode structure 3 in the blocking area R can be formed, so as to realize the first electrode structure 3 with different thicknesses in the pixel area P and the blocking area R.

[0071] In a possible implementation, referring to Figure 5As shown, in the pixel region P, the auxiliary electrode 2 comprises a third indium tin oxide layer 23, and the first electrode 3 comprises a fourth indium tin oxide layer 324 and a fifth indium tin oxide layer 325 arranged in a stack; in the blocking region R, the auxiliary electrode 2 comprises a sixth indium tin oxide layer 24, and the first electrode 32 comprises a fourth crystallized indium tin oxide layer 326. In the embodiment of the present application, when the auxiliary electrode 2 and the first electrode structure 3 in the pixel region P and the blocking region R are formed, the first electrode structure 3 in the pixel region P can be formed first, and then the first electrode structure 3 in the blocking region R is formed, so that the first electrode structure 3 in the pixel region P and the blocking region R can have different thicknesses.

[0072] In a possible implementation, in combination with Figure 2 、 Figure 4 and Figure 5 As shown, the display panel further comprises a source-drain layer 6 between the substrate 1 and the auxiliary electrode 2, and a passivation layer 7 between the source-drain layer 6 and the auxiliary electrode 2; the source-drain layer 6 comprises an auxiliary electrode lead 60; the blocking region R further comprises a via K penetrating the passivation layer 7, and the auxiliary electrode 2 is electrically connected to the auxiliary electrode lead 60 through the via K; the blocking region R has the same auxiliary electrode 2 and first electrode structure 3 as the pixel region P at the position of the via K. In the embodiment of the present application, the auxiliary electrode 2 and the first electrode structure 3 at the via K have the same structure as the pixel region P, so that when the reflective electrode 31 in the blocking region R is formed by patterning, the auxiliary electrode 2 and the first electrode structure 3 at the via K can block the penetration of etching liquid, so as to avoid the corrosion of the etching liquid to the auxiliary lead 6 below the via K, and thus the problem of impedance failure is avoided.

[0073] Based on the same inventive concept, the embodiment of the present application further provides a display device comprising the display panel provided by the embodiment of the present application.

[0074] Based on the same inventive concept, referring to Figure 6 As shown, the embodiment of the present application further provides a manufacturing method of a display panel, which comprises:

[0075] In step S100, an auxiliary electrode and a first electrode structure are formed in a pixel region and a blocking region on one side of a substrate, wherein the first electrode structure is located on the side of the auxiliary electrode away from the substrate, and the thickness of the first electrode structure in the blocking region is greater than the thickness of the first electrode structure in the pixel region;

[0076] In step S200, a light-emitting layer is formed on the side of the first electrode structure away from the auxiliary electrode, wherein the light-emitting layer is interrupted by the first electrode structure in the blocking region;

[0077] In step S300, a second electrode structure is formed on the side of the light-emitting layer away from the first electrode structure, and the second electrode structure is overlapped with the auxiliary electrode at the interruption of the light-emitting layer.

[0078] In a possible implementation, referring to Figures 7a-7d As shown, the blocking area R includes the via K; the pixel area P and the blocking area R on one side of the substrate 1 form the auxiliary electrode 2 and the first electrode structure 3, which can include:

[0079] Referring to Figure 7a As shown, the first sub-indium tin oxide layer 91, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the second sub-indium tin oxide layer 92 are sequentially formed on one side of the substrate 1; specifically, the first sub-indium tin oxide layer 91, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the second sub-indium tin oxide layer 92 can be sequentially formed on one side of the planar layer 83;

[0080] Referring to Figure 7b As shown, the first sub-indium tin oxide layer 91, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the second sub-indium tin oxide layer 92 in the areas other than the pixel area P and the via area K are removed, i.e., the first sub-indium tin oxide layer 91, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the second sub-indium tin oxide layer 92 in the pixel area P and the via area K are retained; specifically, the first shielding glue PR1 can be formed in the pixel area P, and the second shielding glue PR2 can be formed in the via area K; the first sub-indium tin oxide layer 91, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the second sub-indium tin oxide layer 92 in the blocking area R are etched and removed under the shielding of the first shielding glue PR1 and the second shielding glue PR2; then, annealing is performed, and the first sub-indium tin oxide layer 91 in the pixel area P after annealing serves as the first crystallized indium tin oxide layer 22, and the second sub-indium tin oxide layer 92 serves as the second crystallized indium tin oxide layer 322; referring to Figure 7c As shown, the third sub-indium tin oxide layer 93, the copper / molybdenum / niobium stack (which can serve as the reflective layer 31), and the fourth sub-indium tin oxide layer 94 are sequentially formed on the side of the second crystallized indium tin oxide layer 322 away from the first crystallized indium tin oxide layer 22;

[0081] Referring to Figure 7dAs shown, only in the blocking area R, the patterned first photoresist PR3 is formed, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), the fourth sub-ITO layer 94 in the pixel area P and the via area K are removed, the third sub-ITO layer 93 in the blocking area R is used as the first ITO layer 21, the fourth sub-ITO layer 94 is used as the second ITO layer 321, and the third sub-ITO layer 93 in the pixel area P is used as the induced crystallized ITO layer 323. It can be understood that, since the first sub-ITO layer 91, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the second sub-ITO layer 92 are patterned and then annealed, after the third sub-ITO layer 93, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the fourth sub-ITO layer 94 are formed by the AUX Mask, and the third sub-ITO layer 93, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the fourth sub-ITO layer 94 are patterned, no patterned photoresist (Pattern) is needed to shield the pixel area P and the via area K, that is, the crystallized ITO layer at the position is not etched when the fourth sub-ITO layer 94 is etched, and thus no patterned photoresist is needed to be arranged at the position;

[0082] In a possible implementation, referring to Figures 8a-8d As shown, the blocking area R includes the via K; the pixel area P and the blocking area R on one side of the substrate 1 form the auxiliary electrode 2 and the first electrode structure 3, which includes:

[0083] Referring to Figure 8a As shown, the fifth sub-ITO layer 95, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the sixth sub-ITO layer 96 are sequentially formed on one side of the substrate 1; specifically, the fifth sub-ITO layer 95, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the sixth sub-ITO layer 96 can be sequentially formed on one side of the planar layer 83.

[0084] Referring to Figure 8b As shown, the fifth sub-ITO layer 95, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the sixth sub-ITO layer 96 in the areas other than the pixel area P and the via area K are removed, that is, the fifth sub-ITO layer 95, the copper / molybdenum / niobium layer (which can be used as the reflective layer 31), and the sixth sub-ITO layer 96 in the pixel area P and the via area K are retained; specifically, the third shielding glue PR4 can be formed in the pixel area P, and the fourth shielding glue PR5 can be formed in the via area K, and the fifth sub-ITO layer 95 and the sixth sub-ITO layer 96 in the blocking area R are etched and removed under the shielding of the third shielding glue PR4 and the fourth shielding glue PR5, the fifth sub-ITO layer 95 in the pixel area P is used as the third ITO layer 23, and the sixth sub-ITO layer 96 is used as the fourth crystallized ITO layer 326.

[0085] Referring to Figure 8c As shown in the figure, the seventh sub-ITO layer 97, the copper / molybdenum / nitride stack (which can be used as the reflective layer 31), and the eighth sub-ITO layer 98 are formed in sequence on the side of the fourth crystallized ITO layer 326 facing away from the third ITO layer 23;

[0086] Referring to Figure 8d As shown in the figure, the patterned second photoresist PR6 is formed in the blocking area R, the pixel area P, and the via area K, the copper / molybdenum / nitride stack (which can be used as the reflective layer 31) and the eighth sub-ITO layer 98 are removed except in the blocking area R, the seventh sub-ITO layer 97 in the blocking area R is used as the sixth ITO layer 24, the eighth sub-ITO layer 98 is used as the fourth crystallized ITO layer 326, and the seventh sub-ITO layer 97 in the pixel area P is used as the fifth ITO layer 325. It can be understood that the fifth sub-ITO layer 95, the copper / molybdenum / nitride stack (which can be used as the reflective layer 31), and the sixth sub-ITO layer 96 are not annealed after being patterned, and the seventh sub-ITO layer 97, the copper / molybdenum / nitride stack (which can be used as the reflective layer 31), and the eighth sub-ITO layer 98 are formed and patterned by the AUX Mask, so the second photoresist PR6 is needed in the pixel area P and the via area K to prevent etching.

[0087] In the embodiment of the present application, the first electrode structure 3 blocks the light-emitting layer 4 in the blocking area R, so that the second electrode structure 5 is overlapped with the auxiliary electrode 2 at the position where the light-emitting layer 4 is broken; the thickness d1 of the first electrode structure 3 in the blocking area R is greater than the thickness d2 of the first electrode structure 3 in the pixel area P, that is, the first electrode structure 3 is thicker in the blocking area R, which can block the light-emitting layer 4 to achieve the subsequent overlap of the second electrode structure 5 and the auxiliary electrode 2; the first electrode structure 3 is thinner in the pixel area P, which can avoid the problem of more dark spots when the first electrode structure 3 in the pixel area P is thicker, thereby affecting the normal display of the display panel.

[0088] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application cover modifications and changes as long as they come within the scope of the claims and their equivalents.

Claims

1. A display panel, characterized in that: It includes multiple pixel areas located on one side of a base substrate, and a blocking area located on one side of at least part of the pixel areas; the pixel areas and the blocking areas have an auxiliary electrode, a first electrode structure, a light-emitting layer, and a second electrode structure located in sequence on one side of the base substrate; wherein the first electrode structure at least includes: a reflective electrode, and a first electrode located on the side of the reflective electrode away from the auxiliary electrode; the film thickness of the reflective electrode in the blocking area is greater than the film thickness of the reflective electrode in the pixel area; the first electrode structure blocks the light-emitting layer in the blocking area so that the second electrode structure overlaps with the auxiliary electrode at the disconnection point of the light-emitting layer; the thickness of the first electrode structure in the blocking area is greater than the thickness of the first electrode structure in the pixel area.

2. The display panel according to claim 1, wherein In the blocking area, the first electrode includes a first electrode portion and a second electrode portion located outside the first electrode portion, wherein an orthographic projection of the first electrode portion on the base substrate and an orthographic projection of the reflective electrode on the base substrate overlap with each other; In the pixel area, the orthographic projection of the first electrode on the base substrate and the orthographic projection of the reflective electrode on the base substrate overlap with each other.

3. The display panel according to claim 1, wherein In the pixel area, the auxiliary electrode includes: a first crystallized indium tin oxide layer, and the first electrode includes: a second crystallized indium tin oxide layer and an induced crystallized indium tin oxide layer that are stacked; In the blocking region, the auxiliary electrode includes a first indium tin oxide layer, and the first electrode includes a second indium tin oxide layer.

4. The display panel according to claim 1, wherein: In the pixel area, the auxiliary electrode includes: a third indium tin oxide layer, and the first electrode includes: a fourth indium tin oxide layer and a fifth indium tin oxide layer that are stacked; In the blocking region, the auxiliary electrode includes a sixth indium tin oxide layer, and the first electrode includes a seventh indium tin oxide layer.

5. The display panel according to any one of claims 2 to 4, wherein: The display panel further comprises: a source-drain electrode layer located between the base substrate and the auxiliary electrode, and a passivation layer located between the source-drain electrode layer and the auxiliary electrode; the source-drain electrode layer comprises an auxiliary electrode lead; The blocking region further includes a via hole penetrating the passivation layer, and the auxiliary electrode is electrically connected to the auxiliary electrode lead through the via hole; The blocking area has the same auxiliary electrode and first electrode structure as the pixel area at the location of the via hole.

6. The display panel according to claim 1, wherein: The display panel further includes a plurality of transparent areas, wherein the orthographic projections of the transparent areas on the base substrate do not overlap with the orthographic projections of the blocking areas on the base substrate at least partially.

7. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 6.

8. A method for manufacturing a display panel, characterized in that: include: forming a first indium tin oxide sub-layer, a copper / molybdenum / niobium stacked layer, and a second indium tin oxide sub-layer in sequence on one side of the base substrate; removing the first indium tin oxide sub-layer, the copper / molybdenum / niobium stacked layer, and the second indium tin oxide sub-layer from areas other than the pixel area and the via hole area, and performing annealing, and using the first indium tin oxide sub-layer in the pixel area after annealing as a first crystallized indium tin oxide layer, and the second indium tin oxide sub-layer as a second crystallized indium tin oxide layer; forming a third indium tin oxide sub-layer, a copper / molybdenum / niobium stacked layer, and a fourth indium tin oxide sub-layer in sequence on a side of the second crystallized indium tin oxide layer facing away from the first crystallized indium tin oxide layer; forming a patterned first photoresist only in the blocking area, removing the copper / molybdenum / niobium stack and the fourth indium tin oxide layer in the pixel area and the via area, using the third indium tin oxide layer in the blocking area as the first indium tin oxide layer, the fourth indium tin oxide layer as the second indium tin oxide layer, and the third indium tin oxide layer in the pixel area as the induced crystallization indium tin oxide layer; Alternatively, a fifth indium tin oxide layer, a copper / molybdenum / niobium stacked layer, and a sixth indium tin oxide layer are sequentially formed on one side of the base substrate; removing the fifth indium tin oxide layer, the copper / molybdenum / niobium stacked layer, and the sixth indium tin oxide layer from areas other than the pixel area and the via hole area, and using the fifth indium tin oxide layer in the pixel area as the third indium tin oxide layer and the sixth indium tin oxide layer as the fourth crystallized indium tin oxide layer; forming a seventh indium tin oxide sub-layer, a copper / molybdenum / niobium stacked layer, and an eighth indium tin oxide sub-layer in sequence on a side of the fourth crystallized indium tin oxide layer away from the third indium tin oxide layer; forming a patterned second photoresist in the blocking area, the pixel area, and the via area, removing the copper / molybdenum / niobium stack and the eighth indium tin oxide layer outside the blocking area, using the seventh indium tin oxide layer in the blocking area as the sixth indium tin oxide layer, the eighth indium tin oxide layer as the seventh indium tin oxide layer, and using the seventh indium tin oxide layer in the pixel area as the fifth indium tin oxide layer; forming a light-emitting layer on a side of the first electrode structure facing away from the auxiliary electrode, wherein the light-emitting layer is blocked by the first electrode structure in the blocking area; A second electrode structure is formed on a side of the light-emitting layer away from the first electrode structure, and the second electrode structure is overlapped with the auxiliary electrode at a disconnection point of the light-emitting layer.

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