Display substrate and display device

Abstract

The present invention provides a display substrate and a display device, relating to the field of display technology, and is used to improve the layout of various structures arranged in the peripheral area of a special-shaped display product, so as to achieve a narrow frame of the special-shaped display product. The display substrate includes: a display area and a peripheral area surrounding the display area, the peripheral area including a binding area and a special-shaped area, and the display area is located between the binding area and the special-shaped area; the display substrate also includes a plurality of compensation scan lines and a plurality of data lines, the compensation scan lines including a portion located in the special-shaped area, and the data lines including a portion located in the display area and a portion located in the special-shaped area; the special-shaped area includes: an electrostatic discharge circuit and a load compensation structure, at least a portion of the electrostatic discharge circuit being located between the display area and the load compensation structure; the electrostatic discharge circuit is respectively coupled to the plurality of data lines.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application scope of special-shaped display products is becoming increasingly broad. Special-shaped display products include a display area and a peripheral area surrounding the display area. The width of this peripheral area determines the width of the special-shaped display product's border. Therefore, in order to better achieve a narrow border for special-shaped display products, it is necessary to improve the layout of the various structures arranged in the peripheral area of special-shaped display products. Summary of the Invention

[0003] An object of the present invention is to provide a display substrate and a display device for improving the layout of various structures arranged in the peripheral area of a special-shaped display product, so as to achieve a narrow frame of the special-shaped display product.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, comprising: a display area and a peripheral area surrounding the display area, the peripheral area comprising a binding area and a profiled area, at least a portion of the display area being located between the binding area and the profiled area;

[0006] The display substrate further includes a plurality of compensation scan lines and a plurality of data lines, wherein the compensation scan lines include a portion located in the special-shaped area, and the data lines include a portion located in the display area and a portion located in the special-shaped area;

[0007] The special-shaped area includes: an electrostatic discharge circuit and a load compensation structure, at least a portion of the electrostatic discharge circuit is located between the display area and the load compensation structure;

[0008] The electrostatic discharge circuits are respectively coupled to the plurality of data lines.

[0009] Optionally, the display substrate further includes a common signal line, the orthographic projections of the common signal line on the substrate of the display substrate at least partially overlap with the orthographic projections of the multiple compensation scan lines on the substrate, and the common signal line is multiplexed into the load compensation structure.

[0010] Optionally, the common signal trace is arranged around the display area, the common signal trace includes a compensation portion and a non-compensation portion, the compensation portion is located in the special-shaped area, and in a direction perpendicular to an extension direction of the compensation portion, a minimum distance between a boundary of the compensation portion close to the display area and a boundary of the compensation portion far from the display area is greater than a width of the non-compensation portion in a direction perpendicular to its own extension direction;

[0011] The orthographic projections of the compensation portion on the substrate of the display substrate at least partially overlap with the orthographic projections of the plurality of compensation scanning lines on the substrate, and the compensation portion is multiplexed into the load compensation structure.

[0012] Optionally, the compensation portion is formed as a grid structure.

[0013] Optionally, the compensation portion includes a first sub-portion and a second sub-portion, the first sub-portion is located between the display area and the second sub-portion; the first sub-portion includes a hollow area;

[0014] The special-shaped area includes a bottom area and a slope area. Along the direction from the slope area to the bottom area, in a direction perpendicular to the extension direction of the first sub-part, the distance between the boundary of the first sub-part close to the display area and the boundary of the first sub-part away from the display area gradually decreases, and the width of the second sub-part in a direction perpendicular to its own extension direction gradually increases.

[0015] Optionally, the display substrate includes a plurality of rows of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along a first direction; the compensation scan line is coupled to each sub-pixel included in a corresponding row of sub-pixels respectively;

[0016] The plurality of compensation scan lines include a first compensation scan line to an Nth compensation scan line, the number of sub-pixels included in a row of sub-pixels corresponding to the Xth compensation scan line is less than the number of sub-pixels included in a row of sub-pixels corresponding to the X+1th compensation scan line, and 1≤X≤N-1;

[0017] An overlapping area between an orthographic projection of the Xth compensation scan line on the substrate and an orthographic projection of the compensation portion on the substrate is greater than an overlapping area between an orthographic projection of the X+1th compensation scan line on the substrate and an orthographic projection of the compensation portion on the substrate.

[0018] Optionally, the display area includes a first display area and two second display areas, the first display area is located on the same side of the two second display areas, and the special-shaped area is located between the two display areas;

[0019] The multiple rows of sub-pixels include multiple rows of first sub-pixels and multiple rows of second sub-pixels, the multiple rows of first sub-pixels are located in the first display area, and among the multiple rows of second sub-pixels, a portion of the second sub-pixels in each row of second sub-pixels are located in one of the second display areas, and another portion of the second sub-pixels in each row of second sub-pixels are located in another second display area;

[0020] The plurality of compensation scan lines correspond one-to-one to the plurality of rows of second sub-pixels, the compensation scan lines comprising a first line segment, a second line segment, and a third line segment coupled in sequence, the first line segment and the third line segment each including at least a portion extending along the first direction, and the second line segment extending along a boundary of the heteromorphic region;

[0021] The orthographic projection of the first line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate, the orthographic projection of the second line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate, and the orthographic projection of the third line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate.

[0022] Optionally, the display substrate further includes a plurality of non-compensation scan lines, at least a portion of the non-compensation scan lines being located in the first display area, the plurality of non-compensation scan lines corresponding one-to-one to the plurality of rows of first sub-pixels, and the non-compensation scan lines being respectively coupled to each first sub-pixel in a corresponding row of first sub-pixels;

[0023] The compensation scanning line and the non-compensation scanning line are arranged on the same layer, and the common signal line and the data line are arranged on the same layer.

[0024] Optionally, the non-compensating part includes a first non-compensating part and a second non-compensating part, the display area is located between the first non-compensating part and the second non-compensating part, the first end of the first non-compensating part is coupled to the first end of the compensating part, the second end of the first non-compensating part is located in the binding area, the first end of the second non-compensating part is coupled to the second end of the compensating part, and the second end of the second non-compensating part is located in the binding area.

[0025] Optionally, the display substrate further includes a shielding line, the shielding line is located in the peripheral area, the shielding line is arranged around the display area, and the common signal line is located between the display area and the shielding line.

[0026] Optionally, the electrostatic release circuit includes a plurality of electrostatic release sub-circuits, and the plurality of electrostatic release sub-circuits correspond one-to-one to the plurality of data lines;

[0027] The electrostatic release sub-circuit includes a first transistor and a second transistor, the gate of the first transistor is coupled to the input electrode of the first transistor, the input electrode of the first transistor is coupled to the input electrode of the second transistor, the output electrode of the first transistor is coupled to the output electrode of the second transistor, and the gate of the second transistor is coupled to the output electrode of the second transistor; the input electrode of the first transistor is coupled to the corresponding data line.

[0028] Optionally, the input electrode of the first transistor, the input electrode of the second transistor and the corresponding data line form an integrated structure.

[0029] Optionally, the multiple electrostatic release sub-circuits are divided into multiple electrostatic release sub-circuit groups, and the multiple electrostatic release sub-circuit groups are arranged in sequence in the special-shaped area, each electrostatic release sub-circuit group includes at least two electrostatic release sub-circuits, and the gates of the second transistors included in each electrostatic release sub-circuit group form an integrated structure.

[0030] Optionally, the plurality of compensation scan lines are divided into a plurality of compensation scan line groups, each compensation scan line group includes at least two adjacent compensation scan lines, and at least part of the electrostatic release sub-circuit groups are located between adjacent compensation scan line groups.

[0031] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display panel, comprising the above-mentioned display substrate, the display panel further comprising an opposing substrate; the opposing substrate is arranged opposite to the display substrate; the opposing substrate comprises:

[0032] A black matrix layer, the black matrix layer including a display area pattern and a non-display area pattern, the orthographic projection of the display area pattern on the display substrate being located in the display area of the display substrate, and the orthographic projection of the non-display area pattern on the display substrate being located in the peripheral area of the display substrate; a black matrix hollowed-out area is provided between the display area pattern and the non-display area pattern.

[0033] Optionally, the orthographic projection of the electrostatic discharge circuit in the display substrate on the substrate of the display substrate is located between the orthographic projection of the load compensation structure in the display substrate on the substrate and the orthographic projection of the black matrix hollow area on the substrate.

[0034] Optionally, the opposite substrate further includes a supporting layer, at least a portion of which is located in the black matrix hollowing area.

[0035] Optionally, the support layer includes a blue color resist pattern, and the blue color resist pattern includes a portion located in the black matrix hollow area and a portion located around the black matrix hollow area.

[0036] Optionally, the display panel further includes a frame-sealing glue, which is located between the display substrate and the opposing substrate. The orthographic projection of the frame-sealing glue on the display substrate is located in the peripheral area of the display substrate. The orthographic projection of the frame-sealing glue on the substrate at least partially overlaps with the orthographic projection of the hollow area included in the common signal line in the display substrate on the substrate.

[0037] Based on the technical solution of the above-mentioned display panel, a third aspect of the present invention provides a display device including the above-mentioned display panel.

[0038] In the technical solution provided by the present invention, both the electrostatic discharge circuit and the load compensation structure are disposed in the profiled area, and the electrostatic discharge circuit is disposed between the display area and the load compensation structure. Because the electrostatic discharge circuit is disposed close to the display area and there are no other structures between the electrostatic discharge circuit and the display area, the electrostatic discharge circuit can be closely adjacent to the data lines to which it is coupled. This not only reduces the difficulty of coupling the electrostatic discharge circuit with the data lines, but also shortens the distance between the electrostatic discharge circuit and the data lines, reducing the overall layout space occupied by the electrostatic discharge circuit and the data lines to which it is coupled, thereby facilitating a narrow frame on the display substrate side of the profiled area.

[0039] Furthermore, the technical solution provided by the present invention moves the electrostatic discharge circuit, originally located on the lower frame of the display substrate, to the profiled area, effectively reducing the width of the lower frame of the display substrate. Furthermore, when the electrostatic discharge circuit is moved to the profiled area, some structures in the profiled area can be removed, allowing the space originally used for the layout of the electrostatic discharge circuit to be used for the layout of the electrostatic discharge circuit. Therefore, even if the electrostatic discharge circuit is moved to the profiled area, the width of the display substrate frame in the profiled area does not need to be increased.

[0040] In addition, the load compensation structure can perform loading compensation on the compensation scan line, reducing the loading difference between the compensation scan line and the non-compensation scan line, better ensuring the loading uniformity of the compensation scan line and the non-compensation scan line, and effectively improving the display quality of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0042] Figure 1 A first schematic diagram of the overall structure of a display substrate provided by an embodiment of the present invention;

[0043] Figure 2A schematic structural diagram of a display panel near a special-shaped area provided by an embodiment of the present invention;

[0044] Figure 3 for Figure 2 An enlarged schematic diagram of the X1 portion;

[0045] Figure 4 for Figure 3 Schematic diagram of removing common signal routing;

[0046] Figure 5 A schematic diagram of the overlap of common signal lines and compensation scan lines provided by an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of two electrostatic discharge sub-circuits provided in an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of coupling two electrostatic discharge sub-circuits and corresponding data lines provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of coupling an electrostatic discharge sub-circuit group and corresponding data lines provided by an embodiment of the present invention;

[0050] Figure 9 A partial schematic diagram of a black matrix layer provided in an embodiment of the present invention;

[0051] Figure 10 for Figure 3 A schematic cross-sectional view of the X2 portion in the direction perpendicular to the boundary of the profiled region;

[0052] Figure 11 A schematic diagram of the loading difference between the compensated scan line and the non-compensated scan line provided by an embodiment of the present invention;

[0053] Figure 12 A second schematic diagram of the overall structure of a display substrate provided by an embodiment of the present invention;

[0054] Figure 13 A schematic diagram of coupling multiple electrostatic discharge sub-circuits and data lines provided by an embodiment of the present invention;

[0055] Figure 14 for Figure 13 Schematic diagram of the layout of the middle gate metal layer, active layer, and source and drain metal layer;

[0056] Figure 15 for Figure 13 Schematic diagram of the layout of the source and drain metal layer;

[0057] Figure 16 for Figure 13 Schematic diagram of the layout of the indium tin oxide layer. DETAILED DESCRIPTION

[0058] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, they are described in detail below with reference to the accompanying drawings.

[0059] See also Figures 1 to 4 An embodiment of the present invention provides a display substrate, comprising: a display area 10 and a peripheral area surrounding the display area 10, the peripheral area comprising a binding area 12 and a special-shaped area 11, at least a portion of the display area 10 is located between the binding area 12 and the special-shaped area 11; it should be noted that the special-shaped area 11 here refers to a non-linear area of the display panel, such as an arc-shaped area, a broken line area, etc., in the special-shaped area 11, the length between two selected points is greater than the distance of the straight line between the two selected points.

[0060] The display substrate further includes a plurality of compensation scan lines 20 and a plurality of data lines 30, wherein the compensation scan lines 20 include a portion located in the special-shaped area 11, and the data lines 30 include a portion located in the display area 10 and a portion located in the special-shaped area 11;

[0061] The special-shaped area 11 includes: an electrostatic discharge circuit and a load compensation structure, at least a portion of the electrostatic discharge circuit is located between the display area 10 and the load compensation structure;

[0062] The electrostatic discharge circuits are respectively coupled to the plurality of data lines 30 , and the load compensation structure is used to compensate for the load of the compensation scan line 20 .

[0063] Exemplarily, the compensation scan lines 20 also include a portion located in the display area 10. It should be noted that all scan lines in the display substrate are divided into two categories: compensation scan lines and non-compensation scan lines. Non-compensation scan lines include a portion located in the first display area and are connected to the first sub-pixel in the first display area. Compensation scan lines connect to the second sub-pixel in the second display area and include a portion located in both the display area 10 and the profile area 11.

[0064] Exemplarily, the display substrate is applied to a liquid crystal display panel, and the display substrate includes an array substrate. The display substrate includes a display area 10 and a peripheral area. The peripheral area includes a binding area 12 and a special-shaped area 11, wherein the binding area 12 is located at the lower frame of the display substrate, and the special-shaped area 11 is located at the upper frame of the display substrate. Optionally, the binding area 12 is bound to a driver chip, i.e., a COG (chip on glass) solution. Of course, the binding area 12 can also be bound to a flexible circuit board, and the driver chip is bound to the flexible circuit board, i.e., a COF (chip on film) solution, which is not limited here.

[0065] Exemplarily, the display substrate may also be applied to an organic light emitting diode display panel.

[0066] For example, in a display panel to which the display substrate is applied, transistors may include a-Si transistors, low-temperature polysilicon transistors (LTPS), and the like.

[0067] Exemplarily, the compensation scan line 20 includes at least a portion extending along a first direction, and the data line 30 includes at least a portion extending along a second direction, wherein the first direction intersects the second direction. Exemplarily, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0068] Exemplarily, the portion of the compensation scan line 20 located in the display area 10 is coupled to the corresponding sub-pixel. The portion of the data line 30 located in the display area 10 is coupled to a corresponding column of sub-pixels, and the portion of the data line 30 located in the special-shaped area 11 is coupled to the electrostatic discharge circuit.

[0069] Exemplarily, the electrostatic release circuit and the load compensation structure are both located in the special-shaped area 11, and at least part of the positive projection of the electrostatic release circuit on the substrate of the display substrate is located between the positive projection of the load compensation structure on the substrate and the display area 10.

[0070] Exemplarily, the electrostatic discharge circuits are respectively coupled to the plurality of data lines 30 for discharging the static charges on the plurality of data lines 30 to ensure stable operation of the display substrate.

[0071] For example, the irregularly shaped area 11 is V-shaped, U-shaped or arc-shaped. The display substrate includes a first display area 101 and two second display areas 102. The first display area 101 is located on the same side of the two second display areas 102, and the irregularly shaped area 11 is located between the two display areas.

[0072] The display substrate includes multiple rows of sub-pixels, each row of sub-pixels including multiple rows of first sub-pixels and multiple rows of second sub-pixels. The multiple rows of first sub-pixels are located in the first display area 101. In the multiple rows of second sub-pixels, a portion of the second sub-pixels in each row of second sub-pixels are located in one of the second display areas 102, and another portion of the second sub-pixels in each row of second sub-pixels are located in another of the second display areas 102. The number of first sub-pixels in each row of first sub-pixels is greater than the number of second sub-pixels in each row of second sub-pixels.

[0073] The display substrate includes a plurality of compensation scan lines 20 and a plurality of non-compensation scan lines. The plurality of non-compensation scan lines correspond one-to-one with the plurality of rows of first sub-pixels, and the non-compensation scan lines are coupled to each first sub-pixel in a corresponding row of first sub-pixels. The plurality of compensation scan lines 20 correspond one-to-one with the plurality of rows of second sub-pixels, and the compensation scan lines 20 are coupled to each second pixel in a corresponding row of second sub-pixels. It is worth noting that the first and second sub-pixels have the same structure, but are given different names to distinguish them from each other in different display areas.

[0074] Because the number of second sub-pixels coupled to the compensation scan line 20 is less than the number of first sub-pixels coupled to the non-compensation scan line, the loading of the compensation scan line 20 is smaller than that of the non-compensation scan line. To ensure uniform loading between the compensation scan line 20 and the non-compensation scan line, loading compensation is required for the compensation scan line 20. The compensation value for the loading compensation of the compensation scan line 20 is determined based on the difference between the number of second sub-pixels coupled to the scan line and the number of first sub-pixels included in a row of first sub-pixels. This difference is related to the shape of the profiled region 11.

[0075] Exemplarily, the load compensation structure is used to compensate the load of the compensation scan line 20 so that the loading of the compensation scan line 20 is close to or equal to that of the non-compensation scan line.

[0076] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the electrostatic discharge circuit and the load compensation structure are both disposed in the profiled area 11, and the electrostatic discharge circuit is disposed between the display area 10 and the load compensation structure. Because the electrostatic discharge circuit is disposed close to the display area and there is no other structure between the electrostatic discharge circuit and the display area 10, the electrostatic discharge circuit can be in close proximity to the data line 30 to which it is coupled. This not only reduces the difficulty of coupling the electrostatic discharge circuit and the data line 30, but also reduces the distance between the electrostatic discharge circuit and the data line 30, reducing the overall layout space occupied by the electrostatic discharge circuit and the data line 30 to which it is coupled, thereby facilitating a narrow frame on the side of the display substrate in the profiled area 11.

[0077] Furthermore, in the display substrate provided by the embodiment of the present invention, the electrostatic discharge circuit originally located in the lower frame of the display substrate is moved to the profiled area 11, effectively reducing the width of the lower frame of the display substrate. Furthermore, when the electrostatic discharge circuit is moved to the profiled area 11, some structures in the profiled area 11 can be removed, and the space originally used for the layout of these structures can be used to layout the electrostatic discharge circuit. Therefore, even if the electrostatic discharge circuit is moved to the profiled area 11, the width of the display substrate frame at the profiled area 11 does not need to be increased.

[0078] More specifically, in related art, when the electrostatic discharge circuit is placed in the lower bezel, the width of the lower bezel occupied by the electrostatic discharge circuit is between 70 microns and 100 microns, including both end values. In the display substrate provided by the embodiments of the present invention, by removing or modifying some of the structures in the profiled area 11, a portion of the layout space is freed up, and the electrostatic discharge circuit is transferred from the lower bezel to the freed-up layout space. This not only eliminates the need to increase the bezel width in the profiled area 11, but also reduces the width of the lower bezel of the display substrate by at least 70 microns.

[0079] In addition, the load compensation structure can perform loading compensation on the compensation scan line 20, thereby reducing the loading difference between the compensation scan line 20 and the non-compensation scan line, better ensuring the loading uniformity of the compensation scan line 20 and the non-compensation scan line, and effectively improving the display quality of the display substrate.

[0080] like Figures 2 to 4 , Figure 10As shown, in some embodiments, the display substrate further includes a common signal line (including a compensation portion 401 and a non-compensation portion 402), and the orthographic projections of the common signal line on the substrate of the display substrate at least partially overlap with the orthographic projections of the multiple compensation scan lines 20 on the substrate, and the common signal line is multiplexed as the load compensation structure.

[0081] Exemplarily, the common signal trace is used to transmit a common signal.

[0082] Exemplarily, the display substrate also includes a common electrode 81, which is located in the display area 10. The common signal line and the common electrode 81 are independent of each other in structure, but the two are electrically connected to each other, that is, the common signal line provides a common signal to the common electrode, so that a voltage difference is formed between the common electrode and the pixel electrode in the display area, which can drive the liquid crystal to rotate and realize the display function of the display panel.

[0083] Exemplarily, the common signal trace and the compensation scan line 20 are arranged in different layers, with an insulating layer provided between the common signal trace and the compensation scan line 20. The orthographic projection of the common signal trace on the substrate 82 at least partially overlaps with the orthographic projection of the compensation scan line 20 on the substrate 82, forming a compensation capacitor between the common signal trace and the compensation scan line 20, thereby compensating for the capacitive load of the compensation scan line 20. Moreover, the compensation scan line 20 extends along the profiled region 11, resulting in a longer length of the compensation scan line 20, thereby compensating for the resistive load of the compensation scan line 20. Therefore, the display substrate provided in the above embodiment achieves compensation for the resistive and capacitive load of the compensation scan line 20.

[0084] More specifically, in the first display area 101, along the extension direction of the non-compensated scan lines, the number of sub-pixels connected to the non-compensated scan lines is greater than the number of sub-pixels connected to the compensated scan lines in the second display area 102. A sub-pixel is defined by the intersection of a scan line and a data line. A sub-pixel includes its corresponding common electrode and pixel electrode, which together form a capacitor that drives liquid crystal rotation. Therefore, the corresponding capacitors driving liquid crystal rotation in the first display area 101 and the second display area 102 have different values. This means that the loads between the first display area 101 and the second display area 102 are inconsistent, resulting in an uneven display image. The present invention achieves a uniform display image by providing a compensation structure in the irregularly shaped area 11.

[0085] In the display substrate provided in the above embodiment, the common signal traces transmit common signals when the display substrate is in operation. These common signal traces can shield stray signals generated in the surrounding area during operation of the display substrate. Furthermore, they can form a compensation capacitor with the compensation scan line 20, thereby multiplexing the load compensation structure to compensate for the loading of the compensation scan line 20. Therefore, the display substrate provided in the above embodiment, by multiplexing the common signal traces into the load compensation structure, simplifies the structural complexity of the layout of the profiled area 11, thereby facilitating a reduction in the border width of the profiled area 11 of the display substrate.

[0086] In more detail, if Figure 11 As shown, a loading difference curve L4 between a compensated scan line 20 and a non-compensated scan line in an embodiment of the present invention is illustrated, and a loading difference curve L3 between two adjacent scan lines (which can be adjacent compensated scan lines 20 and non-compensated scan lines, or adjacent compensated scan lines 20) in an embodiment of the present invention is illustrated. Figure 11 The middle horizontal axis represents the row number of the second sub-pixel. Figure 11 A positive number indicated by the vertical axis indicates that the loading of the compensated scan line 20 after compensation is greater than the loading of the non-compensated scan line. Figure 11 The negative number indicated by the vertical axis represents that the loading of the compensated scan line 20 after compensation is less than the loading of the non-compensated scan line.

[0087] from Figure 11 It can be seen from the figure that the maximum loading difference between the compensation scan line 20 and the non-compensation scan line in the embodiment of the present invention can be controlled within 7%, and the loading difference between two adjacent scan lines in the embodiment of the present invention can be controlled within ±1%.

[0088] like Figures 2 to 5 As shown, in some embodiments, the common signal line is arranged around the display area 10, and the common signal line includes a compensation portion 401 and a non-compensation portion 402. The compensation portion 401 is located in the special-shaped area 11. In a direction perpendicular to the extension direction of the compensation portion 401, a minimum distance d1 between a boundary of the compensation portion 401 close to the display area 10 and a boundary of the compensation portion 401 far from the display area 10 is greater than a width d2 of the non-compensation portion 402 in a direction perpendicular to its own extension direction.

[0089] The orthographic projections of the compensation portion 401 on the substrate 82 of the display substrate at least partially overlap with the orthographic projections of the plurality of compensation scan lines 20 on the substrate 82 , and the compensation portion 401 is multiplexed as the load compensation structure.

[0090] Exemplarily, the compensation portion 401 and the non-compensation portion 402 are formed into an integral structure, and the compensation portion 401 and the non-compensation portion 402 are manufactured in the same layer.

[0091] Exemplarily, the compensation portion 401 is located in the profiled area 11 , and the non-compensation portion 402 includes a portion located in the profiled area 11 and a portion located in other areas of the peripheral area except the profiled area 11 .

[0092] Exemplarily, the compensation part 401 is reused as the load compensation structure, and the degree of compensation for the loading of the compensation scan line 20 is controlled by controlling the size of the overlapping area between the orthographic projection of the compensation part 401 on the substrate 82 and the orthographic projection of the compensation scan line 20 on the substrate 82.

[0093] The above arrangement is such that, in a direction perpendicular to the extension direction of the compensation portion 401, the minimum distance between the boundary of the compensation portion 401 close to the display area 10 and the boundary of the compensation portion 401 away from the display area 10 is greater than the width of the non-compensation portion 402 in a direction perpendicular to its own extension direction; this enables the compensation portion 401 to better compensate for the loading of the compensation scan line 20, and also enables the non-compensation portion 402 to minimize the border width occupied by itself while ensuring the shielding function, which is conducive to the narrow border of the display substrate.

[0094] In some embodiments, the compensation portion 401 is formed into a grid structure.

[0095] For example, when the display substrate and the opposing substrate are assembled to form a display panel, a frame sealant is formed between the display substrate and the opposing substrate, and the frame sealant is cured by irradiating the frame sealant with ultraviolet light so that the frame sealant bonds the frame of the display panel and the frame of the opposing substrate together.

[0096] Illustratively, the orthographic projection of the sealant on the substrate 82 at least partially overlaps with the orthographic projection of the compensation portion 401 on the substrate 82 .

[0097] The compensation portion 401 is formed into a grid structure, so that when the frame sealant is cured, ultraviolet light can better pass through the compensation portion 401 and irradiate the frame sealant, thereby better improving the curing effect of the frame sealant.

[0098] like Figures 2 to 5As shown, in some embodiments, the compensation portion 401 includes a first sub-portion 4011 and a second sub-portion 4012, wherein the first sub-portion 4011 is located between the display area 10 and the second sub-portion 4012; the first sub-portion 4011 includes a hollow area;

[0099] The special-shaped area 11 includes a bottom area 110 and a slope area 111. Along the direction of the slope area 111 pointing to the bottom area 110, in a direction perpendicular to the extension direction of the first sub-part 4011, the distance between the boundary of the first sub-part 4011 close to the display area 10 and the boundary of the first sub-part 4011 away from the display area 10 gradually decreases, and the width of the second sub-part 4012 in the direction perpendicular to its own extension direction gradually increases.

[0100] Illustratively, the first sub-portion 4011 and the second sub-portion 4012 are formed into an integral structure.

[0101] Exemplarily, the first sub-portion 4011 includes a hollow area, and the second sub-portion 4012 does not include a hollow area.

[0102] Illustratively, at least a portion of the first sub-portion 4011 is located between the display area 10 and the second sub-portion 4012 .

[0103] Exemplarily, the bottom area 110 is closer to the first display area 101 than the slope area 111 .

[0104] The above-mentioned setting is arranged along the direction of the slope area 111 pointing to the bottom area 110. In the direction perpendicular to the extension direction of the first sub-portion 4011, the distance between the boundary of the first sub-portion 4011 close to the display area 10 and the boundary of the first sub-portion 4011 away from the display area 10 gradually decreases, and the width of the second sub-portion 4012 in the direction perpendicular to its own extension direction gradually increases, which not only ensures the curing effect of the frame sealing glue, but also helps to compensate for the loading of the compensation scan line 20.

[0105] In more detail, the closer the compensation scan line 20 is to the first display area 101, the smaller the maximum compensation capacitance that can be formed between it and the compensation portion 401. Therefore, the above-mentioned setting can effectively improve the maximum capacitance compensation value of the compensation scan line 20 close to the first display area 101, thereby being more conducive to the loading uniformity of the scan lines in the display substrate.

[0106] In some embodiments, the display substrate includes multiple rows of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged sequentially along a first direction; the compensation scan line 20 is coupled to each sub-pixel included in a corresponding row of sub-pixels respectively;

[0107] The plurality of compensation scan lines 20 include a first compensation scan line to an Nth compensation scan line, the number of sub-pixels included in a row of sub-pixels corresponding to the Xth compensation scan line is less than the number of sub-pixels included in a row of sub-pixels corresponding to the X+1th compensation scan line, and 1≤X≤N-1;

[0108] The overlapping area between the orthographic projection of the Xth compensation scan line on the substrate 82 and the orthographic projection of the compensation part 401 on the substrate 82 is greater than the overlapping area between the orthographic projection of the X+1th compensation scan line on the substrate 82 and the orthographic projection of the compensation part 401 on the substrate 82.

[0109] Exemplarily, the first compensation scan line to the Nth compensation scan line are sequentially arranged along a direction close to the first display area 101. N is a positive integer.

[0110] Exemplarily, the number of sub-pixels included in a row of sub-pixels coupled to the Xth compensation scan line is less than the number of sub-pixels included in a row of sub-pixels coupled to the X+1th compensation scan line, and the length of the portion of the Xth compensation scan line located in the special-shaped area 11 is greater than the length of the portion of the X+1th compensation scan line located in the special-shaped area 11, so that the overlapping area between the orthographic projection of the Xth compensation scan line on the substrate 82 and the orthographic projection of the compensation portion 401 on the substrate 82 is greater than the overlapping area between the orthographic projection of the X+1th compensation scan line on the substrate 82 and the orthographic projection of the compensation portion 401 on the substrate 82.

[0111] Because the number of sub-pixels included in a row of sub-pixels corresponding to the Xth compensation scan line is smaller than the number of sub-pixels included in a row of sub-pixels corresponding to the X+1th compensation scan line, the loading of the Xth compensation scan line is smaller than the loading of the X+1th compensation scan line. Therefore, by setting the overlapping area between the orthographic projection of the Xth compensation scan line on the substrate 82 and the orthographic projection of the compensation portion 401 on the substrate 82 to be larger than the overlapping area between the orthographic projection of the X+1th compensation scan line on the substrate 82 and the orthographic projection of the compensation portion 401 on the substrate 82, the RC load compensated for the Xth compensation scan line is larger than the RC load compensated for the X+1th compensation scan line, thereby effectively ensuring the uniformity of the loading of the compensation scan lines.

[0112] like Figures 1 to 5As shown, in some embodiments, the display area 10 includes a first display area 101 and two second display areas 102, the first display area 101 is located on the same side of the two second display areas 102, and the special-shaped area 11 is located between the two display areas;

[0113] The multiple rows of sub-pixels include multiple rows of first sub-pixels and multiple rows of second sub-pixels, the multiple rows of first sub-pixels are located in the first display area 101, and among the multiple rows of second sub-pixels, a portion of the second sub-pixels in each row of second sub-pixels are located in one of the second display areas 102, and another portion of the second sub-pixels in each row of second sub-pixels are located in another second display area 102;

[0114] The plurality of compensation scan lines 20 correspond one-to-one to the plurality of rows of second sub-pixels, and the compensation scan lines 20 include a first line segment 201, a second line segment 202, and a third line segment 203 coupled in sequence. The first line segment 201 and the third line segment 203 each include at least a portion extending along the first direction, and the second line segment 202 extends along the boundary of the heteromorphic region 11.

[0115] It is set that the orthographic projection of the first line segment 201 on the substrate 82 at least partially overlaps with the orthographic projection of the compensation part 401 on the substrate 82, the orthographic projection of the second line segment 202 on the substrate 82 at least partially overlaps with the orthographic projection of the compensation part 401 on the substrate 82, and the orthographic projection of the third line segment on the substrate 82 at least partially overlaps with the orthographic projection of the compensation part 401 on the substrate 82.

[0116] Exemplarily, the first line segment 201 , the second line segment 202 and the third line segment form an integrated structure, and the first line segment 201 , the second line segment 202 and the third line segment are prepared in the same layer.

[0117] Illustratively, the extended shape of the second line segment 202 is substantially the same as the boundary shape of the profiled area 11 .

[0118] For example, the first line segment 201 and the corresponding row of second sub-pixels are located in one of the second display areas 102 (eg, located in Figure 2 The third line segment is coupled to each second sub-pixel in a corresponding row of second sub-pixels located in another second display area 102 (eg, located in Figure 2 Exemplarily, the first line segment 201, the second line segment 202 and the third line segment 203 belonging to the same compensation scan line 20 correspond to the second sub-pixels in the same row.

[0119] The above configuration can better perform loading compensation on the compensation scan line 20 .

[0120] In some embodiments, the display substrate further includes a plurality of non-compensation scan lines, at least a portion of the non-compensation scan lines being located in the first display area 101, the plurality of non-compensation scan lines corresponding one-to-one to the plurality of rows of first sub-pixels, and the non-compensation scan lines being coupled to each first sub-pixel in a corresponding row of first sub-pixels;

[0121] The compensation scan line 20 and the non-compensation scan line are disposed on the same layer, and the common signal line and the data line 30 are disposed on the same layer.

[0122] Exemplarily, the non-compensated scan line includes at least a portion extending along the first direction.

[0123] Exemplarily, the compensation scan line 20 and the non-compensation scan line are provided in the same layer and material, and the common signal line and the data line 30 are provided in the same layer and material.

[0124] Exemplarily, the compensation scan line 20 and the non-compensation scan line are made of a first gate metal layer, and the common signal line and the data line 30 are made of a first source / drain metal layer.

[0125] The above arrangement enables the compensation scan line 20 and the non-compensation scan line to be formed in the same patterning process, and the common signal line and the data line 30 to be formed in the same patterning process, which is beneficial to simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0126] like Figure 12 As shown, in some embodiments, the non-compensation part 402 includes a first non-compensation part 4021 and a second non-compensation part 4022, the display area 10 is located between the first non-compensation part 4021 and the second non-compensation part 4022, the first end of the first non-compensation part 4021 is coupled to the first end of the compensation part 401, the second end of the first non-compensation part 4021 is located in the binding area 12, the first end of the second non-compensation part 4022 is coupled to the second end of the compensation part 401, and the second end of the second non-compensation part 4022 is located in the binding area 12.

[0127] Need to explain, Figure 12 The surrounding area 13 is also indicated.

[0128] Illustratively, the first non-compensation part 4021 , the compensation part 401 and the second non-compensation part 4022 are coupled in sequence.

[0129] Exemplarily, a driver chip is bound to the binding area 12 , and the second end of the first non-compensation portion 4021 and the second end of the second non-compensation portion 4022 are respectively coupled to the driver chip.

[0130] The above-mentioned setting method enables the first non-compensation part, the compensation part 401 and the second non-compensation part to be arranged around the display area 10. When the display substrate is in an operating state, the common signal line composed of the first non-compensation part, the compensation part 401 and the second non-compensation part and the common electrode 81 in the display substrate are loaded with the same common signal, which is beneficial to improving the stability of the operation of the display substrate.

[0131] like Figure 3 As shown, in some embodiments, the display substrate further includes a shielding line 50 , which is located in the peripheral area. The shielding line 50 is arranged around the display area 10 , and the common signal line is located between the display area 10 and the shielding line 50 .

[0132] Exemplarily, both ends of the shielding line 50 are respectively coupled to the driving chip, and the driving chip provides a GND signal for the shielding line 50 .

[0133] The display substrate is configured to include the shielding line 50 , so that the shielding line 50 can shield the crosstalk signal around the display substrate.

[0134] like Figures 6 to 8 As shown, in some embodiments, the electrostatic discharge circuit includes a plurality of electrostatic discharge sub-circuits 601, and the plurality of electrostatic discharge sub-circuits 601 correspond one-to-one to the plurality of data lines 30;

[0135] The electrostatic release sub-circuit 601 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is coupled to the input electrode of the first transistor T1, the input electrode of the first transistor T1 is coupled to the input electrode of the second transistor T2, the output electrode of the first transistor T1 is coupled to the output electrode of the second transistor T2, and the gate of the second transistor T2 is coupled to the output electrode of the second transistor T2; the input electrode of the first transistor T1 is coupled to the corresponding data line 30, and the output electrode of the first transistor T1 is coupled to the common signal line.

[0136] Exemplarily, the electrostatic discharge sub-circuit 601 can discharge the electrostatic charge on the corresponding coupled data line 30 to the common signal line through the first transistor T1 and the second transistor T2 .

[0137] In the display substrate provided by the above embodiment, the electrostatic discharge circuit is provided to release the static charge on the data line 30 to the common signal line, which is beneficial to the working stability of the display substrate.

[0138] like Figures 6 to 8 As shown, in some embodiments, the input electrode of the first transistor T1, the input electrode of the second transistor T2 and the corresponding data line 30 form an integrated structure.

[0139] Need to explain, Figure 7 The dotted frame in the convex shape represents the gates of the two second transistors T2. Figure 7 The dotted boxes above and below the convex dotted box are both gates of the first transistor T1. Figure 7 Schematically shows a first active layer 91 included in the first transistor T1 and a second active layer 92 included in the second transistor T2.

[0140] See also Figures 13 to 16 , Figure 13 A schematic diagram of coupling multiple electrostatic discharge sub-circuits and data lines provided by an embodiment of the present invention; Figure 14 for Figure 13 Schematic diagram of the layout of the middle gate metal layer, active layer, and source and drain metal layer; Figure 15 for Figure 13 Schematic diagram of the layout of the source and drain metal layer; Figure 16 for Figure 13 Schematic diagram of the layout of the indium tin oxide layer.

[0141] Figure 14 Schematically shows an input electrode 93 of the first transistor T1 , an output electrode 94 of the first transistor T1 , an input electrode 95 of the second transistor T2 , and an output electrode 96 of the second transistor T2 .

[0142] like Figure 14 and Figure 15 As shown, the output electrode 94 of the first transistor T1 and the output electrode 96 of the second transistor T2 are coupled via a first conductive connection portion 97 .

[0143] like Figure 7 , Figures 13 to 16 As shown, the first conductive connection portion 97 is coupled to the second conductive connection portion 982 through a via hole, and the second conductive connection portion 982 is coupled to the gate of the second transistor T2 through a via hole. The third conductive connection portion 981 is coupled to the gate of the first transistor T1 and the data line 30 through via holes.

[0144] Exemplarily, in the same electrostatic discharge sub-circuit 601, the first transistor T1 and the second transistor T2 are arranged along the extension direction of the data line 30, with the input electrode of the first transistor T1 and the input electrode of the second transistor T2 located on the same side. The output electrode of the first transistor T1 and the output electrode of the second transistor T2 form an integral structure. The output electrode of the first transistor T1 and the output electrode of the second transistor T2 are coupled to the gate of the second transistor T2 via a conductive connection pattern. The conductive connection pattern is made of indium tin oxide and can be formed in the same patterning process as the electrode layer made of indium tin oxide in the display substrate. The orthographic projection of the conductive connection pattern on the substrate 82 overlaps with the orthographic projection of the gate of the second transistor T2 on the substrate 82, and the conductive connection pattern and the gate of the second transistor T2 are coupled via a via. The orthographic projection of the conductive connection pattern on the substrate 82 overlaps with the orthographic projection of the output electrode of the first transistor T1 on the substrate 82, and the conductive connection pattern and the output electrode of the first transistor T1 are coupled via a via.

[0145] The above arrangement enables the input electrode of the first transistor T1, the input electrode of the second transistor T2, and the corresponding data line 30 to be formed simultaneously in the same patterning process, so that the input electrode of the first transistor T1, the input electrode of the second transistor T2, and the corresponding data line 30 can be directly connected without the need for via bridging. This not only reduces the difficulty of coupling between the electrostatic discharge circuit and the data line 30, but also shortens the distance between the electrostatic discharge circuit and the data line 30, reducing the overall layout space occupied by the electrostatic discharge circuit and the coupled data line 30, which is conducive to the narrow frame of the display substrate on the side of the special-shaped area 11.

[0146] like Figure 3 , Figure 4 , Figures 6 to 8 As shown, in some embodiments, the multiple electrostatic release sub-circuits 601 are divided into multiple electrostatic release sub-circuit groups 60, and the multiple electrostatic release sub-circuit groups 60 are arranged in sequence in the special-shaped area 11, each electrostatic release sub-circuit group 60 includes at least two electrostatic release sub-circuits 601, and the gates of the second transistors T2 included in each electrostatic release sub-circuit group 60 are formed into an integrated structure.

[0147] like Figure 4 As shown, Figure 4 7 complete electrostatic discharge sub-circuit groups 60 are shown, and Figure 4 An incomplete set of electrostatic discharge sub-circuit groups 60 is shown in the upper left corner.

[0148] Exemplarily, the at least two electrostatic discharge sub-circuits 601 included in each electrostatic discharge sub-circuit group 60 are arranged along the first direction.

[0149] Illustratively, the number of electrostatic discharge sub-circuits 601 included in each electrostatic discharge sub-circuit group 60 may be the same or different.

[0150] Exemplarily, in each electrostatic discharge sub-circuit group 60 , the output electrodes of some adjacent second transistors T2 are formed into an integrated structure.

[0151] Exemplarily, two adjacent electrostatic discharge sub-circuit groups 60 are staggered along the extending direction of the data line 30 .

[0152] In the display substrate provided by the above embodiment, by dividing the multiple electrostatic release sub-circuits 601 into multiple groups of electrostatic release sub-circuit groups 60, not only can the layout space occupied by the electrostatic release circuit be effectively reduced, but also the layout difficulty of the electrostatic release sub-circuit 601 in the special-shaped area 11 can be reduced, so that the layout of the electrostatic release circuit can better match the shape of the special-shaped area 11.

[0153] The gates of the second transistors T2 included in each electrostatic release sub-circuit group 60 are formed into an integrated structure, which can better achieve electrical connection between the second transistors T2 included in each electrostatic release sub-circuit group 60 and the common signal wiring.

[0154] like Figure 4 As shown, in some embodiments, the multiple compensation scan lines 20 are divided into multiple compensation scan line groups 2, each compensation scan line group 2 includes at least two adjacent compensation scan lines 20, and at least part of the electrostatic release sub-circuit group 60 is located between adjacent compensation scan line groups 2.

[0155] Exemplarily, the profiled region 11 includes a bottom region 110, a first slope region, and a second slope region, with the bottom region 110 located between the first and second slope regions. In the first slope region, the electrostatic discharge sub-circuit groups 60 and the compensation scan line groups 2 are alternately arranged. In the second slope region, the electrostatic discharge sub-circuit groups 60 and the compensation scan line groups 2 are alternately arranged.

[0156] The above configuration more reasonably arranges the compensation scanning line 20 and the electrostatic discharge circuit, fully utilizes the layout space of the special-shaped area 11 , and is conducive to narrowing the frame of the display substrate in the special-shaped area 11 .

[0157] An embodiment of the present invention further provides a display panel, comprising the display substrate provided in the above embodiment, wherein the display panel further comprises an opposing substrate; the opposing substrate is disposed opposite to the display substrate; the opposing substrate comprises:

[0158] like Figure 9 and Figure 10 As shown, the black matrix layer BM includes a display area pattern BM1 and a non-display area pattern BM2. The orthographic projection of the display area pattern BM1 on the display substrate is located in the display area 10 of the display substrate, and the orthographic projection of the non-display area pattern BM2 on the display substrate is located in the peripheral area of the display substrate; there is a black matrix hollowing area BM0 between the display area pattern BM1 and the non-display area pattern BM2.

[0159] Exemplarily, the opposite substrate includes a color filter substrate. The opposite substrate includes a base 83 .

[0160] Exemplarily, the display panel further includes a liquid crystal layer 84 , and the liquid crystal layer 84 is located between the display substrate and the opposite substrate.

[0161] Exemplarily, the display panel includes an organic light emitting diode display panel.

[0162] Exemplarily, the display area graphic BM1 and the non-display area graphic BM2 are independent of each other.

[0163] The above-mentioned arrangement of a black matrix hollowing area BM0 between the display area pattern BM1 and the non-display area pattern BM2 can effectively prevent electrostatic damage and well ensure the yield of the display panel.

[0164] In the display substrate provided by the above embodiment, the electrostatic discharge circuit and the load compensation structure are both arranged in the profiled area 11, and the electrostatic discharge circuit is arranged between the display area 10 and the load compensation structure. Since the electrostatic discharge circuit is arranged close to the display area and there is no other structure between the electrostatic discharge circuit and the display area 10, the electrostatic discharge circuit can be close to the data line 30 to which it is coupled. This not only reduces the difficulty of coupling between the electrostatic discharge circuit and the data line 30, but also reduces the distance between the electrostatic discharge circuit and the data line 30, reducing the overall layout space occupied by the electrostatic discharge circuit and the data line 30 to which it is coupled, which is conducive to the narrow frame of the display substrate on the side of the profiled area 11. Moreover, in the display substrate provided by the above embodiment, the electrostatic discharge circuit originally arranged on the lower frame of the display substrate is moved to the profiled area 11, effectively reducing the width of the lower frame of the display substrate. At the same time, when the electrostatic discharge circuit is moved to the profiled area 11, some structures in the profiled area 11 can be removed, and the space originally used for the layout of the electrostatic discharge circuit can be used to layout the electrostatic discharge circuit. Therefore, even if the electrostatic discharge circuit is moved to the profiled area 11, there is no need to increase the border width of the display substrate in the profiled area 11. In addition, the load compensation structure can compensate for the loading of the compensation scan line 20, reducing the loading difference between the compensation scan line 20 and the non-compensation scan line, better ensuring the loading uniformity of the compensation scan line 20 and the non-compensation scan line, and effectively improving the display quality of the display substrate.

[0165] Therefore, the display panel provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0166] like Figure 3 , Figure 9 and Figure 10 As shown, in some embodiments, the electrostatic release circuit in the display substrate is located between the orthographic projection of the load compensation structure in the display substrate on the substrate 82 and the orthographic projection of the black matrix hollow area BM0 on the substrate 82. The black matrix hollow area BM0 is provided here to prevent static electricity from entering BM1 through BM2, thereby affecting the display.

[0167] like Figure 9 As shown, the black matrix hollow area BM0 is in a broken line shape, and the shape of the black matrix hollow area BM0 matches the boundary shape of the display area.

[0168] The above configuration more reasonably arranges the load compensation structure and the electrostatic discharge circuit, fully utilizes the layout space of the special-shaped area 11 , and is conducive to narrowing the frame of the display substrate in the special-shaped area 11 .

[0169] In some embodiments, the counter substrate further includes a supporting layer, and at least a portion of the supporting layer is located in the black matrix hollowing area BM0.

[0170] Exemplarily, the supporting layer fills the black matrix hollow area BM0 to compensate for the step difference of the black matrix hollow area BM0.

[0171] The exemplary support layer is placed on the display area pattern BM1 and the non-display area pattern BM2 on both sides of the black matrix hollow area BM0.

[0172] The above arrangement better supports the opposite substrate, which is beneficial to the yield of the display panel.

[0173] like Figure 10 As shown, in some embodiments, the support layer includes a blue color resist pattern 80 , and the blue color resist pattern 80 includes a portion located in the black matrix hollow area BM0 and a portion located around the black matrix hollow area BM0 .

[0174] Since the human eye is not sensitive to blue, the support layer is provided with a blue color resist pattern 80, which not only ensures the supporting function, but also ensures that even if light leakage occurs in the black matrix hollow area BM0, the light leakage phenomenon will not be very obvious, that is, the light leakage is improved while the overall display is made uniform.

[0175] In some embodiments, the display panel further includes a frame-sealing glue, which is located between the display substrate and the opposing substrate. The orthographic projection of the frame-sealing glue on the display substrate is located in the peripheral area of the display substrate. The orthographic projection of the frame-sealing glue on the substrate 82 at least partially overlaps with the orthographic projection of the hollow area included in the common signal line in the display substrate on the substrate 82.

[0176] For example, when the display substrate and the opposing substrate are assembled to form a display panel, a frame sealant is formed between the display substrate and the opposing substrate, and the frame sealant is cured by irradiating the frame sealant with ultraviolet light so that the frame sealant bonds the frame of the display panel and the frame of the opposing substrate together.

[0177] Illustratively, the orthographic projection of the sealant on the substrate 82 at least partially overlaps with the orthographic projection of the compensation portion 401 on the substrate 82 .

[0178] Exemplarily, the orthographic projection of the frame sealing adhesive on the substrate 82 completely covers the common signal traces.

[0179] The orthographic projection of the frame-sealing adhesive on the substrate 82 is at least partially overlapped with the orthographic projection of the hollow area included in the common signal wiring in the display substrate on the substrate 82, so that when the frame-sealing adhesive is cured, ultraviolet light can better pass through the compensation portion 401 and irradiate the frame-sealing adhesive, thereby better improving the curing effect of the frame-sealing adhesive.

[0180] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0181] The display panel provided in the above embodiment includes a black matrix hollowed-out area BM0 between the display area pattern BM1 and the non-display area pattern BM2, effectively preventing electrostatic damage and effectively ensuring the yield of the display panel. In the display panel provided in the above embodiment, the electrostatic discharge circuit and the load compensation structure are both located in the profiled area 11, with the electrostatic discharge circuit located between the display area 10 and the load compensation structure. Because the electrostatic discharge circuit is located close to the display area and there are no other structures between the electrostatic discharge circuit and the display area 10, the electrostatic discharge circuit can be located in close proximity to the data lines 30 to which it is coupled. This not only reduces the difficulty of coupling between the electrostatic discharge circuit and the data lines 30, but also reduces the distance between the electrostatic discharge circuit and the data lines 30, reducing the overall layout space occupied by the electrostatic discharge circuit and the coupled data lines 30, thereby facilitating a narrower bezel on the display substrate side of the profiled area 11. Furthermore, in the display panel provided in the above embodiment, the electrostatic discharge circuit, originally located on the lower bezel of the display substrate, is moved to the profiled area 11, effectively reducing the width of the lower bezel of the display substrate. At the same time, when the electrostatic discharge circuit is moved to the profiled area 11, some structures in the profiled area 11 can be removed, and the space originally used for the layout of the electrostatic discharge circuit can be used to layout the electrostatic discharge circuit. Therefore, even if the electrostatic discharge circuit is moved to the profiled area 11, there is no need to increase the border width of the display substrate in the profiled area 11. In addition, the load compensation structure can compensate for the loading of the compensation scan line 20, reducing the loading difference between the compensation scan line 20 and the non-compensation scan line, better ensuring the loading uniformity of the compensation scan line 20 and the non-compensation scan line, and effectively improving the display quality of the display substrate.

[0182] Therefore, the display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display panel, which will not be described in detail here.

[0183] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0184] It should be noted that in the embodiments of the present invention, "the same layer" may refer to film layers on the same structural layer. Alternatively, for example, the film layers on the same layer may be formed using the same film-forming process to form a specific pattern, and then patterned using the same mask through a single patterning process to form the film layer. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0185] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present invention.

[0186] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0187] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0188] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0189] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0190] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: a display area and a peripheral area surrounding the display area, the peripheral area including a binding area and a profiled area, at least a portion of the display area being located between the binding area and the profiled area; The display substrate further includes a plurality of compensation scan lines and a plurality of data lines, wherein the compensation scan lines include a portion located in the special-shaped area, and the data lines include a portion located in the display area and a portion located in the special-shaped area; The special-shaped area includes: an electrostatic discharge circuit and a load compensation structure, at least a portion of the electrostatic discharge circuit is located between the display area and the load compensation structure; The electrostatic discharge circuits are respectively coupled to the plurality of data lines; portions of the data lines located in the irregularly shaped area are coupled to the electrostatic discharge circuits; The electrostatic release circuit includes multiple electrostatic release sub-circuits, which are divided into multiple electrostatic release sub-circuit groups. The multiple compensation scan lines are divided into multiple compensation scan line groups. At least some of the electrostatic release sub-circuit groups are located between adjacent compensation scan line groups.

2. The display substrate according to claim 1, wherein: The display substrate further includes a common signal line, the orthographic projection of the common signal line on the substrate of the display substrate at least partially overlaps with the orthographic projections of the plurality of compensation scan lines on the substrate, and the common signal line is multiplexed into the load compensation structure.

3. The display substrate according to claim 2, wherein: The common signal line is arranged around the display area, and the common signal line includes a compensation portion and a non-compensation portion. The compensation portion is located in the special-shaped area, and in a direction perpendicular to the extension direction of the compensation portion, the minimum distance between the boundary of the compensation portion close to the display area and the boundary of the compensation portion far from the display area is greater than the width of the non-compensation portion in the direction perpendicular to the extension direction of the non-compensation portion. The orthographic projections of the compensation portion on the substrate of the display substrate at least partially overlap with the orthographic projections of the plurality of compensation scanning lines on the substrate, and the compensation portion is multiplexed into the load compensation structure.

4. The display substrate according to claim 3, wherein: The compensating portion is formed in a grid structure.

5. The display substrate according to claim 3, wherein: The compensation portion includes a first sub-portion and a second sub-portion, the first sub-portion is located between the display area and the second sub-portion; the first sub-portion includes a hollow area; The special-shaped area includes a bottom area and a slope area. Along the direction from the slope area to the bottom area, in a direction perpendicular to the extension direction of the first sub-part, the distance between the boundary of the first sub-part close to the display area and the boundary of the first sub-part away from the display area gradually decreases, and the width of the second sub-part in a direction perpendicular to its own extension direction gradually increases.

6. The display substrate according to claim 3, wherein: The display substrate includes a plurality of rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along a first direction; the compensation scan line is coupled to each sub-pixel included in a corresponding row of sub-pixels respectively; The plurality of compensation scan lines include a first compensation scan line to an Nth compensation scan line, the number of sub-pixels included in a row of sub-pixels corresponding to the Xth compensation scan line is less than the number of sub-pixels included in a row of sub-pixels corresponding to the X+1th compensation scan line, and 1≤X≤N-1; An overlapping area between an orthographic projection of the Xth compensation scan line on the substrate and an orthographic projection of the compensation portion on the substrate is greater than an overlapping area between an orthographic projection of the X+1th compensation scan line on the substrate and an orthographic projection of the compensation portion on the substrate.

7. The display substrate according to claim 6, wherein: The display area includes a first display area and two second display areas, the first display area is located on the same side of the two second display areas, and the special-shaped area is located between the two display areas; The multiple rows of sub-pixels include multiple rows of first sub-pixels and multiple rows of second sub-pixels, the multiple rows of first sub-pixels are located in the first display area, and among the multiple rows of second sub-pixels, a portion of the second sub-pixels in each row of second sub-pixels are located in one of the second display areas, and another portion of the second sub-pixels in each row of second sub-pixels are located in another second display area; The plurality of compensation scan lines correspond one-to-one to the plurality of rows of second sub-pixels, the compensation scan lines comprising a first line segment, a second line segment, and a third line segment coupled in sequence, the first line segment and the third line segment each including at least a portion extending along the first direction, and the second line segment extending along a boundary of the heteromorphic region; The orthographic projection of the first line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate, the orthographic projection of the second line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate, and the orthographic projection of the third line segment on the substrate at least partially overlaps with the orthographic projection of the compensation part on the substrate.

8. The display substrate according to claim 7, wherein: The display substrate further includes a plurality of non-compensation scan lines, at least a portion of the non-compensation scan lines being located in the first display area, the plurality of non-compensation scan lines corresponding one-to-one to the plurality of rows of first sub-pixels, and the non-compensation scan lines being coupled to each first sub-pixel in a corresponding row of first sub-pixels; The compensation scan line and the non-compensation scan line are arranged on the same layer, and the common signal line and the data line are arranged on the same layer.

9. The display substrate according to claim 3, wherein: The non-compensating part includes a first non-compensating part and a second non-compensating part, the display area is located between the first non-compensating part and the second non-compensating part, the first end of the first non-compensating part is coupled to the first end of the compensating part, the second end of the first non-compensating part is located in the binding area, the first end of the second non-compensating part is coupled to the second end of the compensating part, and the second end of the second non-compensating part is located in the binding area.

10. The display substrate according to claim 9, wherein: The display substrate further includes a shielding line, which is located in the peripheral area and arranged around the display area. The common signal line is located between the display area and the shielding line.

11. The display substrate according to claim 2, wherein: The multiple electrostatic discharge sub-circuits correspond one-to-one to the multiple data lines; The electrostatic release sub-circuit includes a first transistor and a second transistor, the gate of the first transistor is coupled to the input electrode of the first transistor, the input electrode of the first transistor is coupled to the input electrode of the second transistor, the output electrode of the first transistor is coupled to the output electrode of the second transistor, and the gate of the second transistor is coupled to the output electrode of the second transistor; the input electrode of the first transistor is coupled to the corresponding data line.

12. The display substrate according to claim 11, wherein: The input electrode of the first transistor, the input electrode of the second transistor and the corresponding data line form an integrated structure.

13. The display substrate according to claim 11, wherein: The multiple electrostatic release sub-circuit groups are arranged in sequence in the special-shaped area, each electrostatic release sub-circuit group includes at least two electrostatic release sub-circuits, and the gates of the second transistors included in each electrostatic release sub-circuit group form an integrated structure.

14. The display substrate according to claim 13, wherein: Each compensation scan line group includes at least two adjacent compensation scan lines.

15. A display panel, characterized in that: The display panel comprises a display substrate according to any one of claims 1 to 14, wherein the display panel further comprises an opposite substrate; the opposite substrate is arranged opposite to the display substrate; the opposite substrate comprises: A black matrix layer, the black matrix layer including a display area pattern and a non-display area pattern, the orthographic projection of the display area pattern on the display substrate being located in the display area of the display substrate, and the orthographic projection of the non-display area pattern on the display substrate being located in the peripheral area of the display substrate; a black matrix hollowed-out area is provided between the display area pattern and the non-display area pattern.

16. The display panel according to claim 15, wherein: The orthographic projection of the electrostatic discharge circuit in the display substrate on the substrate of the display substrate is located between the orthographic projection of the load compensation structure in the display substrate on the substrate and the orthographic projection of the black matrix hollowing area on the substrate.

17. The display panel according to claim 15, wherein: The opposite substrate further includes a supporting layer, at least a portion of which is located in the black matrix hollowing area.

18. The display panel according to claim 17, wherein: The supporting layer includes a blue color resist pattern, and the blue color resist pattern includes a portion located in the black matrix hollow area and a portion located around the black matrix hollow area.

19. The display panel according to claim 17, wherein: The display panel also includes a frame sealant, which is located between the display substrate and the opposing substrate. The orthographic projection of the frame sealant on the display substrate is located in a peripheral area of the display substrate. The orthographic projection of the frame sealant on the substrate of the display panel at least partially overlaps with the orthographic projection of the hollow area included in the common signal line in the display substrate on the substrate.

20. A display device, characterized in that: The device comprises the display panel according to any one of claims 15 to 19.

Images