Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel has a display area and a non-display area that at least partially surrounds the display area. The display panel includes: a pixel circuit and a light-emitting element located in the display area, wherein the first electrode of the light-emitting element is electrically connected to the pixel circuit, and the pixel circuit includes a driving transistor; a first reset bus located in the non-display area and electrically connected to the driving transistor; a second reset bus located in the non-display area and electrically connected to the first electrode of the light-emitting element; the orthographic projection of the first reset bus on the plane where the display panel is located at least partially overlaps with the orthographic projection of the second reset bus on the plane where the display panel is located. The display panel and the display device provided according to the embodiments of the present application are conducive to achieving a narrow frame.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous advancement of display panel technology, display panels are gradually developing towards being thinner and lighter, with a high screen-to-body ratio and ultra-narrow bezels. Display panels generally include a display area and a non-display area surrounding the display area, where the non-display area is used to arrange signal lines.

[0003] In pursuit of higher display quality, the number of signal lines in the non-display area increases, which is not conducive to achieving a narrow frame. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device, which are conducive to achieving a narrow frame.

[0005] In a first aspect, an embodiment of the present application provides a display panel having a display area and a non-display area that at least partially surrounds the display area, the display panel including: a pixel circuit and a light-emitting element, located in the display area, the first electrode of the light-emitting element being electrically connected to the pixel circuit, the pixel circuit including a driving transistor; a first reset bus, located in the non-display area, being electrically connected to the driving transistor; a second reset bus, located in the non-display area, being electrically connected to the first electrode of the light-emitting element; the orthographic projection of the first reset bus on the plane where the display panel is located at least partially overlaps with the orthographic projection of the second reset bus on the plane where the display panel is located.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel as described in the embodiment of the first aspect.

[0007] According to the display panel and display device provided by the embodiments of the present application, the driving transistor and the light-emitting element are respectively connected to different reset buses, and then different reset signals can be used to reset the driving transistor and the light-emitting element respectively. This can improve the control flexibility, help reduce power consumption, increase the brightness of the first frame, and improve the short-term ghosting of the display panel. The first reset bus and the second reset bus at least partially overlap, and relative to the two being located in the same film layer, the width of the border occupied by the two can be reduced, which is conducive to a narrow border. Therefore, the display panel provided by the embodiments of the present application can take into account both a narrow border and display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1A schematic diagram showing a top view of a display panel provided by an embodiment of the present application is shown;

[0010] Figure 2 A schematic diagram showing the circuit structure of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0011] Figure 3 A schematic diagram showing the circuit structure of a pixel circuit in a display panel provided by another embodiment of the present application is shown;

[0012] Figure 4 Show Figure 1 A local enlarged schematic diagram of the middle Q region;

[0013] Figure 5 Show Figure 4 A schematic diagram of a cross-sectional structure in the AA direction;

[0014] Figure 6 Show Figure 1 A schematic diagram of a cross-sectional structure in the middle BB direction;

[0015] Figure 7 Show Figure 1 Schematic diagram of another cross-sectional structure in the middle BB direction;

[0016] Figure 8 Show Figure 1 Another cross-sectional structure diagram in the middle BB direction;

[0017] Figure 9 Show Figure 1 Another cross-sectional structure diagram in the middle BB direction;

[0018] Figure 10 Show Figure 1 Another cross-sectional structure diagram in the middle BB direction;

[0019] Figure 11 Show Figure 1 Another cross-sectional structure diagram in the middle BB direction;

[0020] Figure 12 A schematic diagram of a wiring structure in a display panel provided by an embodiment of the present application is shown;

[0021] Figure 13 A schematic diagram showing another wiring structure in a display panel provided by an embodiment of the present application is shown;

[0022] Figure 14 A schematic diagram of the top view of the display device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0025] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0026] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0027] It should be noted that, when an element is described as being “connected” or “electrically connected” to another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0028] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0029] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0030] A pixel circuit and a light-emitting element may be provided in the display panel. The pixel circuit may include a driving transistor. The driving transistor may generate a driving current to drive the light-emitting element to emit light.

[0031] The inventors have discovered that a dual reset signal line setting method can be used, and different reset signals can be used to reset the driving transistor and the light-emitting element respectively. This can improve control flexibility, help reduce power consumption, increase the brightness of the first frame, and improve short-term ghosting of the display panel.

[0032] However, the dual reset signal line configuration increases the border width occupied by the signal line, which is not conducive to achieving a narrow border. If the border width is not increased and the signal line width within the border area is compressed, the impedance of the signal line will increase, affecting the display quality.

[0033] Therefore, how to strike a balance between narrow bezel and display quality has become a difficult problem faced by those skilled in the art.

[0034] In order to solve the above technical problems, embodiments of the present application provide a display panel and a display device. Various embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the display panel 100 may include a display area AA and a non-display area NA at least partially surrounding the display area AA.

[0036] The display panel 100 may include a first reset bus 11 and a second reset bus 12, as well as a plurality of pixel circuits 21 and light-emitting elements 22 electrically connected to the pixel circuits 21. The pixel circuits 21 may be configured to generate a driving current to drive the light-emitting elements 22 to emit light. The light-emitting elements may include organic light-emitting diodes (OLEDs).

[0037] The pixel circuit 21 and the light emitting element 22 are located in the display area AA. Figure 2 or Figure 3As shown, the light-emitting element 22 may include a first electrode and a second electrode. The first electrode of the light-emitting element 22 is electrically connected to the pixel circuit 21. The pixel circuit 21 may include a driving transistor T1. For example, the first electrode of the driving transistor T1 may be electrically connected to the first power supply terminal PVDD, and the second electrode of the driving transistor T1 may be electrically connected to the first electrode of the light-emitting element 22. The second electrode of the light-emitting element 22 is electrically connected to the second power supply terminal PVEE. The first power supply terminal PVDD can be used to provide a positive voltage signal, and the second power supply terminal PVEE can be used to provide a negative voltage signal.

[0038] The first reset bus 11 and the second reset bus 12 are located in the non-display area NA. The first reset bus 11 is electrically connected to the driving transistor T1. For example, the first reset bus 11 is electrically connected to the gate of the driving transistor T1, and the reset signal on the first reset bus 11 can reset the gate of the driving transistor T1. The second reset bus 12 is electrically connected to the first electrode of the light-emitting element 22. The signal on the second reset bus 12 can reset the first electrode of the light-emitting element 22. In this way, different reset signals can be used to reset the driving transistor and the light-emitting element respectively, which can improve control flexibility, help reduce power consumption, improve the brightness of the first frame, and improve problems such as short-term image sticking of the display panel.

[0039] Figure 1 The diagram illustrates that the first reset bus 11 and the second reset bus 12 are distributed in the non-display area NA on both sides of the display area AA in the first direction X. This is not intended to limit the present application. For example, the first reset bus 11 and the second reset bus 12 may be provided only in the non-display area NA on one side of the display area AA in the first direction X, or the first reset bus 11 may be provided in the non-display area NA on one side of the display area AA in the first direction X, and the second reset bus 12 may be provided in the non-display area NA on the other side.

[0040] like Figure 4 and Figure 5 As shown, the orthographic projection of the first reset bus 11 on the display panel plane at least partially overlaps with the orthographic projection of the second reset bus 12 on the display panel plane. It is understandable that the first reset bus 11 and the second reset bus 12 are located in different film layers.

[0041] According to the display panel provided by the embodiment of the present application, the driving transistor and the light-emitting element are respectively connected to different reset buses, and different reset signals can be used to reset the driving transistor and the light-emitting element respectively. This can improve the control flexibility, help reduce power consumption, increase the brightness of the first frame, and improve the short-term ghosting problem of the display panel. The first reset bus 11 and the second reset bus 12 at least partially overlap, and relative to the two being located in the same film layer, the width of the border occupied by the two can be reduced, which is conducive to a narrow border. Therefore, the display panel provided by the embodiment of the present application can take into account both a narrow border and display quality.

[0042] For example, in the first direction X, within the non-display area NA on at least one side of the display area AA, the orthographic projection of the first reset bus 11 on the plane where the display panel is located can overlap with the orthographic projection of the second reset bus 12 on the plane where the display panel is located. This can further reduce the width of the border occupied by the two, which is more conducive to achieving a narrow border.

[0043] For example, Figure 1 As shown, the display area AA of the display panel 100 may include a first connection line 31 and a second connection line 32. Figure 2 or Figure 3 As shown, the pixel circuit may include a fourth transistor T4 and a seventh transistor T7.

[0044] The first connection line 31 can be connected between the first reset bus 11 and the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 is connected to the gate of the driving transistor T1. When the fourth transistor T4 is turned on, the reset signal on the first reset bus 11 can be transmitted to the gate of the driving transistor T1.

[0045] The second connection line 32 can be connected between the second reset bus 12 and the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element 22. When the seventh transistor T7 is turned on, the signal on the second reset bus 12 can be transmitted to the first electrode of the light-emitting element 22.

[0046] One end of the first reset bus 11 can be electrically connected to the first reset signal terminal V1, and one end of the second reset bus 12 can be electrically connected to the second reset signal terminal V2. The first reset signal terminal V1 can be used to provide a first reset signal Vref1, and the second reset signal terminal V2 can be used to provide a second reset signal Vref2. The first reset signal Vref1 and the second reset signal Vref2 can be negative voltage signals. The amplitudes of the first reset signal Vref1 and the second reset signal Vref2 can be different.

[0047] Exemplarily, the non-display area NA of the display panel may include a binding area BA, and the first reset signal terminal V1 and the second reset signal terminal V2 may be located in the binding area BA.

[0048] like Figure 2 or Figure 3 As shown, the pixel circuit may further include a second transistor T2, a third transistor T3, a fifth transistor T5, and a sixth transistor T6. The connection relationship of each transistor can be seen in Figure 2 or Figure 3 , I will not go into details here.

[0049] It should be noted that the transistors of the pixel circuit can be P-type transistors or N-type transistors. When the signal received by the gate of the P-type transistor is a low level, the P-type transistor is turned on; when the signal received by the gate of the P-type transistor is a high level, the P-type transistor is turned off. When the signal received by the gate of the N-type transistor is a high level, the N-type transistor is turned on; when the signal received by the gate of the N-type transistor is a low level, the N-type transistor is turned off.

[0050] like Figure 2 As shown, transistors T1 to T7 can all be P-type transistors. Alternatively, Figure 3 As shown, the third transistor T3 and the fourth transistor T4 are N-type transistors, and the other transistors are P-type transistors.

[0051] In addition, S1, S2, S3, S1N, S2N, and S1P represent scan lines, and EM represents a light-emission control signal line. When the signals on the scan lines S1, S2, S3, S1P, and the light-emission control signal line EM are low, the transistors connected thereto are turned on. When the signals on the scan lines S1, S2, S3, S1P, and the light-emission control signal line EM are high, the transistors connected thereto are turned off. When the signals on the scan lines S1N and S2N are high, the transistors connected thereto are turned on. When the signals on the scan lines S1N and S2N are low, the transistors connected thereto are turned off.

[0052] Since the first reset bus 11 and the second reset bus 12 at least partially overlap, the reset signal on the first reset bus 11 can be different from the reset signal on the second reset bus 12. The inventors have found that if the distance between the first reset bus 11 and the second reset bus 12 is close, the parasitic capacitance between the first reset bus 11 and the second reset bus 12 will be large.

[0053] In some embodiments, as Figure 6 As shown, the display panel 100 may include a plurality of metal layers stacked in a thickness direction thereof. Figure 6 The display panel 100 is exemplarily shown to include a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, which are sequentially away from the substrate 01 in the thickness direction. The thickness direction of the display panel is the stacking direction of its own film layers.

[0054] At least one metal layer may be present between the metal layer where the first reset bus 11 is located and the metal layer where the second reset bus 12 is located. Thus, even if the first reset bus 11 and the second reset bus 12 at least partially overlap, the relatively large distance between them can reduce the parasitic capacitance between the first reset bus 11 and the second reset bus 12, thereby reducing signal interference between the two.

[0055] As an example, the display panel may be a low temperature polysilicon (LTPS) type display panel. Figure 6 As shown, the display panel may include a first semiconductor layer 201. The first semiconductor layer 201 may include an active layer of a transistor. The material of the active layer may include low-temperature polysilicon, such as P-Si. The insulating layer of the display panel may include a first gate insulating layer GI1, a capacitor insulating layer IMD, a first interlayer dielectric layer ILD1, a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3. The display panel may also include a pixel definition layer PDL and support pillars PS.

[0056] refer to Figure 6 One of the first reset bus 11 and the second reset bus 12 may be located in the second metal layer M2 , and the other may be located in the fourth metal layer M4 .

[0057] In various embodiments of the present application, the first reset bus 11 and the second reset bus 12 only need to at least partially overlap. The first reset bus 11 may be located between the substrate 01 and the second reset bus 12, or the second reset bus 12 may be located between the first reset bus 11 and the substrate 01. This application does not limit this.

[0058] As another example, the display panel may be a low temperature polycrystalline oxide (LTPO) type display panel. Figure 7 As shown, the display panel may further include a second semiconductor layer 202 . The second semiconductor layer 202 may include an active layer of a transistor. The material of the active layer may include metal oxide, such as Indium Gallium Zinc Oxide (IGZO). Figure 7 and Figure 6 The similarities are not introduced here, but the differences are as follows: Figure 7 The display panel shown may further include a gate metal layer MG, and the insulating layer may further include a second gate insulating layer GI2 , a third gate insulating layer GI3 , and a second interlayer dielectric layer ILD2 .

[0059] refer to Figure 7One of the first reset bus 11 and the second reset bus 12 may be located in the second metal layer M2 , and the other may be located in the fourth metal layer M4 .

[0060] In some embodiments, as Figure 6 or Figure 7 As shown, the non-display area NA of the display panel may include a gate driving circuit GIP. The gate driving circuit GIP may generate a gate control signal, which may be used to control the on / off state of a transistor in a pixel circuit.

[0061] For example, the gate drive circuit GIP may include a scan drive circuit and a light emitting control drive circuit. The scan drive circuit may be electrically connected to the gate drive circuit. Figure 2 Any one of the scan lines S1, S2, S3 shown, or the scan drive circuit can be electrically connected as shown in FIG. Figure 3 The light emitting control driving circuit can be electrically connected to any one of the scanning lines S1N, S2N, and S1P shown. Figure 2 or Figure 3 The light emission control signal line EM is shown.

[0062] The film layer where at least one of the first reset bus 11 and the second reset bus 12 is located can be different from the film layer where the gate driver circuit GIP is located. In this way, the coupling between at least one of the first reset bus 11 and the second reset bus 12 and the gate driver circuit GIP can be reduced.

[0063] like Figure 6 or Figure 7 As shown, the metal film layers occupied by the gate driver circuit GIP may include a first metal layer M1 and a second metal layer M2. The gate driver circuit GIP may include a capacitor, so the metal film layers occupied by the gate driver circuit GIP may also include a capacitor metal layer MC.

[0064] For example, the first reset bus 11 may be located in the second metal layer M2 , and the film layer where the second reset bus 12 is located may be different from the film layer where the gate driver circuit GIP is located. For example, the second reset bus 12 may be located in the fourth metal layer M4 .

[0065] In some embodiments, as Figure 8 or Figure 9 As shown, the gate driver circuit GIP, the first reset bus 11, and the second reset bus 12 are located on the same side of the substrate 01. In the thickness direction of the display panel, the first reset bus 11 and the second reset bus 12 are both located on the side of the gate driver circuit GIP away from the substrate 01. In other words, the first reset bus 11 and the second reset bus 12 are located on a different film layer than the gate driver circuit GIP. This reduces coupling between the first reset bus 11 and the second reset bus 12 and the gate driver circuit GIP.

[0066] For example, one of the first reset bus 11 and the second reset bus 12 may be located in the third metal layer M3 , and the other may be located in the fourth metal layer M4 .

[0067] In addition to setting the first reset bus 11 and the second reset bus 12, as described above, the display area of ​​the display panel can also be provided with a first connecting line 31, a second connecting line 32, a scan line, and a light-emitting control signal line EM, and a signal line and a data line data connected to the first power supply terminal PVDD need to be provided. The first connecting line 31 and the second connecting line 32 need to include a portion extending along the first direction X, and the first connecting line 31 and the second connecting line 32 can be located in the same film layer. The signal line and the data line data connected to the first power supply terminal PVDD can extend along the second direction Y, and the signal line and the data line data connected to the first power supply terminal PVDD can be located in the same film layer. The scan line and the light-emitting control signal line EM can be located in the same film layer. To avoid signal interference, setting up these signal lines requires a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, and a third metal layer M3.

[0068] In some embodiments, as Figure 10 and Figure 11 As shown, the metal layer where the first reset bus 11 is located can be adjacent to the metal layer where the second reset bus 12 is located. For example, one of the first reset bus 11 and the second reset bus 12 can be located on the second metal layer M2, while the other can be located on the third metal layer M3. This eliminates the need for additional metal layers and insulating layers, facilitating a thinner and lighter display panel.

[0069] In some embodiments, in order to further reduce the interference between the first reset bus 11 and the second reset bus 12 and the gate driver circuit GIP, as shown in FIG. Figures 6 to 11 As shown in any of the accompanying drawings, the orthographic projection of the first reset bus 11 on the plane where the display panel is located may not overlap with the orthographic projection of the gate drive circuit GIP on the plane where the display panel is located; and / or, the orthographic projection of the second reset bus 12 on the plane where the display panel is located may not overlap with the orthographic projection of the gate drive circuit GIP on the plane where the display panel is located.

[0070] In some embodiments, to facilitate connection between the first reset bus 11 and the first connection line 31, the orthographic projection of the first reset bus 11 on the plane where the display panel resides may be located on a side of the orthographic projection of the gate driver circuit GIP on the plane where the display panel resides that is closer to the display area AA. And / or, to facilitate connection between the second reset bus 12 and the second connection line 32, the orthographic projection of the second reset bus 12 on the plane where the display panel resides may be located on a side of the orthographic projection of the gate driver circuit GIP on the plane where the display panel resides that is closer to the display area AA.

[0071] In some embodiments, as Figure 4 As shown, at least a portion of the first reset bus 11 may extend along the second direction Y. The width of the first reset bus 11 in the first direction X is d1, 18 μm ≤ d1 ≤ 25 μm, and the first direction X intersects the second direction Y. For example, d1 may be 18 μm, 20 μm, 22 μm, 25 μm, etc.

[0072] Alternatively, at least a portion of the second reset bus 12 may extend along the second direction Y, and a width d2 of the second reset bus 12 in the first direction X may be 18 μm ≤ d2 ≤ 25 μm. For example, d2 may be 18 μm, 20 μm, 22 μm, 25 μm, etc.

[0073] It should be noted that Figure 2 In order to distinguish the first reset bus 11 from the second reset bus 12, the widths of the first reset bus 11 and the second reset bus 12 in the first direction X are shown as unequal. This does not limit the present application. For example, d1 may be equal to d2. The orthographic projection of the first reset bus 11 and the orthographic projection of the second reset bus 12 on the plane of the display panel may overlap.

[0074] For example, Figure 12 As shown, the first connection line 31 may include a first branch line 311 extending along a first direction X and a second branch line 312 extending along a second direction Y. The first branch line 311 and the second branch line 312 may be located on different metal layers. Multiple first branch lines 311 and multiple second branch lines 312 may intersect with each other to form a grid structure, thereby reducing voltage drop.

[0075] The second connection lines 32 may include a third branch line 321 extending along the first direction X and a fourth branch line 322 extending along the second direction Y. The third branch line 321 and the fourth branch line 322 may be located on different metal layers. Multiple third branch lines 321 and multiple fourth branch lines 322 may intersect to form a grid structure, thereby reducing voltage drop.

[0076] The first branch line 311 and the third branch line 321 may be located in the same metal layer. For example, the first branch line 311 and the third branch line 321 may be located in the capacitor metal layer MC.

[0077] As an example, the second branch line 312 and the fourth branch line 322 may be located in the same metal layer. For example, the second branch line 312 and the fourth branch line 322 may be located in the second metal layer M2 or the third metal layer M3.

[0078] As another example, the second branch line 312 and the data line data are located on the same metal layer, and at least one second branch line 312 may be distributed between two adjacent data lines data. And / or, the fourth branch line 322 and the data line data are located on the same metal layer, and at least one fourth branch line 322 may be distributed between two adjacent data lines data.

[0079] During one frame, the signal on the data line data may jump frequently. The signals on the second branch line 312 and the fourth branch line 322 are usually fixed signals. The second branch line 312 and / or the fourth branch line 322 are used to separate two adjacent data lines data, which can reduce signal interference between the two adjacent data lines data, thereby improving display quality.

[0080] For example, part of the insulating layer of the display panel may be made of organic material, and the insulating layer made of organic material may also be called an organic layer. Figure 6 or Figure 7 Any one of the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 shown may be made of organic materials. For example, the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 may include polyimide (PI), and the organic layer may include the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3.

[0081] The inventors have discovered that the organic layer releases water vapor, causing peeling of the metal traces.

[0082] like Figure 13 As shown, at least one of the first reset bus 11 and the second reset bus 12 may include a hollow area HA. ​​The hollow area can help release moisture, thereby preventing peeling and improving the reliability of the display panel.

[0083] It should be noted that the transistors in the embodiments of the present application may be either N-type transistors or P-type transistors. For N-type transistors, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first and second poles are connected, and when the gate potential of the N-type transistor is a low level, the first and second poles are disconnected. For P-type transistors, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first and second poles are connected, and when the gate potential of the P-type transistor is a high level, the first and second poles are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, depending on the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0084] This application also provides a display device, including the display panel provided by this application. Figure 14 , Figure 14 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 14 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 14 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0085] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area at least partially surrounding the display area, and includes: A pixel circuit and a light-emitting element are located in the display area, a first electrode of the light-emitting element is electrically connected to the pixel circuit, and the pixel circuit includes a driving transistor; a first reset bus located in the non-display area and electrically connected to the driving transistor; a second reset bus located in the non-display area and electrically connected to the first electrode of the light-emitting element; The orthographic projection of the first reset bus on the plane where the display panel is located at least partially overlaps with the orthographic projection of the second reset bus on the plane where the display panel is located; The display area includes a first connection line and a second connection line, the first connection line electrically connecting the first reset bus and the driving transistor, and the second connection line electrically connecting the second reset bus and the first electrode of the light-emitting element; The first connecting lines include first branch lines extending along a first direction and second branch lines extending along a second direction, and a plurality of the first branch lines and a plurality of the second branch lines intersect each other; The second connecting line includes a third branch line extending along the first direction and a fourth branch line extending along the second direction, and a plurality of the third branch lines and a plurality of the fourth branch lines intersect each other; The second branch line and the data line are located in the same metal layer, and at least one second branch line is distributed between two adjacent data lines; and / or the fourth branch line and the data line are located in the same metal layer, and at least one fourth branch line is distributed between two adjacent data lines, and the data line extends along the second direction.

2. The display panel according to claim 1, wherein: The display panel includes a plurality of metal layers stacked in a thickness direction thereof, and the metal layer where the first reset bus is located and the metal layer where the second reset bus is located are separated by at least one metal layer.

3. The display panel according to claim 1, wherein: The display panel includes a gate driving circuit located in the non-display area, and a film layer where at least one of the first reset bus and the second reset bus is located is different from a film layer where the gate driving circuit is located.

4. The display panel according to claim 3, wherein: The display panel includes a substrate, the gate driving circuit, the first reset bus and the second reset bus are located on one side of the substrate, and in the thickness direction of the display panel, the first reset bus and the second reset bus are both located on a side of the gate driving circuit away from the substrate.

5. The display panel according to claim 3 or 4, characterized in that: The display panel includes a plurality of metal layers stacked in a thickness direction thereof, and the metal layer where the first reset bus is located is adjacent to the metal layer where the second reset bus is located.

6. The display panel according to claim 1, wherein: The display panel includes a substrate, and a first metal layer, a capacitor metal layer, a second metal layer, and a third metal layer stacked in a direction away from the substrate, wherein one of the first reset bus and the second reset bus is located in the second metal layer, and the other is located in the third metal layer; Alternatively, the display panel includes a substrate and a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in a direction away from the substrate, one of the first reset bus and the second reset bus is located in the second metal layer, and the other is located in the fourth metal layer; or, one of the first reset bus and the second reset bus is located in the third metal layer, and the other is located in the fourth metal layer.

7. The display panel according to claim 3, wherein: The orthographic projection of the first reset bus on the plane where the display panel is located does not overlap with the orthographic projection of the gate driving circuit on the plane where the display panel is located; And / or, an orthographic projection of the second reset bus on the plane where the display panel is located does not overlap with an orthographic projection of the gate driving circuit on the plane where the display panel is located.

8. The display panel according to claim 7, wherein: The orthographic projection of the first reset bus on the plane where the display panel is located is located on a side of the orthographic projection of the gate driving circuit on the plane where the display panel is located close to the display area; And / or, the orthographic projection of the second reset bus on the plane where the display panel is located is located on a side of the orthographic projection of the gate driving circuit on the plane where the display panel is located close to the display area.

9. The display panel according to claim 1, wherein: At least a portion of the first reset bus extends along a second direction, a width of the first reset bus in the first direction is d1, 18 μm≤d1≤25 μm, and the first direction and the second direction intersect; And / or, at least a portion of the second reset bus extends along the second direction, and a width of the second reset bus in the first direction is d2, where 18 um ≤ d2 ≤ 25 um.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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