A semiconductor structure and its fabrication method

Abstract

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a compositionally graded silicon-germanium virtual substrate layer formed on the substrate, a first silicon-germanium confinement layer formed on the silicon-germanium virtual substrate layer, a silicon quantum well layer formed on the first silicon-germanium confinement layer, a second silicon-germanium confinement layer formed on the silicon quantum well layer, and a cap layer formed on the second silicon-germanium confinement layer. By adjusting the degree of silicon-germanium transition and the growth temperature during the formation of the compositionally graded silicon-germanium virtual substrate layer, the strain magnitude can be controlled, thereby optimizing the silicon-germanium virtual substrate layer and effectively reducing the upward extension of penetrating dislocations, forming a structure that can confine charge carriers. Then, the first silicon-germanium confinement layer, the silicon quantum well layer, and the second silicon-germanium confinement layer are sequentially formed on the silicon-germanium virtual substrate layer, resulting in a semiconductor structure that is a heterojunction structure containing a high-mobility two-dimensional electron gas, enabling the fabrication of a greater number of qubits in the silicon quantum well layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Currently, commonly used quantum computing platforms include physical systems based on superconducting Josephus junctions, cold atoms, ion traps, and semiconductor quantum dots. Compared to the progress towards thousands of qubits on superconducting platforms, semiconductor quantum dots are currently in the early stages of research. Semiconductor quantum dot systems based on Si (silicon) substrates show great promise for compatibility with current mature large-scale advanced manufacturing processes, and Si material naturally contains a large proportion of spinless isotopes. 28 The presence of Si (approximately 92%) allows for the extension of decoherence time to the μs level after eliminating the hyperfine interaction between nuclear spin and electrons. This significantly reduces the difficulty of gate manipulation, a feat unmatched by III-V group materials such as GaAs (whose decoherence time is on the ns level). However, the number of Qubits fabricated using two-dimensional electron gas heterostructures containing Si quantum wells is currently relatively small. Summary of the Invention

[0003] This invention provides a semiconductor structure and its fabrication method, forming a heterojunction structure of a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in a silicon quantum well.

[0004] In a first aspect, the present invention provides a semiconductor structure comprising a substrate, a silicon-germanium virtual substrate layer with a compositional gradient formed thereon the substrate, a first silicon-germanium confinement layer formed thereon the silicon-germanium virtual substrate layer, a silicon quantum well layer formed thereon the first silicon-germanium confinement layer, and a second silicon-germanium confinement layer formed thereon the silicon quantum well layer.

[0005] In the above scheme, by adjusting the degree of transition and growth temperature of the silicon-germanium composition gradient during the formation of the silicon-germanium virtual substrate, the strain magnitude can be controlled, thereby effectively reducing the upward extension of penetrating dislocations through the optimization of the silicon-germanium virtual substrate and forming a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer, a silicon quantum well layer, and a second silicon-germanium confinement layer are formed sequentially on top of the silicon-germanium virtual substrate, so that the final semiconductor structure is a heterojunction structure containing a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in the silicon quantum well layer.

[0006] In one specific embodiment, the material of the silicon-germanium virtual substrate layer is Si. 1-x Ge xWhere x gradually changes from 0 to 0.45 from the bottom to the top of the silicon-germanium virtual substrate. This enables the realization of a heterojunction structure with higher quality and higher mobility of two-dimensional electron gas.

[0007] In one specific embodiment, both the first silicon-germanium confinement layer and the second silicon-germanium confinement layer are made of Si. 1- y Ge y Where 0 < y < 0.45. To achieve a higher quality, high-mobility two-dimensional electron gas heterojunction structure.

[0008] In one specific embodiment, the semiconductor structure further includes: a dislocation isolation pattern at the bottom of at least one layer structure embedded in the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer; wherein the dislocation isolation pattern at the bottom of the layer structure includes multiple dislocation isolation structures; any two adjacent dislocation isolation structures are separated by the layer structure. This confines most of the dislocations and defects in the compositionally graded silicon-germanium to the dislocation isolation pattern region, thus enabling the growth of high-quality germanium material with better strain release on the dislocation isolation pattern region. This increases the dislocation tolerance of the dislocation isolation pattern, enabling dislocation tolerance and blocking the upward extension of penetrating dislocations. It also prevents a large number of penetrating dislocations generated during the preparation of the relaxed silicon-germanium virtual substrate from extending upward, thereby blocking penetrating dislocations caused by lattice mismatch and achieving a heterojunction structure with higher quality and high mobility two-dimensional electron gas.

[0009] In one specific embodiment, the semiconductor structure further includes: a dislocation isolation layer formed between at least one of the layers between the substrate and the silicon-germanium virtual substrate layer, and between the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer, to block the upward extension of penetrating dislocations and prevent a large number of penetrating dislocations generated during the preparation of the relaxed silicon-germanium virtual substrate layer from extending upward, thereby blocking penetrating dislocations generated by lattice mismatch and realizing a heterojunction structure of a higher quality, high-mobility two-dimensional electron gas.

[0010] In one specific embodiment, the semiconductor structure further includes: a dislocation isolation layer formed between at least one of the layers between the substrate and the silicon-germanium virtual substrate layer, and between the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer. Simultaneously, the semiconductor structure also includes: a dislocation isolation pattern embedded at the bottom of at least one layer structure in the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer; wherein the dislocation isolation pattern at the bottom of the layer structure includes multiple dislocation isolation structures; any two adjacent dislocation isolation structures are separated by the layer structure. By simultaneously employing the above two methods, most dislocations and defects in the compositionally graded silicon-germanium are confined to the dislocation isolation pattern region. Therefore, high-quality germanium material with better strain release can be grown on the dislocation isolation pattern region, thereby increasing the dislocation tolerance of the dislocation isolation pattern, achieving dislocation tolerance, blocking the upward extension of penetrating dislocations, preventing a large number of penetrating dislocations generated during the preparation of the relaxed silicon-germanium virtual substrate layer from extending upward, thereby blocking penetrating dislocations caused by lattice mismatch, and realizing a heterojunction structure of higher quality, high-mobility two-dimensional electron gas.

[0011] In one specific implementation, each dislocation isolation structure in the plurality of dislocation isolation structures is made of oxide, nitride, silicon, or germanium. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality heterojunction structure with a high-mobility two-dimensional electron gas.

[0012] In one specific implementation, each of the multiple dislocation isolation structures is a pillar, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality heterojunction structure with a high-mobility two-dimensional electron gas.

[0013] In one specific implementation, the dislocation isolation layer is a silicon lattice structure layer or a silicon-germanium lattice structure layer. Alternatively, the dislocation isolation layer is a superlattice multilayer structure layer formed by alternating growth of silicon and silicon-germanium lattice structure layers for n cycles; where n is a positive integer. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional electron gas heterojunction structure.

[0014] In one specific implementation, the cap layer is made of silicon.

[0015] In a second aspect, the present invention also provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming a silicon-germanium virtual substrate layer with a compositional gradient above the substrate; forming a first silicon-germanium confinement layer above the silicon-germanium virtual substrate layer; forming a silicon quantum well layer on the first silicon-germanium confinement layer; forming a second silicon-germanium confinement layer on the silicon quantum well layer; and growing a cap layer on the second confinement layer.

[0016] In the above scheme, by adjusting the degree of transition and growth temperature of the silicon-germanium composition gradient during the formation of the silicon-germanium virtual substrate, the strain magnitude can be controlled, thereby effectively reducing the upward extension of penetrating dislocations through the optimization of the silicon-germanium virtual substrate and forming a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer, a silicon quantum well layer, and a second silicon-germanium confinement layer are formed sequentially on top of the silicon-germanium virtual substrate, so that the final semiconductor structure is a heterojunction structure containing a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in the silicon quantum well layer. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present invention;

[0018] Figure 2 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a structure after depositing a dislocation isolation structure material on a substrate, as provided in an embodiment of the present invention.

[0020] Figure 4 For etching Figure 3 A schematic diagram of the dislocation isolation pattern formed by the structure shown;

[0021] Figure 5 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0022] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0023] Figure label:

[0024] 10-Substrate; 20-Silicon-germanium virtual substrate layer; 30-First silicon-germanium confinement layer

[0025] 40-Silicon quantum well layer; 50-Second silicon-germanium confinement layer

[0026] 60 - Cap layer; 70 - Dislocation isolation structure; 71 - Dislocation isolation structure material

[0027] 80 - Dislocation isolation layer; 81 - Silicon lattice structure layer; 82 - Silicon-germanium lattice structure layer Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] To facilitate understanding of the semiconductor structure provided in the embodiments of the present invention, the application scenarios of the semiconductor structure provided in the embodiments of the present invention will be described first. This semiconductor structure is applied in processes such as, but not limited to, the fabrication of qubits. The semiconductor structure will now be described in detail with reference to the accompanying drawings.

[0030] refer to Figure 1 The semiconductor structure provided in this embodiment of the invention includes a substrate 10, a silicon-germanium virtual substrate layer 20 with a compositional gradient formed on the substrate 10, a first silicon-germanium confinement layer 30 formed on the silicon-germanium virtual substrate layer 20, a silicon quantum well layer 40 formed on the first silicon-germanium confinement layer 30, a second silicon-germanium confinement layer 50 formed on the silicon quantum well layer 40, and a cap layer 60 formed on the second silicon-germanium confinement layer 50.

[0031] In the above scheme, by adjusting the degree of transition and growth temperature of the silicon-germanium composition gradient during the formation of the silicon-germanium virtual substrate 20, the strain magnitude can be controlled. This optimizes the silicon-germanium virtual substrate 20, effectively reducing the upward extension of penetrating dislocations and forming a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer 30, a silicon quantum well layer 40, and a second silicon-germanium confinement layer 50 are sequentially formed above the silicon-germanium virtual substrate 20. This results in a final semiconductor structure that is a heterojunction structure containing a high-mobility two-dimensional electron gas, enabling the fabrication of a greater number of qubits in the silicon quantum well layer 40. The following section provides a detailed description of each of the above structures in conjunction with the accompanying drawings.

[0032] When setting the substrate 10, a silicon substrate 10 formed of a material such as, but not limited to, silicon can be used as a carrier for setting other material layers and microelectronic devices.

[0033] refer to Figure 1A compositionally graded silicon-germanium virtual substrate layer 20 is formed above the substrate 10. Specifically, the silicon-germanium virtual substrate layer 20 can be formed using epitaxial growth processes such as, but not limited to, MBE (Molecular Beam Epitaxy), UHVCVD (Ultra-High Vacuum Chemical Vapor Deposition), and RPCVD (Reduced Pressure Chemical Vapor Deposition) to epitaxially grow the compositionally graded silicon-germanium virtual substrate layer 20 above the substrate 10. When determining the material composition of the silicon-germanium virtual substrate layer 20, the material of the silicon-germanium virtual substrate layer 20 is Si. 1-x Ge x In this context, x gradually increases from 0 to 0.45 from the bottom to the top of the silicon-germanium virtual substrate 20. That is, in the silicon-germanium virtual substrate 20, the closer to the bottom, the higher the silicon content and the lower the germanium content; at the lowest point, the silicon content is almost 100%, while the germanium content is almost zero. Conversely, the closer to the top, the lower the silicon content and the higher the germanium content; at the very top, the silicon content drops to almost 55%, while the germanium content increases to almost 45%, achieving a higher quality, high-mobility two-dimensional electron gas heterojunction structure. It should be understood that the above only illustrates one method of setting the silicon-germanium virtual substrate 20; other methods can also be used to form the silicon-germanium virtual substrate 20.

[0034] Next, as Figure 1 As shown, a first silicon-germanium confinement layer 30 is formed above the silicon-germanium virtual substrate layer 20, a silicon quantum well layer 40 is formed on the first silicon-germanium confinement layer 30, and a second silicon-germanium confinement layer 50 is formed on the silicon quantum well layer 40. Both the first silicon-germanium confinement layer 30 and the second silicon-germanium confinement layer 50 can be made of Si. 1-y Ge y Where 0 < y < 0.45, specifically, the value of y can be any value greater than 0 and less than 0.45, such as 0.01, 0.05, 0.10, 0.15, 0.20, 0.25, 0.30, 0.34, 0.35, 0.40, 0.44, etc., to achieve a heterojunction structure of a high-quality, high-mobility two-dimensional electron gas. Furthermore, when forming a first silicon-germanium confinement layer 30 above the silicon-germanium virtual substrate layer 20, forming a silicon quantum well layer 40 on the first silicon-germanium confinement layer 30, and forming a second silicon-germanium confinement layer 50 on the silicon quantum well layer 40, epitaxial growth processes such as, but not limited to, MBE, UHVCVD, RPCVD, etc., can be used to sequentially form the first silicon-germanium confinement layer 30 above the silicon-germanium virtual substrate layer 20, the silicon quantum well layer 40 on the first silicon-germanium confinement layer 30, and the second silicon-germanium confinement layer 50 on the silicon quantum well layer 40.

[0035] Compared with the prior art, this application adjusts the degree of transition and growth temperature of the silicon-germanium virtual substrate 20 during the formation of the compositionally graded silicon-germanium virtual substrate 20, thereby controlling the strain magnitude and optimizing the silicon-germanium virtual substrate 20 to effectively reduce the upward extension of penetrating dislocations and form a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer 30, a silicon quantum well layer 40 and a second silicon-germanium confinement layer 50 are sequentially formed on top of the silicon-germanium virtual substrate 20, so that the final semiconductor structure is a heterojunction structure containing a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in the silicon quantum well layer 40.

[0036] Continue to refer to Figure 1 Furthermore, a cap layer 60 can be formed on the surface of the second silicon-germanium confinement layer 50. The material of the cap layer 60 can be silicon, silicon dioxide, or other materials, to protect the second silicon-germanium confinement layer 50.

[0037] Additionally, refer to Figure 2 The semiconductor structure may further include: a dislocation isolation pattern embedded at the bottom of at least one layer structure in the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30; wherein the dislocation isolation pattern at the bottom of the layer structure includes a plurality of dislocation isolation structures 70; any two adjacent dislocation isolation structures 70 are separated by the layer structure. The above-mentioned dislocation isolation pattern can be adopted as follows: Figure 2 The dislocation isolation pattern shown is embedded only at the bottom of the silicon-germanium virtual substrate 20. Of course, the dislocation isolation pattern can also be embedded only at the bottom of the first silicon-germanium confinement layer 30. Furthermore, a dislocation isolation pattern can be embedded at the bottom of each layer structure in both the silicon-germanium virtual substrate 20 and the first silicon-germanium confinement layer 30, meaning that both the silicon-germanium virtual substrate 20 and the first silicon-germanium confinement layer 30 have dislocation isolation patterns embedded at their bottoms. By embedding a dislocation isolation pattern at the bottom of at least one layer structure in the silicon-germanium virtual substrate 20 and the first silicon-germanium confinement layer 30, most of the dislocations and defects in the compositionally graded silicon-germanium are confined to the dislocation isolation pattern region. Therefore, high-quality germanium material with better strain release can be grown on the dislocation isolation pattern region, thereby increasing the dislocation tolerance in the dislocation isolation pattern. This enables dislocation tolerance, blocks the upward extension of penetrating dislocations, and prevents a large number of penetrating dislocations generated during the fabrication of the relaxed silicon-germanium virtual substrate 20 from extending upwards, thereby blocking penetrating dislocations caused by lattice mismatch and achieving a higher-quality, high-mobility two-dimensional electron gas heterojunction structure.

[0038] When setting the dislocation isolation pattern in each layer structure, each dislocation isolation structure 70 in the multiple dislocation isolation structures 70 of the same dislocation isolation pattern can be made of materials such as, but not limited to, oxides, nitrides, silicon, or germanium, wherein the oxide can be an oxide material such as silicon dioxide. This improves the dislocation containment effect, enhances the effect of blocking the upward extension of penetrating dislocations, and enhances the effect of blocking penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional electron gas heterojunction structure.

[0039] Furthermore, each of the multiple dislocation isolation structures 70 can specifically be a cylinder, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape. For example, each dislocation isolation structure 70 can be a cylinder with a rectangular cross-sectional shape; specifically, the rectangle can be a rectangle, in which case each dislocation isolation structure 70 is a long strip structure; the rectangle can also be a square, in which case each dislocation isolation structure 70 is a square cylinder structure. When each dislocation isolation structure 70 is a cylinder with a circular cross-sectional shape, each dislocation isolation structure 70 is a cylindrical structure. When each dislocation isolation structure 70 is a cylinder with a rhomboid cross-sectional shape, each dislocation isolation structure 70 is a rhomboid cylinder structure. When each dislocation isolation structure 70 is a frustum with a rectangular cross-sectional shape, the cross-section of each dislocation isolation structure 70 is rectangular, but the area of ​​the cross-section gradually decreases from the bottom to the top. When each dislocation isolation structure 70 is a frustum with a circular cross-sectional shape, each dislocation isolation structure 70 is a frustum structure. When each dislocation isolation structure 70 is a cone with a circular cross-sectional shape, then each dislocation isolation structure 70 is a conical structure. This arrangement improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, resulting in a higher-quality heterojunction structure with high-mobility two-dimensional electron gas. Furthermore, multiple dislocation isolation structures 70 within the same dislocation isolation pattern can be arranged periodically, making the dislocation isolation effect more uniform at each position within the same dislocation isolation pattern.

[0040] The following is combined Figure 2 , Figure 3 and Figure 4 This paper describes a method for forming dislocation isolation patterns at the bottom of a silicon-germanium virtual substrate 20. For details, please refer to [reference needed]. Figure 3 First, a dislocation isolation structure material 71 is deposited on the substrate 10. This dislocation isolation structure material 71 can be an oxide, nitride, silicon, or germanium as shown above. The specific deposition method can be thermal oxidation or PECVD (Plasma Enhanced Chemical Vapor Deposition) processes. Then, refer to... Figure 4Dislocation isolation patterns are etched onto the dislocation isolation structure material 71 using methods such as photolithography. Then, a silicon-germanium virtual substrate layer 20 is epitaxially grown on the upper surface, sidewalls, and surface of the substrate 10 between adjacent dislocation isolation structures 70, thereby embedding the dislocation isolation pattern at the bottom of the silicon-germanium virtual substrate layer 20. A planarization process, such as but not limited to CMP, can be used to planarize the upper surface of the silicon-germanium virtual substrate layer 20. Then, a first silicon-germanium confinement layer 30, a silicon quantum well layer 40, and a second silicon-germanium confinement layer 50 are sequentially grown on the silicon-germanium virtual substrate layer 20. The above process can also be applied to embedding the dislocation isolation pattern at the bottom of the first silicon-germanium confinement layer 30; the specific embedding can be adjusted according to different placement positions, which will not be elaborated further here.

[0041] Furthermore, refer to Figure 5 The semiconductor structure may further include: a dislocation isolation layer 80 formed between at least one of the layers between the substrate 10 and the silicon-germanium virtual substrate layer 20, and between the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30, to block the upward extension of penetrating dislocations and prevent a large number of penetrating dislocations generated during the fabrication of the relaxed silicon-germanium virtual substrate from extending upward, thereby blocking penetrating dislocations caused by lattice mismatch and realizing a higher quality, high-mobility two-dimensional electron gas heterojunction structure. Specifically, it can be configured as follows: Figure 5 The diagram shows a dislocation isolation layer 80 formed between the substrate 10 and the silicon-germanium virtual substrate layer 20, and also between the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30. That is, a dislocation isolation layer 80 is set between any two adjacent layers in the three layer structures: the substrate 10, the silicon-germanium virtual substrate layer 20, and the first silicon-germanium confinement layer 30. It should be understood that the dislocation isolation layer 80 is not limited to... Figure 5 Besides the configuration shown, other configuration methods can also be used. For example, only one dislocation isolation layer 80 can be configured. Specifically, the dislocation isolation layer 80 can be configured only between the substrate 10 and the silicon-germanium virtual substrate layer 20, or only between the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30.

[0042] Furthermore, before setting each dislocation isolation layer 80, a planarization process, such as but not limited to CMP, can be used to planarize the surface on which the dislocation isolation layer 80 will be grown, before growing the dislocation isolation layer 80. For example, when forming a dislocation isolation layer 80 between the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30, after growing the silicon-germanium virtual substrate layer 20, a planarization process, such as but not limited to CMP, can be used to planarize the surface of the silicon-germanium virtual substrate layer 20, and then the first silicon-germanium confinement layer 30, the silicon quantum well 40, and the second silicon-germanium confinement layer 50 can be sequentially grown on the surface of the silicon-germanium virtual substrate layer 20.

[0043] When specifically configuring each dislocation isolation layer 80, the dislocation isolation layer 80 can be a silicon lattice structure layer, meaning each dislocation isolation layer 80 is formed by only one silicon lattice structure layer. The dislocation isolation layer 80 can also be a silicon-germanium lattice structure layer, meaning each dislocation isolation layer 80 is formed by only one silicon-germanium lattice structure layer. Of course, the configuration of the dislocation isolation layer 80 is not limited to the methods shown above; other methods can also be used. For example, it can be used as follows... Figure 5 The dislocation isolation layer 80 shown is a superlattice multilayer structure formed by alternating growth of a silicon lattice structure layer 81 and a silicon-germanium lattice structure layer 82 for n cycles, where n is a positive integer such as 1, 2, 3, 4, 5, etc. Each growth cycle consists of first growing a silicon lattice structure layer 81, followed by growing a silicon-germanium lattice structure layer 82; or, each growth cycle consists of first growing a silicon-germanium lattice structure layer 82, followed by growing a silicon lattice structure layer 81. For details, refer to... Figure 5 Each superlattice multilayer structure is formed by alternating growth of a silicon lattice structure layer 81 and a silicon-germanium lattice structure layer 82. Specifically, the silicon lattice structure layer 81 or the silicon-germanium lattice structure layer 82 in the dislocation isolation layer 80 can be epitaxially grown using epitaxial growth processes such as, but not limited to, MBE, UHVCVD, and RPCVD, as described above. By configuring the dislocation isolation layer 80 as shown above, the dislocation containment effect can be improved, the effect of blocking the upward extension of penetrating dislocations can be improved, and the effect of blocking penetrating dislocations caused by lattice mismatch can be improved, thus achieving a higher quality, high-mobility two-dimensional electron gas heterojunction structure.

[0044] Furthermore, both a dislocation isolation layer 80 and a dislocation isolation pattern can be disposed in the same semiconductor structure. The dislocation isolation layer 80 is formed between at least one of the layers between the substrate 10 and the silicon-germanium virtual substrate layer 20, and between the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30. The dislocation isolation pattern is embedded at the bottom of at least one layer structure in the silicon-germanium virtual substrate layer 20 and the first silicon-germanium confinement layer 30. The dislocation isolation pattern at the bottom of the aforementioned layer structure includes a plurality of dislocation isolation structures 70; any two adjacent dislocation isolation structures 70 are separated by a layer structure. The specific method of forming the dislocation isolation layer 80 and the dislocation isolation pattern is described above and will not be repeated here. By employing both methods simultaneously, most dislocations and defects in the compositionally graded silicon-germanium are confined to the dislocation isolation pattern region. Therefore, high-quality germanium material with better strain release can be grown on the dislocation isolation pattern region, thereby increasing the dislocation tolerance in the dislocation isolation pattern. This enables dislocation tolerance and blocks the upward extension of penetrating dislocations, preventing a large number of penetrating dislocations generated during the preparation of the relaxed silicon-germanium virtual substrate 20 from extending upward. This also blocks penetrating dislocations caused by lattice mismatch, achieving a heterojunction structure with higher quality and high mobility of two-dimensional electron gas.

[0045] By adjusting the degree of transition and growth temperature of the silicon-germanium virtual substrate 20 during the formation of the composition-gradient silicon-germanium virtual substrate 20, the strain magnitude can be controlled, thereby optimizing the silicon-germanium virtual substrate 20 and effectively reducing the upward extension of penetrating dislocations to form a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer 30, a silicon quantum well layer 40, and a second silicon-germanium confinement layer 50 are sequentially formed on top of the silicon-germanium virtual substrate 20, so that the final semiconductor structure is a heterojunction structure containing a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in the silicon quantum well layer 40.

[0046] In addition, embodiments of the present invention also provide a method for fabricating a semiconductor structure, as referenced in 1 and Figure 6 The preparation method includes:

[0047] S10: Provides a substrate 10;

[0048] S20: A silicon-germanium virtual substrate layer 20 with a compositional gradient is formed above the substrate 10;

[0049] S30: A first silicon-germanium confinement layer 30 is formed above the silicon-germanium virtual substrate layer 20;

[0050] S40: A silicon quantum well layer 40 is formed on the first silicon-germanium confinement layer 30;

[0051] S50: A second silicon-germanium confinement layer 50 is formed on the silicon quantum well layer 40;

[0052] S60: A cap layer 60 is formed on the second silicon-germanium confinement layer 50.

[0053] In the above scheme, by adjusting the degree of transition and growth temperature of the silicon-germanium virtual substrate 20 during the formation of the composition-gradient silicon-germanium virtual substrate 20, the strain magnitude can be controlled, thereby optimizing the silicon-germanium virtual substrate 20 and effectively reducing the upward extension of penetrating dislocations to form a structure that can confine charge carriers. Then, a first silicon-germanium confinement layer 30, a silicon quantum well layer 40, and a second silicon-germanium confinement layer 50 are sequentially formed on top of the silicon-germanium virtual substrate 20, so that the final semiconductor structure is a heterojunction structure containing a high-mobility two-dimensional electron gas, thereby enabling the fabrication of a greater number of qubits in the silicon quantum well layer 40.

[0054] The specific preparation methods for each of the above steps are described in the preceding section on the corresponding parts of the semiconductor structure, and will not be repeated here.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A silicon-germanium virtual substrate layer with a gradually changing composition is formed above the substrate, wherein the material of the silicon-germanium virtual substrate layer is Si. 1-x Ge x x gradually changes from 0 to 0.45 from the bottom of the silicon-germanium virtual substrate to the top of the silicon-germanium virtual substrate. A first silicon-germanium confinement layer is formed above the silicon-germanium virtual substrate layer; A silicon quantum well layer formed on the first silicon-germanium confinement layer; A second silicon-germanium confinement layer is formed on the silicon quantum well layer; A cap layer formed on the second silicon-germanium confinement layer; Also includes: A dislocation isolation pattern is embedded at the bottom of at least one layer structure in the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer, the dislocation isolation pattern at the bottom of the layer structure comprising a plurality of dislocation isolation structures, wherein any two adjacent dislocation isolation structures are separated by the layer structure; and / or, a dislocation isolation layer is formed between at least one layer in the interlayer between the substrate and the silicon-germanium virtual substrate layer, and between the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first silicon-germanium confinement layer and the second silicon-germanium confinement layer are both made of Si. 1-y Ge y , where 0 < y < 0.

45.

3. The semiconductor structure as described in claim 1, characterized in that, The material of each of the plurality of dislocation isolation structures is: oxide, nitride, silicon, or germanium.

4. The semiconductor structure as described in claim 1, characterized in that, Each of the multiple dislocation isolation structures is a cylinder, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape.

5. The semiconductor structure as described in claim 1, characterized in that, The dislocation isolation layer is a silicon lattice structure layer or a silicon-germanium lattice structure layer; or... The dislocation isolation layer is a superlattice multilayer structure formed by alternating growth of silicon lattice structure layers and silicon-germanium lattice structure layers for n cycles; where n is a positive integer.

6. The semiconductor structure as described in claim 1, characterized in that, The cap layer is made of silicon.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A silicon-germanium virtual substrate layer with a compositional gradient is formed above the substrate, wherein the material of the silicon-germanium virtual substrate layer is Si. 1-x Ge x Where x gradually changes from 0 to 0.45 from the bottom of the silicon-germanium virtual substrate to the top of the silicon-germanium virtual substrate; A first silicon-germanium confinement layer is formed above the silicon-germanium virtual substrate layer; A silicon quantum well layer is formed on the first silicon-germanium confinement layer; A second silicon-germanium confinement layer is formed on the silicon quantum well layer; A cap layer is formed on the second silicon-germanium confinement layer; Wherein, a dislocation isolation pattern is embedded at the bottom of at least one of the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer, and the dislocation isolation pattern at the bottom of the layer structure includes a plurality of dislocation isolation structures, wherein any two adjacent dislocation isolation structures are separated by the layer structure; and / or, a dislocation isolation layer is formed in at least one of the interlayers between the substrate and the silicon-germanium virtual substrate layer and between the silicon-germanium virtual substrate layer and the first silicon-germanium confinement layer.

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