Automatic sleep control system and method for user terminal and user terminal

Abstract

The present invention provides an automatic sleep control system, method, and user terminal for a user terminal, relating to the field of communication technology. The method comprises: a wireless radio frequency processing module receives a paging baseband signal from an external base station when the user terminal wakes up from a standby state, and sends the signal to a baseband processing module for modulation and demodulation of the paging baseband signal; a low-speed clock calibration module uses a first clock to perform clock calibration on a second clock each time the user terminal wakes up, and generates a calibration completion signal when the clock calibration is completed; upon detecting that the modulation and demodulation of the paging baseband signal is completed, the baseband processing module is controlled to enter a sleep state; upon receiving the calibration completion signal and receiving a vote of sleep enable signals output by each hardware circuit module, a power-off signal is generated to control a power management chip to stop supplying power and turn off the first clock, thereby controlling the user terminal to enter a standby state. The beneficial effect is that the baseband processing module can be powered off in advance, saving power consumption.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular to an automatic sleep control system and method for a user terminal, and the user terminal. Background Art

[0002] In a communication system, when the user equipment (UE) is working normally, the built-in baseband processing module uses the modulated first clock (26 MHz) to synchronize and time with the base station; when in sleep mode, in order to save power consumption, the second clock (32 kHz) is used to synchronize and time with the base station.

[0003] Generally speaking, the accuracy of a low-speed 32K clock crystal is poor. To ensure the timing accuracy of the baseband processing module during sleep, the first clock needs to be calibrated to the second clock each time the user terminal wakes up. Specifically, a calibration coefficient Cal_Factor is obtained through a fixed calibration time T, where:

[0004] It can be seen that the worse the crystal of the second clock is, the longer the calibration time is required. When the user terminal wakes up each time, the signal reception time of its wireless RF processing module is only a few milliseconds, but it takes 16ms-32ms to calibrate the second clock (32K).

[0005] In the prior art, such as Figure 2 As shown, the baseband processing module must wait until the second clock (32K) calibration is completed before starting the software power-off process, and then notifying the hardware to power off through software voting, resulting in high standby power consumption of the user terminal. Summary of the Invention

[0006] In response to the problems existing in the prior art, the present invention provides an automatic sleep control system for a user terminal. The user terminal is configured with a first clock and a second clock. The clock frequency of the first clock is higher than the clock frequency of the second clock. The automatic sleep control system includes:

[0007] A wireless radio frequency processing module, connected to the baseband processing module, configured to receive a paging baseband signal from an external base station when the user terminal is awakened from a standby state, and send the paging baseband signal to the baseband processing module for modulation and demodulation processing;

[0008] a low-speed clock calibration module, configured to perform clock calibration on the second clock using the first clock each time the user terminal wakes up, and generate a calibration completion signal when the clock calibration is completed;

[0009] a first sleep control module, connected to the baseband processing module, configured to control the baseband processing module to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed;

[0010] The second sleep control module is respectively connected to the power management chip and each hardware circuit module of the user terminal, and is used to generate a power-off signal when the calibration completion signal is received and the sleep enable signals output by each of the hardware circuit modules are voted through, control the power management chip to stop power supply and turn off the first clock, so as to control the user terminal to enter the standby state.

[0011] Preferably, the second sleep control module includes:

[0012] a voting unit, wherein the plurality of input terminals of the voting unit are respectively connected to the sleep enable output terminals of the hardware circuit modules, and are configured to receive the sleep enable signals output by the sleep enable output terminals, and output a voting result indicating that the sleep enable signals have passed voting when an AND operation result of the sleep enable signals is sleep enable;

[0013] A first control unit, wherein the input end of the first control unit is respectively connected to the output end of the voting unit and the output end of the low-speed clock calibration module, and is used to control the power management chip to stop power supply and turn off the first clock when receiving the calibration completion signal and the voting result, so as to control the user terminal to enter the standby state.

[0014] Preferably, the clock input pin of the power management chip is connected to the first clock, the clock output pin of the power management chip is connected to the low-speed clock calibration module, and the sleep control pin of the power management chip is connected to the second sleep control module. The power management chip is used to control its own power supply pin to stop supplying power according to the power-off signal and to control the clock output pin to turn off the output of the first clock.

[0015] Preferably, it also includes a hardware timing module, which is respectively connected to the second sleep control module, the clock output pin of the power management chip and the clock output pin of the low-speed clock calibration module. The hardware timing module uses the first clock for timing when the user terminal wakes up, and switches to using the second clock for timing when receiving the power-off signal, and then enters a sleep state.

[0016] The present invention also provides an automatic sleep control method for a user terminal, which is applied to the above-mentioned automatic sleep control system. The automatic sleep control method includes:

[0017] Step S1, when the user terminal wakes up from the standby state, the automatic sleep control system receives a paging baseband signal from an external base station and sends it to the baseband processing module for modulation and demodulation of the paging baseband signal, while simultaneously calibrating the second clock using the first clock, and generating a calibration completion signal when the clock calibration is completed;

[0018] Step S2, the automatic sleep control system controls the baseband processing module to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed;

[0019] In step S3, when the calibration completion signal is received and the sleep enable signals output by the hardware circuit modules of the user terminal are voted through, the automatic sleep control system controls the power management chip of the user terminal to stop power supply and turn off the first clock to control the user terminal to enter the standby state.

[0020] Preferably, step S3 includes:

[0021] In step S31, the automatic sleep control system receives the sleep enable signal outputted by the sleep enable output terminal of each hardware circuit module, and determines whether the result of the AND operation of each sleep enable signal is sleep enable:

[0022] If yes, output the voting results of each of the sleep enable signals, and then go to step S32;

[0023] If not, return to step S31;

[0024] Step S32 : upon receiving the calibration completion signal and the voting result, the automatic sleep control system controls the power management chip to stop supplying power and turn off the first clock, so as to control the user terminal to enter the standby state.

[0025] The present invention also provides a user terminal including the above-mentioned automatic sleep control system.

[0026] The above technical solution has the following advantages or beneficial effects:

[0027] 1) Decoupling the power-off of the baseband processing module from the calibration of the second clock enables the baseband processing module to enter sleep mode through software control after modulation and demodulation are completed. After the second clock calibration is completed, the chip automatically votes to power off based on the hardware circuit; thus, the baseband processing module can be powered off in advance, saving power consumption.

[0028] 2) When the user terminal is in the CDRX state, the online time of the CDRXonduration processor and the baseband processing module can be shortened, thereby reducing the power consumption of the user terminal;

[0029] 3) The system design of the baseband processing module is simplified. The baseband processing module can go to sleep directly after processing the air interface data. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a structural diagram of an automatic sleep control system for a user terminal in a preferred embodiment of the present invention;

[0031] Figure 2 The power-off logic of the user terminal in the prior art;

[0032] Figure 3 In a preferred embodiment of the present invention, the power-off logic of the user terminal;

[0033] Figure 4 1 is a flow chart of an automatic sleep control method for a user terminal in a preferred embodiment of the present invention;

[0034] Figure 5 This is a sub-flow diagram of step S3 in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0036] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, an automatic sleep control system for a user terminal is provided. Figure 1 As shown, a first clock 1 and a second clock 2 are configured in the user terminal. The clock frequency of the first clock is higher than the clock frequency of the second clock. The automatic sleep control system includes:

[0037] The wireless radio frequency processing module 3 is connected to the baseband processing module 4 and is used to receive the paging baseband signal from the external base station when the user terminal wakes up from the standby state, and send it to the baseband processing module 4 for modulation and demodulation of the paging baseband signal;

[0038] A low-speed clock calibration module 5 is configured to perform clock calibration on the second clock 2 using the first clock 1 each time the user terminal wakes up, and to generate a calibration completion signal when the clock calibration is completed;

[0039] A first sleep control module 6 is connected to the baseband processing module 4 and is used to control the baseband processing module 4 to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed;

[0040] The second sleep control module 7 is respectively connected to the power management chip 8 and each hardware circuit module 9 of the user terminal, and is used to generate a power-off signal when a calibration completion signal is received and the sleep enable signal output by each hardware circuit module 9 is voted through, to control the power management chip 8 to stop power supply and turn off the first clock to control the user terminal to enter the standby state.

[0041] Specifically, the clock frequency of the first clock is preferably 26 MHz, and the clock frequency of the second clock is preferably 32 KHz. Figure 2 As shown, it can be seen that the time duration for the wireless RF processing module 3 to receive the paging baseband signal is relatively short. After the baseband processing module 4 completes the modulation and demodulation of the paging baseband signal, there is still a relatively long period of time before the second clock calibration is completed. During this period, the baseband processing module 4 does not work, but the sleep enable Sleep Enable occurs after the second clock calibration is completed, so that the sleep state of the baseband processing module 4 and the chip occurs after the second clock calibration is completed, which wastes battery power and causes high power consumption.

[0042] Based on this, this technical solution decouples the power-off of the baseband processing module 4 and the calibration process of the second clock. The above-mentioned first sleep control module 6 is implemented by software, and is used to control the baseband processing module 4 to power off immediately after processing the paging baseband signal. The above-mentioned second sleep control module 7 is implemented by hardware, and is used to control the power management chip 8 to stop supplying power after the second clock calibration is completed, thereby powering off the chip, so that the baseband processing module can be powered off in advance to save power consumption.

[0043] To be more specific, the second sleep control module 7 detects the calibration status of the second clock in real time. If the calibration of the second clock is not completed, that is, the calibration completion signal is not received, the second sleep control module 7 and the chip will not enter the sleep state until the calibration of the second clock is completed. At this time, the second sleep control module 7 needs to confirm whether all hardware circuit modules are sleep-enabled. If so, the second sleep control module 7 generates a high-level chipsleep signal to notify the power management chip 8 to turn off the first clock and stop power supply, thereby completing chip power-off.

[0044] In a preferred embodiment of the present invention, the second sleep control module 7 includes:

[0045] A voting unit 71, wherein the multiple input terminals of the voting unit are respectively connected to the sleep enable output terminals of the hardware circuit modules 9, and is configured to receive the sleep enable signals output by the sleep enable output terminals, and output the voting result indicating that the sleep enable signals have passed the voting when the result of the AND operation of the sleep enable signals is sleep enable;

[0046] The first control unit 72, the input end of the first control unit 72 is respectively connected to the output end of the voting unit 71 and the output end of the low-speed clock calibration module 5, and is used to control the power management chip 8 to stop power supply and turn off the first clock 1 when receiving the calibration completion signal and the voting result, so as to control the user terminal to enter the standby state.

[0047] Specifically, in this embodiment, the second sleep control module 7 is connected to each hardware circuit module 9 through a hardware line, and the voting unit 71 is preferably implemented by multiple AND operators. The sleep enable signal is preferably a high level. Only when the AND operation result is a high level, it indicates that the votes of each hardware circuit module 9 are all high levels, and the vote is considered to be passed.

[0048] In a preferred embodiment of the present invention, the clock input pin CLK of the power management chip 8 is connected to the first clock 1, the clock output pin of the power management chip 8 is connected to the low-speed clock calibration module 5, and the sleep control pin ChipSleep of the power management chip 8 is connected to the second sleep control module 7. The power management chip 8 is used to control its own power supply pin VDDOUT to stop supplying power according to the power-off signal and to control the clock output pin CLKOUT to turn off the output of the first clock 1.

[0049] In a preferred embodiment of the present invention, a hardware timing module 10 is also included, which is respectively connected to the clock output pins of the second sleep control module 7, the power management chip 8 and the clock output pin of the low-speed clock calibration module 5. The hardware timing module 10 uses the first clock 1 for timing when the user terminal wakes up, and switches to the second clock 2 for timing when receiving a power-off signal, and then enters a sleep state.

[0050] More specifically, Figure 3 As shown, when the technical solution of the present invention is adopted, after the baseband processing module 4 processes the paging baseband signal, the SleepEnable is pulled high by software to realize that the baseband processing module 4 can be powered off, and after the second clock calibration is completed, the hardware timing module 10 is automatically triggered by hardware to automatically switch from the first clock to the second clock, the TMU sleep is enabled, and then the power supply is stopped, the chip is powered off, and the user terminal enters the sleep state.

[0051] contrast Figure 2 and Figure 3 It can be seen that the power-off time of the baseband processing module 4 is significantly advanced, which effectively saves power consumption.

[0052] The present invention also provides an automatic sleep control method for a user terminal, which is applied to the above automatic sleep control system. Figure 4 As shown, the automatic sleep control method includes:

[0053] Step S1, when the user terminal wakes up from the standby state, the automatic sleep control system receives a paging baseband signal from an external base station and sends it to the baseband processing module for modulation and demodulation of the paging baseband signal. At the same time, the first clock is used to calibrate the second clock, and a calibration completion signal is generated when the clock calibration is completed.

[0054] Step S2, the automatic sleep control system controls the baseband processing module to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed;

[0055] In step S3, when the calibration completion signal is received and the sleep enable signals output by the hardware circuit modules of the user terminal are voted through, the automatic sleep control system controls the power management chip of the user terminal to stop power supply and turn off the first clock to control the user terminal to enter the standby state.

[0056] In a preferred embodiment of the present invention, Figure 5 As shown, step S3 includes:

[0057] Step S31: The automatic sleep control system receives the sleep enable signal outputted by the sleep enable output terminal of each hardware circuit module, and determines whether the AND operation result of each sleep enable signal is sleep enable:

[0058] If yes, the voting results of each sleep enable signal are output, and then the process goes to step S32;

[0059] If not, return to step S31;

[0060] In step S32 , upon receiving the calibration completion signal and the voting result, the automatic sleep control system controls the power management chip to stop supplying power and turn off the first clock, so as to control the user terminal to enter a standby state.

[0061] The present invention also provides a user terminal including the above-mentioned automatic sleep control system.

[0062] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An automatic sleep control system for a user terminal, characterized in that: The user terminal is configured with a first clock and a second clock, wherein the clock frequency of the first clock is higher than the clock frequency of the second clock, and the automatic sleep control system includes: A wireless radio frequency processing module, connected to the baseband processing module, configured to receive a paging baseband signal from an external base station when the user terminal is awakened from a standby state, and send the paging baseband signal to the baseband processing module for modulation and demodulation processing; a low-speed clock calibration module, configured to perform clock calibration on the second clock using the first clock each time the user terminal wakes up, and generate a calibration completion signal when the clock calibration is completed; a first sleep control module, connected to the baseband processing module, configured to control the baseband processing module to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed; The second sleep control module is respectively connected to the power management chip and each hardware circuit module of the user terminal, and is used to generate a power-off signal when the calibration completion signal is received and the sleep enable signals output by each of the hardware circuit modules are voted through, control the power management chip to stop power supply and turn off the first clock, so as to control the user terminal to enter the standby state.

2. The automatic sleep control system according to claim 1, characterized in that: The second sleep control module includes: a voting unit, wherein the plurality of input terminals of the voting unit are respectively connected to the sleep enable output terminals of the hardware circuit modules, and are configured to receive the sleep enable signals output by the sleep enable output terminals, and output a voting result indicating that the sleep enable signals have passed voting when an AND operation result of the sleep enable signals is sleep enable; A first control unit, wherein the input end of the first control unit is respectively connected to the output end of the voting unit and the output end of the low-speed clock calibration module, and is used to control the power management chip to stop power supply and turn off the first clock when receiving the calibration completion signal and the voting result, so as to control the user terminal to enter the standby state.

3. The automatic sleep control system according to claim 1, characterized in that: The clock input pin of the power management chip is connected to the first clock, the clock output pin of the power management chip is connected to the low-speed clock calibration module, and the sleep control pin of the power management chip is connected to the second sleep control module. The power management chip is used to control its own power supply pin to stop supplying power according to the power-off signal and control the clock output pin to turn off the output of the first clock.

4. The automatic sleep control system according to claim 1, characterized in that: It also includes a hardware timing module, which is respectively connected to the second sleep control module, the clock output pin of the power management chip and the clock output pin of the low-speed clock calibration module. The hardware timing module uses the first clock for timing when the user terminal wakes up, and switches to using the second clock for timing when receiving the power-off signal, and then enters a sleep state.

5. A method for automatic sleep control of a user terminal, characterized in that: Applied to the automatic sleep control system according to any one of claims 1 to 4, the automatic sleep control method comprises: Step S1, when the user terminal wakes up from the standby state, the automatic sleep control system receives a paging baseband signal from an external base station and sends it to the baseband processing module for modulation and demodulation of the paging baseband signal, while simultaneously calibrating the second clock using the first clock, and generating a calibration completion signal when the clock calibration is completed; Step S2, the automatic sleep control system controls the baseband processing module to enter a sleep state after detecting that the modulation and demodulation processing of the paging baseband signal is completed; In step S3, when the calibration completion signal is received and the sleep enable signals output by the hardware circuit modules of the user terminal are voted through, the automatic sleep control system controls the power management chip of the user terminal to stop power supply and turn off the first clock to control the user terminal to enter the standby state.

6. The automatic sleep control method according to claim 5, characterized in that: The step S3 comprises: In step S31, the automatic sleep control system receives the sleep enable signal outputted by the sleep enable output terminal of each hardware circuit module, and determines whether the result of the AND operation of each sleep enable signal is sleep enable: If yes, output the voting results of each of the sleep enable signals, and then go to step S32; If not, return to step S31; Step S32 : upon receiving the calibration completion signal and the voting result, the automatic sleep control system controls the power management chip to stop supplying power and turn off the first clock, so as to control the user terminal to enter the standby state.

7. A user terminal, characterized in that: The automatic sleep control system comprises the automatic sleep control system according to any one of claims 1 to 4.

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