Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate, and a plurality of light emitting units and a plurality of light detecting units on the substrate. At least one light emitting unit includes a light emitting element and a pixel circuit connected to the light emitting element, and at least one light detecting unit includes an optical sensing element and a light emitting detecting circuit connected to the optical sensing element. The optical sensing element is provided with at least one inorganic hydrogen barrier layer close to a side of the substrate. The light emitting element has a first light emitting area and a second light emitting area, the first light emitting area of the light emitting element emits light from a side away from the substrate, and the second light emitting area of the light emitting element emits light from a side close to the substrate; the second light emitting area of the light emitting element is completely within the first light emitting area in a projection of the substrate. The projection of the optical sensing element on the substrate at least partially overlaps the projection of the second light emitting area of the at least one light emitting element on the substrate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays have advantages such as low power consumption, self-illumination, good temperature characteristics, fast response, flexibility, ultra-thinness and low cost, and are widely used in display fields such as mobile phones, tablets, and digital cameras, attracting increasing attention. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a substrate and a plurality of light-emitting units and a plurality of light-detecting units located on the substrate. At least one of the plurality of light-emitting units includes: a light-emitting element and a pixel circuit connected to the light-emitting element. At least one of the plurality of light-detecting units includes: an optical sensing element and a light-emitting detection circuit connected to the optical sensing element. The optical sensing element is located on the side of the light-emitting element closer to the substrate; at least one inorganic hydrogen-blocking layer is disposed on the side of the optical sensing element closer to the substrate. The light-emitting element has a first light-emitting region and a second light-emitting region. The first light-emitting region of the light-emitting element emits light from the side away from the substrate, and the second light-emitting region of the light-emitting element emits light from the side closer to the substrate; the orthographic projection of the second light-emitting region of the light-emitting element on the substrate completely falls within the orthographic projection of the first light-emitting region on the substrate. The orthographic projection of at least one of the optical sensing elements on the substrate and the orthographic projection of the second light-emitting region of at least one of the light-emitting elements on the substrate at least partially overlap.

[0006] In some exemplary embodiments, the optical sensing element includes: a first cathode, a photoelectric conversion structure, and a first anode sequentially stacked along a direction away from the substrate; the first anode is made of a light-transmitting material. The at least one inorganic hydrogen-blocking layer is located on the side of the photoelectric conversion structure closest to the substrate.

[0007] In some exemplary embodiments, in a direction perpendicular to the display substrate, the light-emitting detection circuit includes at least: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first cathode of the optical sensing element is co-layered with the first source / drain metal layer. The inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate.

[0008] In some exemplary embodiments, the orthographic projection of the second passivation layer onto the substrate does not overlap with the orthographic projection of the photoelectric conversion structure onto the substrate.

[0009] In some exemplary embodiments, the second passivation layer includes a first inorganic layer and a second inorganic layer stacked together, the first inorganic layer and the second inorganic layer having approximately the same thickness.

[0010] In some exemplary embodiments, the thickness of the first inorganic layer and the second inorganic layer is 1,000 to 3,000 angstroms, and the material of the first inorganic layer and the second inorganic layer is silicon oxide.

[0011] In some exemplary embodiments, in a direction perpendicular to the display substrate, the light-emitting detection circuit includes at least: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate. The inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element.

[0012] In some exemplary embodiments, the third and fourth passivation layers are made of silicon oxide, and the thickness of the third and fourth passivation layers is 1,000 angstroms to 3,000 angstroms.

[0013] In some exemplary embodiments, an organic hydrogen barrier layer is disposed between the fourth passivation layer and the first cathode of the optical sensing element. The orthogonal projection of the organic hydrogen barrier layer onto the substrate covers the orthogonal projection of the photoelectric conversion structure of the optical sensing element onto the substrate; the organic hydrogen barrier layer satisfies at least one of the following: a curing temperature below 230 degrees Celsius; and a thermal decomposition temperature above 450 degrees Celsius.

[0014] In some exemplary embodiments, the etching rate of the interlayer insulating layer is

[0015] In some exemplary embodiments, the light-emitting detection circuit includes at least one transistor. The orthographic projection of the photoelectric conversion structure onto the substrate does not overlap with the orthographic projection of the transistor of the light-emitting detection circuit onto the substrate.

[0016] In some exemplary embodiments, the photoelectric conversion structure includes: a first photoelectric conversion structure and a second photoelectric conversion structure arranged sequentially along a first direction, wherein the transistor of the light emission detection circuit is located between the orthogonal projections of the first photoelectric conversion structure and the second photoelectric conversion structure on the substrate.

[0017] In some exemplary embodiments, the first photoelectric conversion structure and the second photoelectric conversion structure are rectangular in their orthogonal projection onto the substrate.

[0018] In some exemplary embodiments, the light-emitting element includes: a second anode, a light-emitting functional layer, and a second cathode sequentially stacked along a direction away from the substrate. The second cathode is made of a light-transmitting material. The second anode includes a stacked reflective layer and a light-transmitting layer, wherein the orthographic projection of the reflective layer on the substrate does not overlap with the orthographic projection of the second light-emitting area on the substrate, and the orthographic projection of the light-transmitting layer on the substrate covers the orthographic projection of the second light-emitting area on the substrate.

[0019] In some exemplary embodiments, the orthographic projection of the optical sensing element on the substrate at least partially overlaps with the orthographic projection of the light-emitting detection circuit on the substrate, while the orthographic projection of the optical sensing element on the substrate does not overlap with the orthographic projection of the pixel circuit on the substrate.

[0020] In some exemplary embodiments, the orthographic projection of at least one optical sensing element onto the substrate at least partially overlaps with the orthographic projection of the second light-emitting area of ​​eight light-emitting elements onto the substrate.

[0021] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0022] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: forming a circuit structure layer and at least one inorganic hydrogen barrier layer on a substrate, wherein the circuit structure layer includes at least: a pixel circuit of a light-emitting unit and a light-emitting detection circuit of a light-detecting unit; forming an optical sensing element of the light-detecting unit on the side of the circuit structure layer away from the substrate; and forming a light-emitting element of the light-emitting unit on the side of the optical sensing element away from the substrate. The light-emitting element has a first light-emitting region and a second light-emitting region, wherein the first light-emitting region emits light from the side away from the substrate, and the second light-emitting region emits light from the side closer to the substrate; the orthographic projection of the first light-emitting region on the substrate includes the orthographic projection of the second light-emitting region on the substrate. The orthographic projection of at least one optical sensing element on the substrate and the orthographic projection of the second light-emitting region of at least one light-emitting element on the substrate at least partially overlap.

[0023] In some exemplary embodiments, the circuit structure layer includes: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first cathode of the optical sensing element is co-located with the first source / drain metal layer; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate. Alternatively, the first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element.

[0024] In some exemplary embodiments, forming at least one inorganic hydrogen barrier layer on the substrate includes: forming a second passivation layer by deposition, the second passivation layer comprising a stacked first inorganic layer and a second inorganic layer. The deposition method of the first inorganic layer satisfies the following conditions: deposition power of 500 W to 1000 W; deposition pressure of 1000 MToR to 2000 MToR; and a SiH to N2O gas flow rate ratio of 1:30 to 1:50. The deposition method of the second inorganic layer satisfies the following conditions: deposition power of 1000 W to 2000 W; deposition pressure of 1000 MToR to 2000 MToR; and a SiH to N2O gas flow rate ratio of 1:30 to 1:50.

[0025] In some exemplary embodiments, at least one inorganic hydrogen barrier layer is formed on the substrate, including: forming a third passivation layer by deposition. The deposition method of the third passivation layer meets the following conditions: deposition power of 500 watts to 1000 watts; deposition pressure of 1000 mTorr to 2000 mTorr; and SiH to N2O gas flow rate ratio of 1:30 to 1:50.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 2 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 3 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] Figure 4 This is an equivalent circuit diagram of a light emission detection circuit according to at least one embodiment of the present disclosure;

[0032] Figure 5 This is a schematic diagram showing an arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of the present disclosure;

[0033] Figure 6 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 7 These are scanning electron microscope (SEM) images of interlayer insulating layers obtained under different deposition power conditions according to at least one embodiment of this disclosure;

[0035] Figure 8 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 9 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0037] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0038] Figure 11This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0039] Figure 12 This is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0040] Figure 13A This is a partial top view of a display substrate after the shielding layer has been formed, according to at least one embodiment of the present disclosure;

[0041] Figure 13B This is a partial top view of a display substrate after the semiconductor layer has been formed according to at least one embodiment of the present disclosure;

[0042] Figure 13C This is a partial top view of a display substrate after the gate metal layer has been formed, according to at least one embodiment of this disclosure;

[0043] Figure 13D This is a partial top view of a display substrate after the third insulating layer has been formed, according to at least one embodiment of this disclosure;

[0044] Figure 13E This is a partial top view of a display substrate after the first source / drain metal layer has been formed, according to at least one embodiment of this disclosure.

[0045] Figure 13F This is a partial top view of a display substrate after an organic hydrogen barrier layer has been formed, according to at least one embodiment of this disclosure.

[0046] Figure 13G This is a partial top view of a display substrate after the fourth passivation layer has been formed, according to at least one embodiment of this disclosure;

[0047] Figure 13H This is a partial top view of a display substrate after the first cathode, in which the second source / drain metal layer and optical sensing element are formed, is at least one embodiment of the present disclosure.

[0048] Figure 13I This is a partial top view of a display substrate after the photoelectric conversion structure has been formed according to at least one embodiment of the present disclosure;

[0049] Figure 13J This is a partial top view of a display substrate after the first anode of an optical sensing element has been formed, according to at least one embodiment of the present disclosure.

[0050] Figure 13K This is a partial top view of a display substrate after the formation of the first planarization layer, according to at least one embodiment of the present disclosure.

[0051] Figure 13L This is a partial top view of a display substrate after the light-transmitting layer and anode connection electrode have been formed according to at least one embodiment of the present disclosure;

[0052] Figure 13MThis is a partial top view of a display substrate after the reflective layer has been formed according to at least one embodiment of the present disclosure;

[0053] Figure 13N This is a partial top view of a display substrate after the pixel definition layer has been formed, according to at least one embodiment of this disclosure;

[0054] Figure 14 for Figure 13I A partial cross-sectional view along the R-R' direction;

[0055] Figure 15 This is a diagram showing the electrical characteristics of the transistors in the pixel circuit of a display substrate according to at least one embodiment of the present disclosure;

[0056] Figure 16 The diagram shows the electrical characteristics of the transistors in the light-emitting detection circuit of the display substrate according to at least one embodiment of the present disclosure.

[0057] Figure 17 This is a schematic diagram of the test position of a display substrate according to at least one embodiment of the present disclosure;

[0058] Figure 18 This is a schematic diagram of another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of the present disclosure;

[0059] Figure 19 This is a schematic diagram of another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of the present disclosure;

[0060] Figure 20 This is a schematic diagram of another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of the present disclosure;

[0061] Figure 21 This is a schematic diagram of another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of the present disclosure;

[0062] Figure 22 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0063] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0064] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0065] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0066] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0067] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0068] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0069] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0070] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0071] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0072] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0073] In this disclosure, "agreement" means that the limits are not strictly defined and that the process and measurement errors are allowed within a certain range.

[0074] OLED brightness compensation methods can be divided into electrical compensation and optical compensation. Electrical compensation can compensate for changes in threshold voltage and mobility, while optical compensation does not distinguish the causes of brightness changes and can compensate for more factors causing brightness unevenness. In optical compensation, the light emission detection circuit can detect the brightness signal of the OLED device through an optical sensing element to perform brightness compensation based on the brightness signal. Taking a PIN photodiode as the optical sensing element as an example, in the current manufacturing process, the gas atmosphere of each film layer of the PIN photodiode is mainly silicon tetrahydrogenide (SiH4) and hydrogen (H2). Therefore, the display substrate is exposed to a hydrogen atmosphere for a long time. Hydrogen can easily penetrate into the oxide active layer of the thin film transistor (TFT), making the oxide active layer conductive. The conductive oxide active layer will cause the TFT to be in a high current state, affecting the electrical performance of the TFT.

[0075] This disclosure provides a display substrate, including: a substrate and a plurality of light-emitting units and a plurality of light-detecting units located on the substrate. At least one light-emitting unit includes: a light-emitting element and a pixel circuit connected to the light-emitting element. At least one light-detecting unit includes: an optical sensing element and a light-emitting detection circuit connected to the optical sensing element. The optical sensing element is located on the side of the light-emitting element closest to the substrate, and at least one inorganic hydrogen-blocking layer is disposed on the side of the optical sensing element closest to the substrate. The light-emitting element has a first light-emitting region and a second light-emitting region. The first light-emitting region of the light-emitting element emits light from the side away from the substrate, and the second light-emitting region of the light-emitting element emits light from the side closest to the substrate. The orthographic projection of the second light-emitting region of the light-emitting element onto the substrate completely falls within the orthographic projection of the first light-emitting region onto the substrate. The orthographic projection of at least one optical sensing element onto the substrate and the orthographic projection of the second light-emitting region of at least one light-emitting element onto the substrate at least partially overlap.

[0076] This embodiment of the invention achieves optical compensation by designing a top-emitting display substrate and setting an inorganic hydrogen barrier layer on the side of the optical sensing element close to the substrate. This blocks hydrogen during the fabrication process of the optical sensing element, reduces hydrogen penetration into the transistor, ensures the normal electrical characteristics of the transistor, thereby improving the yield of the display substrate and enhancing the display effect.

[0077] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 1 As shown, pixel circuit 21 and light-emitting detection circuit 22 are disposed on substrate 10, and optical sensing element 23 is located on the side of pixel circuit 21 and light-emitting detection circuit 22 away from substrate 10. The orthographic projection of optical sensing element 23 onto substrate 10 overlaps with the orthographic projection of light-emitting detection circuit 22 onto substrate 10. Light-emitting element 24 is located on the side of optical sensing element 23 away from substrate 10. Cover plate 30 is located on the side of light-emitting element 24 away from substrate 10. The orthographic projection of light-emitting element 24 onto substrate 10 overlaps with the orthographic projection of optical sensing element 23 onto substrate 10.

[0078] like Figure 1As shown, the light-emitting element 24 may have a first light-emitting region 100 and a second light-emitting region 200. The first light-emitting region 100 of the light-emitting element 24 emits light from the side away from the substrate 10, and the second light-emitting region 200 of the light-emitting element 24 emits light from the side closer to the substrate 10. The orthographic projection of the second light-emitting region 200 of the light-emitting element 24 onto the substrate 10 completely falls within the orthographic projection of the first light-emitting region 100 onto the substrate 10. That is, the light-emitting element 24 can emit light from both sides. The orthographic projection of the optical sensing element 23 onto the substrate 10 and the orthographic projection of the second light-emitting region of the light-emitting element 24 onto the substrate 10 at least partially overlap. In some embodiments, the region of the light-emitting element 24 corresponding to the optical sensing element 23, that is, the portion of the light-emitting element 24 where its first light-emitting region 100 and second light-emitting region 200 overlap, can be configured to emit light from both sides. In this way, the optical sensing element 23 located on the side of the light-emitting element 24 close to the substrate 10 can receive the light emitted by the light-emitting element 24, and the light emission detection circuit 22 can detect the brightness signal of the light-emitting element 24 through the optical sensing element 23 so as to perform brightness compensation on the light-emitting element 24 according to the brightness signal.

[0079] In this exemplary embodiment, such as Figure 1 As shown, the first light-emitting area of ​​the light-emitting element 24 emits light upward (i.e., emits light to the side away from the substrate 10) to achieve display; part of the light emitted by the second light-emitting area of ​​the light-emitting element 24 downward (i.e., to the side facing the substrate 10) can be provided to the optical sensing element 23 so that the optical sensing element 23 can detect the light intensity, and the remaining light can be directly reflected back to the upper surface of the light-emitting element 24 for display.

[0080] Figure 2 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2 As shown, pixel circuit 21 and light-emitting detection circuit 22 are disposed on substrate 10. The orthographic projection of optical sensing element 23 onto substrate 10 may not overlap with the orthographic projections of light-emitting detection circuit 22 and pixel circuit 21 onto substrate 10. Light-emitting element 24 is located on the side of optical sensing element 24 away from substrate 10, and cover plate 30 is located on the side of light-emitting element 24 away from substrate 10. In this example, light-emitting element 24 has a first light-emitting area 100 and a second light-emitting area 200. The portion of light-emitting element 24 where its first light-emitting area 100 and second light-emitting area 200 overlap may be configured to emit light from both sides. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0081] The display substrate provided in this embodiment adopts a top-emitting structure and is equipped with double-sided light-emitting elements to achieve optical compensation, which not only helps to improve the pixel aperture ratio and resolution, but also supports better display effects.

[0082] In some exemplary embodiments, the optical sensing element may include a first cathode, a photoelectric conversion structure, and a first anode sequentially stacked along a direction away from the substrate. The first anode may be made of a light-transmitting material, and the first cathode may be made of a light-shielding material. At least one inorganic hydrogen-blocking layer may be located on the side of the photoelectric conversion structure closest to the substrate. In some examples, the optical sensing element may be a PIN photodiode. The photoelectric conversion structure may include a first doped layer, an intrinsic layer, and a second doped layer stacked together. However, this embodiment is not limited thereto.

[0083] In some exemplary embodiments, in a direction perpendicular to the display substrate, the light-emitting detection circuit includes at least: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate; the first cathode of the optical sensing element and the first source / drain metal layer are co-layered. The inorganic hydrogen barrier layer may include at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate. For example, the inorganic hydrogen barrier layer may include an interlayer insulating layer, or a second passivation layer, or both. However, this embodiment is not limited in this respect.

[0084] In some exemplary embodiments, the orthographic projection of the second passivation layer onto the substrate does not overlap with the orthographic projection of the photoelectric conversion structure onto the substrate. In this embodiment, the photoelectric conversion structure is formed after the second passivation layer is fabricated.

[0085] In some exemplary embodiments, in a direction perpendicular to the display substrate, the light-emitting detection circuit includes at least: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate. The inorganic hydrogen barrier layer may include at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element. For example, the inorganic hydrogen barrier layer may include an interlayer insulating layer, a third passivation layer, and a fourth passivation layer; or, it may include a third passivation layer and a fourth passivation layer; or, it may include a fourth passivation layer; or, it may include a third passivation layer. However, this embodiment is not limited thereto.

[0086] In some exemplary embodiments, an organic hydrogen barrier layer is disposed between the fourth passivation layer and the first cathode of the optical sensing element. The orthogonal projection of the organic hydrogen barrier layer onto the substrate covers the orthogonal projection of the photoelectric conversion structure of the optical sensing element onto the substrate. The organic hydrogen barrier layer satisfies at least one of the following: a curing temperature below 230 degrees Celsius; and a thermal decomposition temperature above 450 degrees Celsius. In this example, hydrogen blocking during the fabrication process of the optical sensing element is achieved by providing both an inorganic hydrogen barrier layer and an organic hydrogen barrier layer.

[0087] In some exemplary embodiments, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. The light emission detection circuit can adopt a 1T1C design. However, this embodiment is not limited to this.

[0088] Figure 3 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In this exemplary embodiment, the pixel circuit can employ a 3T1C design. Figure 3 As shown, the pixel circuit of this embodiment may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first storage capacitor C1. In this example, the first transistor M1 may be a switching transistor, the second transistor M2 may be a driving transistor, and the third transistor M3 may be a compensation transistor.

[0089] like Figure 3 As shown, the control electrode of the first transistor M1 is electrically connected to the first scan line G1, the first electrode of the first transistor M1 is electrically connected to the data line DL, and the second electrode of the first transistor M1 is electrically connected to the control electrode of the second transistor M2. The first electrode of the second transistor M2 is electrically connected to the first power line VDD, and the second electrode of the second transistor M2 is electrically connected to the second electrode of the third transistor M3. The control electrode of the third transistor M3 is electrically connected to the first scan line G1, and the first electrode of the third transistor M3 is electrically connected to the compensation line Se1. The first electrode of the first storage capacitor C1 is electrically connected to the control electrode of the second transistor M2, and the second electrode of the first storage capacitor C1 is electrically connected to the second electrode of the second transistor M2. The first electrode (anode) of the light-emitting element EL is electrically connected to the second electrode of the second transistor M2, and the second electrode (cathode) of the light-emitting element EL is electrically connected to the second power line VSS.

[0090] In some exemplary embodiments, the first power line VDD can continuously provide a high-level signal, and the second power line VSS can continuously provide a low-level signal. The first transistor M1 to the third transistor M3 can be P-type transistors or N-type transistors. However, this embodiment is not limited to this.

[0091] Figure 4 This is an equivalent circuit diagram of a light emission detection circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 4 As shown, the light emission detection circuit may include a fourth transistor M4 and a second storage capacitor C2. The control electrode of the fourth transistor M4 is electrically connected to the second scan line G2, the first electrode of the fourth transistor M4 is electrically connected to the sensing line Se2, and the second electrode of the fourth transistor M4 is electrically connected to the second electrode (cathode) of the optical sensing element DP. The first electrode of the second storage capacitor C2 is electrically connected to the second electrode of the optical sensing element DP, and the second electrode of the second storage capacitor C2 is electrically connected to the first electrode (anode) of the optical sensing element DP. The second storage capacitor C2 is configured to store the electrical signal converted by the optical sensing element DP. The anode of the optical sensing element DP is electrically connected to the reference voltage line V0. In this example, the optical sensing element DP may be a PIN photodiode. However, this disclosure is not limited thereto.

[0092] Figure 5 This is a schematic diagram illustrating the arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 5 As shown, the display substrate includes a plurality of pixel units arranged in a regular pattern. A pixel unit may include four light-emitting units that emit light of different colors. For example, a pixel unit may include: a first light-emitting unit P1 emitting a first color of light, a second light-emitting unit P2 emitting a second color of light, a third light-emitting unit P3 emitting a third color of light, and a fourth light-emitting unit P4 emitting a fourth color of light. The four light-emitting units in a pixel unit may be arranged horizontally side-by-side, with light-emitting units emitting the same color of light located in the same column. For example, the first light-emitting unit P1 and the fifth light-emitting unit P5 both emit red light, the second light-emitting unit P2 and the sixth light-emitting unit P6 both emit green light, the third light-emitting unit P3 and the seventh light-emitting unit P7 both emit blue light, and the fourth light-emitting unit P4 and the eighth light-emitting unit P8 both emit white light. However, this embodiment is not limited to this.

[0093] In some exemplary implementations, such as Figure 5 As shown, the eight light-emitting units (i.e., the first light-emitting unit P1 to the eighth light-emitting unit P8) arranged in an array can reuse one light detection unit PD. The orthographic projection of the optical sensing element of the light detection unit PD onto the substrate overlaps with the orthographic projection of the second light-emitting area of ​​the light-emitting element of the eight light-emitting units onto the substrate, so as to realize the brightness detection of the eight light-emitting elements.

[0094] In some exemplary implementations, such as Figure 5As shown, the light detection unit PD is configured to detect the light emitted by eight light-emitting units (i.e., the first light-emitting unit P1 to the eighth light-emitting unit P8), thereby realizing brightness detection and compensation for a single light-emitting unit. In some examples, for the eight light-emitting units (i.e., the first light-emitting unit P1 to the eighth light-emitting unit P8), the brightness value of a single light-emitting unit can be obtained through eight brightness detection processes. In the eight brightness detection processes, seven of the eight light-emitting units are lit each time, and a single light-emitting unit is turned off only once in the eight brightness detection processes (i.e., a single light-emitting unit is lit seven times in the eight brightness detection processes and turned off only once). The light detection unit can obtain a sensed brightness value through a single brightness detection; then, using the eight sensed brightness values ​​detected by the light detection unit, the brightness value of a single light-emitting unit can be calculated. Taking the brightness values ​​of the first light-emitting unit as a1, the second light-emitting unit as a2, the third light-emitting unit as a3, the fourth light-emitting unit as a4, the fifth light-emitting unit as a5, the sixth light-emitting unit as a6, the seventh light-emitting unit as a7, and the eighth light-emitting unit as a8 as an example, the following formula can be obtained through eight brightness measurements:

[0095] a1+a2+a3+a4+a5+a6+a7=b1;

[0096] a1+a2+a3+a4+a5+a6+a8=b2;

[0097] a1+a2+a3+a4+a5+a7+a8=b3;

[0098] a1+a2+a3+a4+a6+a7+a8=b4;

[0099] a1+a2+a3+a5+a6+a7+a8=b5;

[0100] a1+a2+a4+a5+a6+a7+a8=b6;

[0101] a1+a3+a4+a5+a6+a7+a8=b7;

[0102] a2+a3+a4+a5+a6+a7+a8=b8.

[0103] Among them, b1 to b8 are the sensed brightness values ​​detected by the light detection unit during the eight brightness detection processes.

[0104] Based on the above formula, we can calculate:

[0105] a1=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b8;

[0106] a2=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b7;

[0107] a3=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b6;

[0108] a4=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b5;

[0109] a5=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b4;

[0110] a6=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b3;

[0111] a7=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b2;

[0112] a8=((b1+b2+b3+b4+b5+b6+b7+b8) / 8)-b1.

[0113] In this way, by using a light detection unit to perform eight brightness detections, and obtaining eight sensed brightness values ​​through the eight brightness detection processes, the brightness values ​​of the eight light-emitting units can be obtained, so that brightness compensation can be performed on the eight light-emitting units respectively.

[0114] If the detection time for the light detection unit to detect the brightness value of one light-emitting unit each time is T, then the total time required to detect the brightness value of eight light-emitting units sequentially is 8T. Using the above detection method, the light detection unit can activate two rows of light-emitting units each time, and the brightness value detected in a single detection is the total brightness value of seven light-emitting units. Therefore, the time required for eight detections is approximately (1 / 7)T*8*2=(16 / 7)T. It can be seen that compared to the method of detecting individual light-emitting units sequentially, the detection time required by the above method can be shortened by about 3.5 times, saving detection time and improving the efficiency of optical sensing.

[0115] The structure of the display substrate is illustrated below using a cross-sectional view.

[0116] Figure 6 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 6As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a circuit structure layer, a sensing structure layer, a first passivation layer 14, a first planarization layer 15, and a light-emitting structure layer sequentially disposed on the substrate 10. The circuit structure layer may include multiple pixel circuits and multiple light-emitting detection circuits. The sensing structure layer may include multiple optical sensing elements. The light-emitting structure layer may include multiple light-emitting elements. Figure 6 The illustration uses only one light-emitting element, one optical sensing element, and one transistor of the light-emitting detection circuit as an example. The first passivation layer 14 and the first planarization layer 15 can cover the circuit structure layer and the sensing structure layer, and the first planarization layer 15 is located on the side of the first passivation layer 14 away from the substrate 10. The first passivation layer 14 can be an inorganic insulating layer, and the first planarization layer 15 can be an organic insulating layer.

[0117] In some exemplary implementations, such as Figure 6 As shown, the circuit structure layer may include: a shielding layer 220 disposed on the substrate 10, a first insulating layer 11 covering the shielding layer 220, a semiconductor layer disposed on the side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 disposed on the side of the semiconductor layer away from the substrate 10, a gate metal layer disposed on the side of the second insulating layer 12 away from the substrate 10, a third insulating layer 13 covering the gate metal layer, and a first source / drain metal layer disposed on the side of the third insulating layer 13 away from the substrate 10. The semiconductor layer includes at least an active layer 221; the gate metal layer includes at least a gate electrode 222; and the first source / drain metal layer includes at least a source electrode 223 and a drain electrode 224. In this example, the active layer 221, the gate electrode 222, the source electrode 223, and the drain electrode 224 may form a transistor, for example, a fourth transistor M4 in a light-emitting detection circuit. In some examples, the first insulating layer 11 may also be called a buffer layer, the second insulating layer 12 may also be called a gate insulating layer, and the third insulating layer 13 may also be called an interlayer insulating layer. The first insulating layer 11 to the third insulating layer 13 can be inorganic insulating layers.

[0118] In some exemplary implementations, such as Figure 6As shown, the optical sensing element may include: a first cathode 231, a photoelectric conversion structure 232, and a first anode 233 stacked sequentially. In this example, the first cathode 231 and the drain electrode 224 of the fourth transistor M4 can be an integral structure. The photoelectric conversion structure 232 may include: a first doped layer 2321, an intrinsic layer 2322, and a second doped layer 2323 stacked sequentially. The first doped layer 2321 can be an N-type semiconductor layer, the second doped layer 2323 can be a P-type semiconductor layer, and the intrinsic layer 2322 can be a low-concentration I-type semiconductor layer. High-concentration P-type and N-type semiconductors are doped on both sides of the intrinsic layer 2322, forming P-type and N-type semiconductor layers. The P-type and N-type semiconductor layers are very thin, absorbing a small proportion of incident light, so that most of the incident light is absorbed within the intrinsic layer, generating a large number of electron-hole pairs. The intrinsic layer is relatively thick, almost occupying the entire depletion region, thereby increasing the width of the depletion region to reduce the influence of diffusion motion and improve the photodiode response speed. The first anode 233 is electrically connected to the anode connecting electrode 234. The anode connecting electrode 234 is electrically connected to the first anode 233 through vias formed in the first planarization layer 15 and the first passivation layer 14. The first connecting electrode 234 and the light-transmitting layer 2411 of the second anode 241 of the light-emitting element can be of the same layer structure. The first anode 233 and the anode connecting electrode 234 can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first anode 233 can be electrically connected to the reference voltage line V0 through the anode connecting electrode 234.

[0119] In some exemplary implementations, such as Figure 6As shown, the light-emitting element may include a second anode 241, a light-emitting functional layer 242, and a second cathode 243 stacked sequentially. The second anode 241 may include a light-transmitting layer 2411 and a reflective layer 2412 stacked together. The reflective layer 2412 may be located on the side of the light-transmitting layer 2411 away from the substrate 10. The light-emitting functional layer 242 contacts the second anode 241 within a pixel opening in the pixel definition layer 244. The light-emitting element has a first light-emitting region 100 and a second light-emitting region 200. The first light-emitting region 100 is formed by the stacked light-transmitting layer 2411, reflective layer 2412, light-emitting functional layer 242, and second cathode 243, and the second light-emitting region 200 is formed by the stacked light-transmitting layer 2411, light-emitting functional layer 242, and second cathode 243. The orthographic projection of the reflective layer 2412 onto the substrate 10 does not overlap with the second light-emitting region 200, and may not overlap with the orthographic projection of the optical sensing element onto the substrate 10. The orthographic projection of the light-transmitting layer 2411 onto the substrate 10 covers the orthographic projection of the second light-emitting area 200 onto the substrate 10. In some examples, the light-transmitting layer 2411 can be made of a transparent conductive material, such as ITO, IZO, etc. The reflective layer 2412 can be made of a metallic material, such as magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), lithium (Li), etc., or alloys of the above metals, such as aluminum-niobium alloy AlNd, molybdenum-niobium alloy MoNb, etc. It can be a multilayer metal, such as Mo / Cu / Mo, or a stacked structure formed of metal and transparent conductive material, such as reflective materials like ITO / Ag / ITO, Mo / AlNd / ITO, etc. However, this embodiment is not limited to this. For example, the light-transmitting layer can be located on the side of the reflective layer away from the substrate.

[0120] In some exemplary implementations, such as Figure 6 As shown, the third insulating layer 13 (i.e., the interlayer insulating layer) can serve as an inorganic hydrogen barrier layer. By controlling the fabrication conditions, a denser third insulating layer can be formed, thus achieving the hydrogen barrier function. For example, the etching rate of the third insulating layer 13 can be approximately 2 Å / s. The porosity of the third insulating layer 13 can be less than 10 pores within the range of 1 micrometer (µm) * 1 µm. The thickness of the third insulating layer 13 can be approximately 3500 angstroms. to In some examples, the deposition method of the third insulating layer 13 can satisfy at least one of the following conditions: deposition power of approximately 1000 watts (W) to 1500 W (e.g., approximately 1000 W, 1100 W, 1200 W, 1300 W, 1400 W, 1500 W, etc.); deposition pressure of approximately 1800 millitors (mt) to 2400 mt (e.g., approximately 1800 mt, 1900 mt, 2000 mt, 2100 mt, 2400 mt, etc.); and deposition time of approximately 220 seconds (s) to 280 s (e.g., approximately 220 s, 230 s, 240 s, 250 s, 260 s, 270 s, 280 s, etc.). In this example, by achieving a high-density third insulating layer, the influence of the hydrogen atmosphere during the formation of the optical sensing element on the thin-film transistor can be blocked by the third insulating layer, thereby ensuring the electrical performance of the thin-film transistor.

[0121] Figure 7 These are scanning electron microscope (SEM) images of interlayer insulating layers obtained under different deposition power conditions according to at least one embodiment of this disclosure. Figure 7 As shown, under the same conditions, the density of the interlayer insulation layer is significantly improved when the deposition power is approximately 1000W to 1500W.

[0122] In this exemplary embodiment, the third insulating layer (i.e., the interlayer insulating layer) is used as an inorganic hydrogen barrier layer, which can block the influence of hydrogen on the thin-film transistor during the fabrication of the optical sensing element, thereby ensuring the electrical performance of the thin-film transistor and improving the display effect.

[0123] Figure 8 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 8 As shown, in a direction perpendicular to the display substrate, the display substrate includes: a substrate 10, a circuit structure layer, a second passivation layer 16, a sensing structure layer, a first passivation layer 14, a first planarization layer 15, and a light-emitting structure layer sequentially disposed on the substrate. The orthographic projection of the second passivation layer 16 onto the substrate 10 does not overlap with the orthographic projection of the photoelectric conversion structure 232 of the optical sensing element of the sensing structure layer onto the substrate 10. In this example, the inorganic hydrogen barrier layer may include: a third insulating layer 13 and a second passivation layer 16; or, it may include the second passivation layer 16. However, this embodiment is not limited to this.

[0124] In some exemplary embodiments, the second passivation layer 16 may include: a stacked first inorganic layer and a second inorganic layer. The thickness ratio of the first inorganic layer and the second inorganic layer may be approximately 1:1. For example, the thicknesses of the first inorganic layer and the second inorganic layer may be approximately... to For example or The first and second inorganic layers of the second passivation layer 16 can be prepared by deposition. For example, the deposition method of the first inorganic layer can meet the following conditions: deposition power of approximately 500W to 1000W, deposition pressure of approximately 1000mt to 2000mt, and a gas flow ratio of SiH to N2O of approximately 1:30 to 1:50. The deposition method of the second inorganic layer can meet the following conditions: deposition power of approximately 1000W to 2000W, deposition pressure of approximately 1000mt to 2000mt, and a gas flow ratio of SiH to N2O of approximately 1:30 to 1:50. The materials of the first and second inorganic layers can be SiO. However, this embodiment is not limited to this.

[0125] In some exemplary implementations, such as Figure 8 As shown, after fabricating the first source / drain metal layer, a first inorganic layer and a second inorganic layer of the first passivation layer 16 are deposited, followed by fabrication of the photoelectric conversion structure 232 of the optical sensing element. During this process, the first passivation layer 16 can be used to block the influence of the hydrogen atmosphere during the fabrication of the photoelectric conversion structure 232 on the transistor.

[0126] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0127] Figure 9 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 9 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a circuit structure layer, a third passivation layer 17, a sensing structure layer, a first passivation layer 14, a first planarization layer 15, and a light-emitting structure layer sequentially disposed on the substrate 10. The third passivation layer 17 is located on the side of the optical sensing element closer to the substrate 10. The orthographic projection of the third passivation layer 17 onto the substrate 10 overlaps with the orthographic projection of the optical sensing element onto the substrate 10. The first cathode 231 of the optical sensing element may be co-located with the second source / drain metal layer of the circuit structure layer. The second source / drain metal layer is located on the side of the first source / drain metal layer of the circuit structure layer away from the substrate 10. The first cathode 231 may be electrically connected to the drain electrode 224 of the fourth transistor M4 of the light-emitting detection circuit of the first source / drain metal layer through a via on the third passivation layer 17. In this example, the inorganic hydrogen barrier layer may include: the third passivation layer 17; or, it may include the third passivation layer 17 and the third insulating layer 13. However, this embodiment is not limited to this.

[0128] In some exemplary embodiments, the material of the third passivation layer 17 may be SiO. The thickness of the third passivation layer 17 may be approximately [missing information]. to For example or The third passivation layer 17 can be prepared by deposition. For example, the deposition method of the third passivation layer 17 can meet the following conditions: deposition power of approximately 500W to 1000W, deposition pressure of approximately 1000mt to 2000mt, and gas flow ratio of SiH to N2O of approximately 1:30 to 1:50. However, this embodiment is not limited to these conditions.

[0129] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0130] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 10 As shown, in the direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a circuit structure layer, a third passivation layer 17, a fourth passivation layer 18, a sensing structure layer, a first passivation layer 14, a first planarization layer 15, and a light-emitting structure layer sequentially disposed on the substrate 10. The orthographic projection of the third passivation layer 17 onto the substrate 10 overlaps with the orthographic projection of the optical sensing element onto the substrate 10. The orthographic projection of the fourth passivation layer 18 onto the substrate 10 overlaps with the orthographic projection of the optical sensing element onto the substrate 10. In some examples, the circuit structure layer may include: a shielding layer 220 disposed on the substrate 10, a semiconductor layer, a gate metal layer, a first source / drain metal layer, and a second source / drain metal layer. The first cathode 231 and the second source / drain metal layer of the optical sensing element may be of the same layer structure. However, this embodiment is not limited to this.

[0131] In this example, the inorganic hydrogen barrier layer may include: a fourth passivation layer 18; or, it may include a third passivation layer 17 and a fourth passivation layer 18; or, it may include a third passivation layer 17, a fourth passivation layer 18, and a third insulating layer 13. However, this embodiment is not limited in this respect.

[0132] In some exemplary embodiments, the materials of the third passivation layer 17 and the fourth passivation layer 18 may be SiO. The thicknesses of the third passivation layer 17 and the fourth passivation layer 18 may be approximately [missing information]. to For example or The third passivation layer 17 and the fourth passivation layer 18 can be prepared by deposition. For example, the deposition method of the third passivation layer 17 or the fourth passivation layer 18 can meet the following conditions: deposition power of approximately 500W to 1000W, deposition pressure of approximately 1000mt to 2000mt, and gas flow ratio of SiH to N2O of approximately 1:30 to 1:50. However, this embodiment is not limited to these conditions.

[0133] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0134] Figure 11 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 11 As shown, in the direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a circuit structure layer, a third passivation layer 17, an organic hydrogen barrier layer 19, a fourth passivation layer 18, a sensing structure layer, a first passivation layer 14, a first planarization layer 15, and a light-emitting structure layer sequentially disposed on the substrate 10. In this example, the organic hydrogen barrier layer 19 is disposed between the third passivation layer 17 and the fourth passivation layer 18. The orthographic projection of the organic hydrogen barrier layer 19 onto the substrate 10 overlaps with the orthographic projection of the optical sensing element onto the substrate 10. For example, the orthographic projection of the organic hydrogen barrier layer 19 onto the substrate 10 may be elongated and located below the optical sensing element. However, this embodiment is not limited to this. In some examples, the organic hydrogen barrier layer may also be a monolithic structure, that is, the orthographic projection of the monolithic organic hydrogen barrier layer onto the substrate may cover the orthographic projections of multiple optical sensing elements onto the substrate. The organic hydrogen barrier layer completely covers the underlying thin-film transistor, which can prevent the hydrogen atmosphere in the process of forming optical sensing elements from affecting the electrical performance of the thin-film transistor and can effectively improve the high current problem of thin-film transistors.

[0135] In this example, the inorganic hydrogen barrier layer may include: a fourth passivation layer 18; or, it may include: a third passivation layer 17 and a fourth passivation layer 18; or, it may include: a third passivation layer 17, a fourth passivation layer 18, and a third insulating layer 13. However, this embodiment is not limited in this respect.

[0136] In some exemplary embodiments, the organic hydrogen barrier layer 19 may have a low curing temperature and a high thermal decomposition temperature. The organic hydrogen barrier layer 19 may satisfy at least one of the following conditions: a curing temperature below 230 degrees Celsius; and a thermal decomposition temperature above 450 degrees Celsius. By setting the curing temperature of the organic hydrogen barrier layer 19 below 230 degrees Celsius, the curing process of the organic hydrogen barrier layer 19 will not adversely affect the thin-film transistor, thereby effectively improving the problem of abnormalities caused by large currents in thin-film transistors in environments above 230 degrees Celsius. By setting the thermal decomposition temperature of the organic hydrogen barrier layer 19 above 450 degrees Celsius, the organic hydrogen barrier layer 19 can effectively withstand the high temperatures of the optical sensing element deposition process, without denaturing or decomposing under the deposition temperature conditions, exhibiting good high-temperature resistance and stability.

[0137] In some examples, the organic hydrogen barrier layer 19 can be made of organic insulating materials, such as silicon-on-glass (SOG) bonding materials or resin materials. The organic hydrogen barrier layer 19 can effectively block the influence of hydrogen on thin-film transistors, improve the dark current problem of optical sensing elements, and is easy to process.

[0138] In this exemplary embodiment, by setting an inorganic hydrogen barrier layer and an organic hydrogen barrier layer, hydrogen can be blocked during the fabrication process of the optical sensing element, reducing the penetration of hydrogen elements into the transistor, ensuring the normal electrical characteristics of the transistor, thereby improving the yield of the display substrate and enhancing the display effect.

[0139] The following is based on Figure 11 The top view structure of the display substrate in the illustrated embodiment will be used as an example for explanation.

[0140] Figure 12 This is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 12 The diagram shows a top view of eight light-emitting units (i.e., the first light-emitting unit P1 to the eighth light-emitting unit P8) and one light detection unit PD. The eight light-emitting units are arranged in two rows and four columns. The light detection unit PD is located in the middle of the two rows of light-emitting units and overlaps with the second light-emitting area 200 of the light-emitting elements of the eight light-emitting units.

[0141] The following reference Figures 13A to 13N The technical solution of this embodiment is illustrated by the example of the fabrication process of the display substrate. The "patterning process" mentioned in this embodiment includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; and etching can be performed using any one or more of dry and wet etching. This embodiment does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0142] In this embodiment of the disclosure, "A and B are set in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0143] The fabrication process of the display substrate in this embodiment may include the following operations. The pixel circuit in this example is... Figure 3 The 3T1C structure shown has a light-emitting detection circuit as follows: Figure 4 The 1T1C structure shown.

[0144] (1) A shielding layer is formed on the substrate.

[0145] In some exemplary embodiments, a first metal thin film is deposited on a substrate 10, and the first metal thin film is patterned using a patterning process to form a masking layer on the substrate 10, such as... Figure 13A As shown. The shielding layer may include: a first electrode plate 331, a first power adapter cable 31, a data connection cable 32, and a sensing shielding layer 41. The first power adapter cable 31 is a horizontal strip structure spanning a row of four light-emitting units in a first direction X. The data connection cable 32 extends along a second direction Y and is located between adjacent first power adapter cables 31. The first direction X and the second direction Y intersect, for example, perpendicular to each other. The sensing shielding layer 41 is located between the data connection cables 32 and has a block structure. The sensing shielding layer 41 is configured to shield the fourth transistor of the light-emitting detection circuit to ensure the performance of the transistor. The first electrode plate 331 serves as both the first electrode plate of the first storage capacitor, configured to form the first storage capacitor with the subsequently formed second electrode plate, and the first electrode plate 331 also serves as a shielding layer, configured to shield the transistor of the pixel circuit, reduce the light intensity illuminating the transistor, reduce leakage current, and thereby reduce the impact of light on the transistor characteristics.

[0146] (2) Forming a semiconductor layer.

[0147] In some exemplary embodiments, a first insulating film and a semiconductor film are sequentially deposited on the substrate 10 on which the aforementioned pattern is formed. The semiconductor film is patterned using a patterning process to form a first insulating layer 11 covering the shielding layer, and a semiconductor layer formed on the first insulating layer 11, such as... Figure 13BAs shown. The semiconductor layer can be made of metal oxide. The semiconductor layer may include: a first active layer M10 of the first transistor M1 of the pixel circuit, a second active layer M20 of the second transistor M2, a third active layer M30 of the third transistor M3, a second electrode 332, and a fourth active layer M40 of the fourth transistor M4 of the light-emitting detection circuit. The orthographic projection of the second electrode 332 onto the substrate 10 overlaps with the orthographic projection of the first electrode 331 onto the substrate 10. The orthographic projections of the first active layer M10, the second active layer M20, and the third active layer M30 onto the substrate 10 overlap with the orthographic projection of the first electrode 331 onto the substrate 10, so that the first electrode 331 can block the channel regions of the first transistor M1, the second transistor M2, and the third transistor M3, preventing light from affecting the channel and thus preventing the channel from affecting the display effect due to photogenerated leakage current.

[0148] In some exemplary embodiments, the second active layer M20, the third active layer M30, and the second electrode plate 332 are integrally structured to facilitate electrical connection between the drain electrodes of the second transistor M2 and the third transistor M3 via the conductive second electrode plate 332. The orthographic projection of the fourth active layer M40 onto the substrate 10 lies within the orthographic projection range of the sensing light-shielding layer 41 onto the substrate 10, thereby allowing the sensing light-shielding layer 41 to completely block the fourth active layer M40, ensuring the performance of the fourth transistor M4.

[0149] (3) Forming a gate metal layer.

[0150] In some exemplary embodiments, a second insulating film and a second metal film are sequentially deposited on a substrate 10 having the aforementioned pattern. The second insulating film and the second metal film are patterned using a patterning process to form a second insulating layer 12 (also referred to as a gate insulating layer) and a gate metal layer disposed on the second insulating layer 12, such as... Figure 13C As shown. The gate metal layer may include: a control electrode M13 of a first transistor M1, a control electrode M23 of a second transistor M2, a control electrode M33 of a third transistor M3, a control electrode M43 of a fourth transistor M4, a compensation connection line 34, a first scan line G1, a second scan line G2, and a reference voltage line V0. The compensation connection line 34, the first scan line G1, the second scan line G2, and the reference voltage line V0 all extend along a first direction X. The control electrode M13 of the first transistor M1, the control electrode M33 of the third transistor M3, and the first scan line G1 can be an integral structure. The control electrode M43 of the fourth transistor M4 and the second scan line G2 can be an integral structure.

[0151] (4) Forming a third insulating layer.

[0152] In some exemplary embodiments, a third insulating film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer 13 (also referred to as an interlayer insulating layer) covering the aforementioned pattern, such as... Figure 13D As shown. The third insulating layer 13 has multiple via patterns. These via patterns may include: first via V1 to nineteenth via V19. Specifically, the third insulating layer 13 within the first via V1 to sixth via V6 is removed, exposing the surface of the semiconductor layer. The seventh via V7 is a transition via, consisting of two half-holes. One half-hole is formed on the third active layer M30, and the other half-hole is formed on the compensation connection line 34. The third insulating layer 13 within both half-holes is etched away, so that the transition via consisting of the two half-holes simultaneously exposes the surface of the third active layer M30 and the surface of the compensation connection line 34. The third insulating layer 13 within the eighth via V8 to fourteenth via V14 is removed, exposing the surface of the gate metal layer. The third insulating layer 13 and the first insulating layer 11 within the fifteenth via V15 to nineteenth via V19 are removed, exposing the surface of the shielding layer.

[0153] (5) Form the first source / drain metal layer.

[0154] In some exemplary embodiments, a third metal thin film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the third metal thin film is patterned by a patterning process to form a first source / drain metal layer on the third insulating layer 13, such as... Figure 13E As shown. The first source-drain metal layer includes at least: multiple data lines DL, a first power line VDD, a compensation line Se1, a sensing line Se2, a first electrode M21 of a second transistor M2, a second electrode M32 of a third transistor, a third electrode plate 333, a second electrode M42 of a fourth transistor, a first scan connection electrode 35, a second scan connection electrode 36, a fourth electrode plate 431, a fifth electrode plate 432, and a first connection electrode 44.

[0155] In some examples, the data line DL is electrically connected to the first doped region of the first active layer M10 of the first transistor M1 via the first via V1, and also electrically connected to the data connection line 32 via the eighteenth via V18. The compensation line Se1 is connected to the compensation connection line 34 via the eighth via V8 and the seventh via V7, and also electrically connected to the first doped region of the third active layer M30 of the third transistor M3 via the seventh via V7. One compensation line Se1 can be electrically connected to the pixel circuit of eight light-emitting units via the compensation connection line 34. The first power line VDD is electrically connected to the first power adapter line 31 via the sixteenth via V16. The second terminal M32 of the third transistor M3 is electrically connected to the second doped region of the third active layer M30 via the third via V3. The first terminal M21 of the second transistor M2 is electrically connected to the first doped region of the second active layer M20 via the fourth via V4, and also electrically connected to the first power adapter line 31 via the seventh via V7. The second electrode M42 of the fourth transistor M4 is electrically connected to the second doped region of the fourth active layer M40 through the fifth via V5. The sensing line Se2 is electrically connected to the first doped region of the fourth active layer M40 through the sixth via V6. The third electrode 333 is electrically connected to the second doped region of the first active layer M10 of the first transistor M1 through the second via V2, and is also electrically connected to the control electrode M23 of the second transistor M2 through the tenth via V10, and to the first electrode 331 through the fifteenth via V15. In this example, the first electrode 331 and the third electrode 333 are electrically connected as the second electrode of the first storage capacitor C1, and the second electrode 332 serves as the first electrode of the first storage capacitor C1.

[0156] In some examples, the first scan connection electrode 35 is electrically connected to the first scan line G1 via the ninth via V9. The second scan connection electrode 36 is electrically connected to the sensing shielding layer 41 via the nineteenth via V19, and also electrically connected to the second scan line G2 via the eleventh via V11. The fourth electrode plate 431 is electrically connected to the reference voltage line V0 via the twelfth via V12. The fifth electrode plate 432 is electrically connected to the reference voltage line V0 via the fourteenth via V14. The first connection electrode 44 is electrically connected to the reference voltage line V0 via the thirteenth via V13. The fourth electrode plate 431 and the fifth electrode plate 432 can serve as the second electrodes of the second storage capacitor.

[0157] (6) Formation of an organic hydrogen barrier layer.

[0158] In some exemplary embodiments, a fourth insulating film is deposited on the substrate 10 on which the aforementioned pattern is formed to form a third passivation layer 17; subsequently, an organic film is coated, and the organic film is patterned by a patterning process to form an organic hydrogen barrier layer 19, such as... Figure 13FAs shown, the orthographic projection of the organic hydrogen barrier layer 19 onto the substrate 10 covers the orthographic projection of the fourth transistor onto the substrate. The orthographic projection of the organic hydrogen barrier layer 19 onto the substrate 10 can be rectangular. However, this embodiment is not limited to this.

[0159] (7) Formation of the fourth passivation layer.

[0160] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fourth passivation layer 18, such as... Figure 13G As shown. Multiple vias are formed on the fourth passivation layer 18, including: via 21 (twenty-first), via 22 (twenty-second), and via 23 (twenty-third). The fourth passivation layer 18 and the third passivation layer 17 within vias 21 to 23 are removed, exposing the surface of the first source / drain metal layer.

[0161] (8) Forming the first cathode of the second source / drain metal layer and optical sensing element.

[0162] In some exemplary embodiments, a fourth metal thin film is deposited on the substrate 10 with the aforementioned pattern, and the fourth metal thin film is patterned by a patterning process. A second source / drain metal layer and a first cathode 231 of the optical sensing element are formed on the fourth passivation layer 18, as shown below. Figure 13H As shown. The second source / drain metal layer includes a second connection electrode 45 and a third connection electrode 37. The second connection electrode 45 is electrically connected to the first connection electrode 44 through a twenty-third via V23, thus achieving electrical connection with the reference voltage line V0. The third connection electrode 37 is electrically connected to the second electrode M32 of the third transistor M3 through a twenty-first via V21. The first cathode 231 of the optical sensing element is electrically connected to the second electrode M42 of the fourth transistor M4 through a twenty-second via V22. The orthographic projection of the first cathode 231 of the optical sensing element onto the substrate 10 overlaps with the orthographic projections of the fourth electrode 431 and the fifth electrode 432 onto the substrate 10. In this example, the first cathode 231 of the optical sensing element also serves as the first electrode of the second storage capacitor C2, and the fourth electrode 431 and the fifth electrode 432 serve as the second electrodes of the second storage capacitor C2.

[0163] (9) Forming a photoelectric conversion structure.

[0164] In some exemplary embodiments, a PIN thin film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the PIN thin film is patterned by a patterning process to form a photoelectric conversion structure, such as... Figure 13IAs shown. The photoelectric conversion structure may include a first photoelectric conversion structure 232a and a second photoelectric conversion structure 232b arranged sequentially along the first direction X. The orthographic projection of the photoelectric conversion structure onto the substrate 10 and the orthographic projection of the transistor (e.g., the fourth transistor) of the light-emitting detection circuit onto the substrate 10 may not overlap. The orthographic projection of the transistor (e.g., the fourth transistor) of the light-emitting detection circuit onto the substrate 10 is located between the orthographic projections of the first photoelectric conversion structure 232a and the second photoelectric conversion structure 232b onto the substrate 10.

[0165] In some exemplary implementations, such as Figure 14 As shown, in the second direction Y, there is a first distance d1 between the first photoelectric conversion structure 232a and the same-side edge of the first cathode 231, and a second distance d2 between the first cathode 231 and the same-side edge of the organic hydrogen barrier layer 19. The distance between the first photoelectric conversion structure 232a and the same-side edge of the organic hydrogen barrier layer 19 is the sum of the first distance d1 and the second distance d2. For example, the first distance d1 can be 2 μm, and the second distance d2 can be 3 μm. However, this embodiment is not limited to this.

[0166] In this example, by setting the fourth passivation layer 18, over-etching of the organic hydrogen barrier layer 19 during the dry etching process of the photoelectric conversion structure can be avoided, thus protecting the organic hydrogen barrier layer 19. Since the organic hydrogen barrier layer 19 will release gas at subsequent high temperatures, setting the second distance d2 provides sufficient venting space for the organic hydrogen barrier layer 19, preventing film bursting. By setting the edge of the organic hydrogen barrier layer 19 in the second direction to be larger than the edge of the photoelectric conversion structure, the flatness of the region where the photoelectric conversion structure is located can be ensured.

[0167] (10) The first anode of the optical sensing element is formed.

[0168] In some exemplary embodiments, a first transparent conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the first transparent conductive film is patterned by a patterning process to form the first anode of the optical sensing element, such as... Figure 13J As shown. The first anode of the optical sensing element may include a first sub-anode 233a and a second sub-anode 233b. The orthographic projections of the first sub-anode 233a and the second sub-anode 233b onto the substrate can both be rectangular. In this example, the first sub-anode 233a, the first photoelectric conversion structure 232a, and the first cathode 231 can form a first sub-optical sensing element, and the second sub-anode 233b, the second photoelectric conversion structure 232b, and the first cathode 231 can form a second sub-optical sensing element. In this example, no transistors are disposed below the first and second sub-optical sensing elements, and there is no via design, which ensures the flatness of the area where the photoelectric conversion structure is located.

[0169] (11) Forming the first passivation layer and the first planarization layer.

[0170] In some exemplary embodiments, a sixth insulating film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a first passivation layer 14; subsequently, a planarization film is coated, and the planarization film is patterned by a patterning process to form a first planarization layer 15, as shown below. Figure 13K As shown. A plurality of vias are formed on the first planarization layer 15, which may include, for example, vias 25 to 28. The first planarization layer 15 and the first passivation layer 14 are removed within the 26th via V26 and the 27th via V27, exposing the surface of the first anode of the optical sensing element. The first planarization layer 15 and the first passivation layer 14 are also removed within the 25th via V25 and the 28th via V28, exposing the surface of the second source / drain metal layer.

[0171] (12) The light-transmitting layer that forms the second anode of the light-emitting element and the anode connecting electrode.

[0172] In some exemplary embodiments, a second transparent conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed. The second transparent conductive film is patterned using a patterning process to form the anode connection electrode 234 of the optical sensing element and the light-transmitting layer 2411 of the second anode of the light-emitting element, such as... Figure 13L As shown. The light-transmitting layer 2411 of the second anode of the light-emitting element is electrically connected to the third connecting electrode 37 through the twenty-fifth via V25, thereby achieving electrical connection with the pixel circuit. The anode connecting electrode 234 is electrically connected to the first sub-anode 233a through the twenty-sixth via V26, to the second sub-anode 233b through the twenty-seventh via V27, and to the second connecting electrode 45 through the twenty-eighth via V28, thereby achieving electrical connection with the reference voltage line V0. The orthographic projection of the anode connecting electrode 234 onto the substrate 10 can be T-shaped. However, this embodiment is not limited to this.

[0173] In some exemplary embodiments, the orthographic projection of the light-transmitting layer 2411 of the second anode of the light-emitting element onto the substrate overlaps with the orthographic projection of the optical sensing element onto the substrate.

[0174] (13) A reflective layer forming the second anode of the light-emitting element.

[0175] In some exemplary embodiments, a conductive thin film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the conductive thin film is patterned by a patterning process to form the reflective layer 2412 of the second anode of the light-emitting element, such as... Figure 13MAs shown. The reflective layer 2412 of the second anode is in direct contact with the light-transmitting layer 2411. The orthographic projection of the reflective layer 2412 on the substrate 10 overlaps with the orthographic projection of the light-transmitting layer 2411 on the substrate, but does not overlap with the orthographic projection of the optical sensing element on the substrate.

[0176] (14) Form a pixel definition layer.

[0177] In some exemplary embodiments, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer 244. For example... Figure 13N As shown, the pixel definition layer 244 has multiple pixel openings OP. The pixel definition layer 244 within the pixel openings OP is removed, exposing part of the surface of the light-transmitting layer 2411 and part of the surface of the reflective layer 2412 of the second anode. In a plane parallel to the display substrate, the shape of the pixel openings OP can be polygonal or other shapes. In a direction perpendicular to the display substrate, the cross-sectional shape of the pixel openings OP can be rectangular or trapezoidal, etc. However, this embodiment is not limited in this respect.

[0178] In some exemplary embodiments, the pixel definition layer 244 may be made of materials such as polyimide, acrylic, or polyethylene terephthalate.

[0179] (15) Forming an organic light-emitting layer and a second cathode.

[0180] In some exemplary embodiments, an organic light-emitting layer is formed on the substrate 10 on which the aforementioned pattern is formed, using vapor deposition or inkjet printing. The organic light-emitting layer of each light-emitting unit can contact the second anode through a pixel opening OP; subsequently, a second cathode covering the organic light-emitting layer is formed by a vapor deposition process. The second cathodes of multiple light-emitting elements can be a monolithic structure connected together.

[0181] In some examples, the organic light-emitting layer may include: an emitting layer (EML) and at least one of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0182] At this point, the light-emitting structure layer is complete. After the light-emitting structure layer is completed, an encapsulation layer can be formed. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, while the second encapsulation layer can be made of organic materials. The second encapsulation layer can be located between the first and third encapsulation layers. Using a stacked structure of inorganic, organic, and inorganic materials ensures that external moisture cannot enter the light-emitting structure layer.

[0183] In this exemplary embodiment, the orthographic projections of the first and second light conversion structures are rectangular, and the orthographic projections of the first and second light conversion structures onto the substrate do not overlap with the orthographic projection of the transistor in the light-emitting detection circuit onto the substrate. This reduces the influence of dark current on the optical sensing element, thereby improving the sensing effect.

[0184] In some exemplary implementations, such as Figure 12 As shown, the orthographic projection of the first sub-optical sensing element onto the substrate overlaps with the second emitting region 200 of four emitting units (e.g., first emitting unit P1, second emitting unit P2, fifth emitting unit P5, and sixth emitting unit P6). Similarly, the orthographic projection of the second sub-optical sensing element onto the substrate overlaps with the second emitting region 200 of four emitting units (e.g., third emitting unit P3, fourth emitting unit P4, seventh emitting unit P7, and eighth emitting unit P8). In total, the orthographic projection of one optical sensing element onto the substrate overlaps with the second emitting regions of eight emitting units, with the overlap area being, for example, approximately 1300 μm. 2 This can improve space utilization.

[0185] In some exemplary embodiments, the shielding layer, gate metal layer, first source / drain metal layer, second source / drain metal layer, and first cathode of the optical sensing element can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. For example, the shielding layer can be made of metallic Mo, and the gate metal layer, first source / drain metal layer, second source / drain metal layer, and first cathode can all be multi-layer composite structures of Mo / Al / Mo or Mo / Cu / Mo. The first insulating layer 11, second insulating layer 12, and third insulating layer 13 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers.

[0186] In some exemplary embodiments, the semiconductor layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The metal oxide layer may be a single layer, a double layer, or a multilayer. For example, the semiconductor layer material may be IGZO.

[0187] In some exemplary embodiments, the thickness of the shielding layer can be approximately to The thickness of the gate metal layer can be approximately to The thickness of the first source / drain metal layer can be approximately [missing information]. to The thickness of the second source / drain metal layer is approximately to The thickness of the semiconductor layer can be approximately to The thickness of the first insulating layer and the second insulating layer can be approximately [missing information]. to The thickness of the third insulating layer can be approximately [missing information]. to The thickness of the third passivation layer can be approximately [missing information]. to The thickness of the fourth passivation layer can be approximately to The thickness of the organic hydrogen barrier layer can be approximately 1 μm to 3 μm. The thickness of the first planarization layer can be approximately 1 μm to 2 μm. The thickness of the first passivation layer can be approximately... to The thickness of the photoelectric conversion structure can be approximately 1 μm. The thickness of the first anode can be approximately... to The thickness of the light-transmitting layer can be approximately to The thickness of the pixel definition layer can be approximately 1µm to 2µm.

[0188] As can be seen from the structure and fabrication process of the display substrate provided in this disclosure, by setting an inorganic hydrogen barrier layer and an organic hydrogen barrier layer, the permeation of hydrogen elements into the active layer of the transistor can be reduced, thereby effectively ensuring the electrical stability of the transistor and the uniformity of its electrical characteristics, thus improving the yield and display effect. The fabrication conditions of the inorganic hydrogen barrier layer in this embodiment can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0189] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0190] Figure 15 This is a diagram showing the electrical characteristics of the transistors in the pixel circuit of a display substrate according to at least one embodiment of the present disclosure. Figure 16 This is a diagram showing the electrical characteristics of the transistors in the light-emitting detection circuit of the display substrate according to at least one embodiment of the present disclosure. Figure 15 and Figure 16 The electrical characteristics of transistors at multiple test locations on the display substrate are illustrated. Figure 17 This is a schematic diagram of the test position of a display substrate according to at least one embodiment of the present disclosure.

[0191] In some exemplary implementations, such as Figure 15 As shown, the aspect ratio (W / L) of the transistors in the pixel circuit is approximately 15 / 6, and the data voltage Vd is approximately 15.1V. According to... Figure 15 The drain current I of the transistor in the pixel circuit shown D and gate voltage V G As can be seen from the curve, the display substrate provided in this embodiment can effectively avoid the influence of the hydrogen environment in the fabrication of optical sensing elements on the TFT device, and can ensure the electrical performance of the TFT device.

[0192] In some exemplary implementations, such as Figure 16 As shown, the aspect ratio of the transistor in the light-emitting detection circuit is approximately 10.5 / 6, and the data voltage Vd is approximately 15.1V. According to... Figure 16 The drain current I of the transistor in the light-emitting detection circuit shown D and gate voltage V G As can be seen from the curve, after the optical sensing element of the display substrate provided in this embodiment is connected to the transistor of the light emission detection circuit, the electrical performance of the TFT device can still be guaranteed.

[0193] Figure 18 This is a schematic diagram illustrating another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 18 As shown, the display substrate includes multiple pixel units arranged in a regular pattern. Each pixel unit includes four light-emitting units that emit light of different colors. The display substrate also includes a first light detection unit PD1 and a second light detection unit PD2. Each light detection unit overlaps with the second light-emitting area of ​​the eight light-emitting units in the orthographic projection onto the substrate. The second light detection unit PD2 serves as a test light detection unit, configured to test whether the light detection units are functioning correctly. The first light detection unit PD1 serves as the light detection unit in actual use, configured to detect the brightness of the light-emitting units.

[0194] The remaining structure of the display substrate in this embodiment can be described with reference to the description of the foregoing embodiment, and therefore will not be repeated here.

[0195] Figure 19 This is a schematic diagram illustrating another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 19 As shown, the display substrate includes multiple pixel units arranged in a regular pattern. Each pixel unit includes four light-emitting units (e.g., first light-emitting unit P1 to fourth light-emitting unit P4) that emit light of different colors. The four light-emitting units in a pixel unit can be arranged horizontally side by side, with light-emitting units emitting the same color of light located in the same column. The four light-emitting units arranged in an array (i.e., four light-emitting units arranged in a 2*2 pattern) can reuse a single photodetector unit (PD). The orthographic projection of the optical sensing element of the photodetector unit (PD) onto the substrate overlaps with the orthographic projection of the second light-emitting area of ​​the light-emitting elements of the eight light-emitting units onto the substrate.

[0196] The remaining structure of the display substrate in this embodiment can be described with reference to the description of the foregoing embodiment, and therefore will not be repeated here.

[0197] Figure 20 This is a schematic diagram illustrating another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 20 As shown, the display substrate includes multiple pixel units arranged in a regular pattern. Each pixel unit includes four light-emitting units (e.g., first light-emitting unit P1 to fourth light-emitting unit P4) that emit light of different colors. The four light-emitting units in a pixel unit can be arranged horizontally side by side, and light-emitting units emitting the same color of light are not located in the same column. The four light-emitting units arranged in an array (i.e., four light-emitting units arranged in a 2*2 pattern) can reuse a single light detection unit PD. The orthographic projection of the optical sensing element of the light detection unit PD onto the substrate overlaps with the orthographic projection of the second light-emitting area of ​​the light-emitting elements of the eight light-emitting units onto the substrate.

[0198] The remaining structure of the display substrate in this embodiment can be described with reference to the description of the foregoing embodiment, and therefore will not be repeated here.

[0199] Figure 21 This is a schematic diagram illustrating another arrangement of the light-emitting unit and the light-detecting unit according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 21 As shown, the display substrate includes multiple pixel units arranged in a regular pattern. Each pixel unit includes four light-emitting units (e.g., first light-emitting unit P1 to fourth light-emitting unit P4) that emit light of different colors. The four light-emitting units in a pixel unit can be arranged in a horizontal parallel manner. A photodetector unit PD can correspond one-to-one with a light-emitting unit. The orthographic projection of the optical sensing element of a photodetector unit PD onto the substrate overlaps with the orthographic projection of the second light-emitting area of ​​the light-emitting element of a light-emitting unit onto the substrate.

[0200] The remaining structure of the display substrate in this embodiment can be described with reference to the description of the foregoing embodiment, and therefore will not be repeated here.

[0201] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, comprising: forming a circuit structure layer and at least one inorganic hydrogen barrier layer on a substrate, wherein the circuit structure layer includes at least: a pixel circuit of a light-emitting unit and a light-emitting detection circuit of a light-emitting unit; forming an optical sensing element of a light-emitting unit on the side of the circuit structure layer away from the substrate; and forming a light-emitting element of a light-emitting unit on the side of the optical sensing element away from the substrate. The light-emitting element has a first light-emitting region and a second light-emitting region, wherein the first light-emitting region of the light-emitting element emits light from the side away from the substrate, and the second light-emitting region of the light-emitting element emits light from the side closer to the substrate; the orthographic projection of the first light-emitting region of the light-emitting element onto the substrate includes the orthographic projection of the second light-emitting region onto the substrate, and the orthographic projection of at least one optical sensing element onto the substrate at least partially overlaps with the orthographic projection of the second light-emitting region of at least one light-emitting element onto the substrate.

[0202] In some exemplary embodiments, the circuit structure layer includes: a semiconductor layer, a gate metal layer, and a first source / drain metal layer sequentially disposed on a substrate. The first cathode of the optical sensing element and the first source / drain metal layer are co-layered; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate. Alternatively, the first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element.

[0203] In some exemplary embodiments, forming at least one inorganic hydrogen barrier layer on a substrate includes: forming a second passivation layer by deposition. The second passivation layer includes a first inorganic layer and a second inorganic layer stacked together. The deposition method of the first inorganic layer satisfies the following conditions: deposition power of 500 W to 1000 W; deposition pressure of 1000 mTorr to 2000 mTorr; and SiH to N2O gas flow rate ratio of 1:30 to 1:50. The deposition method of the second inorganic layer satisfies the following conditions: deposition power of 1000 W to 2000 W; deposition pressure of 1000 mTorr to 2000 mTorr; and SiH to N2O gas flow rate ratio of 1:30 to 1:50.

[0204] In some exemplary embodiments, forming at least one inorganic hydrogen barrier layer on a substrate includes forming a third passivation layer by deposition. The deposition method of the third passivation layer meets the following conditions: deposition power of 500 watts to 1000 watts; deposition pressure of 1000 mTorr to 2000 mTorr; and SiH to N2O gas flow ratio of 1:30 to 1:50.

[0205] The preparation process of the display substrate provided in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0206] Figure 22 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 22 As shown, this embodiment provides a display device 900, including a display substrate 910. The display substrate 910 is the display substrate provided in the foregoing embodiment. In some examples, the display substrate 910 can be an OLED display substrate. The display device 900 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, in-vehicle display, watch, or bracelet. However, this embodiment is not limited to this.

[0207] In the description of the embodiments of this disclosure, the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0208] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate comprises a substrate and a plurality of light-emitting units and a plurality of light-detecting units located on the substrate. At least one of the plurality of light-emitting units includes a light-emitting element and a pixel circuit connected to the light-emitting element. At least one of the plurality of light-detecting units includes an optical sensing element and a light-emitting detection circuit connected to the optical sensing element. The pixel circuit includes at least one transistor. The light-emitting detection circuit includes at least one transistor. The optical sensing element includes a first cathode, a photoelectric conversion structure, and a first anode, which are sequentially stacked in a direction away from the substrate. The orthographic projection of the photoelectric conversion structure onto the substrate does not overlap with the orthographic projections of the active layers of the transistors in the light-emitting detection circuit and the active layers of the transistors in the pixel circuit onto the substrate. The optical sensing element is located on the side of the light-emitting element closer to the substrate; at least one inorganic hydrogen barrier layer is disposed on the side of the optical sensing element closer to the substrate. The light-emitting element has a first light-emitting area and a second light-emitting area. The first light-emitting area of ​​the light-emitting element emits light from the side away from the substrate, and the second light-emitting area of ​​the light-emitting element emits light from the side close to the substrate. The orthographic projection of the second light-emitting area of ​​the light-emitting element onto the substrate falls completely within the orthographic projection of the first light-emitting area onto the substrate. The orthographic projection of at least one of the optical sensing elements onto the substrate and the orthographic projection of the second light-emitting area of ​​at least one of the light-emitting elements onto the substrate at least partially overlap; The pixel circuit further includes a first storage capacitor; in a direction perpendicular to the display substrate, the circuit structure layer includes: a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a gate metal layer, a third insulating layer, and a first source / drain metal layer sequentially disposed on the substrate; the shielding layer includes: a first electrode of the first storage capacitor; the semiconductor layer includes: a second electrode of the first storage capacitor; the first source / drain metal layer includes: a third electrode of the first storage capacitor; the first electrode and the third electrode are electrically connected as a second electrode of the first storage capacitor, and the second electrode serves as a first electrode of the first storage capacitor.

2. The display substrate according to claim 1, wherein, The first anode is made of a light-transmitting material; The at least one inorganic hydrogen barrier layer is located on the side of the photoelectric conversion structure closest to the substrate.

3. The display substrate according to claim 2, wherein, The first cathode of the optical sensing element and the first source / drain metal layer are of the same layer structure. The inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate.

4. The display substrate according to claim 3, wherein, The orthographic projection of the second passivation layer onto the substrate does not overlap with the orthographic projection of the photoelectric conversion structure onto the substrate.

5. The display substrate according to claim 3, wherein, The second passivation layer comprises a first inorganic layer and a second inorganic layer stacked together, the first inorganic layer and the second inorganic layer having approximately the same thickness.

6. The display substrate according to claim 5, wherein, The thickness of the first inorganic layer and the second inorganic layer is 1000 angstroms to 3000 angstroms, and the material of the first inorganic layer and the second inorganic layer is silicon oxide.

7. The display substrate according to claim 2, wherein, The first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate. The inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element.

8. The display substrate according to claim 7, wherein, The third and fourth passivation layers are made of silicon oxide, and their thicknesses range from 1,000 angstroms to 3,000 angstroms.

9. The display substrate according to claim 7, wherein, An organic hydrogen barrier layer is disposed between the fourth passivation layer and the first cathode of the optical sensing element. The orthogonal projection of the organic hydrogen barrier layer onto the substrate covers the orthogonal projection of the photoelectric conversion structure of the optical sensing element onto the substrate. The organic hydrogen barrier layer satisfies at least one of the following: Curing temperature below 230 degrees Celsius; The thermal decomposition temperature is greater than 450 degrees Celsius.

10. The display substrate according to claim 3, wherein, The etching rate of the interlayer insulating layer is 2 Å / s.

11. The display substrate according to claim 1, wherein, The photoelectric conversion structure includes a first photoelectric conversion structure and a second photoelectric conversion structure arranged sequentially along a first direction, wherein the transistor of the light emission detection circuit is located between the orthogonal projections of the first photoelectric conversion structure and the second photoelectric conversion structure on the substrate.

12. The display substrate according to claim 11, wherein, The first photoelectric conversion structure and the second photoelectric conversion structure are rectangular when projected onto the substrate.

13. The display substrate according to any one of claims 1 to 12, wherein, The light-emitting element includes: a second anode, a light-emitting functional layer, and a second cathode, which are sequentially stacked along a direction away from the substrate. The second cathode is made of a light-transmitting material, and the second anode includes a stacked reflective layer and a light-transmitting layer. The orthogonal projection of the reflective layer onto the substrate does not overlap with the orthogonal projection of the second light-emitting area onto the substrate, and the orthogonal projection of the light-transmitting layer onto the substrate covers the orthogonal projection of the second light-emitting area onto the substrate.

14. The display substrate according to any one of claims 1 to 12, wherein, The orthographic projection of at least one optical sensing element onto the substrate at least partially overlaps with the orthographic projection of the second light-emitting area of ​​eight light-emitting elements onto the substrate.

15. A display device comprising a display substrate as claimed in any one of claims 1 to 14.

16. A method for preparing a display substrate, comprising: A circuit structure layer and at least one inorganic hydrogen barrier layer are formed on a substrate. The circuit structure layer includes at least: a pixel circuit of a light-emitting unit and a light-emitting detection circuit of a light-detecting unit. An optical sensing element for a light detection unit is formed on the side of the circuit structure layer away from the substrate. The light-emitting element of the light-emitting unit is formed on the side of the optical sensing element away from the substrate. The light-emitting element has a first light-emitting area and a second light-emitting area. The first light-emitting area of ​​the light-emitting element emits light from the side away from the substrate, and the second light-emitting area of ​​the light-emitting element emits light from the side close to the substrate. The orthographic projection of the first light-emitting area of ​​the light-emitting element onto the substrate includes the orthographic projection of the second light-emitting area onto the substrate. The orthographic projection of at least one optical sensing element onto the substrate at least partially overlaps with the orthographic projection of the second light-emitting area of ​​at least one light-emitting element onto the substrate. The pixel circuit includes at least one transistor; the light-emitting detection circuit includes at least one transistor; the optical sensing element includes a first cathode, a photoelectric conversion structure, and a first anode, which are sequentially stacked along a direction away from the substrate; the orthographic projection of the photoelectric conversion structure onto the substrate does not overlap with the orthographic projections of the active layer of the transistor in the light-emitting detection circuit and the active layer of the transistor in the pixel circuit onto the substrate. The pixel circuit further includes a first storage capacitor; in a direction perpendicular to the display substrate, the circuit structure layer includes: a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a gate metal layer, a third insulating layer, and a first source / drain metal layer sequentially disposed on the substrate; the shielding layer includes: a first electrode of the first storage capacitor; the semiconductor layer includes: a second electrode of the first storage capacitor; the first source / drain metal layer includes: a third electrode of the first storage capacitor; the first electrode and the third electrode are electrically connected as a second electrode of the first storage capacitor, and the second electrode serves as a first electrode of the first storage capacitor.

17. The preparation method according to claim 16, wherein, The first cathode of the optical sensing element and the first source / drain metal layer are co-layered; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, and a second passivation layer located on the side of the first source / drain metal layer away from the substrate. Alternatively, the first cathode of the optical sensing element is located on the side of the first source / drain metal layer away from the substrate; the inorganic hydrogen barrier layer includes at least one of the following: an interlayer insulating layer located between the gate metal layer and the first source / drain metal layer, a third passivation layer located between the first source / drain metal layer and the first cathode of the optical sensing element, and a fourth passivation layer located between the third passivation layer and the first cathode of the optical sensing element.

18. The preparation method according to claim 17, wherein, At least one inorganic hydrogen barrier layer is formed on the substrate, including: A second passivation layer is formed by deposition, the second passivation layer comprising a first inorganic layer and a second inorganic layer stacked together; the deposition method of the first inorganic layer satisfies the following conditions: deposition power of 500 watts to 1000 watts; deposition pressure of 1000 mTorr to 2000 mTorr; and SiH to N2O gas flow ratio of 1:30 to 1:

50. The deposition method of the second inorganic layer meets the following conditions: deposition power of 1000 watts to 2000 watts; deposition pressure of 1000 millitor to 2000 millitor; and gas flow ratio of SiH to N2O of 1:30 to 1:

50.

19. The preparation method according to claim 17, wherein, At least one inorganic hydrogen barrier layer is formed on the substrate, including: A third passivation layer is formed by deposition; the deposition method of the third passivation layer meets the following conditions: deposition power of 500 watts to 1000 watts; deposition pressure of 1000 millitor to 2000 millitor; and gas flow ratio of SiH to N2O of 1:30 to 1:50.

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