Gate drive circuit, display substrate, and display device

Abstract

A gate drive circuit, a display substrate, and a display device. The gate drive circuit comprises a plurality of cascaded shift registers (GOA) and M clock signal lines connected to the plurality of shift registers (GOA), wherein M is an even number greater than or equal to 4; a first signal input end (input) of an Nth-stage shift register (GOA) is connected to a signal output end of an (N-M2)th-stage shift register (GOA), wherein N is a positive integer; a second signal input end (PD_F) of the Nth-stage shift register (GOA) is connected to a signal output end of an (N-M / 2-P)th-stage shift register (GOA), wherein P is a positive integer greater than 0 and less than or equal to M / 2; or the second signal input end (PD_F) of the Nth-stage shift register (GOA) is connected to a pull-up output end (PU_out) of an (N-M / 2+J)-stage shift register (GOA), and the pull-up output end (PU_out) is connected to a pull-up node (PU), wherein J is a positive integer greater than 0 and less than M / 2. In the gate drive circuit, the contention relationship between the pull-up node (PU) and a pull-down node (PD) is reduced, and the output capability is improved.

Description

Gate driving circuit, display substrate and display device Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a gate driving circuit, a display substrate, and a display device. Background Technology

[0002] In related technologies, the output control sub-circuit of the shift register transmits the clock signal to the signal output terminal under the control of the pull-up node voltage, and transmits the second operating voltage provided by the second power supply terminal to the signal output terminal under the control of the pull-down node voltage. The voltage of the pull-down node affects the lifting of the pull-up node, resulting in a competition between the pull-up node and the pull-down node, which in turn affects the product's low-temperature start-up capability and service life.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a gate driving circuit, a display substrate and a display device.

[0005] To achieve the above objectives, according to one aspect of this disclosure, a gate driving circuit is provided, comprising: a plurality of cascaded shift registers and M clock signal lines connected to the plurality of shift registers, each shift register including an input sub-circuit, an output control sub-circuit, and a noise reduction control sub-circuit, wherein the input sub-circuit and the output control sub-circuit are connected to a pull-up node, and the noise reduction control sub-circuit and the output control sub-circuit are connected to a first node; the input sub-circuit is configured to charge the pull-up node under the control of a first input signal terminal; the output control sub-circuit is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node, and to output a second operating voltage to the signal output terminal under the control of the potential of the first node; the noise reduction control sub-circuit is configured to pull down the potential of the first node under the control of a second input signal terminal; wherein the first node includes a pull-down node and / or a pull-down control node, and M is an even number greater than or equal to 4;

[0006] The first signal input terminal of the shift registers of stages 1 to M / 2 is connected to their respective first start signal terminals. Except for the shift registers of stages 1 to M / 2, the first signal input terminal of the shift register of stage N is connected to the signal output terminal of the shift register of stage (NM / 2).

[0007] The second signal input terminals of the shift registers from level 1 to level M / 2+P are connected to their respective second start signal terminals. Except for the shift registers from level 1 to level M / 2+P, the second signal input terminal of the shift register from level N is connected to the signal output terminal of the shift register from level (NM / 2-P), where P is a positive integer greater than 0 and less than or equal to M / 2, and N is a positive integer greater than M / 2+P. Alternatively, the second signal input terminals of the shift registers from level 1 to level M / 2-J are connected to their respective second start signal terminals. Except for the shift registers from level 1 to level M / 2-J, the second signal input terminal of the shift register from level N is connected to the pull-up output terminal of the shift register from level (NM / 2+J), and the pull-up output terminal is connected to the pull-up node, where J is a positive integer greater than 0 and less than M / 2.

[0008] In some embodiments, the input sub-circuit includes a first reset module connected to the pull-up node. The first reset module is configured to pull down the potential of the pull-up node under the control of a first reset signal input.

[0009] Except for the shift registers of the last M / 2+1 stage, the first reset signal input terminal of the shift register of the Nth stage is connected to the signal output terminal of the shift register of the N+M / 2+1 stage, and the first reset signal input terminal of the shift register of the last M / 2+1 stage is connected to its respective first reset signal terminal.

[0010] In some embodiments, the pull-down node includes a first pull-down node and a second pull-down node, and the noise reduction control sub-circuit includes:

[0011] The first transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the first pull-down node, and its second electrode connected to the second power supply terminal.

[0012] The second transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the second pull-down node, and its second electrode connected to the second power supply terminal.

[0013] In some embodiments, the pull-down control node includes a first pull-down control node and a second pull-down control node, and the noise reduction control sub-circuit includes:

[0014] The third transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the first pull-down control node, and its second electrode connected to the second power supply terminal.

[0015] The fourth transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the second pull-down control node, and its second electrode connected to the second power supply terminal.

[0016] In some embodiments, the output control sub-circuit includes: a pull-up module, a first pull-down control module, and a first pull-down module, wherein the first pull-down control module and the first pull-down module are connected to a first pull-down node, and the signal output terminal includes a first signal output terminal and a second signal output terminal;

[0017] The pull-up module is connected to the pull-up node, the clock signal input terminal, the first signal output terminal, and the second signal output terminal. In response to the control of the potential of the pull-up node, it is used to input the clock signal provided by the clock signal input terminal to the first signal output terminal and the second signal output terminal when the potential of the pull-up node is at an effective level.

[0018] The first pull-down control module is connected to the pull-up node, the first pull-down node, the second power supply terminal, and the third power supply terminal. In response to the control of the potential of the pull-up node, it is used to input the second operating voltage provided by the second power supply terminal to the first pull-down node when the potential of the pull-up node is at an effective level, and to input the third operating voltage provided by the third power supply terminal to the first pull-down node when the potential of the pull-up node is at an ineffective level.

[0019] The first pull-down module is connected to the first pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal. In response to the control of the potential of the first pull-down node, it is used to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and input the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the first pull-down node is at an effective level.

[0020] In some embodiments, the pull-up module includes a fifth transistor, a sixth transistor, and a first capacitor.

[0021] The control terminals of the fifth transistor and the sixth transistor are connected to the pull-up node, the first terminals of the fifth transistor and the sixth transistor are connected to the clock signal input terminal, the second terminal of the fifth transistor is connected to the first signal output terminal, and the second terminal of the sixth transistor is connected to the second signal output terminal.

[0022] The first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the first signal output terminal.

[0023] In some embodiments, the clock signal input terminal includes a first clock signal input terminal and a second clock signal input terminal, and the pull-up module includes a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor.

[0024] The control electrode of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first clock signal input terminal, and the second electrode of the fifth transistor is connected to the first signal output terminal.

[0025] The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second clock signal input terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal.

[0026] The first terminal of the first capacitor is connected to the pull-up node, and the second terminal of the first capacitor is connected to the first signal output terminal.

[0027] The first end of the second capacitor is connected to the pull-up node, and the second end of the second capacitor is connected to the second signal output terminal.

[0028] In some embodiments, the first pull-down control module includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0029] The control electrode of the seventh transistor is connected to the third power supply terminal, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the first pull-down control node.

[0030] The control electrode of the eighth transistor is connected to the first pull-down control node, the first electrode of the eighth transistor is connected to the third power supply terminal, and the second electrode of the eighth transistor is connected to the first pull-down node.

[0031] The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the first pull-down control node, and the second electrode of the ninth transistor is connected to the second power supply terminal.

[0032] The control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the first pull-down node, and the second electrode of the tenth transistor is connected to the second power supply terminal.

[0033] The first pull-down module includes: an eleventh transistor and a twelfth transistor;

[0034] The control electrode of the eleventh transistor is connected to the first pull-down node, the first electrode of the eleventh transistor is connected to the first signal output terminal, and the second electrode of the eleventh transistor is connected to the fifth power supply terminal.

[0035] The control electrode of the twelfth transistor is connected to the first pull-down node, the first electrode of the twelfth transistor is connected to the second signal output terminal, and the second electrode of the twelfth transistor is connected to the second power supply terminal.

[0036] In some embodiments, the output control sub-circuit further includes a second pull-down module and a second pull-down control module, wherein the second pull-down control module and the second pull-down module are connected to the second pull-down node;

[0037] The second pull-down control module is connected to the pull-up node, the second pull-down node, the second power supply terminal, and the fourth power supply terminal. In response to the control of the potential of the pull-up node, it is used to input the second operating voltage provided by the second power supply terminal to the second pull-down node when the potential of the pull-up node is at an effective level, and to input the fourth operating voltage provided by the fourth power supply terminal to the second pull-down node when the potential of the pull-up node is at an ineffective level.

[0038] The second pull-down module is connected to the second pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal. It responds to the control of the potential of the second pull-down node and is used to input the second working voltage provided by the second power supply terminal to the second signal output terminal and the fifth working voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the second pull-down node is at an effective level.

[0039] The third operating voltage switches between an effective level state and an ineffective level state, and the fourth operating voltage switches between an effective level state and an ineffective level state; at any given time, one of the third operating voltage and the fourth operating voltage is in an effective level state, and the other is in an ineffective level state.

[0040] In some embodiments, the second pull-down control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0041] The control electrode of the thirteenth transistor is connected to the fourth power supply terminal, the first electrode of the thirteenth transistor is connected to the fourth power supply terminal, and the second electrode of the thirteenth transistor is connected to the second pull-down control node.

[0042] The control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode of the fourteenth transistor is connected to the fourth power supply terminal, and the second electrode of the fourteenth transistor is connected to the second pull-down node.

[0043] The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode of the fifteenth transistor is connected to the second pull-down control node, and the second electrode of the fifteenth transistor is connected to the second power supply terminal.

[0044] The control electrode of the sixteenth transistor is connected to the pull-up node, the first electrode of the sixteenth transistor is connected to the second pull-down node, and the second electrode of the sixteenth transistor is connected to the second power supply terminal.

[0045] The second pull-down module includes: a seventeenth transistor and an eighteenth transistor;

[0046] The control electrode of the seventeenth transistor is connected to the second pull-down node, the first electrode of the seventeenth transistor is connected to the first signal output terminal, and the second electrode of the seventeenth transistor is connected to the fifth power supply terminal.

[0047] The control electrode of the eighteenth transistor is connected to the second pull-down node, the first electrode of the eighteenth transistor is connected to the second signal output terminal, and the second electrode of the eighteenth transistor is connected to the second power supply terminal.

[0048] In some embodiments, the output control subcircuit further includes a first noise reduction module and a second noise reduction module.

[0049] The first noise reduction module is connected to the pull-up node, the first pull-down node and the second power supply terminal. In response to the control of the potential of the first pull-down node, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the potential of the first pull-down node is at an effective level.

[0050] The second noise reduction module is connected to the pull-up node, the second pull-down node and the second power supply terminal. In response to the control of the potential of the second pull-down node, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the potential of the second pull-down node is at an effective level.

[0051] In some embodiments, the first noise reduction module includes a nineteenth transistor, the control electrode of the nineteenth transistor is connected to the first pull-down node, the first electrode of the nineteenth transistor is connected to the pull-up node, and the second electrode of the nineteenth transistor is connected to the second power supply terminal;

[0052] The second noise reduction module includes a twentieth transistor. The control electrode of the twentieth transistor is connected to the second pull-down node, the first electrode of the twentieth transistor is connected to the pull-up node, and the second electrode of the twentieth transistor is connected to the second power supply terminal.

[0053] In some embodiments, the input sub-circuit includes: a signal input module, a first reset module, and a second reset module;

[0054] The signal input module is connected to the pull-up node, the first signal input terminal, and the first power supply terminal. In response to the voltage control of the first signal input terminal, it is used to input the first operating voltage provided by the first power supply terminal to the pull-up node when the first input signal provided by the first signal input terminal is at an effective level.

[0055] The first reset module is connected to the pull-up node, the first reset signal input terminal, and the second power supply terminal. In response to the voltage control of the first reset signal input terminal, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the first reset signal input terminal is at an effective level.

[0056] The second reset module is connected to the pull-up node, the second reset signal input terminal, and the second power supply terminal. In response to the voltage control of the second reset signal input terminal, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the second reset signal input terminal is at an effective level.

[0057] In some embodiments, the signal input module includes a twenty-first transistor, the control electrode of the twenty-first transistor is connected to the first signal input terminal, the first electrode of the twenty-first transistor is connected to the first power supply terminal, and the second electrode of the twenty-first transistor is connected to the pull-up node;

[0058] The first reset module includes a twenty-second transistor, the control electrode of the twenty-second transistor is connected to the first reset signal input terminal, the first electrode of the twenty-second transistor is connected to the pull-up node, and the second electrode of the twenty-second transistor is connected to the second power supply terminal;

[0059] The second reset module includes a twenty-third transistor. The control electrode of the twenty-third transistor is connected to the second reset signal input terminal, the first electrode of the twenty-third transistor is connected to the pull-up node, and the second electrode of the twenty-third transistor is connected to the second power supply terminal.

[0060] According to another aspect of this disclosure, a display substrate is provided, including a substrate and the gate driving circuit described above, the gate driving circuit being disposed on the substrate.

[0061] In some embodiments, the shift register in the gate drive circuit includes:

[0062] The fifth transistor;

[0063] The sixth transistor, wherein the fifth transistor and the sixth transistor are arranged at intervals along a first direction;

[0064] A first capacitor, the first capacitor and the sixth transistor are located on the same side of the fifth transistor and are spaced apart along a second direction, the first direction intersecting the second direction. The first capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other. The second electrode plate is located on the side of the first electrode plate away from the substrate. The first electrode plate is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

[0065] In some embodiments, the display substrate includes a gate metal layer, a semiconductor layer, and a source / drain metal layer sequentially disposed along a direction away from the substrate, wherein...

[0066] The control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are all located in the gate metal layer. At least a portion of the control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are integrally formed.

[0067] The first electrode of the fifth transistor, the second electrode of the fifth transistor, the first electrode of the sixth transistor, the second electrode of the sixth transistor, and the second electrode plate of the first capacitor are all located in the source and drain metal layer.

[0068] In some embodiments, the shift register further includes a first adapter electrode and a first connection line. The first connection line of the (NM / 2+J)th stage shift register is electrically connected to the second signal input terminal of the Nth stage shift register. The first adapter electrode is connected to the first connection line through a first via and to the first electrode plate through a second via.

[0069] In some embodiments, the display substrate further includes a first signal transmission line extending along a second direction, wherein the first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register, and the orthographic projection of the first connection line on the substrate intersects with the orthographic projection of the first signal transmission line on the substrate.

[0070] In some embodiments, the shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially disposed along a direction away from the substrate, wherein...

[0071] The first electrode plate is located in the gate metal layer;

[0072] The first connection line is located in the source / drain metal layer;

[0073] The first transfer electrode is located in the transparent conductive layer.

[0074] In some embodiments, the display substrate further includes a first signal transmission line, and the shift register further includes a second adapter electrode and a second connection line. One end of the second connection line is connected to the second adapter electrode, and the other end of the second connection line is connected to the second electrode of the sixth transistor. The second adapter electrode is connected to the second connection line through a third via and to the first signal transmission line through a fourth via. The first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register.

[0075] In some embodiments, the first signal transmission line of the shift register of the (NM / 2-P)th stage is connected to the second signal input terminal of the shift register of the Nth stage.

[0076] In some embodiments, the shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially disposed along a direction away from the substrate, wherein...

[0077] The first signal transmission line is located in the gate metal layer;

[0078] The second connection line is located in the source / drain metal layer;

[0079] The second transfer electrode is located in the transparent conductive layer.

[0080] In some embodiments, the shift register further includes a second capacitor, the second capacitor comprising:

[0081] The first sub-capacitor includes a first sub-plate and a second sub-plate that are disposed opposite to each other;

[0082] The second sub-capacitor includes a third sub-plate and a fourth sub-plate arranged opposite to each other;

[0083] The third sub-capacitor includes a fifth sub-plate and a sixth sub-plate that are arranged opposite to each other;

[0084] The second sub-electrode, the fourth sub-electrode, and the fifth sub-electrode are electrically connected, and the first sub-electrode, the third sub-electrode, and the sixth sub-electrode are electrically connected.

[0085] In some embodiments, the first sub-electrode plate, the third sub-electrode plate, the fifth sub-electrode plate, and the first electrode plate are disposed in the same layer;

[0086] The second sub-electrode plate, the fourth sub-electrode plate, and the sixth sub-electrode plate are arranged in the same layer.

[0087] In some embodiments, the first sub-electrode plate and the first electrode plate are an integral structure.

[0088] In some embodiments, the shift register further includes a second transfer electrode, the second sub-electrode and the fourth sub-electrode are connected to the second transfer electrode through a third via, and the fifth sub-electrode is connected to the second transfer electrode through a fourth via.

[0089] In some embodiments, the display substrate further includes a first signal transmission line, wherein the first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register, and a portion of the first signal transmission line serves as the fifth sub-electrode plate.

[0090] In some embodiments, the sixth sub-electrode includes a first extension and a second extension, the first extension and the second extension are cross-connected, the first extension is parallel to the first signal transmission line, and the two ends of the second extension are electrically connected to the first sub-electrode and the third sub-electrode, respectively.

[0091] In some embodiments, the shift register further includes a first adapter electrode and a first connection line, a portion of the first connection line serving as a second extension, the first adapter electrode being connected to the second extension via a first via, and the first adapter electrode being connected to the first extension via a second via.

[0092] In some embodiments, the shift register further includes a second capacitor, the orthographic projection of the second capacitor on the substrate being located between the orthographic projection of the first capacitor on the substrate and the orthographic projection of the sixth transistor on the substrate, the second capacitor including a third electrode plate and a fourth electrode plate, the third electrode plate being integral with the first electrode plate, and the second electrode plate being disposed on the same layer as the fourth electrode plate.

[0093] In some embodiments, the first capacitor further includes a fifth electrode plate located on the side of the second electrode plate away from the first electrode plate, and the fifth electrode plate is electrically connected to the first electrode plate.

[0094] The second capacitor also includes a sixth electrode plate, which is located on the side of the fourth electrode plate away from the third electrode plate. The sixth electrode plate is electrically connected to the third electrode plate, and the fifth electrode plate and the sixth electrode plate are disposed on the same layer.

[0095] In some embodiments, the shift register further includes a first transfer electrode, which is connected to the first electrode plate through a second via, and the first transfer electrode is integrally formed with the fifth electrode plate and the sixth electrode plate.

[0096] In some embodiments, the active layer of the fifth transistor and the active layer of the sixth transistor, wherein the active layer of the fifth transistor includes a first active region and a second active region, the first active region and the second active region being arranged at a distance along a second direction.

[0097] The first capacitor and the first active region are arranged at intervals along the first direction;

[0098] The active layer of the sixth transistor and the second active region are arranged at intervals along a first direction, and the first capacitor and the active layer of the sixth transistor are arranged at intervals along a second direction, wherein the first direction and the second direction intersect.

[0099] In some embodiments, the display substrate has a display area and a non-display area, the gate driving circuit is located in the non-display area, and the display substrate further includes a transparent electrode located in the display area, the transparent electrode being disposed on the same layer as the first transition electrode.

[0100] According to another aspect of this disclosure, a display device is provided, including the display substrate described above. Attached Figure Description

[0101] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0102] Figure 1 shows an example structural diagram of a gate drive circuit according to an alternative embodiment of the present disclosure;

[0103] Figure 2 shows a schematic diagram of one structure of the shift register in Figure 1;

[0104] Figure 3 shows a schematic diagram of the structure of a shift register as shown in Figure 1;

[0105] Figure 4 shows a schematic diagram of another shift register in Figure 1;

[0106] Figure 5 shows a comparison of the signal outputs of the two shift registers in Figures 3 and 4;

[0107] Figure 6 shows an example structural diagram of a gate drive circuit according to another alternative embodiment of the present disclosure;

[0108] Figure 7 shows a schematic diagram of the structure of a shift register as shown in Figure 6;

[0109] Figure 8 shows a schematic diagram of another shift register structure in Figure 6;

[0110] Figure 9 shows a comparison of the signal outputs of the two shift registers in Figures 4 and 8;

[0111] Figure 10 shows a comparison of the output capabilities of the two shift registers in Figures 4 and 8;

[0112] Figure 11 shows an example structural diagram of a gate drive circuit according to another alternative embodiment of the present disclosure;

[0113] Figure 12 shows a schematic diagram of the structure of a shift register as shown in Figure 11;

[0114] Figure 13 shows a schematic diagram of another shift register in Figure 11;

[0115] Figure 14 shows the timing diagram of each signal in the shift register in Figure 11;

[0116] Figure 15 shows a comparison of the signal outputs of the two shift registers in Figures 8 and 13;

[0117] Figure 16 shows a comparison of the output capability and charge rate of the two shift registers in Figures 8 and 13;

[0118] Figure 17 shows a simulation diagram of the capacitance design of the second capacitor in 12 of Figure 11;

[0119] Figure 18 shows a timing diagram of the clock signal in an alternative embodiment of this disclosure;

[0120] Figure 19 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer of the display substrate in an optional embodiment of the present disclosure;

[0121] Figure 20 shows a planar schematic diagram of the gate metal layer in Figure 19;

[0122] Figure 21 shows a planar schematic diagram of the semiconductor layer in Figure 19;

[0123] Figure 22 shows a planar schematic diagram of the source and drain metal layers in Figure 19;

[0124] Figure 23 shows a planar schematic diagram of the insulating layer in Figure 19;

[0125] Figure 24 shows a planar schematic diagram of the transparent conductive layer in Figure 19;

[0126] Figure 25 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer of the display substrate in another optional embodiment of the present disclosure;

[0127] Figure 26 shows a planar schematic diagram of the gate metal layer in Figure 25;

[0128] Figure 27 shows a planar schematic diagram of the semiconductor layer in Figure 25;

[0129] Figure 28 shows a planar schematic diagram of the source and drain metal layers in Figure 25;

[0130] Figure 29 shows a planar schematic diagram of the insulating layer in Figure 25;

[0131] Figure 30 shows a planar schematic diagram of the transparent conductive layer in Figure 25;

[0132] Figure 31 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer of the display substrate in another optional embodiment of the present disclosure;

[0133] Figure 32 shows a planar schematic diagram of the gate metal layer in Figure 31;

[0134] Figure 33 shows a planar schematic diagram of the semiconductor layer in Figure 31;

[0135] Figure 34 shows a planar schematic diagram of the source and drain metal layers in Figure 31;

[0136] Figure 35 shows a planar schematic diagram of the insulating layer in Figure 31;

[0137] Figure 36 shows a planar schematic diagram of the transparent conductive layer in Figure 31.

[0138] 10. Input sub-circuit; 11. Signal input module; 12. First reset module; 13. Second reset module; 20. Output control sub-circuit; 21. Pull-up module; 22. First pull-down control module; 23. First pull-down module; 24. Second pull-down module; 25. Second pull-down control module; 30. Noise reduction control sub-circuit; 41. First electrode plate; 42. Second electrode plate; 43. Fifth electrode plate; 80. First adapter electrode; 90. First connecting line; 100. First via; 110. Second via; 120. First signal transmission line; 130. Second adapter electrode; 140. Second connecting line; 150. Third via; 160. Fourth via; 181 182. First sub-electrode plate; 183. Second sub-electrode plate; 184. Third sub-electrode plate; 185. Fourth sub-electrode plate; 186. Sixth sub-electrode plate; 187. First extension; 188. Second extension; 191. Third electrode plate; 192. Fourth electrode plate; 193. Sixth electrode plate; 230. Second signal transmission line; 240. Third adapter electrode; 250. Fifth via; 260. Sixth via; 270. Third connecting line. Detailed Implementation

[0139] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0140] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0141] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0142] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0143] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0144] It should be noted that the transistor in this invention can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics. A transistor generally includes three terminals: a gate, a source, and a drain. The source and drain of a transistor are structurally symmetrical and can be interchanged as needed. In this invention, the control terminal refers to the gate of the transistor; one of the first and second terminals is the source, and the other is the drain.

[0145] Furthermore, based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is N-type, its on-state voltage is a high-level voltage, and its off-state voltage is a low-level voltage. When a transistor is P-type, its on-state voltage is a low-level voltage, and its off-state voltage is a high-level voltage. In this invention, "effective level" refers to the voltage that controls the corresponding transistor to turn on, and "ineffective level" refers to the voltage that controls the corresponding transistor to turn off. Therefore, when the transistor is N-type, the effective level is high, and the ineffective level is low; when the transistor is P-type, the effective level is low, and the ineffective level is high.

[0146] In the following descriptions of the embodiments, examples are provided exemplarily where all transistors are N-type transistors. In this case, an active level refers to a high level, and an inactive level refers to a low level.

[0147] In this disclosure, "same-layer arrangement" means that multiple structures are formed from the same material layer through a patterning process, which simplifies the fabrication process. The multiple structures in the same-layer arrangement are in the same layer in terms of their stacking relationship; however, this does not mean that the distance between the multiple structures and the substrate must be the same.

[0148] Figure 1 shows an example structural diagram of a gate drive circuit of an optional embodiment of the present disclosure; Figure 2 shows a structural schematic diagram of a shift register in Figure 1; Figure 3 shows a structural schematic diagram of a shift register in Figure 1; Figure 4 shows a structural schematic diagram of another shift register in Figure 1; Figure 5 shows a comparison diagram of the signal outputs of the two shift registers in Figures 3 and 4.

[0149] In a first aspect, this disclosure provides a gate driving circuit, as shown in Figures 1 and 2. The gate driving circuit includes multiple cascaded shift registers (GOAs) and M clock signal lines connected to the multiple shift registers (GOAs). Each shift register (GOA) includes an input sub-circuit 10, an output control sub-circuit 20, and a noise reduction control sub-circuit 30. The input sub-circuit 10 and the output control sub-circuit 20 are connected to a pull-up node (PU). The noise reduction control sub-circuit 30 and the output control sub-circuit 20 are connected to a first node. The input sub-circuit 10 is configured to charge the pull-up node (PU) under the control of a first input signal terminal. The output control sub-circuit 20 is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node (PU), and to output a second operating voltage to the signal output terminal under the control of the potential of the first node. The noise reduction control sub-circuit 30 is configured to pull down the potential of the first node under the control of a second input signal terminal. The first node includes a pull-down node and / or a pull-down control node. M is an even number greater than or equal to 4.

[0150] The first input terminals of shift registers 1 through M / 2 are connected to their respective first start signals. Except for shift registers 1 through M / 2, the first input terminal of shift register N is connected to the output terminal of shift register (NM / 2), where N is a positive integer greater than M / 2 + P.

[0151] The second signal input terminal PD_F of the shift registers from level 1 to level M / 2-J is connected to their respective second start signal terminals. Except for the shift registers from level 1 to level M / 2-J, the second signal input terminal PD_F of the shift register of level N is connected to the pull-up output terminal PU_out of the shift register of level (NM / 2+J). The pull-up output terminal PU_out is connected to the pull-up node, where J is a positive integer greater than 0 and less than M / 2. The second signal input terminal PD_F is used to provide a second input signal for the noise reduction control sub-circuit 30.

[0152] In this way, when the pull-up node PU potential of the (M / 2-J)th stage shift register GOA (the NM / 2+Jth stage shift register) before this stage shift register rises, the noise reduction control sub-circuit 30 of the current stage shift register (the Nth stage shift register) GOA is simultaneously activated to pre-pull down the pull-up node and / or pull-down control node of the current stage shift register GOA. That is, before the pull-up node PU potential of the current stage shift register GOA rises, the pull-down node of the current stage shift register GOA has already been pulled down, thereby improving the competition relationship between the pull-up node and the pull-down node to improve the product's low-temperature start-up capability and service life.

[0153] It should be noted that when the pull-down node is in an active state, the output control sub-circuit outputs the second operating voltage provided by the second power supply terminal. When the pull-down control node is in an active state, the pull-down node is in an active state, and at this time, the output control sub-circuit outputs the second operating voltage provided by the second power supply terminal. In other words, the output control sub-circuit responds to the control of the pull-down control node.

[0154] For example, the gate drive circuit includes 6 clock signal lines, so M=6. The first signal input terminal Input of the first to third stage shift registers is connected to their respective first start signal terminals. Except for the first to third stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-3th stage shift register.

[0155] J is a positive integer greater than 0 and less than 3. For example, if J = 1, then the second signal input terminal PD_F of the first and second stage shift registers is connected to their respective second start signal terminals. Except for the first and second stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the (N-2)th stage shift register. For another example, if J = 2, then the second signal input terminal PD_F of the first stage shift register is connected to its respective second start signal terminal. Except for the first stage shift register, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the (N-1)th stage shift register.

[0156] For example, the gate drive circuit includes 8 clock signal lines. Please refer to Figure 1. Then M=8. The first signal input terminals of the shift registers of stages 1 to 4 are connected to their respective first start signal terminals. Except for the shift registers of stages 1 to 4, the first signal input terminal of the shift register of stage N is connected to the signal output terminal of the shift register of stage N-4.

[0157] J is a positive integer greater than 0 and less than 4. For example, if J = 1, then the second signal input terminal PD_F of the first to third stage shift registers is connected to their respective second start signal terminals. Except for the first to third stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the (N-3)th stage shift register. Similarly, if J = 2, then the second signal input terminal PD_F of the first to second stage shift registers is connected to their respective second start signal terminals. Except for the first to second stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the (N-2)th stage shift register. (See Figures 1, 3, and 4). Similarly, if J = 3, then the second signal input terminal PD_F of the first stage shift register is connected to its respective second start signal terminal. Except for the first stage shift register, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the (N-1)th stage shift register. And so on.

[0158] It should be noted that the first and second start signal terminals mentioned above can be connected to the frame start signal. There are no specific restrictions here, as long as it is ensured that the shift registers GOA at different levels are not started at the same time.

[0159] Each pair of M adjacent shift register units is connected to M clock signal lines in a one-to-one correspondence, and the first clock signal terminal CLKA of the i-th shift register and the i+Mn-th shift register are connected to the same clock signal line, where n is an integer not less than 0 and i is a positive integer greater than 0 and less than or equal to M.

[0160] For example, in the gate drive circuit, M is 8, which means that the gate drive circuit includes eight clock signal lines, namely the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8.

[0161] Specifically, the clock signal input terminals of the shift registers include a first clock signal input terminal CLKA. Specifically, the first clock signal input terminal CLKA of the (8n+1)th stage shift register GOA is connected to the first clock signal line CK1; the first clock signal input terminal CLKA of the (8n+2)th stage shift register GOA is connected to the second clock signal line CK2; the first clock signal input terminal CLKA of the (8n+3)th stage shift register GOA is connected to the third clock signal line CK3; and the first clock signal input terminal CLKA of the (8n+4)th stage shift register GOA is connected to the... The four clock signal lines CK4 are connected. The first clock signal input terminal CLKA of the 8n+5th stage shift register GOA is connected to the fifth clock signal line CK5. The first clock signal input terminal CLKA of the 8n+6th stage shift register GOA is connected to the sixth clock signal line CK6. The first clock signal input terminal CLKA of the 8n+7th stage shift register GOA is connected to the seventh clock signal line CK7. The first clock signal input terminal CLKA of the 8n+8th stage shift register GOA is connected to the eighth clock signal line CK8. Here, n is an integer not less than 0.

[0162] Figure 2 is a schematic diagram of the signals loaded on the clock control signal lines in Figure 1. The duty cycle of the clock signals provided by the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8 is 1 / 2. Assuming the period of the clock signal is 8H, in this embodiment, the clock signals provided by the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK4, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8 are delayed by H in sequence.

[0163] In the specific embodiments shown in Figures 1, 3, and 4, M=8 and J=2 in the gate drive circuit. Therefore, the second signal input terminal PD_F of the Nth-stage shift register is connected to the pull-up output terminal PU_out of the (N-2)th-stage shift register. This means that when the pull-up node PU potential of the upper two-stage shift register GOA (the (N-2)th-stage shift register) rises, the pull-up node and / or pull-down control node of the current-stage shift register GOA (the Nth-stage shift register) are simultaneously pre-pulled low. In other words, before the pull-up node PU potential of the current-stage shift register GOA rises, the pull-down node of the current-stage shift register GOA is pre-pulled low 2H in advance, thereby improving the competition between the pull-up and pull-down nodes to enhance the product's low-temperature start-up capability and service life.

[0164] In some alternative embodiments, the input sub-circuit 10 includes a first reset module 12, which is connected to the pull-up node PU. The first reset module 12 is configured to pull down the potential of the pull-up node PU under the control of the first reset signal input terminal Reset.

[0165] Except for the last M / 2+1 stage shift register GOA, the first reset signal input terminal Reset of the Nth stage shift register GOA is connected to the signal output terminal of the N+M / 2+1th stage shift register GOA, and the first reset signal input terminal Reset of the last M / 2+1th stage shift register GOA is connected to its corresponding first reset signal terminal. For example, if M=4, then except for the last 3 stages of shift registers, the first reset signal input terminal Reset of the Nth stage shift register GOA is connected to the signal output terminal of the N+3rd stage shift register, and the first reset signal input terminal Reset of the last 3 stages of shift registers is connected to the first reset signal terminal. For example, if M=8, except for the last 5 stages of shift register GOA, the first reset signal input terminal Reset of the Nth stage shift register GOA is connected to the signal output terminal of the K+5th stage shift register GOA, and the first reset signal input terminal Reset of the last 5 stages of shift register GOA is connected to the first reset signal terminal.

[0166] Figure 3 is a schematic diagram of a shift register provided by the present invention, and Figure 4 is a schematic diagram of another shift register provided by the present invention. The shift register shown in Figure 3 is a specific embodiment based on the shift register shown in Figure 1; the shift register shown in Figure 4 is another specific embodiment based on the shift register shown in Figure 1. The shift register includes an input sub-circuit 10, an output control sub-circuit 20, and a noise reduction control sub-circuit 30.

[0167] In the specific embodiments shown in Figures 3 and 4, the input sub-circuit 10 is connected to the first signal input terminal Input and the first power supply terminal VDS, and is used to transmit the first operating voltage provided by the first power supply terminal VDS to the pull-up node PU under the control of the first input signal provided by the first signal input terminal Input.

[0168] As shown in Figures 3 and 4, the input sub-circuit 10 includes a signal input module 11, a first reset module 12, and a second reset module 13 connected to the pull-up node PU.

[0169] The signal input module 11 is connected to the pull-up node PU, the first signal input terminal Input, and the first power supply terminal VDS. In response to voltage control at the first signal input terminal Input, it inputs the first operating voltage provided by the first power supply terminal VDS to the pull-up node PU when the first input signal provided by the first signal input terminal Input is at a valid level. Specifically, the signal input module 11 includes a twenty-first transistor M21. The control electrode of the twenty-first transistor M21 is connected to the first signal input terminal Input, the first electrode of the twenty-first transistor M21 is connected to the first power supply terminal VDS, and the second electrode of the twenty-first transistor M21 is connected to the pull-up node PU.

[0170] In the specific embodiments shown in Figures 3 and 4, the first reset module 12 is connected to the pull-up node PU, the first reset signal input terminal Reset, and the second power supply terminal LVGL. In response to voltage control at the first reset signal input terminal Reset, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the signal provided by the first reset signal input terminal Reset is at a valid level. The first reset module 12 is used to reset the pull-up node PU during the reset phase at the beginning of each scan cycle.

[0171] Specifically, the first reset module 12 includes a twenty-second transistor M22. The control electrode of the twenty-second transistor M22 is connected to the first reset signal input terminal Reset, the first electrode of the twenty-second transistor M22 is connected to the pull-up node PU, and the second electrode of the twenty-second transistor M22 is connected to the second power supply terminal LVGL.

[0172] In the specific embodiments shown in Figures 3 and 4, the second reset module 13 is connected to the pull-up node PU, the second reset signal input terminal STV0, and the second power supply terminal LVGL. In response to voltage control at the second reset signal input terminal STV0, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the signal provided by the second reset signal input terminal STV0 is at a valid level. The second reset module 13 is configured to reset the pull-up node PU at the beginning of each frame.

[0173] Specifically, the second reset module 13 includes a twenty-third transistor M23. The control terminal of the twenty-third transistor M23 is connected to the second reset signal input terminal STV0. The first terminal of the twenty-third transistor M23 is connected to the pull-up node PU. The second terminal of the twenty-third transistor M23 is connected to the second power supply terminal LVGL.

[0174] In the specific embodiments shown in Figures 3 and 4, the output control sub-circuit 20 is connected to the clock signal input terminal, the second power supply terminal LVGL, and the signal output terminal. In response to the control of the voltage of the pull-up node PU, it is used to input the clock signal provided by the clock signal input terminal to the signal output terminal when the voltage of the pull-up node PU is at an effective level, and to input the second operating voltage provided by the second power supply terminal LVGL to the signal output terminal when the voltage of the pull-up node PU is at an ineffective level.

[0175] In the specific embodiments shown in Figures 3 and 4, the output control sub-circuit 20 includes a pull-up module 21, a first pull-down control module 22, and a first pull-down module 23. The first pull-down control module 22 and the first pull-down module 23 are connected to the first pull-down node PD_A. The signal output terminal includes a first signal output terminal Gout and a second signal output terminal OC.

[0176] In the specific embodiments shown in Figures 3 and 4, the pull-up module 21 is connected to the pull-up node PU, the clock signal input terminal, the first signal output terminal Gout, and the second signal output terminal OC. In response to the voltage control of the pull-up node PU, it is used to input the clock signal provided by the clock signal input terminal to the first signal output terminal Gout and the second signal output terminal OC when the voltage of the pull-up node PU is at an effective level.

[0177] In some optional embodiments, please refer to Figures 3 and 4. The clock signal input terminal includes a first clock signal input terminal CLKA. The pull-up module 21 includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The control terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the pull-up node PU. The first terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the first clock signal input terminal CLKA. The second terminal of the fifth transistor M5 is connected to the first signal output terminal Gout. The second terminal of the sixth transistor M6 is connected to the second signal output terminal OC. The first terminal of the first capacitor C1 is connected to the pull-up node PU, and the second terminal of the first capacitor C1 is connected to the first signal output terminal Gout.

[0178] It should be noted that the first signal output terminal Gout is used to connect to the gate line and provide a signal for the sub-pixels in the same row connected to the gate line. The first signal output terminal Gout of different shift registers is connected to different gate lines, thereby providing signals for sub-pixels in different rows. The second signal output terminal OC is used to connect to shift registers of different levels.

[0179] In the specific embodiments shown in Figures 3 and 4, the first pull-down control module 22 is connected to the pull-up node PU, the first pull-down node PD_A, the second power supply terminal LVGL, and the third power supply terminal VDD1. In response to the voltage control of the pull-up node PU, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the first pull-down node PD_A when the voltage of the pull-up node PU is at an effective level, and to input the third operating voltage provided by the third power supply terminal VDD1 to the first pull-down node PD_A when the voltage of the pull-up node PU is at an ineffective level.

[0180] Specifically, the first pull-down control module 22 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; the control electrode of the seventh transistor M7 is connected to the third power supply terminal VDD1, the first electrode of the seventh transistor M7 is connected to the third power supply terminal VDD1, and the second electrode of the seventh transistor M7 is connected to the first pull-down control node PD_CNA; the control electrode of the eighth transistor M8 is connected to the first pull-down control node PD_CNA, the first electrode of the eighth transistor M8 is connected to the third power supply terminal VDD1, and the second electrode of the eighth transistor M8 is connected to the first pull-down node PD_A; the control electrode of the ninth transistor M9 is connected to the pull-up node PU, the first electrode of the ninth transistor M9 is connected to the first pull-down control node PD_CNA, and the second electrode of the ninth transistor M9 is connected to the second power supply terminal LVGL; the control electrode of the tenth transistor M10 is connected to the pull-up node PU, the first electrode of the tenth transistor M10 is connected to the first pull-down node PD_A, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal LVGL.

[0181] In the specific embodiments shown in Figures 3 and 4, the first pull-down module 23 is connected to the first pull-down node PD_A, the first signal output terminal Gout, the second signal output terminal OC, the second power supply terminal LVGL, and the fifth power supply terminal VGL. In response to the voltage control of the first pull-down node PD_A, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the second signal output terminal OC and the fifth operating voltage provided by the fifth power supply terminal VGL to the first signal output terminal Gout when the voltage of the first pull-down node PD_A is at an effective level.

[0182] It should be noted that the second power supply terminal LVGL and the fifth power supply terminal VGL can be the same port.

[0183] Specifically, the first pull-down module 23 includes an eleventh transistor M11 and a twelfth transistor M12; the control electrode of the eleventh transistor M11 is connected to the first pull-down node PD_A, the first electrode of the eleventh transistor M11 is connected to the first signal output terminal Gout, and the second electrode of the eleventh transistor M11 is connected to the fifth power supply terminal VGL; the control electrode of the twelfth transistor M12 is connected to the first pull-down node PD_A, the first electrode of the twelfth transistor M12 is connected to the second signal output terminal OC, and the second electrode of the twelfth transistor M12 is connected to the second power supply terminal LVGL.

[0184] In some alternative embodiments, please refer to Figures 3 and 4. The output control sub-circuit 20 further includes a second pull-down module 24 and a second pull-down control module 25, wherein the second pull-down control module 25 and the second pull-down module 24 are connected to the second pull-down node PD_B.

[0185] In the specific embodiments shown in Figures 3 and 4, the second pull-down control module 25 is connected to the pull-up node PU, the second pull-down node PD_B, the second power supply terminal LVGL, and the fourth power supply terminal VDD2. In response to the voltage control of the pull-up node PU, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the second pull-down node PD_B when the voltage of the pull-up node PU is at an effective level, and to input the fourth operating voltage provided by the fourth power supply terminal VDD2 to the second pull-down node PD_B when the voltage of the pull-up node PU is at an ineffective level.

[0186] The third operating voltage switches between an active and inactive level, and the fourth operating voltage also switches between an active and inactive level. At any given time, one of the third and fourth operating voltages is active, while the other is inactive. In other words, the first pull-down control module 22 and the second pull-down control module 25 switch between operating modes.

[0187] Specifically, the second pull-down control module 25 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16. The control electrode of the thirteenth transistor M13 is connected to the fourth power supply terminal VDD2, the first electrode of the thirteenth transistor M13 is connected to the fourth power supply terminal VDD2, and the second electrode of the thirteenth transistor M13 is connected to the second pull-down control node. The control electrode of the fourteenth transistor M14 is connected to the second pull-down control node PD_CNB, the first electrode of the fourteenth transistor M14 is connected to the fourth power supply terminal VDD2, and the second electrode of the fourteenth transistor M14 is connected to the second pull-down node PD_B. The control electrode of the fifteenth transistor M15 is connected to the pull-up node PU, the first electrode of the fifteenth transistor M15 is connected to the second pull-down control node PD_CNB, and the second electrode of the fifteenth transistor M15 is connected to the second power supply terminal LVGL. The control electrode of the sixteenth transistor M16 is connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is connected to the second pull-down node PD_B, and the second electrode of the sixteenth transistor M16 is connected to the second power supply terminal LVGL.

[0188] In the specific embodiments shown in Figures 3 and 4, the second pull-down module 24 is connected to the second pull-down node PD_B, the first signal output terminal Gout, the second signal output terminal OC, the second power supply terminal LVGL, and the fifth power supply terminal VGL. In response to the voltage control of the second pull-down node PD_B, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the second signal output terminal OC and the fifth operating voltage provided by the fifth power supply terminal VGL to the first signal output terminal Gout when the voltage of the second pull-down node PD_B is at an effective level.

[0189] Specifically, the second pull-down module 24 includes a seventeenth transistor M17 and an eighteenth transistor M18; the control electrode of the seventeenth transistor M17 is connected to the second pull-down node PD_B, the first electrode of the seventeenth transistor M17 is connected to the first signal output terminal Gout, and the second electrode of the seventeenth transistor M17 is connected to the fifth power supply terminal VGL; the control electrode of the eighteenth transistor M18 is connected to the second pull-down node PD_B, the first electrode of the eighteenth transistor M18 is connected to the second signal output terminal OC, and the second electrode of the eighteenth transistor M18 is connected to the second power supply terminal LVGL.

[0190] In some alternative embodiments, the output control subcircuit 20 further includes a first noise reduction module 26 and a second noise reduction module 27, as shown in Figures 3 and 4.

[0191] In the specific embodiments shown in Figures 3 and 4, the first noise reduction module 26 is connected to the pull-up node PU, the first pull-down node PD_A, and the second power supply terminal LVGL. In response to the voltage control of the first pull-down node PD_A, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the voltage of the first pull-down node PD_A is at an effective level.

[0192] Specifically, the first noise reduction module 26 includes a nineteenth transistor M19. The control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD_A, the first electrode of the nineteenth transistor M19 is connected to the pull-up node PU, and the second electrode of the nineteenth transistor M19 is connected to the second power supply terminal LVGL.

[0193] In the specific embodiments shown in Figures 3 and 4, the second noise reduction module 27 is connected to the pull-up node PU, the second pull-down node PD_B, and the second power supply terminal LVGL. In response to the voltage control of the second pull-down node PD_B, it is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the voltage of the second pull-down node PD_B is at an effective level.

[0194] Specifically, the second noise reduction module 27 includes a twentieth transistor M20. The control electrode of the twentieth transistor M20 is connected to the second pull-down node PD_B, the first electrode of the twentieth transistor M20 is connected to the pull-up node PU, and the second electrode of the twentieth transistor M20 is connected to the second power supply terminal LVGL.

[0195] In some optional embodiments, the pull-down nodes include a first pull-down node PD_A and a second pull-down node PD_B. The noise reduction control sub-circuit 30 includes a first transistor M1 and a second transistor M2. Please refer to Figures 3 and 4. The control electrode of the first transistor M1 is connected to the second signal input terminal PD_F, the first electrode of the first transistor M1 is connected to the first pull-down node PD_A, and the second electrode of the first transistor M1 is connected to the second power supply terminal LVGL. The control electrode of the second transistor M2 is connected to the second signal input terminal PD_F, the first electrode of the second transistor M2 is connected to the second pull-down node PD_B, and the second electrode of the second transistor M2 is connected to the second power supply terminal LVGL.

[0196] In some optional embodiments, referring to Figure 3, the pull-down control node includes a first pull-down control node PD_CNA and a second pull-down control node PD_CNB. The noise reduction control sub-circuit 30 includes a third transistor M3 and a fourth transistor M4. The control electrode of the third transistor M3 is connected to the second signal input terminal PD_F, the first electrode of the third transistor M3 is connected to the first pull-down control node PD_CNA, and the second electrode of the third transistor M3 is connected to the second power supply terminal LVGL. The control electrode of the fourth transistor M4 is connected to the second signal input terminal PD_F, the first electrode of the fourth transistor M4 is connected to the second pull-down control node PD_CNB, and the second electrode of the fourth transistor M4 is connected to the second power supply terminal LVGL.

[0197] It should be noted that in the specific embodiment shown in Figure 3, the noise reduction control sub-circuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. In the specific embodiment shown in Figure 4, the noise reduction control sub-circuit 30 includes a first transistor M1 and a second transistor M2. That is, in the specific embodiment shown in Figure 3, the shift register has 23 transistors, while in the specific embodiment shown in Figure 4, the shift register has 21 transistors. This is beneficial for achieving a narrow bezel. Furthermore, as can be seen from Figure 5, the shift register shown in Figure 3 is a 23T1C-P, and the shift register shown in Figure 4 is a 21T1C-P; the output of each signal in the two shift registers is not significantly different.

[0198] Therefore, by removing the third transistor M3 and the fourth transistor M4 from the pull-down control node of the 23T1C-P shift register shown in Figure 3, it becomes the 21T1C-P shift register shown in Figure 4. This reduces the circuit complexity of the shift register and effectively reduces the product bezel, increasing the screen ratio and improving aesthetics, while ensuring the shift register's functionality remains unaffected. After removing the third transistor M3 and the fourth transistor M4, the pull-down node can still be effectively pulled low, reducing the parasitic capacitance at the pull-up node PU. Compared to the 23T1C-P shift register, the 21T1C-P shift register has a 0.04V voltage increase and a 0.13V increase in the Gout output voltage, resulting in enhanced output capability.

[0199] Figure 6 shows an example structural diagram of the gate drive circuit of another alternative embodiment of the present disclosure; Figure 7 shows a structural schematic diagram of a shift register in Figure 6; Figure 8 shows a structural schematic diagram of another shift register in Figure 6; Figure 9 shows a comparison diagram of the signal output of the two shift registers in Figures 4 and 8; Figure 10 shows a comparison diagram of the output capabilities of the two shift registers in Figures 4 and 8.

[0200] In some alternative embodiments, the shift register GOA is not connected to the pull-up output PU_out, but to the signal output terminal; please refer to the specific embodiments shown in Figures 6 to 8. Compared to the embodiment shown in Figure 3, the shift register in the embodiment shown in Figure 7 does not have a pull-up output PU_out, while the other structures are the same as the shift register structure shown in Figure 7.

[0201] Specifically, the first signal input terminals (Input) of the shift registers at stages 1 to M / 2 are connected to their respective first start signal terminals. Except for the shift registers at stages 1 to M / 2, the first signal input terminal (Input) of the shift register at stage N is connected to the signal output terminal of the shift register at stage (NM / 2), where N is a positive integer. The second signal input terminals (PD_F) of the shift registers at stages 1 to M / 2+P are connected to their respective second start signal terminals. Except for the shift registers at stages 1 to M / 2+P, the second signal input terminal (PD_F) of the shift register at stage N is connected to the signal output terminal of the shift register at stage (NM / 2-P), where P is a positive integer greater than 0 and less than or equal to M / 2. When the pull-up node PU potential of the upper P-level shift register GOA rises, the noise reduction control sub-circuit 30 of the current-level shift register (N-level shift register) GOA is simultaneously activated to pre-pull down the pull-up node and / or pull-down control node of the current-level shift register GOA. In other words, before the pull-up node PU potential of the current-level shift register GOA rises, the pull-down node of the current-level shift register GOA has already been pulled down, thereby improving the competition relationship between the pull-up node and the pull-down node to improve the product's low-temperature start-up capability and service life.

[0202] For example, the gate drive circuit includes 4 clock signal lines, so M=4. The first signal input terminal Input of the first and second stage shift registers is connected to their respective first start signal terminals. Except for the first and second stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-2th stage shift register.

[0203] P is a positive integer greater than 0 and less than or equal to 2. For example, if P = 1, then the second signal input terminal PD_F of the shift registers at stages 1 to 3 is connected to their respective second start signal terminals. Except for the shift registers at stages 1 to 3, the second signal input terminal PD_F of the shift registers at stages 1 to 3 is connected to their respective second start signal terminals. Except for the shift registers at stages 1 to 3, the second signal input terminal PD_F of the shift register at stage N is connected to the signal output terminal of the shift register at stage N-3. Similarly, if P = 2, then the second signal input terminal PD_F of the shift registers at stages 1 to 4 is connected to their respective second start signal terminals. Except for the shift registers at stages 1 to 4, the second signal input terminal PD_F of the shift registers at stages 1 to 4 is connected to their respective second start signal terminals. Except for the shift registers at stages 1 to 4, the second signal input terminal PD_F of the shift register at stage N is connected to the signal output terminal of the shift register at stage N-4.

[0204] For example, if the gate drive circuit includes 6 clock signal lines, then M=6. The first signal input terminals of the first to third stage shift registers are connected to their respective first start signal terminals. Except for the first to third stage shift registers, the first signal input terminal of the Nth stage shift register is connected to the signal output terminal of the N-3th stage shift register.

[0205] P is a positive integer greater than 0 and less than or equal to 3. For example, if P = 1, then the second signal input terminal PD_F of shift registers 1 to 4 is connected to their respective second start signal terminals. Except for shift registers 1 to 4, the second signal input terminal PD_F of shift register N is connected to the signal output terminal of shift register N-4. Similarly, if P = 2, then the second signal input terminal PD_F of shift registers 1 to 5 is connected to their respective second start signal terminals. Except for shift registers 1 to 5, the second signal input terminal PD_F of shift register N is connected to the signal output terminal of shift register N-5, and so on.

[0206] In the specific embodiment shown in Figure 6, the gate drive circuit includes 8 clock signal lines, so M=8. The first signal input terminals Input of the 1st to 4th stage shift registers are connected to their respective first start signal terminals. Except for the 1st to 4th stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-4th stage shift register.

[0207] In the specific embodiments shown in Figures 6 to 8, P = 2, then the second signal input terminal PD_F of the shift registers of stages 1 to 6 is connected to their respective second start signal terminals. Except for the shift registers of stages 1 to 6, the second signal input terminal PD_F of the shift registers of stages 1 to 6 is connected to their respective second start signal terminals. Except for the shift registers of stages 1 to 6, the second signal input terminal PD_F of the shift register of stage N is connected to the signal output terminal of the shift register of stage N-6.

[0208] The cascading method of the shift register GOA in the gate drive circuit shown in Figure 6 is different from that in the gate drive circuit shown in Figure 1. By changing the cascading method, when the second signal output terminal OC of the N-6th stage shift register starts to output, the noise reduction control sub-circuit 30 of the Nth stage shift register GOA pulls down the pull-down node and pull-down control node of the Nth stage shift register GOA respectively. After 2H, the pull-up node PU of the Nth stage shift register GOA starts to rise. At this time, the pull-down node and pull-down control node are at a low level, which can improve the competition relationship between the pull-up node PU and the pull-down node. By adopting the cascading method shown in Figure 6, parasitic capacitance can be avoided to the pull-up node PU, improving the output capability of the circuit. At the same time, it avoids the rapid deterioration of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 caused by the second-order rise of the pull-up node PU, thus improving the stability of the circuit.

[0209] It should be noted that in the specific embodiment shown in Figure 7, the noise reduction control sub-circuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. In the specific embodiment shown in Figure 8, the noise reduction control sub-circuit 30 includes a first transistor M1 and a second transistor M2. That is, in the specific implementation shown in Figure 7, the shift register has 23 transistors; therefore, the shift register GOA shown in Figure 7 is 23T1C-O, and the shift register GOA shown in Figure 8 is 21T1C-O. This reduces the circuit complexity in the shift register while ensuring that the shift register function is not affected, effectively reducing the product bezel, increasing the screen-to-body ratio, and improving aesthetics.

[0210] Figure 9 compares the output of each signal in the 21T1C-O shift register and the 21T1C-P shift register, while Figure 10 compares their output capabilities. It can be seen that the output shapes of each signal in the 21T1C-O and 21T1C-P shift registers are similar, and the output capability of the 21T1C-O shift register is higher than that of the 21T1C-P shift register. The descent speed of the pull-down node in the 21T1C-O shift register is better than that in the 21T1C-P shift register.

[0211] Compared to the 21T1C-P shift register, the 21T1C-O shift register has a 4.31V increase in the voltage at the pull-up node PU, a 0.33V increase in the output voltage at room temperature, a 1.04V increase at -10℃, and a 3.99V increase at -20℃. The 21T1C-O shift register still has high output capability at low temperatures.

[0212] Figure 11 shows an example structural diagram of the gate drive circuit of another optional embodiment of the present disclosure; Figure 12 shows a structural schematic diagram of one type of shift register in Figure 11; Figure 13 shows a structural schematic diagram of another type of shift register in Figure 11; Figure 14 shows a timing diagram of each signal in the shift register in Figure 11; Figure 15 shows a comparison diagram of the output of each signal of the two types of shift registers in Figures 8 and 13; Figure 16 shows a comparison diagram of the output capability and charging rate of the two types of shift registers in Figures 8 and 13; Figure 17 shows a simulation diagram of the capacitance design of the second capacitor in Figure 12; Figure 18 shows a timing diagram of the clock signal in an optional embodiment of the present disclosure.

[0213] The cascading method of the gate drive circuit shown in Figure 11 is the same as that shown in Figure 6. However, the signals output by the first signal output terminal Gout and the second signal output terminal OC of the gate drive circuit shown in Figure 11 are different. The first signal output terminal Gout outputs the clock signal input by the first clock signal terminal CLKA, and the second signal output terminal OC outputs the clock signal input by the second clock signal terminal CLKB. The clock signal of the second clock signal terminal CLKB is delayed by H compared to the first clock signal terminal CLKA. In addition, the shift register structure shown in Figure 12 adds a second clock signal input terminal CLKB and a second capacitor C2 compared to the shift register structure shown in Figure 7.

[0214] In the specific embodiment shown in Figure 12, the clock signal input terminal includes a first clock signal input terminal CLKA and a second clock signal input terminal CLKB. The pull-up module 21 includes a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2. The control electrode of the fifth transistor M5 is connected to the pull-up node PU, the first electrode of the fifth transistor M5 is connected to the first clock signal input terminal CLKA, and the second electrode of the fifth transistor M5 is connected to the first signal output terminal Gout. The control electrode of the sixth transistor M6 is connected to the pull-up node PU, the first electrode of the sixth transistor M6 is connected to the second clock signal input terminal CLKB, and the second electrode of the sixth transistor M6 is connected to the second signal output terminal OC. The first terminal of the first capacitor C1 is connected to the pull-up node PU, and the second terminal of the first capacitor C1 is connected to the first signal output terminal Gout. The first terminal of the second capacitor C2 is connected to the pull-up node PU, and the second terminal of the second capacitor C2 is connected to the second signal output terminal OC.

[0215] In some optional embodiments, the second capacitor C2 and the first capacitor C1 have the same capacitance, separating the first signal output terminal Gout from the second signal output terminal OC. These are controlled by the first clock signal input terminal CLKA (input CTi signal) and the second clock signal input terminal CLKB (input CTi+1 signal), respectively, to achieve asynchronous output. The second signal input terminal PD_F (row N-6 OC) of the Nth stage shift register outputs a high level 1H before the first signal input terminal Input (row N-4 OC) to pull down the pull-down node and the pull-down control node. After 1H, the first signal input terminal Input begins to output a high level, at which point the pull-down node and the pull-down control node are at a low level, which improves the competition between the pull-up node and the pull-down connection.

[0216] It should be noted that 1H is the time required to scan one row of subpixels, and the start and end times of the periods when two adjacent rows of subpixels are in the on state differ by a unit scan time H; correspondingly, the start and end times of the pre-charging period of two adjacent rows of subpixels differ by a unit scan time H, and the start and end times of the charging period of two adjacent rows of subpixels differ by a unit scan time H.

[0217] The first clock signal terminal CLKA of the i-th stage shift register is connected to the first clock signal terminal CLKA of the (i+Mn)-th stage shift register, and the second clock signal terminal CLKB of the i-th stage shift register is connected to the same clock signal line.

[0218] The first clock signal terminal CLKA of the i-th stage shift register and the second clock signal terminal CLKB of the i-th stage shift register are connected to different clock signal lines. For example, the first clock signal terminal CLKA of the i-th stage shift register is connected to the i-th clock signal line, while the second clock signal terminal CLKB of the i-th stage shift register is connected to the (i+1)-th clock signal line.

[0219] When the first signal input terminal Input of the Nth stage shift register starts to output a high level, the voltage of the pull-up node PU is charged to VGH1. At this time, the voltage of the first signal output terminal Gout is raised from VGL to VGH. Through the bootstrap effect of the first capacitor C1, the voltage of the pull-up node PU is coupled to VGH2 (VGH2>VGH1). After 1 hour, the voltage of the second signal output terminal OC starts to rise to VGH. Through the bootstrap effect of the second capacitor C2, the voltage of the pull-up node PU is coupled to VGH3 (VGH3>VGH2>VGH1). At this time, the gate voltage of the fifth transistor M5 is VGH3. After the first signal output terminal Gout finishes outputting, the voltage at the first clock signal input terminal CLKA changes from VGH to VGL. At this time, the voltage of the pull-up node PU is coupled to VGH4 through the bootstrap effect of the first capacitor C1 (VGH4 > VGH5; this voltage value can be controlled by adjusting the relationship between C1 and C2). The voltage at the first signal output terminal Gout discharges to VGL through M5. Subsequently, the voltage at the second signal output terminal OC discharges from VGH to VGL. The voltage at the pull-up node PU is coupled to VGH5 by the second capacitor C2. Finally, the first reset signal input terminal Reset signal turns on the twenty-second transistor M22, and the voltage at the pull-up node PU returns to VGL.

[0220] The shift register in Figure 12 has 23 transistors, two capacitors, and is cascaded with the second signal output terminal OC and the second signal input terminal PD_F. Therefore, the shift register in Figure 12 is 23T2C-C. The shift register in Figure 13 has 21 transistors, which is two fewer transistors than the shift register shown in Figure 12. This helps to reduce the bezel and increase the screen ratio.

[0221] Figure 15 shows a comparison of the signal outputs of the two shift registers in Figures 8 and 13. Compared to the shift register shown in Figure 8, the shift register shown in Figure 13 has a higher voltage and a significantly reduced Tf at the first signal output terminal Gout. By adjusting the GOE time (ensuring ≥Tf), the charging time can be increased, improving the product charging rate, avoiding related defects, and improving image quality.

[0222] As can be seen from Figure 12, as the capacitance of the second capacitor C2 increases, the Tf of the first signal output terminal Gout decreases monotonically. However, considering the size of the frame, the second capacitor C2 and the first capacitor C1 remain the same at 3Pf.

[0223] The working principle of the shift register unit in this embodiment will be explained below.

[0224] During the discharge phase, before the frame is displayed, a high-level signal is first input to the second reset signal input terminal STV0. The pull-up node PU is discharged through the low-level signal input terminal (e.g., the second power supply terminal LVGL, the fifth power supply terminal VGL) to prevent residual charge in the pull-up node PU from causing display abnormalities.

[0225] During the input phase, a high-level signal is input to the first signal input terminal Input, the twenty-first transistor M21 is turned on, the high-level signal pulls up the pull-up node PU, and charges the first capacitor C1.

[0226] During the output phase, since the pull-up node PU is pulled high during the input phase, both the fifth transistor M5 and the sixth transistor M6 are turned on, and the high-level signal input at the clock signal terminal is output through the first signal output terminal Gout and the first signal output terminal OC.

[0227] During the reset phase, a high-level signal is input to the second reset signal input terminal STV0, turning on the twenty-third transistor 23. A low-level signal is input to the second power supply terminal LVGL, pulling down the potential of the pull-up node PU to reset it. Because the pull-up node PU is pulled low, the fifth transistor M5 and the sixth transistor M6 are turned off, and both the first signal output terminals Gout and OC no longer output high-level signals. Simultaneously, the first pull-down control nodes PD_CNA and PD_A are both high-level signals, turning on the eleventh transistors M11 and M12, and the nineteenth transistor M19, respectively, to reduce noise in the outputs of the pull-up node PU, the first signal output terminal Gout, and the first signal output terminal OC, until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0228] In a second aspect, this disclosure provides a display substrate, which includes a substrate and the aforementioned gate driving circuit, the gate driving circuit being disposed on the substrate.

[0229] Figure 19 shows a schematic diagram of the superimposed gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in an optional embodiment of the present disclosure; Figure 20 shows a planar schematic diagram of the gate metal layer in Figure 19; Figure 21 shows a planar schematic diagram of the semiconductor layer in Figure 19; Figure 22 shows a planar schematic diagram of the source / drain metal layer in Figure 19; Figure 23 shows a planar schematic diagram of the insulating layer in Figure 19; Figure 24 shows a planar schematic diagram of the transparent conductive layer TL in Figure 19.

[0230] As shown in Figure 19, the shift register GOA in the gate drive circuit includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The fifth transistor M5 and the sixth transistor M6 are arranged at intervals along a first direction. The first capacitor C1 and the sixth transistor M6 are located on the same side of the fifth transistor M5 and are arranged at intervals along a second direction Y. The first direction X intersects the second direction Y. The first capacitor C1 includes a first electrode plate 41 and a second electrode plate 42 disposed opposite to each other. The second electrode plate 42 is located on the side of the first electrode plate 41 away from the substrate. The first electrode plate 41 is connected to the control electrode M5_g of the fifth transistor M5 and the control electrode M6_g of the sixth transistor M6. This arrangement makes full use of the space on the substrate, which is beneficial for the display substrate to achieve a narrow bezel.

[0231] Specifically, the display substrate includes a gate metal layer (Gate), a semiconductor layer (ACT), and a source / drain metal layer (SD) sequentially disposed along a direction away from the substrate. The semiconductor layer (ACT) is disposed on the substrate, and can be patterned using a semiconductor material, such as polycrystalline silicon. The semiconductor layer (ACT) may include the active layer and doped region patterns of each transistor in the pixel driving circuit. For the same transistor, doped region patterns are provided on both sides of the active layer, and the doped region patterns on both sides of the active layer can serve as the first and second electrodes of the transistor, respectively.

[0232] As shown in Figure 20, the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 are all located in the gate metal layer. At least a portion of the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 are integrated into a single structure. The first electrode M5_1, the second electrode M5_2 of the fifth transistor M5, the first electrode M6_1, the second electrode M6_2 of the sixth transistor M6, and the second electrode plate 42 of the first capacitor C1 are all located in the source-drain metal layer SD. Integrating at least a portion of the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 into a single structure effectively improves the tightness of the connection between the fifth transistor M5, the sixth transistor M6, and the first electrode plate 41, while also improving space utilization.

[0233] In the specific implementation shown in Figures 19 to 23, the shift register GOA also includes a first transfer electrode 80 and a first connection line 90. The first connection line 90 of the (NM / 2+J)th stage shift register GOA is electrically connected to the second signal input terminal PD_F of the Nth stage shift register GOA. The first transfer electrode 80 is connected to the first connection line 90 through the first via 100, and the first transfer electrode 80 is connected to the first electrode plate 41 through the second via 110.

[0234] As shown in Figures 19 to 23, the display substrate further includes a second signal transmission line 230 and a third adapter electrode 240. One end of the first connection line 90 is connected to the first adapter electrode 80 through a first via 100, and the other end of the first connection line 90 is connected to the third adapter electrode 240 through a fifth via 250. The third adapter electrode 240 is connected to the second signal transmission line 230 through a sixth via 260. The second signal transmission line 230 of the (NM / 2+J)th stage shift register GOA is connected to the second signal input terminal PD_F of the Nth stage shift register GOA.

[0235] The second signal transmission line 230 extends along the second direction Y, the first transition electrode 80 is equivalent to the pull-up node PU in the circuit structure of the shift register GOA, and the third transition electrode 240 is equivalent to the pull-up output terminal PU_out in the circuit structure of the shift register GOA.

[0236] As shown in Figures 19, 20 and 22, the display substrate also includes a first signal transmission line 120 extending along the second direction Y. The first signal transmission line 120 of the (NM / 2)th stage shift register GOA is connected to the first signal input terminal Input of the Nth stage shift register GOA. The orthographic projection of the first connection line 90 on the substrate and the orthographic projection of the first signal transmission line 120 on the substrate are intersected.

[0237] As shown in Figure 19, the display substrate also includes multiple signal transmission lines extending along the second direction Y. The orthographic projection of the first connecting line 90 on the substrate intersects with the orthographic projection of the multiple signal transmission lines on the substrate. In other words, the first connecting line 90 spans multiple transmission lines, which is beneficial to improving space utilization and thus facilitates the development of the display substrate towards a narrow bezel.

[0238] In the specific embodiments shown in Figures 19 to 24, the shift register GOA includes a gate metal layer Gate, a semiconductor layer ACT, a source / drain metal layer SD, and a transparent conductive layer TL arranged sequentially along the direction away from the substrate. The first electrode plate 41 is located in the gate metal layer Gate; the first connection line 90 is located in the source / drain metal layer SD; and the first transfer electrode 80 is located in the transparent conductive layer TL.

[0239] In the specific embodiments shown in Figures 22 and 24, the shift register GOA further includes a second transition electrode 130 and a second connecting line 140. One end of the second connecting line 140 is connected to the second transition electrode 130, and the other end of the second connecting line 140 is connected to the second electrode M6_2 of the sixth transistor M6. The second transition electrode 130 is connected to the second connecting line 140 through a third via 150, and the second transition electrode 130 is connected to the first signal transmission line 120 through a fourth via 160. The first signal transmission line 120 of the (NM / 2)th stage shift register GOA is connected to the first signal input terminal Input of the Nth stage shift register GOA. The second connecting line 140 is located in the source / drain metal layer SD, and the second transition electrode 130 is located in the transparent conductive layer TL.

[0240] In some alternative embodiments, the first signal transmission line 120 of the (NM / 2+J)th stage shift register GOA is connected to the second signal input terminal PD_F of the Nth stage shift register GOA (not shown in the figure).

[0241] In some optional embodiments, the shift register GOA includes a gate metal layer Gate, a semiconductor layer ACT, a source / drain metal layer SD, and a transparent conductive layer TL arranged sequentially in a direction away from the substrate, wherein a first signal transmission line 120 is located in the gate metal layer Gate; a second connection line 140 is located in the source / drain metal layer SD; and a second transfer electrode 130 is located in the transparent conductive layer TL.

[0242] Figure 25 shows a schematic diagram of the superimposed gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in another optional embodiment of this disclosure; Figure 26 shows a planar schematic diagram of the gate metal layer in Figure 25; Figure 27 shows a planar schematic diagram of the semiconductor layer in Figure 25; Figure 28 shows a planar schematic diagram of the source / drain metal layer in Figure 25; Figure 29 shows a planar schematic diagram of the insulating layer in Figure 25; Figure 30 shows a planar schematic diagram of the transparent conductive layer TL in Figure 25.

[0243] In some optional embodiments, please refer to Figures 25 to 29. The shift register GOA also includes a second capacitor C2. The second capacitor C2 includes a first sub-capacitor C2A, a second sub-capacitor C2B, and a third sub-capacitor C2C. The first sub-capacitor C2A, the second sub-capacitor C2B, and the third sub-capacitor C2C are connected in series to form the second capacitor C2 to ensure the capacitance of the second capacitor C2.

[0244] As shown in Figures 26 and 28, the first sub-capacitor C2A includes a first sub-plate 181 and a second sub-plate 182 arranged opposite to each other; the second sub-capacitor C2B includes a third sub-plate 183 and a fourth sub-plate 184 arranged opposite to each other; the third sub-capacitor C2C includes a fifth sub-plate 185 and a sixth sub-plate 186 arranged opposite to each other; the second sub-plate 182, the fourth sub-plate 184, and the fifth sub-plate 185 are electrically connected, and the first sub-plate 181, the third sub-plate 183, and the sixth sub-plate 186 are electrically connected. This arrangement connects the first sub-capacitor C2A, the second sub-capacitor C2B, and the third sub-capacitor C2C in series, which avoids increasing the bezel size, improves the utilization of the substrate space, and achieves a narrow bezel.

[0245] In the specific embodiment shown in Figure 26, the first sub-electrode plate 181, the third sub-electrode plate 183, the fifth sub-electrode plate 185, and the first electrode plate 41 are arranged in the same layer. Compared with the embodiment shown in Figure 20, the first sub-electrode plate 181 in Figure 26 is located between the control electrode M6_g of the sixth transistor M6 and the signal transmission line, while the second sub-electrode plate 182 is located on the side of the first signal transmission line 120 away from the sixth transistor M6, so as to improve space utilization. The first sub-electrode plate 181, the first electrode plate 41, and the control electrode M6_g of the sixth transistor M6 are integrated into a single structure, connecting the first capacitor C1 and the second capacitor C2 together.

[0246] In the specific embodiment shown in Figure 28, the second sub-electrode plate 182, the fourth sub-electrode plate 184, and the sixth sub-electrode plate 186 are arranged in the same layer.

[0247] In the specific embodiments shown in Figures 26 to 30, the shift register GOA further includes a second transition electrode 130. The second sub-electrode 182 and the fourth sub-electrode 184 are connected to the second transition electrode 130 via a third via 150, and the fifth sub-electrode 185 is connected to the second transition electrode 130 via a fourth via 160. The second sub-electrode 182 and the fourth sub-electrode 184 are an integral structure and are connected to the fifth sub-electrode 185 via the second transition electrode 130. Simultaneously, the second sub-electrode 182 and the fourth sub-electrode 184 span multiple signal transmission lines, increasing the capacitance of the second capacitor C2 without increasing the frame width, thus improving space utilization.

[0248] In the specific embodiment shown in Figure 26, the display substrate further includes a first signal transmission line 120. The first signal transmission line 120 of the (NM / 2)th stage shift register GOA is connected to the first signal input terminal Input of the Nth stage shift register GOA. A portion of the first signal transmission line 120 serves as the fifth sub-electrode plate 185. The third sub-capacitor C2C uses a portion of the first signal transmission line 120 as the electrode plate of the second sub-capacitor C2C. This increases the capacitance of the second capacitor C2 without increasing the bezel width, thus improving space utilization.

[0249] Specifically, referring to Figure 28, the sixth sub-plate 186 includes a first extension 187 and a second extension 188. The first extension 187 and the second extension 188 are cross-connected. The first extension 187 is parallel to the first signal transmission line 120. The two ends of the second extension 188 are electrically connected to the first sub-plate 181 and the third sub-plate 183, respectively. The first extension 187 is parallel to the first signal transmission line 120, that is, the orthographic projection of the first extension 187 on the gate metal layer coincides with a part of the first signal transmission line 120, so as to serve as the third sub-capacitor C2C. The arrangement of the first extension 187 can increase the capacitance of the second capacitor C2.

[0250] As shown in Figure 28, the shift register GOA also includes a first transfer electrode 80 and a first connecting line 90. A portion of the first connecting line 90 serves as a second extension 188. The first transfer electrode 80 is connected to the second extension 188 through a first via 100, and the first transfer electrode 80 is also connected to the second extension 188 through a second via 110. By using the first connecting line 90 as the second extension 188, there is no need to separately provide a second extension 188, thus improving the space utilization of the display substrate.

[0251] Figure 31 shows a schematic diagram of the superimposed gate metal layer, semiconductor layer, source / drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in another optional embodiment of the present disclosure; Figure 32 shows a planar schematic diagram of the gate metal layer in Figure 31; Figure 33 shows a planar schematic diagram of the semiconductor layer in Figure 31; Figure 34 shows a planar schematic diagram of the source / drain metal layer in Figure 31; Figure 35 shows a planar schematic diagram of the insulating layer in Figure 31; Figure 36 shows a planar schematic diagram of the transparent conductive layer TL in Figure 31.

[0252] In the specific embodiments shown in Figures 31 to 36, the shift register GOA further includes a second capacitor C2. The orthographic projection of the second capacitor C2 onto the substrate lies between the orthographic projection of the first capacitor C1 onto the substrate and the orthographic projection of the sixth transistor M6 onto the substrate. The second capacitor C2 includes a third electrode plate 191 and a fourth electrode plate 192. The third electrode plate 191 and the first electrode plate 41 are integrally formed, and the second electrode plate 42 and the fourth electrode plate 192 are disposed on the same layer. This configuration increases the second capacitor C2 without increasing the width of the frame, thus improving the utilization rate of the frame.

[0253] In the specific embodiment shown in Figure 36, the first capacitor C1 further includes a fifth electrode plate 43. The fifth electrode plate 43 is located on the side of the second electrode plate 42 away from the first electrode plate 41, and the fifth electrode plate 43 is electrically connected to the first electrode plate 41. The first capacitor C1 is a series capacitor, that is, a sub-capacitor is formed between the first electrode plate 41 and the second electrode plate 42, and a sub-capacitor is formed between the second electrode plate 42 and the fifth electrode plate 43. The two sub-capacitors are connected in series to form the first capacitor C1. While ensuring the capacitance of the first capacitor C1, the area of ​​the orthogonal projection of the first capacitor C1 on the substrate is reduced, thereby improving space utilization.

[0254] In the specific embodiment shown in Figure 36, the second capacitor C2 further includes a sixth electrode plate 193. The sixth electrode plate 193 is located on the side of the fourth electrode plate 192 away from the third electrode plate 191. The sixth electrode plate 193 is electrically connected to the third electrode plate 191. The fifth electrode plate 43 and the sixth electrode plate 193 are disposed on the same layer. The second capacitor C2 is a series capacitor, that is, a sub-capacitor is formed between the third electrode plate 191 and the fourth electrode plate 192, and a sub-capacitor is formed between the fourth electrode plate 192 and the sixth electrode plate 193. The two sub-capacitors are connected in series to form the second capacitor C2, which reduces the area of ​​the orthogonal projection of the second capacitor C2 on the substrate, improves the space utilization, and increases the capacitance of the second capacitor C2.

[0255] In the specific embodiment shown in Figure 31, the shift register GOA further includes a first transfer electrode 80, which is connected to the first electrode plate 41 through a second via 110. The first transfer electrode 80, the fifth electrode plate 43, and the sixth electrode plate 193 are integrally formed. The first electrode plate 41 and the third electrode plate 191 are integrally formed, and the first electrode plate 41 and the fifth electrode plate 43 are electrically connected through the first transfer electrode 80, thereby increasing the capacitance of the first capacitor C1. The third electrode plate 191 and the sixth electrode plate 193 are electrically connected through the first transfer electrode 80, thereby increasing the capacitance of the second capacitor C2.

[0256] As shown in Figure 33, the active layer M5_a of the fifth transistor M5 and the active layer M6_a of the sixth transistor M6 are shown. The active layer M5_a of the fifth transistor M5 includes a first active region M5_a1 and a second active region M5_a2. The first active region M5_a1 and the second active region M5_a2 are arranged at intervals along the second direction Y. The first capacitor C1 and the first active region M5_a1 are arranged at intervals along the first direction X. The active layer M6_a and the second active region M5_a2 of the sixth transistor M6 are arranged at intervals along the first direction X. The first capacitor C1 and the active layer M6_a of the sixth transistor M6 are arranged at intervals along the second direction Y. The first direction X and the second direction Y intersect.

[0257] The display substrate also includes a third connection line 270, which is used to connect other signal transmission lines and other transistors. The third connection line 270 is parallel to and spaced apart from the first connection line 90. The first connection line 90 and the third connection line 270 are arranged along the second direction Y. The first connection line 90 is located between the second connection line 140 and the third connection line 270.

[0258] It should be noted that the first via 100, the second via 110, the third via 150, the fourth via 160, the fifth via 250, and the sixth via 260 are located within the insulating layer PVX.

[0259] In some optional embodiments, the display substrate has a display area and a non-display area, with the gate driving circuit located in the non-display area. The display substrate also includes a transparent electrode located in the display area, which is disposed on the same layer as the first transition electrode 80. The transparent electrode can be a pixel electrode or a common electrode; no specific limitation is made here.

[0260] This disclosure also provides a display device, including the aforementioned display substrate. The display device can include any device or product with display functionality. For example, the display device can be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0261] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A gate driving circuit, wherein, include: A cascaded plurality of shift registers and M clock signal lines connected to the plurality of shift registers are configured. Each shift register includes an input sub-circuit, an output control sub-circuit, and a noise reduction control sub-circuit. The input sub-circuit and the output control sub-circuit are connected to a pull-up node, and the noise reduction control sub-circuit and the output control sub-circuit are connected to a first node. The input sub-circuit is configured to charge the pull-up node under the control of a first input signal terminal. The output control sub-circuit is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node, and to output a second operating voltage to the signal output terminal under the control of the potential of the first node. The noise reduction control sub-circuit is configured to pull down the potential of the first node under the control of a second input signal terminal. The first node includes a pull-down node and / or a pull-down control node, and M is an even number greater than or equal to 4. The first signal input terminal of the shift registers of stages 1 to M / 2 is connected to their respective first start signal terminals. Except for the shift registers of stages 1 to M / 2, the first signal input terminal of the shift register of stage N is connected to the signal output terminal of the shift register of stage (NM / 2). The second signal input terminals of the shift registers from level 1 to level M / 2+P are connected to their respective second start signal terminals. Except for the shift registers from level 1 to level M / 2+P, the second signal input terminal of the shift register of level N is connected to the signal output terminal of the shift register of level (NM / 2-P), where P is a positive integer greater than 0 and less than or equal to M / 2, and N is a positive integer greater than M / 2+P. Alternatively, the second signal input terminal of the shift registers of stages 1 to M / 2-J is connected to their respective second start signal terminals. In addition to the shift registers of stages 1 to M / 2-J, the second signal input terminal of the shift register of stage N is connected to the pull-up output terminal of the shift register of stage (NM / 2+J), and the pull-up output terminal is connected to the pull-up node, wherein J is a positive integer greater than 0 and less than M / 2.

2. The gate driving circuit according to claim 1, wherein, The input sub-circuit is also configured to pull down the potential of the pull-up node under the control of the first reset signal input. Except for the shift registers of the last M / 2+1 stage, the first reset signal input terminal of the shift register of the Nth stage is connected to the signal output terminal of the shift register of the N+M / 2+1 stage, and the first reset signal input terminal of the shift register of the last M / 2+1 stage is connected to its respective first reset signal terminal.

3. The gate driving circuit according to claim 1 or 2, wherein, The pull-down node includes a first pull-down node and a second pull-down node, and the noise reduction control sub-circuit includes: The first transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the first pull-down node, and its second electrode connected to the second power supply terminal. The second transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the second pull-down node, and its second electrode connected to the second power supply terminal.

4. The gate drive circuit according to any one of claims 1 to 3, wherein, The pull-down control node includes a first pull-down control node and a second pull-down control node, and the noise reduction control sub-circuit includes: The third transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the first pull-down control node, and its second electrode connected to the second power supply terminal. The fourth transistor has its control electrode connected to the second signal input terminal, its first electrode connected to the second pull-down control node, and its second electrode connected to the second power supply terminal.

5. The gate drive circuit according to any one of claims 1 to 4, wherein, The output control sub-circuit includes: a pull-up module, a first pull-down control module, and a first pull-down module. The first pull-down control module and the first pull-down module are connected to the first pull-down node. The signal output terminal includes a first signal output terminal and a second signal output terminal. The pull-up module, the pull-up node, the clock signal input terminal, and the first signal output are described. The terminal is connected to the second signal output terminal, and in response to the control of the potential of the pull-up node, it is used to input the clock signal provided by the clock signal input terminal to the first signal output terminal and the second signal output terminal when the potential of the pull-up node is at an effective level. The first pull-down control module is connected to the pull-up node, the first pull-down node, the second power supply terminal, and the third power supply terminal. In response to the control of the potential of the pull-up node, it is used to input the second operating voltage provided by the second power supply terminal to the first pull-down node when the potential of the pull-up node is at an effective level, and to input the third operating voltage provided by the third power supply terminal to the first pull-down node when the potential of the pull-up node is at an ineffective level. The first pull-down module is connected to the first pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal. In response to the control of the potential of the first pull-down node, it is used to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and input the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the first pull-down node is at an effective level.

6. The gate driving circuit according to claim 5, wherein, The pull-up module includes a fifth transistor, a sixth transistor, and a first capacitor. The control terminals of the fifth transistor and the sixth transistor are connected to the pull-up node, the first terminals of the fifth transistor and the sixth transistor are connected to the clock signal input terminal, the second terminal of the fifth transistor is connected to the first signal output terminal, and the second terminal of the sixth transistor is connected to the second signal output terminal. The first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the first signal output terminal.

7. The gate driving circuit according to claim 5, wherein, The clock signal input terminal includes a first clock signal input terminal and a second clock signal input terminal, and the pull-up module includes a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor. The control electrode of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first clock signal input terminal, and the second electrode of the fifth transistor is connected to the first clock signal input terminal. Connect the output terminal; The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second clock signal input terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal. The first terminal of the first capacitor is connected to the pull-up node, and the second terminal of the first capacitor is connected to the first signal output terminal. The first end of the second capacitor is connected to the pull-up node, and the second end of the second capacitor is connected to the second signal output terminal.

8. The gate drive circuit according to any one of claims 5 to 7, wherein, The first pull-down control module includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The control electrode of the seventh transistor is connected to the third power supply terminal, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the first pull-down control node. The control electrode of the eighth transistor is connected to the first pull-down control node, the first electrode of the eighth transistor is connected to the third power supply terminal, and the second electrode of the eighth transistor is connected to the first pull-down node. The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the first pull-down control node, and the second electrode of the ninth transistor is connected to the second power supply terminal. The control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the first pull-down node, and the second electrode of the tenth transistor is connected to the second power supply terminal. The first pull-down module includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is connected to the first pull-down node, the first electrode of the eleventh transistor is connected to the first signal output terminal, and the second electrode of the eleventh transistor is connected to the... Connect the fifth power supply terminal; The control electrode of the twelfth transistor is connected to the first pull-down node, the first electrode of the twelfth transistor is connected to the second signal output terminal, and the second electrode of the twelfth transistor is connected to the second power supply terminal.

9. The gate drive circuit according to any one of claims 5 to 8, wherein, The output control sub-circuit further includes a second pull-down module and a second pull-down control module, wherein the second pull-down control module and the second pull-down module are connected to the second pull-down node; The second pull-down control module is connected to the pull-up node, the second pull-down node, the second power supply terminal, and the fourth power supply terminal. In response to the control of the potential of the pull-up node, it is used to input the second operating voltage provided by the second power supply terminal to the second pull-down node when the potential of the pull-up node is at an effective level, and to input the fourth operating voltage provided by the fourth power supply terminal to the second pull-down node when the potential of the pull-up node is at an ineffective level. The second pull-down module is connected to the second pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal. It responds to the control of the potential of the second pull-down node and is used to input the second working voltage provided by the second power supply terminal to the second signal output terminal and the fifth working voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the second pull-down node is at an effective level. The third operating voltage switches between an active level state and an inactive level state, and the fourth operating voltage switches between an active level state and an inactive level state. At any given time, one of the third operating voltage and the fourth operating voltage is in an effective level state, while the other is in an ineffective level state.

10. The gate driving circuit according to claim 9, wherein, The second pull-down control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The control electrode of the thirteenth transistor is connected to the fourth power supply terminal, the first electrode of the thirteenth transistor is connected to the fourth power supply terminal, and the second electrode of the thirteenth transistor is connected to the second pull-down control electrode. Control node connection; The control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode of the fourteenth transistor is connected to the fourth power supply terminal, and the second electrode of the fourteenth transistor is connected to the second pull-down node. The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode of the fifteenth transistor is connected to the second pull-down control node, and the second electrode of the fifteenth transistor is connected to the second power supply terminal. The control electrode of the sixteenth transistor is connected to the pull-up node, the first electrode of the sixteenth transistor is connected to the second pull-down node, and the second electrode of the sixteenth transistor is connected to the second power supply terminal. The second pull-down module includes: a seventeenth transistor and an eighteenth transistor; The control electrode of the seventeenth transistor is connected to the second pull-down node, the first electrode of the seventeenth transistor is connected to the first signal output terminal, and the second electrode of the seventeenth transistor is connected to the fifth power supply terminal. The control electrode of the eighteenth transistor is connected to the second pull-down node, the first electrode of the eighteenth transistor is connected to the second signal output terminal, and the second electrode of the eighteenth transistor is connected to the second power supply terminal.

11. The gate driving circuit according to claim 9, wherein, The output control sub-circuit also includes a first noise reduction module and a second noise reduction module. The first noise reduction module is connected to the pull-up node, the first pull-down node and the second power supply terminal. In response to the control of the potential of the first pull-down node, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the potential of the first pull-down node is at an effective level. The second noise reduction module is connected to the pull-up node, the second pull-down node, and the second power supply terminal. Responding to the control of the potential of the second pull-down node, it is used to output the second operating voltage provided by the second power supply terminal when the potential of the second pull-down node is at an effective level. Enter into the aforementioned pull-up node.

12. The gate driving circuit according to claim 11, wherein, The first noise reduction module includes a nineteenth transistor, the control electrode of the nineteenth transistor is connected to the first pull-down node, the first electrode of the nineteenth transistor is connected to the pull-up node, and the second electrode of the nineteenth transistor is connected to the second power supply terminal; The second noise reduction module includes a twentieth transistor. The control electrode of the twentieth transistor is connected to the second pull-down node, the first electrode of the twentieth transistor is connected to the pull-up node, and the second electrode of the twentieth transistor is connected to the second power supply terminal.

13. The gate drive circuit according to any one of claims 1 to 12, wherein, The input sub-circuit includes: a signal input module, a first reset module, and a second reset module; The signal input module is connected to the pull-up node, the first signal input terminal, and the first power supply terminal. In response to the voltage control of the first signal input terminal, it is used to input the first operating voltage provided by the first power supply terminal to the pull-up node when the first input signal provided by the first signal input terminal is at an effective level. The first reset module is connected to the pull-up node, the first reset signal input terminal, and the second power supply terminal. In response to the voltage control of the first reset signal input terminal, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the first reset signal input terminal is at an effective level. The second reset module is connected to the pull-up node, the second reset signal input terminal, and the second power supply terminal. In response to the voltage control of the second reset signal input terminal, it is used to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the second reset signal input terminal is at an effective level.

14. The gate drive circuit according to claim 13, wherein, The signal input module includes a 21st transistor, the control electrode of the 21st transistor is connected to the first signal input terminal, the first electrode of the 21st transistor is connected to the first power supply terminal, and the second electrode of the 21st transistor is connected to the pull-up node. The first reset module includes a twenty-second transistor, the control electrode of the twenty-second transistor is connected to the first reset signal input terminal, the first electrode of the twenty-second transistor is connected to the pull-up node, and the second electrode of the twenty-second transistor is connected to the second power supply terminal; The second reset module includes a twenty-third transistor. The control electrode of the twenty-third transistor is connected to the second reset signal input terminal, the first electrode of the twenty-third transistor is connected to the pull-up node, and the second electrode of the twenty-third transistor is connected to the second power supply terminal.

15. A display substrate, wherein, It includes a substrate and a gate driving circuit as described in any one of claims 1 to 14, wherein the gate driving circuit is disposed on the substrate.

16. The display substrate according to claim 15, wherein, The shift register in the gate drive circuit includes: The fifth transistor; The sixth transistor, wherein the fifth transistor and the sixth transistor are arranged at intervals along a first direction; A first capacitor, the first capacitor and the sixth transistor are located on the same side of the fifth transistor and are spaced apart along a second direction, the first direction intersecting the second direction. The first capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other. The second electrode plate is located on the side of the first electrode plate away from the substrate. The first electrode plate is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

17. The display substrate according to claim 16, wherein, The display substrate includes a gate metal layer, a semiconductor layer, and a source / drain metal layer sequentially disposed along a direction away from the substrate. The control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are all located in the gate metal layer. At least a portion of the control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are integrally formed. The first electrode of the fifth transistor, the second electrode of the fifth transistor, the first electrode of the sixth transistor, the second electrode of the sixth transistor, and the second electrode plate of the first capacitor are all located in the source and drain metal layer.

18. The display substrate according to claim 16, wherein, The shift register further includes a first adapter electrode and a first connecting line. The first connecting line of the (NM / 2+J)th stage shift register is electrically connected to the second signal input terminal of the Nth stage shift register. The first adapter electrode is connected to the first connecting line through a first via and to the first electrode plate through a second via.

19. The display substrate according to claim 18, wherein, The display substrate further includes a first signal transmission line extending along a second direction. The first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register. The orthographic projection of the first connection line on the substrate intersects with the orthographic projection of the first signal transmission line on the substrate.

20. The display substrate according to claim 18, wherein, The shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially disposed along a direction away from the substrate. The first electrode plate is located in the gate metal layer; The first connection line is located in the source / drain metal layer; The first transfer electrode is located in the transparent conductive layer.

21. The display substrate according to any one of claims 16 to 20, wherein, The display substrate further includes a first signal transmission line, and the shift register further includes a second adapter electrode and a second connecting line. One end of the second connecting line is connected to the second adapter electrode, and the other end of the second connecting line is connected to the second electrode of the sixth transistor. The second adapter electrode is connected to the second connecting line through a third via and to the first signal transmission line through a fourth via. The first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register.

22. The display substrate according to claim 21, wherein, The first signal transmission line of the shift register of the (NM / 2-P)th stage is connected to the second signal input terminal of the shift register of the Nth stage.

23. The display substrate according to claim 21, wherein, The shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially disposed along a direction away from the substrate. The first signal transmission line is located in the gate metal layer; The second connection line is located in the source / drain metal layer; The second transfer electrode is located in the transparent conductive layer.

24. The display substrate according to any one of claims 16 to 23, wherein, The shift register further includes a second capacitor, the second capacitor comprising: The first sub-capacitor includes a first sub-plate and a second sub-plate that are disposed opposite to each other; The second sub-capacitor includes a third sub-plate and a fourth sub-plate arranged opposite to each other; The third sub-capacitor includes a fifth sub-plate and a sixth sub-plate that are arranged opposite to each other; The second sub-electrode plate, the fourth sub-electrode plate, and the fifth sub-electrode plate are electrically connected, and the first sub-electrode plate, the third sub-electrode plate, and the sixth sub-electrode plate are electrically connected. The first sub-electrode plate, the third sub-electrode plate, the fifth sub-electrode plate, and the first electrode plate are arranged in the same layer. The second sub-electrode plate, the fourth sub-electrode plate, and the sixth sub-electrode plate are arranged in the same layer.

25. The display substrate according to claim 24, wherein, The first sub-electrode plate and the first electrode plate are an integral structure.

26. The display substrate according to claim 24, wherein, The shift register further includes a second transfer electrode, the second sub-electrode and the fourth sub-electrode are connected to the second transfer electrode through a third via, and the fifth sub-electrode is connected to the second transfer electrode through a fourth via.

27. The display substrate according to claim 26, wherein, The display substrate further includes a first signal transmission line, the first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register, and a portion of the first signal transmission line serves as the fifth sub-electrode plate.

28. The display substrate according to claim 27, wherein, The sixth sub-electrode includes a first extension and a second extension, the first extension and the second extension are cross-connected, the first extension is parallel to the first signal transmission line, and the two ends of the second extension are electrically connected to the first sub-electrode and the third sub-electrode, respectively.

29. The display substrate according to claim 28, wherein, The shift register further includes a first adapter electrode and a first connecting line, a portion of the first connecting line serving as the second extension, the first adapter electrode being connected to the second extension via a first via, and the first adapter electrode being connected to the first extension via a second via.

30. The display substrate according to any one of claims 16 to 23, wherein, The shift register further includes a second capacitor, the orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the first capacitor on the substrate and the orthographic projection of the sixth transistor on the substrate, the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate and the first electrode plate are integrally formed, and the second electrode plate and the fourth electrode plate are disposed on the same layer.

31. The display substrate according to claim 30, wherein, The first capacitor further includes a fifth electrode plate, which is located on the side of the second electrode plate away from the first electrode plate, and the fifth electrode plate is electrically connected to the first electrode plate. The second capacitor also includes a sixth electrode plate, which is located on the side of the fourth electrode plate away from the third electrode plate. The sixth electrode plate is electrically connected to the third electrode plate, and the fifth electrode plate and the sixth electrode plate are disposed on the same layer.

32. The display substrate according to claim 31, wherein, The shift register further includes a first transfer electrode, which is connected to the first electrode plate through a second via. The first transfer electrode, the fifth electrode plate, and the sixth electrode plate are integrally formed.

33. The display substrate according to any one of claims 16 to 32, wherein, The active layer of the fifth transistor and the active layer of the sixth transistor, wherein the active layer of the fifth transistor includes a first active region and a second active region, the first active region and the second active region being arranged at intervals along a second direction. The first capacitor and the first active region are arranged at intervals along the first direction; The active layer of the sixth transistor and the second active region are arranged at intervals along the first direction. The first capacitor and the active layer of the sixth transistor are arranged at intervals along a second direction, and the first direction intersects the second direction.

34. The display substrate according to claim 18, wherein, The display substrate has a display area and a non-display area. The gate driving circuit is located in the non-display area. The display substrate also includes a transparent electrode located in the display area. The transparent electrode is disposed on the same layer as the first transfer electrode.

35. A display device, wherein, The display substrate includes any one of claims 15 to 34.

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