sensing resistor

Abstract

The present disclosure relates to sense resistors. Systems and methods for sense resistors are disclosed. In one aspect, an integrated sense resistor includes a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction, and a plurality of thin film resistors each disposed between and electrically connected to a pair of adjacent ones of the first and second metal bumps. The integrated sense resistor can be configured to sense a voltage resulting from a current flowing through the integrated sense resistor to determine a value of the current.

Description

[0001] Cross-references to related applications

[0002] Any and all applications that identify foreign or domestic priority claims in the application data sheet filed with this application are incorporated herein by reference in accordance with 37 CFR 1.57.

[0003] This application claims priority to U.S. Provisional Application No. 63 / 246915, filed December 3, 2021, and U.S. Provisional Application No. 63 / 265252, filed December 10, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0004] Embodiments of the present invention relate to electronic systems, and more specifically, to systems and methods for integrating sensing resistors into a circuit board. Background Technology

[0005] Current-sensing resistors (also known as sensing resistors) are typically discrete resistors soldered onto a customer's circuit board. However, such resistors may not be well-suited to meet the performance goals of an upcoming sensing resistor design, such as low impedance. Therefore, there is a need to improve the performance of the sensing resistor. Summary of the Invention

[0006] The methods and apparatuses described in the technology each have several aspects, none of which are solely responsible for their desired properties.

[0007] In one aspect, an integrated sensing resistor is provided, comprising: a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction; and a plurality of thin-film resistors, each thin-film resistor disposed between and electrically connected to a pair of adjacent first and second metal bumps, wherein the integrated sensing resistor is configured to sense a voltage generated by a current flowing through the integrated sensing resistor to determine the value of the current.

[0008] In another aspect, a packaged system (SiP) is provided, comprising: a substrate; and an integrated sensing resistor, comprising: a plurality of first metal pads or bumps alternating with a plurality of second metal pads or bumps in at least a first lateral direction, and a plurality of thin-film resistors, each thin-film resistor disposed between and electrically connected to a pair of adjacent first and second metal pads or bumps; wherein the first metal pads or bumps are electrically connected to each other through the substrate, and wherein the second metal contact pads or bumps are electrically connected to each other through the substrate.

[0009] In another aspect, an integrated sensing resistor is provided, comprising: a plurality of first metal pads alternating with a plurality of second metal pads in at least a first lateral direction; and a plurality of thin-film resistors, each thin-film resistor disposed between and electrically connected to a pair of adjacent first and second metal pads, wherein the first metal pads are electrically disconnected from each other, and wherein the second metal pads are electrically disconnected from each other. Attached Figure Description

[0010] These accompanying drawings and related descriptions are provided to illustrate specific embodiments of the invention, and not to limit it.

[0011] Figure 1 An example of a sensing resistor integrated into a partially assembled module according to aspects of this disclosure is shown, the module including the sensing resistor.

[0012] Figure 2 It shows Figure 1 The module includes bumps and is encapsulated in a molded part.

[0013] Figure 3 An integrated resistor with alternating first and second metal bumps in the vertical direction is shown.

[0014] Figure 4 An integrated resistor with alternating first and second metal bumps in the vertical and horizontal directions is shown.

[0015] Figure 5A and 5B An exemplary vertical metal level is shown according to aspects of this disclosure.

[0016] Figure 6A and 6B An embodiment of a thin-film resistor according to aspects of this disclosure is shown.

[0017] Figure 7 Another embodiment of a thin-film resistor constructed for a waffle design sensing resistor according to aspects of this disclosure is shown.

[0018] Figure 8A and 8B A view of a thin-film resistor at the stage of integration into a sensing resistor, according to aspects of this disclosure, is shown. Detailed Implementation

[0019] The various aspects of the novel systems, apparatus, and methods will be described more fully below with reference to the accompanying drawings. However, aspects of this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete and will fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that this disclosure is intended to cover any aspect of the novel systems, apparatus, and methods disclosed herein, whether implemented independently of or in combination with any other aspect. For example, any number of aspects set forth herein may be used to implement an apparatus or practice method. Furthermore, the scope is intended to include an apparatus or method that is practiced using structures, functions, or structures and functions other than those set forth herein. It should be understood that any aspect disclosed herein may be embodied by one or more elements of the claims.

[0020] While specific aspects are described herein, numerous variations and arrangements of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of this disclosure is not intended to be limited to specific benefits, uses, or purposes. Rather, aspects of this disclosure are intended to be broadly applicable to various wired and wireless technologies, system configurations, networks (including optical networks, hard disks, and transport protocols), some of which are illustrated by way of example in the accompanying drawings and in the following description of preferred aspects. The detailed description and accompanying drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0021] In this specification, reference is made to the accompanying drawings, wherein similar reference numerals may indicate the same or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it should be understood that some embodiments may include more elements than shown in the drawings and / or a subset of the elements illustrated in the drawings. Additionally, some embodiments may combine any suitable combination of features from two or more drawings.

[0022] Current sensing resistor overview

[0023] Current-sensing resistors (also known as sensing resistors) are typically discrete resistors soldered onto a customer's circuit board. Some sensing resistors are integrated with other integrated circuit components, which can limit their footprint. Therefore, there is a need for the ability to manufacture very compact sensing resistors at a relatively low cost.

[0024] Some traditional integrated resistor architectures may not be well-suited to meeting the performance targets of sensing resistors, including low impedance. This is likely because integrated precision resistors typically use resistive films with high thin-film resistance. Furthermore, metal interconnects can also have relatively high impedance. In addition, absolute resistance error, temperature drift, and limited heat dissipation also make integrated sensing resistors very challenging.

[0025] To meet these and other needs, this paper discloses an integrated sensing resistor.

[0026] Figure 1 An example of a sensing resistor integrated into a partially assembled module according to aspects of this disclosure is shown, the module including the sensing resistor. Reference Figure 1 Module 100 includes a printed circuit board (PCB) 102, a first integrated circuit 104, a second integrated circuit 106, a sensing resistor 108, and one or more discrete components 110. In some embodiments, the sensing resistor 108 may be implemented as a third integrated circuit. Furthermore, the one or more discrete components 110 may include passive components, such as capacitors. According to an embodiment, the printed circuit board 102 may be implemented as a laminated printed circuit board. Figure 2 It shows Figure 1 Module 100 includes bumps 122 and is encapsulated in a molding 124. Module 100 may represent a system in a package (SiP).

[0027] There are many considerations and / or properties when designing modules with integrated sense resistors. One consideration is to reduce or minimize the resistance of the sense resistor to reduce the voltage drop of relatively high current signals. This can pose challenges for some existing technologies, such as precision thin-film resistors with relatively high sheet resistance.

[0028] Another consideration is to reduce or minimize parasitic resistance to reduce headroom loss. This can be challenging when the interconnect metal layer thickness is less than about 1 μm when fabricated using integrated interconnect metallization processes.

[0029] Another consideration is the accuracy of the absolute resistance, as the error in measuring current can be proportional to the error in resistance. Manufacturing tolerances may be wider than the acceptable error margin for current sensing, which could lead to unacceptably large measurement errors.

[0030] A desirable property of sensing resistors is to provide temperature stability, as temperature drift can cause errors in the measured current. Thin films can be relatively temperature stable, but further improvements in temperature stability are desirable.

[0031] Another desirable property is good power handling, which enables higher measurement currents. When thin-film resistors are formed in an oxide stack, the resulting thermal insulation can increase the operating temperature of the thin-film resistor. Reducing the amount of heating can be expected to enable the measurement of higher currents.

[0032] Another consideration is the size of the sensing resistor, as available space on the module may be limited. The space occupied by the sensing resistor may be related to its power handling capability; therefore, higher power handling capability is required to achieve a smaller sensing resistor size.

[0033] Another consideration is the cost of manufacturing the sensing resistor, which can be used to integrate multiple sensing resistor modules. Since integrated circuit manufacturing is generally more complex than discrete manufacturing, cost can be a significant factor in the manufacturing of sensing resistors.

[0034] According to one aspect of this disclosure, the integrated sensing resistor includes a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction. The metal bumps may include any suitable solder metal bumps, including lead-based and lead-free solder bumps, and may include metallic elements such as lead (Pb), tin (Sn), silver (Ag), bismuth (Bi), antimony (Sb), indium (In), and cadmium (Cd). The sensing resistor further includes a plurality of thin-film resistors, each disposed between and electrically connected to a pair of adjacent first and second metal bumps. The integrated sensing resistor is configured to sense the voltage generated by a current flowing through the integrated sensing resistor to determine the value of the current. For example, the resistance of the sensing resistor (Rsense) may be predetermined, and the unknown current can be calculated based on the relationship I = (Vmeasured) / (Rsense) by measuring the voltage on the sensing line caused by an unknown current flowing therethrough.

[0035] In some embodiments, during manufacturing, the first metal bumps are electrically disconnected from each other, and the second metal bumps are electrically disconnected from each other. In these embodiments, an integrated sensing resistor may be formed on a substrate such that the first and second metal bumps are electrically connected to each other through the substrate, and the second metal bump is electrically connected to each other via the substrate.

[0036] Figure 3 and Figure 4 An example configuration of an integrated resistor according to aspects of this disclosure is shown. Specifically, Figure 3 An integrated resistor with alternating first and second metal bumps in the vertical direction is shown. Figure 4 An integrated resistor with alternating first and second metal bumps in the vertical and horizontal directions is shown.

[0037] refer to Figure 3The integrated sensing resistor 300 includes a plurality of first bumps 302 (also labeled "A"), a plurality of second bumps 304 (also labeled "B"), and a plurality of thin-film resistors 306. The first bumps 302 and second bumps 304 may also be referred to as first metal pads 302 and second metal pads 304. The first bumps 302 and second bumps 304 are arranged in rows of width "X", and the thin-film resistors 306 have a width of "Y". Since the thin-film resistors are positioned between adjacent rows, each row is separated by a distance "Y". Therefore, the rows of first bumps 302 and second bumps 304 can extend in a first lateral direction, and these rows can alternate in a second lateral direction orthogonal to the first lateral direction.

[0038] refer to Figure 4 The integrated sensing resistor 310 also includes a plurality of first bumps 302 (also labeled "A") and a plurality of second bumps 304 (also labeled "B"). In this embodiment, the first bumps 302 and the second bumps 304 are arranged in rows of width "X", with each row spaced apart by a distance "Y". (Refer to reference...) Figure 3 The described integrated sensing resistor 300 differs from the one in that... Figure 4 In the illustrated embodiment, the first metal bump 302 and the second metal bump 304 alternate in each of the first and second lateral directions, such that the first and second metal bumps 302 and 304 are arranged in a checkerboard or waffle pattern.

[0039] In some embodiments, the first metal bump 302 and the second metal bump 304 form an array including rows extending in a first lateral direction and columns extending in a second lateral direction, wherein each of the rows and columns includes a first metal bump 302 alternating with the second metal bump 304.

[0040] In some embodiments, adjacent rows are separated by a first lateral direction (e.g., Figure 4 A row of thin-film resistors 306 aligned in the horizontal direction is inserted, and adjacent columns are formed by a second lateral direction (e.g., Figure 4 A row of thin-film resistors 306 are inserted, aligned vertically.

[0041] like Figure 3 and 4 As shown, each thin-film resistor 306 has a rectangular trace defined by a first lateral dimension (e.g., a length having a distance Y) and a second lateral dimension greater than the first lateral dimension (e.g., a width having a distance X), wherein the second lateral dimension corresponds to the length of the thin-film resistor through which the current flows. As at least in Figure 4 In waffle designs, the area footprint of integrated sensing resistors can be significantly reduced. For example, for illustrative purposes only, when Figure 3The thin-film resistor 306 of the integrated sensing resistor 300 shown is... Figure 4 The integrated sensing resistor 310 shown has thin-film resistors 306 with the same width and length, and when the integrated sensing transistor 300 and the integrated sensing resistor 310 have the same total footprint, the integrated sensing resistor 300 integrates 16 thin-film resistors 306, while the integrated sensing resistor 310 integrates 25 thin-film resistors 308. Therefore, Figure 4 The waffle design shown (where the first and second metal bumps 302, 304 alternate in two lateral directions) can provide further reductions in footprint or higher resistor density per unit area, relative to Figure 3 The design shown has the first and second metal bumps 302, 304 alternating on one of them in the lateral direction instead of the other.

[0042] In some embodiments, the array of first metal bumps 302 and second metal bumps 304 includes the same number of thin-film resistors 306, wherein current flows from left to right in a first lateral direction, while current in the thin-film resistors 306 flows from right to left in a first lateral direction. Furthermore, the array of first metal bumps 302 and second metal bumps 304 includes the same number of thin-film resistors 306, wherein current flows from top to bottom in a second lateral direction, relative to current in the thin-film resistors 306 flowing from bottom to top in the second lateral direction. Due to this arrangement, the Seebeck effect caused by the temperature gradient across the integrated sensing resistor can be substantially canceled.

[0043] Figure 5A and 5B An exemplary vertical metal level is shown according to aspects of this disclosure. Specifically, Figure 5A A first vertical metal level 500 (also referred to as a first board substrate) is shown, including an opening 502 and a region 504 (e.g., a pad), the opening 502 being configured to allow a first metal bump 302 to pass through the first vertical metal level 500, and the region 504 being configured to be electrically connected to a second metal bump 304. Figure 5B A second vertical metal level 510 (also referred to as a second board substrate) is shown, including a region 512 (e.g., a pad) configured to be electrically connected to a first metal bump 302.

[0044] In some embodiments, the first metal bumps 302 are electrically connected to each other at a second vertical metal level 510, and the second metal bumps are electrically connected to each other at a first vertical metal level 500, which is different from the second vertical metal level 510. In some embodiments, the vertical metal layers 500 and 510 may be implemented as laminates receiving metal layers and / or metal sheets.

[0045] Figure 6A and6B Embodiments of thin-film resistors according to aspects of this disclosure are shown. In particular, according to aspects of this disclosure, Figure 6A A cross-section of a thin-film resistor 600 in operation is shown. Figure 6B A top view of a thin-film resistor 600 according to aspects of this disclosure is shown.

[0046] Reference Figure 6A and 6B The thin-film resistor 600 includes a first layer 602, a second layer 604, a plurality of through-holes 606, and a plurality of metal interconnects (also referred to as sensing lines), the metal interconnects including A Sense Interconnect 608, A Force Interconnect 610, B Sense Interconnect 612 and B Force Interconnect 614. In some embodiments, the first layer 602 is formed of silicon-chromium (SiCr) and the second layer 604 is formed of tungsten-titanium (TiW).

[0047] The thin-film resistor 600 may also include two distinct regions, including a first region 616 having a positive resistivity (TCR) and a second region 618 having a negative TCR, the second region being arranged, for example, in series, such that the net TCR is smaller than the TCR of each of the first and second regions 616, 618. In some embodiments, the total TCR of the first region 616 and the second region 618 together may be substantially zero. For example, but not limited to, the first region 616 may be formed of a TiW thin film with a positive TCR, while the second region 618 may be formed of a SiCr thin film with a negative TCR, such that the overall TCR is significantly reduced relative to the TCR of each of the first and second regions 616, 618. Sensing lines 608-614 may be electrically coupled to the thin-film resistor 600 at the resistor level (e.g., at the level of the first layer 602 and the second layer 604) through vias 606. Additionally, sensing lines 608-614 and vias 606 may be formed outside the sensing loop defined by the first region 616 and the second region 618. In one example, current 620 can be drawn from A Force Interconnect 610 flows through the thin-film resistor, through the first region 616 and the second region 618, and out of B. Force Interconnection 614.

[0048] Figure 7 A sensing resistor 310 for waffles is shown according to aspects of this disclosure. Figure 4 Another embodiment of the thin-film resistor 700 constructed therefrom. Specifically, Figure 7 The thin-film resistor 700 can have substantially the same components as the thin-film resistor 600 in Figure 6, and its layout can be configured as a "waffle" design sensing resistor, for example... Figure 4 The sensing resistor 310.

[0049] Figure 8A and 8B A view of a thin-film resistor 700 integrated into a sensing resistor 310, according to aspects of this disclosure, is shown. Specifically, Figure 8A A thin-film resistor 700 is shown disposed between a first bump 302 and a second bump 304 of an integrated sensing resistor 310. (See reference...) Figure 7 and 8A The first protrusion 302 can be connected to A Sense Interconnect 608, and the second bump 304 can be connected to B. Sense Interconnect 612. Figure 8B The location of the thin-film resistor 700 within an example layout of the integrated sensing resistor 310 is shown.

[0050] In various embodiments, the thin-film resistor 600 is photolithographically patterned on a semiconductor substrate.

[0051] In some embodiments, the integrated sensing resistor is formed on a board substrate including a laminated polymer substrate (e.g., a laminated PCB), and additional discrete integrated circuit components are formed on this substrate. One embodiment of such a PCB is... Figure 1 PCB 102.

[0052] On the other hand, the system-in-package (SiP) includes a substrate and an integrated sensing resistor 310. The integrated sensing resistor 310 includes a plurality of first metal pads or bumps 302 alternating with a plurality of second metal pads or bumps 304 in at least a first lateral direction, and a plurality of thin-film resistors 600, each thin-film resistor 600 disposed between and electrically connected to a pair of adjacent metal pads and bumps of the first and second metal pads or bumps 302 and 304. The first metal pads or bumps 302 are electrically connected to each other via the substrate, and the second metal contact pads or bumps 304 are electrically connected to each other via the substrate.

[0053] On the other hand, the integrated sensing resistor 310 includes a plurality of first metal pads 302 alternating with a plurality of second metal pads 304 at least in a first lateral direction. The integrated sensing resistor 310 also includes a plurality of thin-film resistors 600, each thin-film resistor 600 disposed between and electrically connected to a pair of adjacent metal pads of the first and second metal pads 302 and 304. As manufactured, the first metal pads 304 are electrically disconnected from each other, and the second metal pads 304 are electrically disconnected from each other.

[0054] As disclosed herein, the disclosed sensing resistor achieves area efficiency through the use of a "waffle" design, which allows for a resistor width increase of over 60% in a given die region compared to a standard strip resistor. The disclosed sensing resistor leverages the benefits of low-resistance thick copper traces on a laminated substrate, where the thick copper traces are integrated into the resistor design, significantly reducing parasitic resistance. Furthermore, the integrated sensing resistor can be configured to at least partially cancel thermoelectric effects. Therefore, even with a temperature gradient across the sensing resistor die, the voltage generated by the Seebeck effect can be substantially canceled by a corresponding Seebeck effect voltage in the opposite direction. Combining the waffle design with the use of distributed bumps / pillars on the integrated sensing resistor optimizes heat dissipation. Finally, using the resistor material itself on the back side of the sensing resistor allows for a relatively direct method of canceling negative and positive TCRs, thus keeping the total TCR close to zero ppm / °C.

[0055] Another example:

[0056] 1. An integrated sensing resistor, comprising:

[0057] A plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction; and

[0058] Multiple thin-film resistors, each disposed between a pair of adjacent ones of the first and second metal bumps and electrically connected,

[0059] The integrated sensing resistor is configured to sense the voltage generated by the current flowing through the integrated sensing resistor in order to determine the value of the current.

[0060] 2. The integrated sensing resistor of embodiment 1, wherein the first metal bumps are electrically disconnected from each other, and wherein the second metal bumps are electrically disconnected from each other.

[0061] 3. The integrated sensing resistor of Embodiment 1, wherein the integrated sensing resistor is formed on a substrate, wherein the first and second metal bumps are electrically connected to each other through the substrate, and wherein the second metal bumps are electrically connected to each other through the substrate.

[0062] 4. The integrated sensing resistor of embodiment 1, wherein the first metal bump and the second metal bump are further alternated in a second direction intersecting the first lateral direction.

[0063] 5. The integrated sensing resistor of embodiment 1, wherein the first metal bump and the second metal bump are further alternated in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal bumps are arranged in a checkerboard pattern.

[0064] 6. An integrated sensing resistor of embodiment 1, wherein the first metal bump and the second metal bump are further alternated in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal bumps form an array, the array comprising rows extending in the first lateral direction and columns extending in the second lateral direction, each of the rows and columns comprising a first metal bump alternating with the second metal bump.

[0065] 7. An integrated sensing resistor of embodiment 5, wherein adjacent rows are inserted by a row of thin-film resistors aligned in the first lateral direction, and wherein adjacent columns are inserted by a column of thin-film resistors aligned in the second lateral direction.

[0066] 8. An integrated sensing resistor in any of the above embodiments, wherein the thin-film resistor comprises the same number of thin-film resistors, wherein the current flows from left to right in the first lateral direction relative to the thin-film resistors from right to left in the first lateral direction.

[0067] 9. An integrated sensing resistor according to any of the above embodiments, wherein the thin-film resistor is photolithographically patterned on a semiconductor substrate.

[0068] 10. An integrated sensing resistor according to any of the above embodiments, wherein the thin-film resistor comprises a stack, the stack comprising a first layer having a positive resistivity (TCR) and a second layer having a negative TCR, such that the net TCR has a smaller magnitude than the TCR of each of the first layer and the second layer.

[0069] 11. An integrated sensing resistor according to any of the above embodiments, wherein each of the thin-film resistors has a rectangular trace defined by a first lateral dimension and a second lateral dimension greater than the first lateral dimension, wherein the second lateral dimension corresponds to the length of the thin-film resistor through which current flows.

[0070] 12. An integrated sensing resistor according to any of the above embodiments, wherein the first metal bumps are electrically connected to each other at a first vertical metal level, and the second metal bumps are electrically connected to each other at a second vertical metal level different from the first vertical metal level.

[0071] 13. The integrated sensing resistor of embodiment 12, wherein the first metal pads or bumps are electrically connected to each other via a first metal sheet at the first vertical metal level, and the second metal pads or bumps are electrically connected to each other via a second metal sheet at the second vertical metal level.

[0072] 14. An integrated sensing resistor according to any of the above embodiments, wherein the integrated sensing resistor is formed on a substrate comprising a laminated polymer substrate, on which additional discrete integrated circuit components are formed.

[0073] 15. A packaging system (SiP), comprising:

[0074] Board substrate; and

[0075] Integrated sensing resistor, including:

[0076] A plurality of first metal pads or bumps alternating with a plurality of second metal pads or bumps in at least a first lateral direction, and

[0077] Multiple thin-film resistors, each thin-film resistor is disposed between a pair of adjacent first and second metal pads or bumps and electrically connected;

[0078] The first metal pads or bumps are electrically connected to each other through the substrate, and the second metal contact pads or bumps are electrically connected to each other through the substrate.

[0079] 16. The SiP of Example 15, wherein the first metal pad or bump and the second metal pad or bump further alternate in a second direction intersecting the first lateral direction.

[0080] 17. The SiP of Example 15, wherein the first metal pad or bump and the second metal pad or bump further alternate in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal pads or bumps are arranged in a checkerboard pattern.

[0081] 18. The SiP of Example 15, wherein the first metal pad or bump and the second metal pad or bump further alternate in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal pads or bumps form an array comprising rows extending in the first lateral direction and columns extending in the second lateral direction, each row and column comprising the first metal pad or bump alternating with the second metal pad or bump.

[0082] 19. The SiP of Example 18, wherein adjacent rows are inserted by a row of thin-film resistors aligned in the first lateral direction, and wherein adjacent columns are inserted by a column of thin-film resistors aligned in the second lateral direction.

[0083] 20. The SiP of any one of Examples 15-19, wherein the thin film resistor comprises the same number of thin film resistors, wherein the current flows from left to right in the first lateral direction relative to the thin film resistors that flow from right to left in the first lateral direction.

[0084] 21. The SiP of any one of Examples 15-20, wherein the thin film resistor is photolithographically patterned on a semiconductor substrate.

[0085] 22. The SiP of any one of Examples 15-21, wherein the thin film resistor comprises a stack including a first layer having a positive resistivity (TCR) and a second layer having a negative TCR, such that the net TCR has a smaller magnitude than the TCR of each of the first layer and the second layer.

[0086] 23. The SiP of any one of Examples 15-22, wherein each of the thin-film resistors has a rectangular trace defined by a first lateral dimension and a second lateral dimension greater than the first lateral dimension, wherein the second lateral dimension corresponds to the length of the thin-film resistor through which current flows.

[0087] 24. The SiP of any one of Examples 15-23, wherein the first metal pads or bumps are electrically connected to each other at a first vertical metal level, and the second metal pads or bumps are electrically connected to each other at a second vertical metal level different from the first vertical metal level.

[0088] 25. The SiP of Example 24, wherein the first metal pads or bumps are electrically connected to each other at the first vertical metal level via a first metal sheet, and the second metal pads or bumps are electrically connected to each other at the second vertical metal level via a second metal sheet.

[0089] 26. The SiP of any one of Examples 15-25, wherein the substrate comprises a laminated polymer substrate, and wherein additional discrete integrated circuit components are formed thereon on the substrate.

[0090] 27. An integrated sensing resistor, comprising:

[0091] A plurality of first metal pads alternating with a plurality of second metal pads in at least a first lateral direction; and

[0092] Multiple thin-film resistors, each disposed between a pair of adjacent first and second metal pads and electrically connected,

[0093] The first metal pads are electrically disconnected from each other, and the second metal pads are electrically disconnected from each other.

[0094] 28. An integrated sensing resistor of embodiment 27, wherein the first metal pads are configured to be electrically connected to each other via a substrate, and wherein the second metal contact pads are configured to be electrically connected to each other via the substrate.

[0095] 29. An integrated sensing resistor of embodiment 27 or 28, wherein the first metal pad and the second metal pad are further alternated in a second direction intersecting the first lateral direction.

[0096] 30. An integrated sensing resistor of embodiment 27 or 28, wherein the first metal pad and the second metal pad are further alternated in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal pads are arranged in a checkerboard pattern.

[0097] 31. An integrated sensing resistor of embodiment 27 or 28, wherein the first metal pad and the second metal pad are further alternated in a second lateral direction orthogonal to the first lateral direction, such that the first and second metal pads form an array including rows extending in the first lateral direction and columns extending in the second lateral direction, each row and column including the first metal pads alternating with the second metal pads.

[0098] 32. An integrated sensing resistor of embodiment 31, wherein adjacent rows are inserted by a row of thin-film resistors aligned in the first lateral direction, and wherein adjacent columns are inserted by a column of thin-film resistors aligned in the second lateral direction.

[0099] 33. An integrated sensing resistor of any one of embodiments 27-32, wherein the thin-film resistor comprises the same number of thin-film resistors, wherein the current flows from left to right in the first lateral direction relative to the thin-film resistors that flow from right to left in the first lateral direction.

[0100] 34. An integrated sensing resistor of any one of Examples 27-33, wherein the thin-film resistor is photolithographically patterned on a semiconductor substrate.

[0101] 35. An integrated sensing resistor of any one of embodiments 27-34, wherein the thin-film resistor comprises a stack including a first layer having a positive resistivity (TCR) and a second layer having a negative TCR, such that the net TCR has a smaller magnitude than the TCR of each of the first layer and the second layer.

[0102] 36. An integrated sensing resistor of any one of embodiments 27-35, wherein each of the thin-film resistors has a rectangular trace defined by a first lateral dimension and a second lateral dimension greater than the first lateral dimension, wherein the second lateral dimension corresponds to the length of the thin-film resistor through which current flows.

[0103] 37. An integrated sensing resistor of any of embodiments 27-36, wherein the first metal pads are electrically connected to each other at a first vertical metal level, and the second metal pads are electrically connected to each other at a second vertical metal level different from the first vertical metal level.

[0104] 38. An integrated sensing resistor of embodiment 37, wherein the first metal pads are electrically connected to each other via a first metal sheet at the first vertical metal level, and the second metal pads are electrically connected to each other via a second metal sheet at the second vertical metal level.

[0105] in conclusion

[0106] As will be appreciated above, any feature of any embodiment may be combined with or replaced with any other feature of any other embodiment.

[0107] The aspects of this disclosure can be implemented in a variety of electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic testing equipment, cellular communication infrastructure such as base stations, wearable computing devices such as smartwatches or headphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptops, tablets, personal digital assistants (PDAs), microwave ovens, refrigerators, vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable storage chips, washing machines, dryers, washer / dryer systems, peripherals, clocks, etc. Furthermore, electronic devices may include unfinished products.

[0108] Unless the context explicitly requires otherwise, throughout the specification and claims, the terms “comprising,” “including,” “containing,” “supposing,” and “containing” should be interpreted as inclusive, not exclusive or exhaustive; that is, in the sense of “including but not limited to,” the term “coupled” as commonly used herein refers to two or more elements that can be directly connected, or connected by one or more intermediate elements. Similarly, as generally used herein, the term “connected” refers to two or more elements that can be directly connected, or connected by one or more intermediate elements. Furthermore, the terms “here,” “above,” “below,” and terms with similar meanings used in this application should refer to the entire application, and not any particular part of it. Where the context permits, singular or plural terms used in the above detailed description may also include plural or singular, respectively. The term “or” refers to a list of two or more items, and this term encompasses all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0109] Furthermore, the conditional language used herein, such as “may,” “possibly,” “can,” “e.g.,” “as,” etc., unless otherwise specifically stated or otherwise understood in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or states, while other embodiments do not. Therefore, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, or states are included or will be performed in any particular embodiment.

[0110] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, when blocks are presented in a given arrangement, alternative embodiments may use different components and / or circuit topologies to perform similar functions, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above may be combined to provide further embodiments. The various features and processes described above may be implemented independently of each other or may be combined in various ways. All possible combinations and sub-combinations of the features of this disclosure are intended to fall within the scope of this disclosure.

Claims

1. An integrated sensing resistor, comprising: A plurality of first metal bumps alternating with a plurality of second metal bumps in a first lateral direction, wherein the first metal bumps and the second metal bumps further alternate in a second direction intersecting the first lateral direction, wherein the second direction is orthogonal to the first lateral direction, such that the first metal bumps and the second metal bumps are arranged in a checkerboard pattern. and Multiple thin-film resistors, each thin-film resistor being disposed between and electrically connected to a pair of adjacent first and second metal bumps in the first and second metal bumps. The integrated sensing resistor is configured to sense the voltage generated by the current flowing through the integrated sensing resistor in order to determine the value of the current.

2. The integrated sensing resistor according to claim 1, wherein, The integrated sensing resistor is formed on a substrate, wherein the first metal bump and the second metal bump are electrically connected to each other through the substrate, and wherein the second metal bump is electrically connected to each other through the substrate.

3. The integrated sensing resistor according to claim 1, wherein, The first metal bump and the second metal bump form an array, the array including rows extending in the first lateral direction and columns extending in the second direction, each of the rows and columns including a first metal bump alternating with the second metal bump.

4. The integrated sensing resistor according to claim 3, wherein, Adjacent rows are inserted by a row of thin-film resistors aligned in the first lateral direction, and adjacent columns are inserted by a column of thin-film resistors aligned in the second direction.

5. The integrated sensing resistor according to claim 1, wherein, The thin-film resistor is photolithographically patterned on a semiconductor substrate.

6. The integrated sensing resistor according to claim 1, wherein, The first metal bumps are electrically connected to each other at a first vertical metal level, and the second metal bumps are electrically connected to each other at a second vertical metal level different from the first vertical metal level.

7. A SiP (System-in-Package) packaging system, comprising: Board substrate; and Integrated sensing resistor, including: A plurality of first metal pads or bumps alternate with a plurality of second metal pads or bumps in a first lateral direction, and wherein the first metal pads or bumps and the second metal pads or bumps further alternate in a second direction intersecting the first lateral direction, wherein the second direction is orthogonal to the first lateral direction, such that the first metal pads or bumps and the second metal pads or bumps are arranged in a checkerboard pattern. Multiple thin-film resistors, each thin-film resistor being disposed between and electrically connected to a pair of adjacent first metal pads or bumps and second metal pads or bumps in the first metal pad or bump and the second metal pad or bump. The first metal pads or bumps are electrically connected to each other through the substrate, and the second metal pads or bumps are electrically connected to each other through the substrate.

8. The SiP packaging system according to claim 7, wherein, The thin-film resistor is photolithographically patterned on a semiconductor substrate.

9. The SiP packaging system according to claim 7, wherein, The first metal pads or bumps are electrically connected to each other at a first vertical metal level, and the second metal pads or bumps are electrically connected to each other at a second vertical metal level different from the first vertical metal level.

10. The SiP packaging system according to claim 9, wherein, The first metal pads or bumps are electrically connected to each other at the first vertical metal level via a first metal sheet, and the second metal pads or bumps are electrically connected to each other at the second vertical metal level via a second metal sheet.

11. The SiP packaging system according to claim 7, wherein, The substrate includes a laminated polymer substrate, and wherein additional discrete integrated circuit components are formed thereon on the substrate.

12. An integrated sensing resistor, comprising: A plurality of first metal pads alternating with a plurality of second metal pads in a first lateral direction, wherein the first metal pads and the second metal pads further alternate in a second direction intersecting the first lateral direction, wherein the second direction is orthogonal to the first lateral direction, such that the first metal pads and the second metal pads are arranged in a checkerboard pattern; and Multiple thin-film resistors, each thin-film resistor being disposed between and electrically connected to a pair of adjacent first and second metal pads. in, The first metal pads are electrically disconnected from each other, and the second metal pads are electrically disconnected from each other.

13. The integrated sensing resistor according to claim 12, wherein, The first metal pads are configured to be electrically connected to each other via a substrate, and the second metal pads are configured to be electrically connected to each other via the substrate.

14. The integrated sensing resistor according to claim 12, wherein, The thin-film resistor includes the same number of thin-film resistors in which current flows from right to left in the first lateral direction, relative to the thin-film resistor in which current flows from left to right in the first lateral direction.

15. The integrated sensing resistor according to claim 12, wherein, The thin-film resistor comprises a stack including a first layer having a positive resistivity TCR and a second layer having a negative TCR, such that the net TCR has a smaller magnitude than the TCR of each of the first and second layers.

16. The integrated sensing resistor according to claim 13, wherein, The first metal pads are configured to be electrically connected to each other at a first vertical metal level above the substrate, and the second metal pads are configured to be electrically connected to each other at a second vertical metal level above the substrate, which is different from the first vertical metal level.

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