Multi-channel DDR read and write arbitration device based on FPGA

Abstract

The present invention discloses a multi-channel DDR read / write arbitration device based on an FPGA, comprising: an acquisition module for receiving first data through multiple channels and storing the data in a FIFO write module, generating write command protocol data corresponding to the first data, and sending the data to an arbitration module; an excitation source module for generating read command protocol data according to a preset display format and sending the data to the arbitration module; an arbitration module for storing write command protocol data or read command protocol data on a first-come, first-served basis; and a device for writing the first data into the DDR according to the write command protocol data, and reading second data from the DDR according to the read command protocol data, and storing the second data in the FIFO read module. The embodiment of the present invention avoids the need for more logic resources to calculate the remaining channel space due to the uncertainty of the input data width when reading and writing the DDR, thereby improving read and write efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a multi-channel DDR read-write arbitration device based on FPGA. Background Art

[0002] With the rapid development of the information age, the total amount of data is constantly increasing, requiring memory capacity to be increased and improved. DDR (Double Data Rate Synchronous Dynamic Random Access Memory) chips are a product of this technological advancement. From SDRAM to DDR2, 3, 4, and 5, each generation has seen significant improvements in speed and capacity. Simultaneously, the interface complexity has increased, leading to the development of a dedicated controller physical layer (DDR PHY). Based on this controller, users can leverage the fast programmability of FPGAs to develop a wide range of video and communications products, accelerating time to market. In the field of video display, there are numerous application solutions. Multi-channel video input and output is one of them. This solution is mainly used in control centers such as airports and railway stations, and can also be used in advertising displays. The transmission of video information requires a large capacity for storage, so in the hardware circuit, DDR is an indispensable storage device. Since DDR is an independent particle, a controller is generally required to store data. The general controller is called MC, or "memory controller". Since the controller circuit is very complex, today's DDR controllers are basically integrated into the chip and used directly as a hard-core module. Common chips with controllers include ASIC (Application Specific Integrated Circuit), MCU (Multi Control Unit), FPGA (Field Programmable Gate Array), etc.; existing technologies, such as patent CN111581132B, are based on FPGA and use fifo (First Input First Output (FIFO) is used to cache external data, and two FIFOs are used to store read and write commands. The remaining storage data size of each channel is compared to determine the priority of each channel's storage data, implement data arbitration, and then store the sorted data in sequence into DDR3. However, during multi-channel arbitration, it takes time to calculate the number of data written to the FIFO to determine the remaining space on each channel and perform another priority sorting. This will cause some channels to wait for a while before reading or writing, occupying more chip resources. Summary of the Invention

[0003] The present invention provides a multi-channel DDR read / write arbitration device based on FPGA to solve the technical problems of high chip resource occupation and low processing efficiency in the prior art when performing DDR read / write.

[0004] In order to solve the above technical problems, an embodiment of the present invention provides a multi-channel DDR read and write arbitration device based on FPGA, comprising: an acquisition module, a fifo write module, a fifo read module, an arbitration module, an output module and an excitation source module;

[0005] The acquisition module is configured to receive first data through multiple channels and store the first data in the fifo write module; and to generate write command protocol data corresponding to the first data and send the write command protocol data to the arbitration module;

[0006] The excitation source module is used to generate read command protocol data according to a display format preset by a user, and send the read command protocol data to the arbitration module;

[0007] The arbitration module is used to store the write command protocol data or the read command protocol data in a first-come, first-served manner; and is used to write the first data in the fifo write module into the DDR particles according to the write command protocol data; and is used to read the second data from the DDR particles according to the read command protocol data, and store the second data into the fifo read module, so that the output module obtains and outputs the second data from the fifo read module.

[0008] The acquisition module of the present invention generates write command protocol data upon receiving the first data, the excitation source module generates read command protocol data after responding to the display format setting of the user, and the arbitration module stores the two command protocol data in a first-come-first-served manner and directly performs read and write operations on DDR particles based on the command protocol data, thereby avoiding spending more resources to calculate the remaining space capacity of each channel, thereby saving time waiting for data sorting, reducing resource usage and improving processing efficiency.

[0009] Furthermore, the acquisition module includes: a data receiving unit, an address counter and a write command generator;

[0010] The data receiving unit is used to adjust the first data to a first preset bit width according to the resolution information of the first data, and then transmit the first data to the FIFO writing module;

[0011] The address counter is used to count according to the clock signal, data start flag and data end flag of the first data to obtain the data width of the first data, and send the data width and the channel parameter of the first data to the write command generator;

[0012] The write command generator is used to generate the write command protocol data recording the DDR write position according to the data width and channel parameters.

[0013] After receiving the first data through the data receiving unit, the acquisition module of the present invention generates write command protocol data through the address counter and the write command generator, and continuously stores the write command protocol data into the arbitration module, so that the arbitration module performs the DDR write operation according to the write command protocol data, thereby avoiding the expenditure of additional resources to calculate the remaining space capacity of each channel, saving the time for data waiting for sorting, and improving processing efficiency.

[0014] Furthermore, the fifo write module is used to receive the first data transmitted by the acquisition module; and is used to convert the first data from a first preset bit width to a second preset bit width before transmitting the first data to the arbitration module; wherein the second preset bit width is greater than the first preset bit width.

[0015] Furthermore, the fifo reading module is used to receive the second data transmitted by the arbitration module; and is used to restore the second data from the second preset bit width to the first preset bit width before outputting the second data.

[0016] The FIFO writing module and the FIFO reading module in the present invention convert the bit widths of the first data and the second data, so that the clock when the arbitration module receives the first data is greater than the clock when the first data is input into the acquisition module. This helps the arbitration module to read and write the first data and the second data in a high-bit-width manner, improves the reading and writing efficiency, and can expand the reading and writing of data to more input and output ports.

[0017] Furthermore, the arbitration module includes: a fifo command unit and an execution unit;

[0018] The fifo command unit is configured to receive and store the write command protocol data or the read command protocol data, and transmit the write command protocol data or the read command protocol data to the execution unit in sequence after receiving the first enable signal from the execution unit;

[0019] The execution unit is configured to, when idle, send a first enable signal to the fifo command unit and receive the write command protocol data or the read command protocol data transmitted by the fifo command unit; and to read the first data of the corresponding channel in the fifo write module according to the write command protocol data, and store the first data in the DDR particle using the DDR IP module; and to read the second data from the DDR particle according to the read command protocol data, and transmit the second data to the channel corresponding to the fifo read module.

[0020] The execution unit of the present invention performs read and write operations on DDR particles in sequence according to the command protocol data, and cooperates with the storage method and transmission rules of the FIFO command unit to implement first-come-first-served execution of the command protocol data, thereby avoiding separate comparison of the read / write process and the time required for waiting for comparison, thereby improving the read and write efficiency of the arbitration module.

[0021] Furthermore, the execution unit includes: a command protocol parsing subunit, a DDR writing control subunit, a DDR reading control subunit and a data processing subunit;

[0022] The parsing command protocol subunit is used to send the first enable signal to the FIFO command unit according to the first level signal sent by the data processing subunit; and is used to receive the write command protocol data sent by the FIFO command unit, and parse the write command protocol data and transmit it to the write DDR control subunit; and is used to receive the read command protocol data sent by the FIFO command unit, and parse the read command protocol data and transmit it to the read DDR control subunit;

[0023] The write DDR control subunit is used to obtain a DDR write data address and a DDR write length according to the parsed write command protocol data; and is used to generate write address information according to the DDR write data address and the DDR write length, and send the write address information and write preparation information to the data processing subunit;

[0024] The read DDR control subunit is used to obtain a DDR read data address and a DDR read length according to the parsed write command protocol data; and is used to generate read address information according to the DDR read data address and the DDR read length, and send the read address information and read preparation information to the data processing subunit;

[0025] The data processing subunit is used to, after receiving the write preparation information, receive the first data according to the write address information, and enable the DDR IP module to write the first data into the DDR particles; and, after receiving the read preparation information, enable the DDR IP module to read the second data from the DDR particles according to the read address information, and transmit the second data to the channel corresponding to the FIFO reading module; and, when the data processing subunit is idle, send the first level signal to the command parsing protocol subunit.

[0026] Furthermore, receiving the first data according to the write address information and causing the DDR IP module to write the first data into the DDR particles is specifically as follows:

[0027] receiving the first data from the fifo write module, and determining a starting storage address in a DDR particle according to the write address information;

[0028] generating a first control instruction according to the starting storage address;

[0029] The first data is cached, and the first control instruction is sent to the DDR IP module, so that the DDR IP module stores the cached first data in the DDR particle according to the first control instruction.

[0030] Furthermore, the DDR IP module is enabled to read the second data from the DDR particle according to the read address information, and the second data is transmitted to the channel corresponding to the fifo reading module, specifically:

[0031] Determine the starting read address in the DDR particle according to the read address information;

[0032] generating a second control instruction according to the starting read address;

[0033] Sending the second control instruction to the DDR IP module, so that the DDR IP module reads and returns the second data from the DDR particle according to the second control instruction;

[0034] The second data is transmitted to the channel corresponding to the fifo reading module.

[0035] After receiving the write / read command protocol data, the command protocol parsing subunit of the present invention does not determine the remaining space and the write / read process, but directly parses the data through the write DDR control subunit and the read DDR control subunit in the order of receipt. The data processing subunit uses control instructions to enable the DDR IP module to perform read and write operations on the DDR particles in response, thereby improving the read and write efficiency.

[0036] Furthermore, the DDR IP module includes a memory controller configured to perform read and write operations on DDR particles according to control instructions of the execution unit.

[0037] Furthermore, the output module is used to send a second enable signal to the fifo reading module according to the display format sent by the excitation source module, so as to obtain the second data from the corresponding channel of the fifo reading module, and fill the second data into the display format to generate an image data stream. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural diagram of an embodiment of a multi-channel DDR read / write arbitration device based on FPGA provided by the present invention;

[0039] Figure 2 A schematic structural diagram of an embodiment of the acquisition module provided by the present invention;

[0040] Figure 3 A schematic structural diagram of an embodiment of the arbitration module provided by the present invention;

[0041] Figure 4 This is a processing flow chart of the FPGA-based multi-channel DDR read-write arbitration device provided by the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] Example 1

[0044] Please refer to Figure 1 , is a structural diagram of an embodiment of a multi-channel DDR read / write arbitration device based on FPGA provided by the present invention, comprising: an acquisition module, a FIFO writing module, a FIFO reading module, an arbitration module, an output module and an excitation source module;

[0045] The acquisition module is configured to receive first data through multiple channels and store the first data in the fifo write module; and to generate write command protocol data corresponding to the first data and send the write command protocol data to the arbitration module;

[0046] The excitation source module is used to generate read command protocol data according to a display format preset by a user, and send the read command protocol data to the arbitration module;

[0047] The arbitration module is used to store the write command protocol data or the read command protocol data in a first-come, first-served manner; and is used to write the first data in the fifo write module into the DDR particles according to the write command protocol data; and is used to read the second data from the DDR particles according to the read command protocol data, and store the second data into the fifo read module, so that the output module obtains and outputs the second data from the fifo read module.

[0048] In this embodiment, the acquisition module includes multiple channels, such as Figure 1 Each channel of the acquisition module corresponds to a channel in the fifo write module, such as fifo_i0 to fifo_i n. Figure 2 , is a structural diagram of an embodiment of the acquisition module provided by the present invention, wherein the acquisition module includes: a data receiving unit, an address counter and a write command generator;

[0049] The data receiving unit is used to adjust the first data to a first preset bit width according to the resolution information of the first data, and then transmit the first data to the FIFO writing module;

[0050] The address counter is used to count according to the clock signal, data start flag and data end flag of the first data to obtain the data width of the first data, and send the data width and the channel parameter of the first data to the write command generator;

[0051] The write command generator is used to generate the write command protocol data recording the DDR write position according to the data width and channel parameters.

[0052] After receiving the first data through the data receiving unit, the acquisition module of the present invention generates write command protocol data through the address counter and the write command generator, and continuously stores the write command protocol data into the arbitration module, so that the arbitration module performs the DDR write operation according to the write command protocol data, thereby avoiding the expenditure of additional resources to calculate the remaining space capacity of each channel, saving the time for data waiting for sorting, and improving processing efficiency.

[0053] In this embodiment, the resolution information includes the effective height and effective width of the input first data, and the first preset bit width is a x16-bit bit width with a fixed format of RGB.

[0054] In this embodiment, counting is performed based on the clock signal, data start flag and data end flag of the first data to obtain the data width of the first data, and the data width and the channel parameters of the first data are sent to the write command generator, specifically: according to the clock signal of the first data, the first data and the internal synchronization signal of the first data are sampled to obtain the data start flag; according to the data start flag, counting is performed, and when the count reaches the width at the end of the image resolution, the count is set to 0 to obtain the data width; the data width and the channel parameters are sent to the write command generator.

[0055] In this embodiment, both the write command protocol data and the read command protocol data include: a read / write flag, a channel number, a data width, and a read / write DDR location. A low level or 0 for the read / write flag indicates a write; a high level or 1 for the read / write flag indicates a read. The channel number indicates the channel number of the acquisition module or output module, starting at 0 and increasing in increments. The data width indicates the resolution width of the image corresponding to the first data. The read / write DDR location defaults to 0; the first data is actually allocated to the address space of the DDR particle based on the channel number.

[0056] In this embodiment, the user can set the image format to 1080P at the IO port of the excitation source module. If the IO port input is low level 0, it indicates that all output channels are 1080P format image data. The excitation source module is also used to generate a standard image format, such as a 1080P image frame, after receiving the user instruction. At the beginning of each line of image data, such as the second data, when the clock arrives, it sends the "read command protocol data" of each output channel to the arbitration module for reading the data stored in the DDR of each channel. At the same time, it sends the image information to be displayed to each output module, so that the output module is ready to receive the second data.

[0057] Furthermore, the fifo write module is used to receive the first data transmitted by the acquisition module; and is used to convert the first data from a first preset bit width to a second preset bit width before transmitting the first data to the arbitration module; wherein the second preset bit width is greater than the first preset bit width.

[0058] Furthermore, the fifo reading module is used to receive the second data transmitted by the arbitration module; and is used to restore the second data from the second preset bit width to the first preset bit width before outputting the second data.

[0059] In this embodiment, the second preset bit width is a x128-bit bit width with a fixed format of RGB. Through asynchronous clock processing, the clock input to the FIFO write module is smaller than the output clock, thereby increasing the number of channels.

[0060] In this embodiment, after receiving the read data enable signal from the output module, the FIFO reading module outputs the earliest data in the FIFO reading module and restores the input second data from 128 bits to 16 bits.

[0061] The FIFO writing module and the FIFO reading module in the present invention convert the bit widths of the first data and the second data, so that the clock when the arbitration module receives the first data is greater than the clock when the first data is input into the acquisition module. This helps the arbitration module to read and write the first data and the second data in a high-bit-width manner, improves the reading and writing efficiency, and can expand the reading and writing of data to more input and output ports.

[0062] Furthermore, the output module is used to send a second enable signal to the fifo reading module according to the display format sent by the excitation source module, so as to obtain the second data from the corresponding channel of the fifo reading module, and fill the second data into the display format to generate an image data stream.

[0063] Please refer to Figure 4 , which is a processing flow chart of the FPGA-based multi-channel DDR read-write arbitration device provided by the present invention, wherein the external data is the first data in the present invention, and the first data stored in the FIFO write module is written to the DDR particle through transmission by the data acquisition module; after receiving the read command protocol data, the arbitration module reads the second data from the DDR particle and writes the second data to the FIFO read module, and finally outputs the second data as a video data stream by connecting to the display device.

[0064] Please refer to Figure 3 , is a structural diagram of an embodiment of the arbitration module provided by the present invention, wherein the arbitration module includes: a fifo command unit and an execution unit;

[0065] The fifo command unit is configured to receive and store the write command protocol data or the read command protocol data, and transmit the write command protocol data or the read command protocol data to the execution unit in sequence after receiving the first enable signal from the execution unit;

[0066] The execution unit is configured to, when idle, send a first enable signal to the fifo command unit and receive the write command protocol data or the read command protocol data transmitted by the fifo command unit; and to read the first data of the corresponding channel in the fifo write module according to the write command protocol data, and store the first data in the DDR particle using the DDR IP module; and to read the second data from the DDR particle according to the read command protocol data, and transmit the second data to the channel corresponding to the fifo read module.

[0067] In this embodiment, the arbitration module first determines whether the execution unit is idle. The idle flag can be fl ag_end. When the signal is high level 1, it indicates that the execution module is idle. If there is data in the fifo command unit, the execution unit will generate a first enable signal to read the "fifo command unit". The fifo command unit will send out the data stored in the module earliest, and only send one group of data at a time.

[0068] In this embodiment, the FIFO command unit stores command protocol data from the acquisition module and the excitation source module. When data arrives simultaneously, the write command (which can also be defined as read command priority) is first stored according to the write command protocol data priority principle. When the read enable signal returned by the "execution unit" is high, the internally stored data is output. The FIFO command unit is set to a depth of 64 and a bit width of 32 to meet the storage of write command data. The user can also manually change it according to actual needs.

[0069] In this embodiment, after acquiring the write or read command protocol data, the execution unit parses the command, including the read / write channel number. It then determines whether the command is a DDR read or write. If the command is a write, it issues a third enable signal to read the FIFO write module for a specific channel. The acquired data is processed and sent to the DDR IP for further processing before being stored in the DDR chip. If the command is a read, the execution module reads the data for the corresponding channel from the DDR chip and sends it to the corresponding FIFO read module, implementing read and write arbitration for multiple channels of data.

[0070] The execution unit of the present invention performs read and write operations on DDR particles in sequence according to the command protocol data, and cooperates with the storage method and transmission rules of the FIFO command unit to implement first-come-first-served execution of the command protocol data, thereby avoiding separate comparison of the read / write process and the time required for waiting for comparison, thereby improving the read and write efficiency of the arbitration module.

[0071] Furthermore, the execution unit includes: a command protocol parsing subunit, a DDR writing control subunit, a DDR reading control subunit and a data processing subunit;

[0072] The parsing command protocol subunit is used to send the first enable signal to the FIFO command unit according to the first level signal sent by the data processing subunit; and is used to receive the write command protocol data sent by the FIFO command unit, and parse the write command protocol data and transmit it to the write DDR control subunit; and is used to receive the read command protocol data sent by the FIFO command unit, and parse the read command protocol data and transmit it to the read DDR control subunit;

[0073] The write DDR control subunit is used to obtain a DDR write data address and a DDR write length according to the parsed write command protocol data; and is used to generate write address information according to the DDR write data address and the DDR write length, and send the write address information and write preparation information to the data processing subunit;

[0074] The read DDR control subunit is used to obtain a DDR read data address and a DDR read length according to the parsed write command protocol data; and is used to generate read address information according to the DDR read data address and the DDR read length, and send the read address information and read preparation information to the data processing subunit;

[0075] The data processing subunit is used to, after receiving the write preparation information, receive the first data according to the write address information, and enable the DDR IP module to write the first data into the DDR particles; and, after receiving the read preparation information, enable the DDR IP module to read the second data from the DDR particles according to the read address information, and transmit the second data to the channel corresponding to the FIFO reading module; and, when the data processing subunit is idle, send the first level signal to the command parsing protocol subunit.

[0076] In this embodiment, the first level signal is flag_end. When the flag_end signal is high level 1, the command protocol parsing subunit generates an enable pulse signal for the read fifo command unit. When data starts to be read or written, flag_end needs to be pulled low and then wait for data to be returned.

[0077] In this embodiment, the write DDR control subunit further obtains the channel number from the parsed data, i.e., the write command protocol data, and sends a third enable signal to the corresponding channel in the FIFO write module. The clock cycle length of the third enable signal is a calculated value. For example, when the first data is 1080-format video data, the length is 1920*16 / 128, which equals 240 cycles. Here, 1920 is the resolution width, 16 is the width of the input fifo_i, and 128 is the bit width that the arbitration module can read at one time. The write data processing subunit then sends write preparation information w_ready and write address information w_addr to the write data processing subunit.

[0078] Furthermore, receiving the first data according to the write address information and causing the DDR IP module to write the first data into the DDR particles is specifically as follows:

[0079] receiving the first data from the fifo write module, and determining a starting storage address in a DDR particle according to the write address information;

[0080] generating a first control instruction according to the starting storage address;

[0081] The first data is cached, and the first control instruction is sent to the DDR IP module, so that the DDR IP module stores the cached first data in the DDR particle according to the first control instruction.

[0082] Furthermore, the DDR IP module is enabled to read the second data from the DDR particle according to the read address information, and the second data is transmitted to the channel corresponding to the fifo reading module, specifically:

[0083] Determine the starting read address in the DDR particle according to the read address information;

[0084] generating a second control instruction according to the starting read address;

[0085] Sending the second control instruction to the DDR IP module, so that the DDR IP module reads and returns the second data from the DDR particle according to the second control instruction;

[0086] The second data is transmitted to the channel corresponding to the fifo reading module.

[0087] In this embodiment, the addr accumulation module in the data processing subunit uses the address in the write address information as the base address, i.e., the starting address stored in the DDR. The addr accumulation module then increments the address by 8 with each address cycle and resets the address to 0 after the first data is stored. The enable control module in the data processing subunit generates an enable signal for reading / writing the DDR. The cmd generation module in the data processing subunit generates a first control instruction or a second control instruction for controlling the DDR IP module. The data cache module in the data processing subunit caches the first data before writing it to the DDR core. After completing a DDR read or write, the data processing subunit pulls a first-level signal high to indicate that the DDR is idle. When a read command arrives, the data processing subunit obtains parameter information from the read DDR control module, including the read ready information r_ready and the read address information r_addr. The process for reading data from the DDR is the opposite of the write process. When the data read is complete, the first-level signal flag_end is pulled high to indicate that the DDR is idle.

[0088] After receiving the write / read command protocol data, the command protocol parsing subunit of the present invention does not determine the remaining space and the write / read process, but directly parses the data through the write DDR control subunit and the read DDR control subunit in the order of receipt. The data processing subunit uses control instructions to enable the DDR IP module to perform read and write operations on the DDR particles in response, thereby improving the read and write efficiency.

[0089] Furthermore, the DDR IP module includes a memory controller (MC) configured to perform read and write operations on the DDR particles according to control instructions of the execution unit.

[0090] The acquisition module of the present invention generates write command protocol data upon receiving the first data, the excitation source module generates read command protocol data after responding to the display format setting of the user, and the arbitration module stores the two command protocol data in a first-come-first-served manner and directly performs read and write operations on DDR particles based on the command protocol data, thereby avoiding spending more resources to calculate the remaining space capacity of each channel, thereby saving time waiting for data sorting, reducing resource usage and improving processing efficiency.

[0091] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A multi-channel DDR read / write arbitration device based on FPGA, characterized in that: include: Acquisition module, fifo writing module, fifo reading module, arbitration module, output module and excitation source module; The acquisition module is configured to receive first data through multiple channels and store the first data in the fifo write module; and to generate write command protocol data corresponding to the first data and send the write command protocol data to the arbitration module; The excitation source module is used to generate read command protocol data according to a display format preset by a user, and send the read command protocol data to the arbitration module; The arbitration module is configured to store the write command protocol data or the read command protocol data in a first-come, first-served manner; and to write the first data in the fifo write module into the DDR particle according to the write command protocol data; and to read second data from the DDR particle according to the read command protocol data, and store the second data into the fifo read module, so that the output module obtains and outputs the second data from the fifo read module; The arbitration module includes: a fifo command unit and an execution unit; The fifo command unit is configured to receive and store the write command protocol data or the read command protocol data, and transmit the write command protocol data or the read command protocol data to the execution unit in sequence after receiving the first enable signal from the execution unit; The execution unit is configured to, when idle, send a first enable signal to the fifo command unit and receive the write command protocol data or the read command protocol data transmitted by the fifo command unit; and to read the first data of the corresponding channel in the fifo write module according to the write command protocol data, and store the first data in the DDR particle using the DDR IP module; and to read the second data from the DDR particle according to the read command protocol data, and transmit the second data to the channel corresponding to the fifo read module.

2. The multi-channel DDR read / write arbitration device based on FPGA according to claim 1, characterized in that: The acquisition module includes: a data receiving unit, an address counter and a write command generator; The data receiving unit is used to adjust the first data to a first preset bit width according to the resolution information of the first data, and then transmit the first data to the fifo writing module; The address counter is used to count according to the clock signal, data start flag and data end flag of the first data to obtain the data width of the first data, and send the data width and the channel parameter of the first data to the write command generator; The write command generator is used to generate the write command protocol data recording the DDR write position according to the data width and channel parameters.

3. The FPGA-based multi-channel DDR read / write arbitration device according to claim 2, wherein: The fifo writing module is used to receive the first data transmitted by the acquisition module; and is configured to convert the first data from a first preset bit width to a second preset bit width before transmitting the first data to the arbitration module; wherein the second preset bit width is greater than the first preset bit width.

4. The FPGA-based multi-channel DDR read / write arbitration device according to claim 3, wherein: The fifo reading module is used to receive the second data transmitted by the arbitration module; and is used to restore the second data from the second preset bit width to the first preset bit width before outputting the second data.

5. The FPGA-based multi-channel DDR read / write arbitration device according to claim 1, wherein: The execution unit includes: a command protocol parsing subunit, a DDR writing control subunit, a DDR reading control subunit and a data processing subunit; The parsing command protocol subunit is used to send the first enable signal to the fifo command unit according to the first level signal sent by the data processing subunit; and is used to receive the write command protocol data sent by the fifo command unit, and parse the write command protocol data and transmit it to the write DDR control subunit; and is used to receive the read command protocol data sent by the fifo command unit, and parse the read command protocol data and transmit it to the read DDR control subunit; The write DDR control subunit is used to obtain a DDR write data address and a DDR write length according to the parsed write command protocol data; and is used to generate write address information according to the DDR write data address and the DDR write length, and send the write address information and write preparation information to the data processing subunit; The read DDR control subunit is used to obtain a DDR read data address and a DDR read length according to the parsed write command protocol data; and is used to generate read address information according to the DDR read data address and the DDR read length, and send the read address information and read preparation information to the data processing subunit; The data processing subunit is used to, after receiving the write preparation information, receive the first data according to the write address information, and enable the DDR IP module to write the first data into the DDR particles; and, after receiving the read preparation information, enable the DDR IP module to read the second data from the DDR particles according to the read address information, and transmit the second data to the channel corresponding to the FIFO reading module; and, when the data processing subunit is idle, send the first level signal to the command parsing protocol subunit.

6. The FPGA-based multi-channel DDR read / write arbitration device according to claim 5, wherein: The receiving the first data according to the write address information and causing the DDR IP module to write the first data into a DDR particle is specifically: receiving the first data from the fifo write module, and determining a starting storage address in a DDR particle according to the write address information; generating a first control instruction according to the starting storage address; The first data is cached, and the first control instruction is sent to the DDR IP module, so that the DDR IP module stores the cached first data in the DDR particle according to the first control instruction.

7. The FPGA-based multi-channel DDR read / write arbitration device according to claim 5, wherein: The step of enabling the DDR IP module to read the second data from the DDR particle according to the read address information and transmitting the second data to a channel corresponding to the FIFO reading module is specifically as follows: Determine the starting read address in the DDR particle according to the read address information; generating a second control instruction according to the starting read address; Sending the second control instruction to the DDR IP module, so that the DDR IP module reads and returns the second data from the DDR particle according to the second control instruction; The second data is transmitted to the channel corresponding to the fifo reading module.

8. The FPGA-based multi-channel DDR read / write arbitration device according to claim 1, 5, 6 or 7, wherein: The DDR IP module includes a memory controller configured to perform read and write operations on DDR particles according to control instructions of the execution unit.

9. The FPGA-based multi-channel DDR read / write arbitration device according to any one of claims 1 to 7, wherein: The output module is used to send a second enable signal to the fifo reading module according to the display format sent by the excitation source module, so as to obtain the second data from the corresponding channel of the fifo reading module, and fill the second data into the display format to generate an image data stream.

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