An optoelectronic chip layout wiring method, device, equipment and storage medium

Abstract

The application discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, relates to the technical field of optoelectronic chip layout automatic design wiring, and comprises the following steps: mapping an optoelectronic chip layout into a grid, mapping PCell ports into point coordinates, and mapping waveguides needing wiring into line segments; taking a cross-shaped grid in the grid as a basic unit, defining the center coordinates of the cross-shaped grid, path intersection conditions and line segment combination modes passing through the center coordinates of the cross-shaped grid as variables; setting restriction conditions of paths between PCell ports, points on the paths and line segments; utilizing the variables to represent the length of the paths, calculating corresponding variable values based on the restriction conditions and according to equal-length paths to be implemented, so as to determine path planning, map the path planning into waveguide wiring, and add a Crossing waveguide unit at a corresponding position. The application can guarantee that the lengths of waveguides are equal, the number of curved waveguides is equal, the number of Crossing waveguide units is equal, the occupied area of the waveguides is minimum, and the total length of the waveguides is shortest.

Description

Technical Field

[0001] This invention relates to the field of automated design and wiring technology for optoelectronic chips, specifically to a method, apparatus, device, and storage medium for layout wiring of optoelectronic chips. Background Technology

[0002] Existing automated design tools for optoelectronic chip layouts automatically generate waveguide routes according to the Manhattan algorithm for port links between parameterized cells (PCells) or between system links, thus planning the shortest horizontal and vertical paths.

[0003] However, the waveguide routing design for coherent optical chip layouts needs to consider the issues of multiple waveguides having equal lengths and the same number of crossover units—equal waveguide lengths, equal number of bent waveguides (usually assuming consistent bent waveguide radii), and consistent number of crossover units along the path. Simultaneously, it is desirable to have smaller waveguide lengths to reduce optical power loss (although the loss per unit length is very small in silicon photonics) and phase delay, a smaller number of crossovers with consistent crossovers across all waveguides to reduce the impact on optical modes, and to minimize the overall module area to reduce manufacturing costs and increase integration.

[0004] The tools mentioned above, while addressing the issue of equal-length waveguides, do not achieve automated equal-length routing. They still rely on manually calculating the length difference and the number of bent waveguides, and then adding control points along the waveguide path to change its orientation, thereby altering the waveguide length, the number of bent waveguides, and the number of crossing PCELLs. This semi-manual, semi-automatic approach to equal-length waveguide routing is labor-intensive, time-consuming, and error-prone. Furthermore, the final equal-length waveguide may not represent the optimal solution in terms of total waveguide length and overall module area. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the first aspect of this invention provides a method for routing optoelectronic chip layouts, which ensures that waveguide lengths are equal, the number of bent waveguides is equal, the number of Crossing waveguide units on the waveguides is equal, and the waveguide area occupied and the total waveguide length is minimized during routing.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for layout wiring of an optoelectronic chip, the method comprising the following steps:

[0008] The optoelectronic chip layout is mapped into a grid, and the parameterized unit PCell port is mapped into point coordinates. The waveguide that needs to be wired is mapped into line segments.

[0009] Using the grid as the basic unit, the center coordinates of the grid, the path intersection, and the combination of line segments passing through the center coordinates of the grid are defined as variables;

[0010] Set the constraints for the paths between PCell ports, the points on the paths, and the line segments. The constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments.

[0011] The path length is represented by the variable, and based on the constraints, the corresponding variable values ​​are calculated according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide traces, and Crossing waveguide units are added at the corresponding positions.

[0012] In some embodiments, the step of using a grid of squares as the basic unit, defining the center coordinates of the squares, path intersections, and line segment combinations passing through the center coordinates of the squares as variables, includes:

[0013] Set the center coordinates of the grid to (i, j);

[0014] And set the value to either 0 or 1:

[0015] Whether the horizontal segment in row i and column j is on path-k: If on path-k, then otherwise

[0016] The variable indicating whether the vertical segment in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0017] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0018] The variable determining whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0;

[0019] Whether the point in the i-th row and j-th column is an additional point for intersection is a variable: E ij If the intersection point is established separately, then E ij =1, otherwise E ij =0;

[0020] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0021] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0022] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0023] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0024] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0025] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0026] Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then otherwise

[0027] Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then otherwise

[0028] In some embodiments, the constraints on the paths between PCell ports, the points on the paths, and the line segments are defined. These constraints include path intersection conditions, path input points, output points, and the existence of line segments, including:

[0029] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies

[0030] Limit input point I k Output point O k All are only in path-k;

[0031] Through the formula: Each segment can only be on one path at most;

[0032] Through the formula: Each point can be on at most two paths;

[0033] Through the formula: Whether the constraint point is at the intersection of two paths;

[0034] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0035] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0036] Through the formula:

[0037]

[0038] The two paths are restricted to intersecting only perpendicularly at their intersection point.

[0039] Through the formula:

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046] Restrict the points in the i-th row and j-th column

[0047] Through the formula:

[0048]

[0049] When additional intersections are established at a certain point, that point must be on only one path, and the two segments connected to that point on the same path must be either horizontal or vertical.

[0050] In some embodiments, according to the formula:

[0051]

[0052] Calculate the length L of path-k k Where a is the unit length of the grid, R is the corner radius, and a equals R;

[0053] According to the formula: Calculate the total number of Crossing waveguide elements on path-k;

[0054] When path-k1 and path-k2 need to be equal, we have

[0055] In some embodiments, it also includes:

[0056] Through the formula: The optimization aims to minimize the total length of all paths and the total number of intersections, where α is the weighting coefficient.

[0057] The second aspect of the present invention provides a layout wiring device for optoelectronic chips, which can ensure that the waveguide length is equal, the number of bent waveguides is equal, the number of waveguide crossing waveguide units is equal, and at the same time ensures that the waveguide occupancy area is minimized and the total waveguide length is minimized.

[0058] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0059] A layout wiring device for an optoelectronic chip, comprising:

[0060] The mapping module is used to map the optoelectronic chip layout into a grid, map the parameterized unit PCell port into point coordinates, and map the waveguide that needs to be wired into line segments.

[0061] The configuration module is used to define the center coordinates of the grid, the path intersection, and the combination of line segments passing through the center coordinates of the grid as variables, using the grid as the basic unit.

[0062] The calculation module is used to set the constraints on the paths between PCell ports, the points on the paths, and the line segments. The constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments. The calculation module is also used to use the variables to represent the length of the path, and based on the constraints, calculate the corresponding variable values ​​according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide routing, and cross-waveguide units are added at the corresponding positions.

[0063] In some embodiments, the configuration module uses a grid of squares as the basic unit, defining the center coordinates of the squares, path intersections, and line segment combinations passing through the center coordinates of the squares as variables, including:

[0064] Set the center coordinates of the grid to (i, j);

[0065] And set the value to either 0 or 1:

[0066] Whether the horizontal segment in row i and column j is on path-k: If on path-k, then otherwise

[0067] The variable indicating whether the vertical segment in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0068] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0069] The variable determining whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0;

[0070] Whether the point in the i-th row and j-th column is an additional point for intersection is a variable: E ij If the intersection point is established separately, then E ij =1, otherwise E ij =0;

[0071] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0072] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0073] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0074] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0075] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0076] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0077] Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then otherwise

[0078] Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then otherwise

[0079] In some embodiments, the computing module sets constraints on paths between PCell ports, points on those paths, and line segments. These constraints include path intersection conditions, path input points, output points, and the existence of line segments, including:

[0080] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies

[0081] Limit input point I k Output point O k All are only in path-k;

[0082] Through the formula: Each segment can only be on one path at most;

[0083] Through the formula: Each point can be on at most two paths;

[0084] Through the formula: Whether the constraint point is at the intersection of two paths;

[0085] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0086] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0087] Through the formula:

[0088]

[0089] The two paths are restricted to intersecting only perpendicularly at their intersection point.

[0090] Through the formula:

[0091]

[0092]

[0093]

[0094]

[0095]

[0096]

[0097] Restrict the points in the i-th row and j-th column

[0098] Through the formula:

[0099]

[0100] When additional intersections are established at a certain point, that point must be on only one path, and the two segments connected to that point on the same path must be either horizontal or vertical.

[0101] A third aspect of the present invention provides a device that can ensure that the waveguide length is equal, the number of bent waveguides is equal, the number of waveguide crossing waveguide units is equal, and at the same time ensures that the waveguide occupancy area is minimized and the total waveguide length is minimized.

[0102] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0103] An apparatus comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the aforementioned optoelectronic chip layout wiring method.

[0104] The fourth aspect of the present invention provides a computer-readable storage medium that can ensure that the waveguide length is equal, the number of bent waveguides is equal, the number of waveguide crossing waveguide units is equal, and at the same time ensures that the waveguide occupied area is minimized and the total waveguide length is minimized.

[0105] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0106] A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described optoelectronic chip layout wiring method.

[0107] Compared with the prior art, the advantages of the present invention are as follows:

[0108] The optoelectronic chip layout routing method of this invention maps the optoelectronic chip layout into a grid and the parameterized PCell ports into point coordinates. Using the grid's grid lines as basic units, the center coordinates of the grid lines, path intersections, and line segment combinations passing through the grid center coordinates are defined as variables. Constraints are set on the paths between PCell ports, and on the points and line segments along those paths. These constraints include path intersection conditions, path input points, output points, and the existence of line segments. The variables represent the path length, and based on the constraints and the desired equal-length paths, the corresponding variable values ​​are calculated to determine the path planning. This ensures that waveguide lengths, the number of bent waveguides, and the number of crossing waveguide units are equal during routing, while minimizing the waveguide area and the total waveguide length. Attached Figure Description

[0109] Figure 1This is a flowchart of the optoelectronic chip layout wiring method in an embodiment of the present invention;

[0110] Figure 2 This is a schematic diagram of variables in an embodiment of the present invention;

[0111] Figure 3 This is a wiring diagram in an embodiment of the present invention. Detailed Implementation

[0112] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0113] See Figure 1 As shown, this embodiment of the invention provides a method for routing a layout of an optoelectronic chip, which includes the following steps:

[0114] S1. Map the optoelectronic chip layout to a grid and map the parameterized cell PCell port to point coordinates.

[0115] It is worth noting that, addressing the shortcomings of current automated design tools for optoelectronic chip layouts in waveguide length equalization routing, this invention implements an automated routing mathematical model. This model enables the automated and balanced routing of multiple waveguides generated through pairwise interconnections between multiple ports—ensuring equal waveguide lengths, equal numbers of bent waveguides (typically assuming consistent bent waveguide radii), and equal numbers of crossing waveguide units, while minimizing waveguide area and total waveguide length. This significantly reduces layout drawing time and improves layout accuracy.

[0116] This invention primarily presents a mathematical model for automated routing. The model maps the optoelectronic chip layout to a grid and the PCell ports to point coordinates. First, an N x M (N×M) grid is established, requiring K sets of input points I. k and output point O k K waveguide paths are generated between (1≤k≤K), and the grid has segments and vertices.

[0117] S2. Using the grid's grid lines as the basic unit, define the grid center coordinates, path intersections, and line segment combinations passing through the grid center coordinates as variables.

[0118] In this embodiment of the invention, the following variables are defined. All variables are non-negative integers and can only take the value (0, 1). Their specific meanings are as follows: Figure 2 As shown, the coordinates of the center point of all the grids are (i, j).

[0119] Specifically, the following were defined:

[0120] The horizontal segment in the i-th row and j-th column (i.e. and Variables on path-k between two points: If on path-k, then otherwise

[0121] The vertical segment in the i-th row and j-th column (i.e.) and Variables on path-k between two points: If on path-k, then otherwise

[0122] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0123] The variable determining whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0;

[0124] Whether the point in the i-th row and j-th column is an additional point for intersection is a variable: E ij If the intersection point is established separately, then E ij =1, otherwise E ij =0;

[0125] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0126] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0127] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0128] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0129] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0130] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0131] Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then otherwise

[0132] Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then otherwise

[0133] S3. Set the constraints for the paths between PCell ports, the points on the paths, and the line segments. The constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments.

[0134] Meanwhile, the embodiments of the present invention also set some limiting conditions, specifically:

[0135] (1) For each input point I on path-k k (i,j):

[0136]

[0137] (2) For each output point O on path-k k (i,j):

[0138]

[0139] (3) Input point I k Output point O k They only appear in path-k and will not appear in other paths.

[0140] (4) Each segment can only be on one path at most:

[0141]

[0142] (5) Each vertex can only be on a maximum of two paths:

[0143]

[0144] (6) Is the vertex the intersection of two paths?

[0145]

[0146] (7) If a vertex is on path-k, then exactly two of its four segments (up, down, left, and right) are also on path-k:

[0147]

[0148] Specifically, for input and output points, only one of the four segments (up, down, left, right) can be on the path.

[0149] (8) If a segment is on path-k, then both of its endpoints are also on path k:

[0150]

[0151] (9) If a vertex is the intersection of two paths, then the two paths can only intersect perpendicularly through that point, and neither path can appear at that vertex as a turn:

[0152]

[0153]

[0154] (10) The vertex in the i-th row and j-th column The corresponding position connected to this vertex and Direct decision, Equivalent to have:

[0155]

[0156]

[0157]

[0158]

[0159]

[0160]

[0161] (11) For a given vertex, an additional intersection needs to be established, provided that the point is on only one path and the two segments connected to the point on the path are either horizontal or vertical; otherwise, an intersection cannot be established.

[0162]

[0163]

[0164] S4. Use the variables to represent the length of the path, and based on the constraints, calculate the corresponding variable values ​​according to the equal-length path to be achieved, so as to determine the path planning.

[0165] It is worth noting that the equal-length paths to be achieved can be achieved by having a reference path and then setting up several paths based on the reference path; or by ensuring that at least two paths have equal waveguide lengths and equal numbers of bent waveguides without having a reference path, through wiring.

[0166] In this embodiment of the invention, according to the formula:

[0167]

[0168] Calculate the length L of path-k k Where a is the unit length of the grid, R is the corner radius, and a equals R;

[0169] According to the formula: Calculate the total number of Crossing waveguide elements on path-k;

[0170] When path-k1 and path-k2 need to be equal, we have

[0171] When a and R are both 2, that is, equation (1):

[0172]

[0173] To achieve: L k1 =Lk2 =……=L kK That is, equation (2):

[0174] It can be known that:

[0175]

[0176] Meanwhile, in order to minimize the area occupied by waveguide wiring, the total length of the paths should be optimized to the shortest possible value, i.e., equation (3):

[0177]

[0178] By solving the problem that satisfies the above constraints and optimizes the waveguide length, one or more sets of... and Minimize the total length of the paths.

[0179] By solving the above model, the optimal routing method can be obtained. See also... Figure 3 As shown, three paths are created, as follows: Figure 3 (ac) is shown as a line segment. Figure 3 (d) The black dot on the left is the intersection of path 1 and path 2. The black dot on the right is a Crossing waveguide unit point created because path 3 needs to be balanced with the previous two paths. Final wiring... Figure 3 As shown in (d).

[0180] It is understood that, compared to manually drawing the layout, manually calculating the number of bends in the waveguide, and constantly modifying and testing the layout, the method in this embodiment of the invention can quickly and efficiently generate multiple paths that meet the requirements of equal length, equal number of bends, and equal number of intersections. Moreover, it can be generated automatically in one go without having to modify the layout multiple times, which greatly saves manpower and time.

[0181] Furthermore, compared to the automatic routing algorithms in existing optoelectronic chip layout automation design tools on the market, which can only generate the shortest path according to the Manhattan algorithm after defining the connection relationship between input and output ports, potentially resulting in waveguide crossings and failing to automatically generate paths of equal length, this patent can automatically generate multiple paths that meet the requirements of equal length, equal number of bends, and equal number of crossing waveguide units at once, without the need to manually add control points to the path to change the waveguide routing direction, and without the need to modify the layout multiple times.

[0182] Furthermore, compared to manual drawing and other automated design tools for optoelectronic chip layouts, this patent can automatically optimize waveguide path lengths to minimize the area occupied by the layout, avoid wasting layout area, and improve the effective utilization rate.

[0183] In summary, the optoelectronic chip layout routing method of this invention maps the optoelectronic chip layout into a grid and the parameterized PCell ports into point coordinates. Using the grid's grid lines as basic units, the grid center coordinates, path intersections, and line segment combinations passing through the grid center coordinates are defined as variables. Constraints are set on the paths between PCell ports, and on the points and line segments along those paths. These constraints include path intersection conditions, path input points, output points, and the existence of line segments. The variables represent the path length, and based on the constraints and the desired equal-length paths, the corresponding variable values ​​are calculated to determine the path planning. This ensures that waveguide lengths, the number of bent waveguides, and the number of crossing waveguide units are equal during routing, while minimizing the waveguide area and the total waveguide length.

[0184] Meanwhile, embodiments of the present invention also provide an optoelectronic chip layout wiring device, which includes a mapping module, a configuration module and a calculation module.

[0185] The mapping module maps the optoelectronic chip layout into a grid and the parameterized PCell ports into point coordinates. The configuration module uses the grid's grid center coordinates, path intersections, and line segment combinations passing through the grid center coordinates as variables. The calculation module sets the constraints on the paths between PCell ports, the points on the paths, and the line segments on the paths. These constraints include path intersection conditions, path input points, output points, and the existence of line segments. The calculation module also uses the variables to represent the path length and, based on the constraints, calculates the corresponding variable values ​​according to the desired equal-length paths to determine the path planning.

[0186] In some embodiments, the configuration module uses a grid of squares as the basic unit, defining the center coordinates of the squares, path intersections, and line segment combinations passing through the center coordinates of the squares as variables, including:

[0187] Set the center coordinates of the grid to (i, j);

[0188] And set the value to either 0 or 1:

[0189] Whether the horizontal segment in row i and column j is on path-k: If on path-k, then otherwise

[0190] The variable indicating whether the vertical segment in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0191] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0192] The variable determining whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0;

[0193] Whether the point in the i-th row and j-th column is an additional point for intersection is a variable: E ij If the intersection point is established separately, then E ij =1, otherwise E ij =0;

[0194] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0195] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0196] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0197] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0198] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0199] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0200] Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then otherwise

[0201] Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then otherwise

[0202] In some embodiments, the computing module sets constraints on paths between PCell ports, points on those paths, and line segments. These constraints include path intersection conditions, path input points, output points, and the existence of line segments, including:

[0203] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies

[0204] Limit input point I k Output point O k All are only in path-k;

[0205] Through the formula: Each segment can only be on one path at most;

[0206] Through the formula: Each point can be on at most two paths;

[0207] Through the formula: Whether the constraint point is at the intersection of two paths;

[0208] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0209] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0210] Through the formula:

[0211]

[0212] The two paths are restricted to intersecting only perpendicularly at their intersection point.

[0213] Through the formula:

[0214]

[0215]

[0216]

[0217]

[0218]

[0219]

[0220] Restrict the points in the i-th row and j-th column

[0221] Through the formula:

[0222]

[0223] When additional intersections are established at a certain point, that point must be on only one path, and the two segments connected to that point on the same path must be either horizontal or vertical.

[0224] In some embodiments, according to the formula:

[0225]

[0226] Calculate the length L of path-k k Where a is the unit length of the grid, R is the corner radius, and a equals R;

[0227] According to the formula: Calculate the total number of Crossing waveguide elements on path-k;

[0228] When path-k1 and path-k2 need to be equal, we have

[0229] In some embodiments, the calculation module also uses the formula: The optimization aims to minimize the total length of all paths and the total number of intersections, where α is the weighting coefficient.

[0230] This invention also provides an apparatus comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the above-described optoelectronic chip layout wiring method.

[0231] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0232] This invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described optoelectronic chip layout wiring method.

[0233] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0234] As is known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0235] For example, the computer-readable storage medium may be an internal storage unit of the electronic device described in the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., provided on the electronic device.

[0236] The above are merely specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.

Claims

1. A method for routing layouts of an optoelectronic chip, characterized in that, The method includes the following steps: The optoelectronic chip layout is mapped into a grid, and the parameterized unit PCell port is mapped into point coordinates. The waveguide that needs to be wired is mapped into line segments. Using the grid as the basic unit, the center coordinates of the grid, the path intersection, and the combination of line segments passing through the center coordinates of the grid are defined as variables; Set the constraints for the paths between PCell ports, the points on the paths, and the line segments. The constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments. The variable is used to represent the length of the path, and based on the constraints, the corresponding variable values ​​are calculated according to the equal-length path to be achieved in order to determine the path planning. Finally, the path planning is mapped to waveguide routing, and cross-waveguide units are added at the corresponding positions. The method uses the grid's grid lines as basic units, defining the grid center coordinates, path intersections, and line segment combinations passing through the grid center coordinates as variables, including: Set the center coordinates of the grid as (i, j); And set the value to either 0 or 1: Whether the horizontal segment in row i and column j is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the vertical segment in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0; Whether the point in the i-th row and j-th column is a variable for additionally creating intersection points: E ij If additional intersection points are established, then E ij =1, otherwise E ij =0; The variable determining whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then ,otherwise ; The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then ;otherwise ; The variable determining whether the left segment of the point in row i and column j is on path k: If both the top left and bottom segments are on path-k, then ;otherwise ; Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper right and lower right segments are on path-k, then ;otherwise ; Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the bottom left and right segments are within path- On k, then ;otherwise ; Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then ;otherwise ; Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then ;otherwise ; Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then ;otherwise ; The constraints on the paths between PCell ports, the points on those paths, and the line segments are defined. These constraints include path intersection conditions, path input points, output points, and the existence of line segments, including: Restrict input points on path-k satisfy Output point satisfy ; Limit input point I k Output point O k All are only in path-k; Through the formula: Each segment can only be on one path at most; Through the formula: Each point can be on at most two paths; Through the formula: C ij , C ij The constraint is whether the point is at the intersection of two paths; Through the formula: For a point on path-k, exactly two of its four segments (up, down, left, and right) lie on path-k. Through the formula: The two endpoints of the segment restricted to path-k are also on path-k; Through the formula: C ij , C ij ， The two paths are restricted to intersecting only perpendicularly at their intersection point; Through the formula: Restrict the points in the i-th row and j-th column ; Through the formula: E ij , E ij , E ij ， When additional intersections are established at a certain point, that point must be on only one path, and the two segments connected to that point on the same path must be either horizontal or vertical.

2. The optoelectronic chip layout wiring method as described in claim 1, characterized in that: According to the formula: Calculate the length L of path-k k Where a is the unit length of the grid, R is the corner radius, and a equals R; According to the formula: C k C ij + E ij Calculate the total number of Crossing waveguide units on path-k; When path-k1 and path-k2 need to be equal, we have .

3. The optoelectronic chip layout wiring method as described in claim 2, characterized in that, Also includes: Through the formula: Optimize to minimize the total length of all paths and the total number of intersections. These are the weighting coefficients.

4. A layout wiring device for an optoelectronic chip, characterized in that, include: The mapping module is used to map the optoelectronic chip layout into a grid, map the parameterized unit PCell port into point coordinates, and map the waveguide that needs to be wired into line segments. The configuration module is used to define the center coordinates of the grid, the path intersection, and the combination of line segments passing through the center coordinates of the grid as variables, using the grid as the basic unit. The calculation module is used to set the constraints of the path between PCell ports, the points on the path, and the line segments. The constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments. The calculation module is also used to use the variables to represent the length of the path, and based on the constraints, calculate the corresponding variable values ​​according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide traces, and Crossing waveguide units are added at the corresponding positions. The configuration module uses the grid's grid lines as the basic unit, defining the grid center coordinates, path intersections, and line segment combinations passing through the grid center coordinates as variables, including: Set the center coordinates of the grid as (i, j); And set the value to either 0 or 1: Whether the horizontal segment in row i and column j is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the vertical segment in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is the intersection of two paths: C ij If it is the intersection of two paths, then C ij =1, otherwise C ij =0; Whether the point in the i-th row and j-th column is a variable for additionally creating intersection points: E ij If additional intersection points are established, then E ij =1, otherwise E ij =0; The variable determining whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then ,otherwise ; The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then ;otherwise ; The variable determining whether the left segment of the point in row i and column j is on path k: If both the top left and bottom segments are on path-k, then ;otherwise ; Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper right and lower right segments are on path-k, then ;otherwise ; Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then ;otherwise ; Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then ;otherwise ; Whether the point in the i-th row and j-th column is on path-k and another path: If it is on path-k and another path, then ;otherwise ; Whether the point in the i-th row and j-th column is on path-k and an additional variable for the Crossing waveguide element: If a Crossing waveguide unit is added to path-k, then ;otherwise ; The computing module sets constraints on the paths between PCell ports, the points on the paths, and the line segments. These constraints include path intersection conditions, path input points, output points, and the existence conditions of line segments, including: Restrict input points on path-k satisfy Output point satisfy ; Limit input point I k Output point O k All are only in path-k; Through the formula: Each segment can only be on one path at most; Through the formula: Each point can be on at most two paths; Through the formula: C ij , C ij The constraint is whether the point is at the intersection of two paths; Through the formula: For a point on path-k, exactly two of its four segments (up, down, left, and right) lie on path-k. Through the formula: The two endpoints of the segment restricted to path-k are also on path-k; Through the formula: C ij , C ij ， The two paths are restricted to intersecting only perpendicularly at their intersection point; Through the formula: ； ； Restrict the points in the i-th row and j-th column ; Through the formula: E ij , E ij , E ij ， When additional intersections are established at a certain point, that point must be on only one path, and the two segments connected to that point on the same path must be either horizontal or vertical.

5. A device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of a photoelectric chip layout wiring method as described in any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of a photoelectric chip layout wiring method as described in any one of claims 1 to 3.

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