A method, device and storage medium for transmitting routing table items

Abstract

The embodiment of the present invention provides a method, device and storage medium for transmitting routing table items, which relates to the field of data processing. A mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible by the above-mentioned main control CPU and the window in the memory block of the NP chip. The above-mentioned window is: a continuous memory space of the NP chip. The above-mentioned mapping relationship is: a one-to-one mapping relationship between the address of the above-mentioned preset memory space and the address of the above-mentioned window. The above-mentioned method includes: determining the first target address segment to be written in the routing table item in the NP chip; if the first target address segment is located in the above-mentioned window, then according to the above-mentioned mapping relationship, determining the second target address segment in the above-mentioned preset memory space; writing the above-mentioned routing table item into the above-mentioned second target address segment; writing the above-mentioned routing table item into the above-mentioned first target address segment. The scheme provided by the embodiment of the present invention can improve the transmission efficiency of routing table items.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data processing, and in particular to a routing table item transmission method, device and storage medium. Background Art

[0002] In the prior art, the NP (Network Processor) chip is responsible for message processing and forwarding. In order to enable the NP chip to process network data with maximum performance, a main control CPU is usually used to control and manage the NP chip, so as to save CPU and other resources of the NP chip and enable the NP chip to focus on message data processing.

[0003] The NP chip needs to query the routing table for message processing and forwarding, and the routing table needs to be transmitted from the main control CPU to the NP chip. In the process of message processing and forwarding by the NP chip, new routing table entries may be continuously required, so the main control CPU needs to continuously transmit new routing table entries to the NP chip. In the case of a large number of routing table entries, the transmission efficiency of the routing table entries may be low. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a method, device and storage medium for transmitting routing table entries, so as to improve the transmission efficiency of routing table entries. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present invention provides a method for transmitting routing table entries, which is applied to a master control CPU, wherein a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible to the master control CPU and a window in a memory block of a network processor NP chip, wherein the window is a continuous memory space in a memory block of the NP chip, and the mapping relationship is a one-to-one mapping relationship between an address of the preset memory space and an address of the window, and the method comprises:

[0006] Determine a first target address segment of a routing table entry to be written in the NP chip;

[0007] If the first target address segment is within the window, determining, according to the mapping relationship, a second target address segment in the preset memory space corresponding to the first target address segment;

[0008] Writing the routing table entry into the second target address segment in the preset memory space;

[0009] Based on the preset memory mapping protocol, the routing table entry is written into the first target address segment in the window of the NP chip.

[0010] In one embodiment of the present invention, the method further comprises:

[0011] If the first target address segment is outside the window, a window update notification is sent to the NP chip to control the NP chip to update the window to a position including the first target address segment, and continue to execute the step of determining the second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship.

[0012] In one embodiment of the present invention, sending a window update notification to the NP chip to control the NP chip to update the window to a position including the first target address segment includes:

[0013] Writing a parameter representing the position to which the window is to be updated into a first register of the NP chip;

[0014] Sending a window update notification to the NP chip, so that the NP chip queries the first register, obtains the parameter, updates the window to the position indicated by the parameter, and writes a target mark to its second register, wherein the target mark indicates that the NP chip has completed the position update of the window;

[0015] When the master CPU finds the target tag in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

[0016] In one embodiment of the present invention, the first target address segment is represented by the identifier of the target memory block, the entry offset of the routing table entry and the data length of the routing table entry, wherein the target memory block is: the memory block in the NP chip to which the routing table entry is to be written, and the entry offset is: the difference between the starting write address of the routing table entry and the starting address of the target memory block, and whether the first target address segment is located in the window is determined by the following method:

[0017] When the identifier of the target memory block is different from the identifier of the memory block where the window is located, determining that the first target address segment is not located in the window;

[0018] When the identifier of the target memory block is the same as the identifier of the memory block where the window is located, if the sum of the table entry offset and the data length is greater than the sum of the window offset and the size of the window, it is determined that the first target address segment is not located in the window, wherein the window offset is: the difference between the starting address of the window and the starting address of the memory block where the window is located.

[0019] In one embodiment of the present invention, a mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible to the master CPU and each window in the NP chip, and each window is located in a different memory block of the NP chip. If the first target address segment is located in the window, then according to the mapping relationship, determining the second target address segment in the preset memory space corresponding to the first target address segment includes:

[0020] If there is a target window including the first target address segment among the windows, a second target address segment in the preset memory space corresponding to the first target address segment is determined according to a mapping relationship corresponding to the target window.

[0021] In a second aspect, an embodiment of the present invention provides a method for transmitting routing table entries, which is applied to a network processor NP chip, wherein a mapping relationship based on a preset memory mapping protocol is established between a window in a memory block of the NP chip and a preset memory space accessible to a main control CPU, wherein the window is a continuous memory space in a memory block of the NP chip, and the mapping relationship is a one-to-one mapping relationship between an address of the window and an address of the preset memory space, and the method comprises:

[0022] Receive a routing table entry written into the first target address segment within the window and sent by the master CPU based on the preset memory mapping protocol, wherein the routing table entry is: a routing table entry written by the master CPU into the second target address segment within the preset memory space, and the second target address segment is: when the first target address segment is located within the window, the master CPU determines based on the mapping relationship and corresponds to the first target address segment.

[0023] In one embodiment of the present invention, the method further comprises:

[0024] Upon receiving a window update notification sent by the master CPU, the window is updated to a position including the first target address segment, wherein the window update notification is: when the first target address segment is not located in the original window, the master CPU sends a notification indicating an update window position to the NP chip.

[0025] In one embodiment of the present invention, updating the window to a position including the first target address segment includes:

[0026] querying its own first register to obtain a parameter indicating the position to which the window is to be updated, wherein the parameter is written by the main control CPU;

[0027] updating the window to a position indicated by the parameter according to the parameter;

[0028] A target mark is written into its own second register so that the master CPU determines that the NP chip has updated the window to a position including the first target address segment, wherein the target mark indicates that the NP chip has updated the window to a position including the first target address segment.

[0029] In a third aspect, an embodiment of the present invention provides a routing table item transmission device, which is applied to a main control CPU, wherein a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the main control CPU and a window in a memory block of a network processor NP chip, wherein the window is a continuous memory space in a memory block of the NP chip, and the mapping relationship is a one-to-one mapping relationship between an address of the preset memory space and an address of the window, wherein the device comprises:

[0030] A first determining module, used to determine a first target address segment to be written into the routing table entry in the NP chip;

[0031] a second determining module, configured to determine, if the first target address segment is within the window, a second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship;

[0032] A writing module, used for writing the routing table entry into the second target address segment in the preset memory space;

[0033] A transmission module is used to write the routing table entry into the first target address segment in the window of the NP chip based on the preset memory mapping protocol.

[0034] In a fourth aspect, an embodiment of the present invention provides a routing table item transmission device, which is applied to a network processor NP chip, wherein a mapping relationship based on a preset memory mapping protocol is established between a window in a memory block of the NP chip and a preset memory space accessible to a main control CPU, wherein the window is a continuous memory space in a memory block of the NP chip, and the mapping relationship is a one-to-one mapping relationship between an address of the window and an address of the preset memory space, and the device comprises:

[0035] A receiving module is used to receive a routing table entry written into the first target address segment within the window and sent by the master CPU based on the preset memory mapping protocol, wherein the routing table entry is: a routing table entry written by the master CPU into the second target address segment within the preset memory space, and the second target address segment is: when the first target address segment is located within the window, the master CPU determines based on the mapping relationship and corresponds to the first target address segment.

[0036] In a fifth aspect, an embodiment of the present invention provides an electronic device, comprising: a main control CPU and a network processor NP chip, wherein a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the main control CPU and a window in a memory block of the NP chip, wherein the window is a continuous memory space in the memory block of the NP chip, and the mapping relationship is a one-to-one mapping relationship between an address of the preset memory space and an address of the window;

[0037] The main control CPU is used to determine a first target address segment to be written into the routing table entry in the NP chip; if the first target address segment is within the window, determine a second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship; write the routing table entry into the second target address segment in the preset memory space; based on the preset memory mapping protocol, write the routing table entry into the first target address segment in the window of the NP chip;

[0038] The NP chip is used to receive the routing table entry written into the first target address segment in the window and sent by the main control CPU based on the preset memory mapping protocol.

[0039] In one embodiment of the present invention, the main control CPU is further used for:

[0040] If the first target address segment is outside the window, sending a window update notification to the NP chip;

[0041] The NP chip is also used for:

[0042] Upon receiving a window update notification sent by the master CPU, updating the window to a position including the first target address segment;

[0043] The main control CPU is also used for:

[0044] Continue to execute the step of determining, according to the mapping relationship, a second target address segment in the preset memory space corresponding to the first target address segment.

[0045] In one embodiment of the present invention, the main control CPU is specifically used for:

[0046] If the first target address segment is outside the window, writing a parameter indicating the position to which the window is to be updated into a first register of the NP chip; sending a window update notification to the NP chip;

[0047] The NP chip is specifically used for:

[0048] Upon receiving the window update notification sent by the master CPU, query its own first register to obtain a parameter indicating the position to which the window is to be updated; update the window to the position indicated by the parameter according to the parameter; write a target mark into its own second register, wherein the target mark indicates that the NP chip has updated the window to the position including the first target address segment;

[0049] The main control CPU is also specifically used for:

[0050] When the master CPU finds the target tag in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

[0051] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of the first aspect or the second aspect are implemented.

[0052] Beneficial effects of the embodiments of the present invention:

[0053] An embodiment of the present invention provides a method for transmitting routing table entries, wherein a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible to a main control CPU and a window in a memory block of an NP chip, wherein the window is: a continuous memory space in the memory block of the NP chip, and the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window, and the method comprises: determining a first target address segment to be written into the routing table entry in the NP chip; if the first target address segment is within the window, determining, according to the mapping relationship, a second target address segment in the preset memory space corresponding to the first target address segment; writing the routing table entry into the second target address segment in the preset memory space; and writing the routing table entry into the first target address segment in the window of the NP chip based on the preset memory mapping protocol.

[0054] As can be seen from the above, in the solution provided by the embodiment of the present invention, if it is determined that the first target address segment of the above-mentioned routing table item is located within the above-mentioned window, the second target address segment of the above-mentioned routing table item in the above-mentioned preset memory space can be determined according to the above-mentioned mapping relationship, and then the routing table item written into the above-mentioned second target address segment can be directly transmitted to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and written into the above-mentioned first target address segment. Therefore, the solution provided by the embodiment of the present invention can make the above-mentioned routing table item be directly transmitted from the above-mentioned main control CPU to the above-mentioned NP chip, simplifying the transmission path of the above-mentioned routing table item and improving the transmission efficiency of the routing table item. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0056] Figure 1 It is a structural diagram of the processing and forwarding of network messages in the prior art;

[0057] Figure 2 A schematic diagram of the structure of a PCIe connection device used in the prior art;

[0058] Figure 3 A schematic diagram of a first routing table item transmission solution in the prior art;

[0059] Figure 4 A schematic diagram of a second routing table item transmission scheme in the prior art;

[0060] Figure 5 A schematic diagram of a specific process of a second routing table item transmission solution in the prior art;

[0061] Figure 6 A schematic diagram of a flow chart of a first routing table entry transmission method provided in an embodiment of the present invention;

[0062] Figure 7 A schematic diagram of the mapping relationship between the preset memory space accessible by the master control CPU and the window in the NP chip provided in an embodiment of the present invention;

[0063] Figure 8 A schematic diagram of a flow chart of a second routing table entry transmission method provided in an embodiment of the present invention;

[0064] Fig.9A A schematic diagram of a first update window position provided by an embodiment of the present invention;

[0065] Fig. 9B A schematic diagram of a second update window position provided by an embodiment of the present invention;

[0066] Fig.10 A schematic diagram of a routing table entry transmission solution provided by an embodiment of the present invention;

[0067] Fig.11 A schematic diagram of the structure of a routing table entry transmission device provided by an embodiment of the present invention;

[0068] Fig.12 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field based on the present invention belong to the scope of protection of the present invention.

[0070] In the prior art, the structural diagram of processing and forwarding network messages is as follows: Figure 1 As shown. Figure 1 It can be seen that the main control CPU and the NP chip are connected through SPI (Serial Peripheral Interface) or SMI (Serial Management Interface) or PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus, etc., so that the main control CPU can be used to control and manage the NP chip, so as to save the CPU and other resources of the NP chip and enable the NP chip to focus on network message data processing.

[0071] The transmission of routing table items from the main control CPU to the NP chip requires the transmission path to have the characteristics of high bandwidth and low latency. Since the PCIe bus has the characteristics of high bandwidth and low latency, the NP chip is connected to the PCIe bus as a PCIe Endpoint device, which not only meets the high bandwidth and low latency requirements of the main control CPU for routing table item transmission, but also enables the main control CPU to control and manage the NP chip. Figure 2 As shown in the figure, it is a schematic diagram of the structure of connecting devices using PCIe. Figure 2 As can be seen in the figure, PCIe uses an end-to-end connection mode. Only one device can be connected to each end of a PCIe link. These two devices are the data transmitter and receiver of each other. Figure 2 In the figure, PCIe Endpoint represents a PCIe endpoint, PCIe Link represents a PCIe link, Root Complex represents a root complex device, which is integrated on the main control CPU and represents the processor to generate PCI (Peripheral Component Interconnect, a standard that defines local buses) transaction requests, Memory represents a memory, PCI / PCI-X Bridge represents a PCI / PCI-X bridge, and Switch represents a switch.

[0072] See also Figure 3 , is a schematic diagram of the first routing table item transmission scheme in the prior art. Figure 3 As can be seen from the figure, the main control CPU accesses the memory space of the NP chip through the SPI, SMI or PCIe bus. The specific steps for the main control CPU to transfer the routing table entries to the memory space of the NP chip are as follows:

[0073] Step X1: Obtain the NP chip memory access register interface offset address, and initiate access to the memory access register through the PCIe or SMI or SPI bus;

[0074] Step X2: Fill the protocol header supported by the chip into the access register 1;

[0075] Step X3: Fill the routing table entry content into the access register 2;

[0076] Step X4: Fill the memory block ID (identity document) of the routing table entry to be written and the address offset of the routing table entry in the memory block into the memory access register 3;

[0077] Step X5: configure one of the memory access registers to enable the hardware module to move data from the memory access register 2 to the memory space specified by the data filled in the memory access register 3 in the NP chip. After the hardware module completes the move, it will update the completion flag bit;

[0078] Step X6: The main control CPU polls the completion flag to confirm that the routing table entry transmission is completed, and then proceeds to the next routing table entry transmission.

[0079] exist Figure 3 In the scheme shown, the memory space of the NP chip is not visible to the main control CPU. The main control CPU can only fill the content of the routing table entry in the access register according to certain rules, and then the hardware module transmits it. Therefore, the routing table entry cannot be directly written into the NP memory space. Moreover, the hardware module and the access register can only perform a transmission operation of one routing table entry at a time. The main control CPU can only perform the next transmission after the current routing table entry is transmitted. As a result, when there are a large number of routing table entries to be transmitted, the NP chip resources will be greatly occupied, and the transmission efficiency of the routing table entries is not high. In addition, PCIe is a high-speed serial bus interface. Figure 3 The solution shown is only used to configure the memory access register. Due to the slow data transmission rate of the hardware module, efficient data transmission cannot be achieved. The main control CPU also needs a lot of software code logic to check the protocol header, making the software access memory interface complex and difficult to understand, making the software inconvenient to use.

[0080] See also Figure 4 , is a schematic diagram of the second routing table item transmission scheme in the prior art. Figure 4As can be seen in the figure, this solution uses DMA (Direct Memory Access) to transfer routing table entries, sets up a memory space for the NP chip on the main control CPU, and informs the NP chip of the starting address and size of this memory space. Figure 5 , is a schematic diagram of the specific process of the second routing table item transmission solution in the prior art, from Figure 5 It can be seen that there are four steps:

[0081] Step Y1: The master CPU writes the routing table entry into the specified location of the local memory;

[0082] Step Y2: The main control CPU informs the DMA Controller (Direct Memory Access Controller) of the NP chip of the size and address offset of the routing table entry, and at the same time informs the DMA Controller of the memory block ID where the routing table entry is to be written to the NP chip and the address offset of the routing table entry in the memory block;

[0083] Step Y3: The DMA Controller parses the information about the routing table items sent by the master CPU, and then reads the routing table items from the specified location of the master CPU memory space and writes them to the specified location of the NP chip memory space;

[0084] Step Y4: After the DMA Controller writes the routing table entry into the NP chip, it notifies the main control CPU that the routing table entry transfer has been completed.

[0085] exist Figure 4 , Figure 5 In the scheme shown, if the NP chip does not support DMA, the scheme cannot be used to transmit the routing table items. At the same time, each process of transmitting the routing table items requires the DMA Controller of the NP chip to interact with the main control CPU three times (i.e., step Y2, step Y3 and step Y4) to complete. When a large number of routing table items need to be transmitted, the NP chip cannot release more resources for network message data processing, and the transmission efficiency of the routing table items is not high.

[0086] Therefore, the existing technology may have the problem of low transmission efficiency of routing table entries.

[0087] In order to solve the above problems, the embodiments of the present invention provide a method, device and storage medium for transmitting routing table entries, which are described in detail below.

[0088] First, a routing table entry transmission method provided by an embodiment of the present invention is described.

[0089] See also Figure 6, which is a flow chart of the first routing table item transmission method provided in an embodiment of the present invention, the method is applied to a master CPU, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the master CPU and a window in a memory block of the NP chip, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window, the method includes the following steps S601-S604.

[0090] Specifically, when the master CPU and the NP chip are connected via a PCIe bus, the preset memory mapping protocol may be a BAR (Base Address Registers) address mapping function defined based on the PCIe 3.0 protocol. The BAR address mapping function may map a continuous memory space, i.e., a window, in each memory block of the NP chip to the master CPU for access, i.e., establish the mapping relationship between the preset memory space accessible to the master CPU and the window. The preset memory space accessible to the master CPU refers to a memory domain, i.e., an address space, provided by the master CPU, and is not a real DDR (Double Data Rate) memory space; the memory block of the NP chip refers to a memory block in the real DDR memory space to which the NP chip is mounted.

[0091] Step S601, determining a first target address segment of a routing table entry to be written in the NP chip.

[0092] Specifically, the first target address segment may be represented by an identifier of a memory block of the NP chip into which the routing table entry is to be written, a data length of the routing table entry, and a starting address of the first target address segment.

[0093] Step S602: If the first target address segment is located in the window, a second target address segment in the preset memory space corresponding to the first target address segment is determined according to the mapping relationship.

[0094] It is understandable that when the main control CPU determines that the above-mentioned first target address segment is located in the above-mentioned window, the above-mentioned main control CPU can determine the above-mentioned second target address segment according to the above-mentioned mapping relationship, that is, determine to write the above-mentioned routing table entry into the memory space corresponding to the above-mentioned second target address segment.

[0095] In one embodiment of the present invention, the master control CPU and the NP chip are connected by a PCIe bus, and the mapping relationship between the preset memory space accessible by the master control CPU and the window is as follows: Figure 7 See Figure 7, it can be seen that the DDR memory space connected to the NP chip contains N memory blocks, namely memory block 0, memory block 1, ..., memory block N. The window is a continuous memory space in the memory block 0, with a starting address of ID0_Offset0 and an ending address of ID0_Offset1. After the master CPU and the NP chip establish a link through PCIe, when the preset memory mapping protocol is based on the BAR address mapping function defined in the PCIe 3.0 protocol, the master CPU will scan the BAR register of the NP chip to obtain the size of the memory space that the NP chip maps to the master CPU and can access, that is, the size of the window is obtained. From Figure 7 It can be seen that the starting address of the above-mentioned preset memory space is CPU_Address0. The above-mentioned master CPU establishes a one-to-one mapping relationship with the address in the above-mentioned window starting from the CPU_Address0 address in the user-mode driver, that is, the above-mentioned CPU_Address0 address corresponds to the above-mentioned ID0_Offset0 address, and the next address adjacent to the above-mentioned CPU_Address0 address in the above-mentioned preset memory space corresponds to the next address adjacent to the above-mentioned ID0_Offset0 address in the above-mentioned window, and so on. If the above-mentioned master CPU wants to access the ID0_OffsetX address in the above-mentioned window, it only needs to access the CPU_AddressX address corresponding to the above-mentioned ID0_OffsetX address in the above-mentioned preset memory space in the form of a pointer. Specifically, the above-mentioned master CPU can find the above-mentioned CPU_AddressX address by obtaining the offset from the above-mentioned ID0_Offset0 address to the above-mentioned ID0_OffsetX address, wherein the offset from the above-mentioned CPU_Address0 address to the above-mentioned CPU_AddressX address is equal to the offset from the above-mentioned ID0_Offset0 address to the above-mentioned ID0_OffsetX address. Therefore, when the main control CPU determines the first target address segment, it can determine the second target address segment according to the mapping relationship.

[0096] Step S603, writing the routing table entry into the second target address segment in the preset memory space.

[0097] Specifically, after obtaining the second target address segment, the master CPU writes the routing table entry into the second target address segment, that is, the master CPU writes the routing table entry into the memory space corresponding to the second target address segment, so as to subsequently transmit the routing table entry to the NP chip.

[0098] Step S604: based on the preset memory mapping protocol, write the routing table entry into the first target address segment in the window of the NP chip.

[0099] After the above-mentioned master CPU writes the above-mentioned routing table entry into the memory space corresponding to the above-mentioned second target address segment, since the above-mentioned master CPU has obtained the writing position of the above-mentioned routing table entry in the above-mentioned window, the above-mentioned master CPU can directly transfer the above-mentioned routing table entry to the above-mentioned first target address segment of the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, thereby completing the process of transmitting the above-mentioned routing table entry to the above-mentioned NP chip.

[0100] In the aforementioned Figure 3 In the solution shown, the main control CPU needs to use a large amount of software code logic to check the protocol header, while in the solution provided by the embodiment of the present invention, the method of transmitting the above-mentioned routing table items based on the above-mentioned preset memory mapping protocol does not need to fill in the protocol header, and the protocol header will not be checked. The software code logic used will not be much, so the corresponding software use will be more convenient. And in the above-mentioned Figure 3 In the scheme shown, the transmission of routing table entries needs to go through the memory access register; whereas in the scheme provided in the embodiment of the present invention, routing table entries are directly transmitted from the above-mentioned main control CPU to the above-mentioned NP chip, and there is no need for the above-mentioned main control CPU to transmit the above-mentioned routing table entries to other components, and then the other components transmit the above-mentioned routing table entries to the above-mentioned NP chip, so that the transmission efficiency of the above-mentioned routing table entries will not be limited by other components. In addition, for multiple routing table entries with different addresses to be written in the NP chip, the main control CPU in the embodiment of the present invention can simultaneously determine the addresses of multiple routing table entries to be written in the NP chip, and can transmit multiple routing table entries at one time, as long as the computing resources of the transmission system including the above-mentioned main control CPU and the above-mentioned NP chip allow. The aforementioned Figure 4 The solution shown requires the NP chip to support the above DMA, while the solution provided by the embodiment of the present invention does not require the NP chip to support the above DMA, so that the NP chip that does not support the above DMA can also use the solution provided by the embodiment of the present invention to realize routing table entry transmission.

[0101] As can be seen from the above, in the solution provided by the embodiment of the present invention, if it is determined that the first target address segment of the above-mentioned routing table item is located within the above-mentioned window, the second target address segment of the above-mentioned routing table item in the above-mentioned preset memory space can be determined according to the above-mentioned mapping relationship, and then the routing table item written into the above-mentioned second target address segment can be directly transmitted to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and written into the above-mentioned first target address segment. Therefore, the solution provided by the embodiment of the present invention can make the above-mentioned routing table item be directly transmitted from the above-mentioned main control CPU to the above-mentioned NP chip, simplifying the transmission path of the above-mentioned routing table item and improving the transmission efficiency of the routing table item.

[0102] In step S601, the main control CPU may determine that the first target address segment of the routing table entry to be written in the NP chip is not within the window. Figure 6 Compared with the embodiment shown, the embodiment of the present invention provides Figure 8 The embodiment shown.

[0103] See also Figure 8 , is a flow chart of a second routing table entry transmission method provided in an embodiment of the present invention, which is similar to the aforementioned Figure 6 Compared with the embodiment shown, the above method further includes the following step S605.

[0104] Step S605: If the first target address segment is outside the window, a window update notification is sent to the NP chip to control the NP chip to update the window to a position including the first target address segment.

[0105] Specifically, when the master control CPU determines that the first target address segment is not within the window, that is, the window does not completely contain the first target address segment, specifically, the first target address segment is not within the window, or the window only contains a part of the first target address segment, the NP chip needs to update the window to a position containing the first target address segment. The master control CPU may notify the NP chip to move the window by triggering a soft interrupt, and the window update notification may contain information about the first target address segment, so that the NP chip can determine the target memory block where the first target address segment is located, as well as the start address and end address of the first target address segment after receiving the window update notification, so that the NP chip can determine a continuous memory space in its own target memory block, and the start address and end address of the first target address segment are both within the memory space. Specifically, the memory space may be any space with the first target address segment as the head, the end, or containing the first target address segment, and the position of the memory space is the position to be updated to the window, and the NP chip updates the position of the window accordingly.

[0106] See also Fig.9A , which is a schematic diagram of the first update window position provided by an embodiment of the present invention. The window included in the figure is: the memory space between the dotted lines in memory block 0, the current starting address is ID0_Offset0, and the ending address is ID0_Offset1. The two dotted lines between the memory mapping in the master CPU and memory block 0 indicate that there is a preset memory mapping relationship between the window in memory block 0 and the memory space in the master CPU. The portion shown in the gray area in the figure is the first target address segment. It can be seen from the figure that the above-mentioned first target address segment is in memory block N, not in the above-mentioned window, and the position of the above-mentioned window needs to be updated.

[0107] See also Fig. 9B , is a schematic diagram of a second update window position provided by an embodiment of the present invention. Fig.9AIn comparison, the memory space between the relatively sparse dotted lines in the figure is the location of the window before the update, and the memory space between the relatively dense dotted lines in the figure is the location of the window after the update. The two relatively dense dotted lines between the memory mapping in the main control CPU and the memory block N indicate that there is a preset memory mapping relationship between the window located in the memory block N after the update and the memory space in the main control CPU. As can be seen from the figure, the window is updated from memory block 0 to memory block N. The starting address of the updated window is IDN_Offset2, and the ending address is IDN_Offset3. The updated window contains the above-mentioned first target address segment. It can be understood that the offset from the above-mentioned ID0_Offset0 address to the above-mentioned ID0_Offset1 address is equal to the offset from the above-mentioned IDN_Offset2 address to the above-mentioned IDN_Offset3 address.

[0108] Before and after the window updates its position, the manner in which a mapping relationship is established between the preset memory space accessible to the main control CPU and the window is the same as that in the previous text. Figure 6 The manner of establishing the mapping relationship mentioned in the description of the illustrated embodiment is the same. Therefore, after the NP chip updates the window to a position including the first target address segment, the steps S602 to S604 can be continued to write the routing table entry into the first target address segment of the NP chip.

[0109] As can be seen from the above, in the solution provided by the embodiment of the present invention, if the above-mentioned master CPU determines that the above-mentioned first target address segment is outside the current position range of the above-mentioned window, the above-mentioned master CPU can control the above-mentioned NP chip to update the above-mentioned window to a position including the above-mentioned first target address segment. After the above-mentioned window updates the position, the above-mentioned master CPU can continue to write routing table entries into its own memory space, thereby transmitting the routing table entries to the updated window. That is, by adjusting the position of the window, the master CPU can write routing table entries into various positions in the NP chip, reflecting the flexibility of the transmission of the above-mentioned routing table entries. Moreover, no matter where the window is located, the master CPU can realize the transmission of the routing table entries by writing routing table entries into its own memory space, so the window update has little impact on the master CPU, and this process is imperceptible to the master CPU.

[0110] With the aforementioned Figure 8 Compared with the embodiment shown, in one embodiment of the present invention, the above step S605 is implemented by the following steps A-C to more specifically reflect the process in which the above master CPU sends the above window update notification to the above NP chip to control the above NP chip to update the above window.

[0111] Step A: if the first target address segment is outside the window, write a parameter indicating the position to which the window is to be updated into the first register of the NP chip.

[0112] When the master CPU determines that the first target address segment is outside the window, the master CPU writes the parameters of the position to be updated in the window into the first register, and the NP chip can obtain the parameters by querying the first register to prepare for the subsequent update of the window. Specifically, the first register is a register in the NP chip that allows the master CPU to write information, and the NP chip can query and obtain the information in the register. In addition, the embodiment of the present invention does not specifically limit the type of the first register.

[0113] Step B, sending a window update notification to the NP chip, so that the NP chip queries the first register, obtains the parameters, updates the window to the position indicated by the parameters, and writes the target mark to its own second register.

[0114] The target mark indicates that the NP chip has completed the position update of the window.

[0115] After the master CPU writes the parameters into the first register, the master CPU sends the window update notification to the NP chip, which enables the NP chip to query the first register to obtain the parameters, update the window to the position indicated by the parameters, and write the target mark to the second register after updating the window.

[0116] Specifically, the above parameters may include the target identifier of the target memory block where the above first target address segment is located, and the above window offset, that is, the offset between the start address of the above window and the start address of the above target memory block. Therefore, the above NP chip can determine the memory block where the position to be updated of the above window is located according to the above parameters, and determine a continuous memory space in the memory block, so that the memory space includes the start address and end address of the above first target address segment, thereby determining the position to be updated of the above window.

[0117] In addition, the target mark can be represented in the form of numbers, characters or strings, or can be represented by a target bit in a string, where the target bit is 0, indicating that the NP chip has not completed the position update of the window; the target bit is 1, indicating that the NP chip has completed the position update of the window. The second register is a register in the NP chip that allows the NP chip to write information, and the main control CPU can query the information in the register. In addition, the embodiment of the present invention does not specifically limit the type of the second register.

[0118] Step C: when the master control CPU finds the target mark in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

[0119] Specifically, after the master CPU sends the window update notification to the NP chip, the master CPU will continue to query the information in the second register until the target mark is found in the second register. In this case, the master CPU can determine that the NP chip has updated the window to a position including the first target address segment, and thus can continue to execute steps S602-S604.

[0120] It can also be seen that in a transmission of a single routing table entry, compared with the above Figure 4 , Figure 5 In the scheme shown, the main control CPU needs to interact with the NP chip 3 times. In the embodiment of the present invention, the number of interactions between the main control CPU and the NP chip is 0 or 2 times. Specifically, in the above Figure 6 In the embodiment of the present invention shown in FIG. 1 , the master CPU directly writes the routing table entry into the first target address segment in the NP chip, and the number of interactions between the master CPU and the NP chip is 0; in the Figure 8 In the embodiment of the present invention in which step S605 of the illustrated embodiment is implemented by the above-mentioned steps A to C, the above-mentioned master CPU writes the parameter representing the position to which the above-mentioned window is to be updated into the above-mentioned first register, and sends a window update notification to the above-mentioned NP chip. After the above-mentioned NP chip completes the window update and writes the above-mentioned target mark into the above-mentioned second register, the above-mentioned master CPU can query the above-mentioned target mark in the above-mentioned second register. The number of interactions between the above-mentioned master CPU and the above-mentioned NP chip is 2 times. When the number of transmissions of routing table items is large, the number of interactions between the above-mentioned master CPU and the above-mentioned NP chip can be effectively reduced, and the above-mentioned NP chip can release more resources for network message data processing.

[0121] It can be seen from the above that in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU will inform the above-mentioned NP chip of the parameters representing the position to which the above-mentioned window is to be updated, so that the above-mentioned NP chip updates the above-mentioned window according to the parameters, and the above-mentioned NP chip writes the above-mentioned target mark in the above-mentioned second register. When the above-mentioned main control CPU queries the above-mentioned target mark, it confirms that the above-mentioned NP chip has completed the update of the above-mentioned window, which can ensure the reliability of the above-mentioned window update result, and also ensure that in the subsequent process of the above-mentioned main control CPU transmitting the above-mentioned routing table entry, the above-mentioned routing table entry can be accurately written into the specified position of the above-mentioned NP chip.

[0122] In one embodiment of the present invention, the first target address segment is represented by the identifier of the target memory block, the entry offset of the routing table entry and the data length of the routing table entry, wherein the target memory block is: the memory block in the NP chip to which the routing table entry is to be written, and the entry offset is: the difference between the starting write address of the routing table entry and the starting address of the target memory block. Specifically, the difference can be the offset from the starting address of the target memory block to the starting write address of the routing table entry. Whether the first target address segment is located in the window can be determined by following steps D and E.

[0123] Step D: when the identifier of the target memory block is different from the identifier of the memory block where the window is located, determining that the first target address segment is not located in the window.

[0124] Specifically, the master control CPU may obtain relevant information of the first target address segment, that is, the identifier of the target memory block, the entry offset of the routing table entry, and the data length of the routing table entry; the master control CPU may also obtain relevant information of the window, such as the identifier of the memory block where the window is located. In the process of determining whether the first target address segment is located in the window, the master control CPU may first compare the identifier of the target memory block with the identifier of the memory block where the window is located. If the two are different, it may be directly determined that the first target address segment is not located in the window.

[0125] Step E, when the identifier of the target memory block is the same as the identifier of the memory block where the window is located, if the sum of the table entry offset and the data length is greater than the sum of the window offset and the size of the window, it is determined that the first target address segment is not located in the window.

[0126] The window offset is the difference between the starting address of the window and the starting address of the memory block where the window is located. Specifically, the difference may be the offset from the starting address of the memory block where the window is located to the starting address of the window.

[0127] In the case where the identifier of the target memory block is the same as the identifier of the memory block where the window is located, the main control CPU can first determine that the first target address segment and the window are in the same memory block. Since the entry offset is the offset from the starting address of the target memory block to the starting write address of the routing table item, the sum of the entry offset and the data length is the sum of the offset from the starting address of the target memory block to the starting write address of the routing table item and the data length, which determines the offset from the starting address of the target memory block to the ending address of the first target address segment; similarly, according to the window offset and the window size, the offset from the starting address of the target memory block to the ending address of the window can be determined. Therefore, if the sum of the entry offset and the data length is greater than the sum of the window offset and the size of the window, that is, the ending address of the first target address segment is located after the ending address of the window, indicating that the ending address of the first target address segment is outside the window, so it can be determined that the first target address segment is not located in the window.

[0128] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU first determines whether the identifier of the above-mentioned target memory block is the same as the identifier of the memory block where the above-mentioned window is located. If they are different, it is determined that the above-mentioned first target address segment is not located in the above-mentioned window; if they are the same, the sum of the above-mentioned table entry offset and the above-mentioned data length, and the sum of the above-mentioned window offset and the size of the above-mentioned window are calculated, and the above-mentioned first target address segment is determined by comparing the sizes of the two. Therefore, the above-mentioned main control CPU can simply and quickly determine whether the above-mentioned first target address segment is located in the above-mentioned window.

[0129] When the mapping relationship is established between the preset memory space accessible by the master CPU and the window, since the NP chip may contain multiple memory blocks, if the number of windows is 1, the probability that the first target address segment is not located in the window is relatively high, and the master CPU needs to frequently control the NP chip to update the window. To this end, in one embodiment of the present invention, multiple windows may be set, and the preset memory space accessible by the master CPU may establish a mapping relationship based on a preset memory mapping protocol with each window in the NP chip, and each window is located in a different memory block of the NP chip, and the step S602 may be implemented by the following step F.

[0130] Step F: if there is a target window including the first target address segment among the windows, then according to the mapping relationship corresponding to the target window, determine the second target address segment in the preset memory space corresponding to the first target address segment.

[0131] Specifically, when a mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible by the master CPU and each window in the NP chip, the number of the windows can be set as needed, and the embodiment of the present invention does not limit this.

[0132] Furthermore, in the case where a mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible by the master CPU and each window in the NP chip, the master CPU may transmit the routing table entry in the following manner: Fig.10 shown.

[0133] See also Fig.10 , is a schematic diagram of a routing table entry transmission solution provided by an embodiment of the present invention, from Fig.10 It can be seen that the process of the master CPU transmitting the routing table entry to the NP chip can be divided into the following four steps:

[0134] Step Z1: the main control CPU determines the first target address segment and determines whether the first target address segment is located in any window of the current windows. If so, the window is used as the target window to perform the transmission operation on the routing table item; if not, the window update notification is sent to the NP chip to control the NP chip to update one of the current windows to a position containing the first target address segment.

[0135] Step Z2: the NP chip performs a window update operation in response to the window update notification, and writes the target mark into the second register of the NP chip after the window update is completed;

[0136] Step Z3: After sending the window update notification to the NP chip, the master CPU will continue to query the second register, and when the target mark is found in the second register, it is confirmed that the NP chip has completed the window update;

[0137] Step Z4: the master CPU performs a transmission operation on the routing table entry.

[0138] As can be seen from the above, in the scheme proposed in the embodiment of the present invention, the above-mentioned master control CPU will establish the above-mentioned mapping relationship with the multiple windows in the above-mentioned NP chip, thereby increasing the possibility that the above-mentioned first target address segment is included in each current window of the above-mentioned NP chip, thereby reducing the possibility of controlling the above-mentioned NP chip to update the window, so that the computing resources of the above-mentioned master control CPU and the above-mentioned NP chip can be saved as much as possible. In addition, each window can be distinguished according to the memory block where each window is located, and the CPU can map multiple windows with one space, without occupying additional CPU space.

[0139] Corresponding to the aforementioned routing table entry transmission method applied to the main control CPU, the embodiment of the present invention further provides a routing table entry transmission method applied to the NP chip.

[0140] In one embodiment of the present invention, a mapping relationship based on a preset memory mapping protocol is established between the window in the memory block of the above-mentioned NP chip and the preset memory space accessible to the main control CPU, the above-mentioned window is: a continuous memory space in the memory block of the above-mentioned NP chip, and the above-mentioned mapping relationship is: a one-to-one mapping relationship between the address of the above-mentioned window and the address of the above-mentioned preset memory space, including the following steps G.

[0141] Step G, receiving the routing table entry written into the first target address segment in the window, which is sent by the master CPU based on the preset memory mapping protocol.

[0142] Among them, the above-mentioned routing table entry is: the routing table entry written by the above-mentioned main control CPU at the second target address segment in the above-mentioned preset memory space, and the above-mentioned second target address segment is: when the first target address segment is located in the above-mentioned window, the above-mentioned main control CPU determines based on the above-mentioned mapping relationship, and the address segment corresponding to the above-mentioned first target address segment.

[0143] Specifically, the main control CPU will write the routing table entry into the first target address segment based on the preset memory mapping protocol, and the NP chip only needs to receive the routing table entry.

[0144] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned master CPU can directly transmit the routing table items written into the above-mentioned second target address segment to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and write the above-mentioned routing table items into the above-mentioned first target address segment, and the above-mentioned NP chip only needs to receive the above-mentioned routing table items. Therefore, the application of the solution provided by the embodiment of the present invention can make the above-mentioned routing table items directly transmitted from the above-mentioned master CPU to the above-mentioned NP chip, simplifying the above-mentioned routing table item transmission path and improving the routing table item transmission efficiency.

[0145] In addition, in view of the situation that the first target address segment of the routing table entry to be written in the NP chip is not within the window currently contained in the NP chip, the embodiment of the present invention provides the following step H.

[0146] Step H: upon receiving the window update notification sent by the master CPU, updating the window to a position including the first target address segment.

[0147] The window update notification is a notification indicating the update of the window position sent by the main control CPU to the NP chip when the first target address segment is not located in the original window.

[0148] Specifically, after receiving the above-mentioned window update notification sent by the above-mentioned main control CPU, the above-mentioned NP chip will determine a continuous memory space in one of its own memory blocks, and the starting address and the ending address of the above-mentioned first target address segment are both within this memory space, and provide this memory space to the above-mentioned main control CPU for access, thereby completing the update of the above-mentioned window to the position containing the above-mentioned first target address segment.

[0149] As can be seen from the above, in the solution provided by the embodiment of the present invention, the NP chip updates the window to a position including the first target address segment, and the master CPU can continue to write routing table entries into its own memory space, thereby transmitting the routing table entries to the updated window. That is, by adjusting the position of the window, the master CPU can write routing table entries into various positions in the NP chip, reflecting the flexibility of transmitting the routing table entries. Moreover, no matter where the window is located, the master CPU can transmit the routing table entries by writing routing table entries into its own memory space, so the window update has little impact on the master CPU, and this process is imperceptible to the master CPU.

[0150] Compared with the aforementioned embodiment including step H, in one embodiment of the present invention, the above step H is implemented by the following steps H1-H3 to describe in more detail the process of the above NP chip updating the above window to a position including the above first target address segment.

[0151] Step H1, querying the first register of the self to obtain the parameter representing the position to which the above window is to be updated.

[0152] Among them, the above parameters are written by the above main control CPU, and the above parameters may include the target identifier of the target memory block where the above first target address segment is located, and the above window offset, that is, the offset between the starting address of the above window and the starting address of the above target memory block.

[0153] Step H2: updating the window to the position indicated by the parameters according to the parameters.

[0154] Specifically, the NP chip can determine the memory block where the window is to be updated based on the parameters, and determine a continuous memory space in the memory block, so that the memory space contains the start address and the end address of the first target address segment. In this way, the position to which the window is to be updated is determined, and the memory space is provided to the main control CPU for access, so that the window can be updated to the position containing the first target address segment.

[0155] Step H3, writing a target mark into its own second register, so that the master CPU determines that the NP chip has updated the window to a position including the first target address segment.

[0156] Among them, the above-mentioned target mark indicates that the above-mentioned NP chip has updated the above-mentioned window to a position including the above-mentioned first target address segment. Therefore, after querying the above-mentioned target mark, the above-mentioned main control CPU can determine that the above-mentioned NP chip has completed the update of the above-mentioned window, and thus continue to transmit the above-mentioned routing table entry.

[0157] It can be seen from the above that in the solution provided by the embodiment of the present invention, the above-mentioned NP chip updates the above-mentioned window according to the above-mentioned parameters, and after completing the update of the above-mentioned window, writes the above-mentioned target mark in the above-mentioned second register, so that the above-mentioned master CPU can confirm that the above-mentioned NP chip has completed the update of the above-mentioned window, and can ensure that in the subsequent process of the above-mentioned master CPU transmitting the above-mentioned routing table entry, the above-mentioned routing table entry can be accurately written into the specified position of the above-mentioned NP chip.

[0158] Specifically, the solution provided in the embodiment of the present invention and the aforementioned Figure 3 The schemes in the comparison are compared in terms of routing table item transmission efficiency. See Table 1 for the time required to transmit routing table items of different data lengths.

[0159] Table 1

[0160] Solution of the embodiment of the present invention Figure 3 The solution in 32M data 2.85s 104.48s 16M data 1.42s 52.35s 1M data 0.08s 3.67s 2M data 0.17s 6.91s

[0161] From the data in Table 1, we can see that compared with Figure 3 The solution in the embodiment of the present invention is used to transmit routing table entries, and its efficiency is improved by nearly 36 times.

[0162] Corresponding to the aforementioned method for transmitting routing table entries applied to a master control CPU, an embodiment of the present invention further provides a device for transmitting routing table entries applied to a master control CPU.

[0163] See also Fig.11 , is a schematic diagram of the structure of a routing table item transmission device provided by an embodiment of the present invention, the device is applied to a main control CPU, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the main control CPU and a window in a memory block of an NP chip, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window, the device comprises:

[0164] The first determining module 1101 is used to determine a first target address segment of a routing table entry to be written in the NP chip.

[0165] The second determining module 1102 is configured to determine, if the first target address segment is within the window, a second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship.

[0166] The writing module 1103 is used to write the above-mentioned routing table entry into the above-mentioned second target address segment in the above-mentioned preset memory space.

[0167] The transmission module 1104 is used to write the routing table entry into the first target address segment in the window of the NP chip based on the preset memory mapping protocol.

[0168] As can be seen from the above, in the solution provided by the embodiment of the present invention, if it is determined that the first target address segment of the above-mentioned routing table item is located within the above-mentioned window, the second target address segment of the above-mentioned routing table item in the above-mentioned preset memory space can be determined according to the above-mentioned mapping relationship, and then the routing table item written into the above-mentioned second target address segment can be directly transmitted to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and written into the above-mentioned first target address segment. Therefore, the solution provided by the embodiment of the present invention can make the above-mentioned routing table item be directly transmitted from the above-mentioned main control CPU to the above-mentioned NP chip, simplifying the transmission path of the above-mentioned routing table item and improving the transmission efficiency of the routing table item.

[0169] In one embodiment of the present invention, Fig.11 Compared with the illustrated embodiment, the following first updating module 1105 is also included.

[0170] The first updating module 1105 is configured to send a window updating notification to the NP chip if the first target address segment is outside the window, so as to control the NP chip to update the window to a position including the first target address segment.

[0171] Specifically, after controlling the NP chip to update the window to a position including the first target address segment, the second determination module 1102 continues to perform the step of determining the second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship. It can be understood that the writing module 1103 and the transmission module 1104 also continue to perform corresponding steps.

[0172] As can be seen from the above, in the solution provided by the embodiment of the present invention, if the above-mentioned master CPU determines that the above-mentioned first target address segment is outside the current position range of the above-mentioned window, the above-mentioned master CPU can control the above-mentioned NP chip to update the above-mentioned window to a position including the above-mentioned first target address segment. After the above-mentioned window updates the position, the above-mentioned master CPU can continue to write routing table entries into its own memory space, thereby transmitting the routing table entries to the updated window. That is, by adjusting the position of the window, the master CPU can write routing table entries into various positions in the NP chip, reflecting the flexibility of the transmission of the above-mentioned routing table entries. Moreover, no matter where the window is located, the master CPU can realize the transmission of the routing table entries by writing routing table entries into its own memory space, so the window update has little impact on the master CPU, and this process is imperceptible to the master CPU.

[0173] In one embodiment of the present invention, the first updating module 1105 is specifically used to:

[0174] A parameter indicating the position to which the window is to be updated is written into the first register of the NP chip.

[0175] A window update notification is sent to the NP chip, so that the NP chip queries the first register, obtains the parameters, updates the window to the position indicated by the parameters, and writes the target mark to its second register.

[0176] The target mark indicates that the NP chip has completed the position update of the window.

[0177] When the master CPU finds the target mark in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

[0178] It can be seen from the above that in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU will inform the above-mentioned NP chip of the parameters representing the position to which the above-mentioned window is to be updated, so that the above-mentioned NP chip updates the above-mentioned window according to the parameters, and the above-mentioned NP chip writes the above-mentioned target mark in the above-mentioned second register. When the above-mentioned main control CPU queries the above-mentioned target mark, it confirms that the above-mentioned NP chip has completed the update of the above-mentioned window, which can ensure the reliability of the above-mentioned window update result, and also ensure that in the subsequent process of the above-mentioned main control CPU transmitting the above-mentioned routing table entry, the above-mentioned routing table entry can be accurately written into the specified position of the above-mentioned NP chip.

[0179] In one embodiment of the present invention, Fig.11Compared with the embodiment shown or the embodiment including the above-mentioned first update module 1105, the above-mentioned first target address segment is represented by the identifier of the target memory block, the table offset of the above-mentioned routing table item and the data length of the above-mentioned routing table item, wherein the above-mentioned target memory block is: the memory block in the above-mentioned NP chip to which the above-mentioned routing table item is to be written, and the above-mentioned table item offset is: the difference between the starting write address of the above-mentioned routing table item and the starting address of the above-mentioned target memory block, and also includes the following third determination module 1106 and fourth determination module 1107.

[0180] The third determining module 1106 is configured to determine that the first target address segment is not located in the window when the identifier of the target memory block is different from the identifier of the memory block where the window is located.

[0181] The fourth determination module 1107 is used to determine that the first target address segment is not located in the above-mentioned window if the identifier of the above-mentioned target memory block is the same as the identifier of the memory block where the above-mentioned window is located and if the sum of the above-mentioned table entry offset and the above-mentioned data length is greater than the sum of the window offset and the size of the above-mentioned window.

[0182] The window offset is the difference between the start address of the window and the start address of the memory block where the window is located.

[0183] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU first determines whether the identifier of the above-mentioned target memory block is the same as the identifier of the memory block where the above-mentioned window is located. If they are different, it is determined that the above-mentioned first target address segment is not located in the above-mentioned window; if they are the same, the sum of the above-mentioned table entry offset and the above-mentioned data length, and the sum of the above-mentioned window offset and the size of the above-mentioned window are calculated, and the above-mentioned first target address segment is determined by comparing the sizes of the two. Therefore, the above-mentioned main control CPU can simply and quickly determine whether the above-mentioned first target address segment is located in the above-mentioned window.

[0184] In one embodiment of the present invention, Fig.11 Compared with the embodiment shown in the figure, a mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible by the master CPU and each window in the NP chip, and each window is located in a different memory block of the NP chip. The second determining module 1102 is specifically used to:

[0185] If there is a target window including the first target address segment among the windows, then the second target address segment in the preset memory space corresponding to the first target address segment is determined according to the mapping relationship corresponding to the target window.

[0186] As can be seen from the above, in the scheme proposed in the embodiment of the present invention, the above-mentioned master control CPU will establish the above-mentioned mapping relationship with the multiple windows in the above-mentioned NP chip, thereby increasing the possibility that the above-mentioned first target address segment is included in each current window of the above-mentioned NP chip, thereby reducing the possibility of controlling the above-mentioned NP chip to update the window, thereby saving the computing resources of the above-mentioned master control CPU and the above-mentioned NP chip as much as possible. In addition, each window can be distinguished according to the memory block where each window is located, and the CPU can map multiple windows with one space, without occupying additional CPU space.

[0187] Corresponding to the aforementioned method for transmitting routing table entries applied to an NP chip, an embodiment of the present invention further provides a device for transmitting routing table entries applied to an NP chip.

[0188] In one embodiment of the present invention, a mapping relationship based on a preset memory mapping protocol is established between the window in the memory block of the NP chip and the preset memory space accessible to the main control CPU, the window is: a continuous memory space in the memory block of the NP chip, and the mapping relationship is: a one-to-one mapping relationship between the address of the window and the address of the preset memory space, including the following means:

[0189] The receiving module I is used to receive the routing table entry written into the first target address segment in the above-mentioned window and sent by the above-mentioned main control CPU based on the above-mentioned preset memory mapping protocol.

[0190] The routing table entry is: the routing table entry written by the master control CPU at the second target address segment in the preset memory space, and the second target address segment is: the address segment corresponding to the first target address segment determined by the master control CPU based on the mapping relationship when the first target address segment is located in the window;

[0191] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned master CPU can directly transmit the routing table items written into the above-mentioned second target address segment to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and write the above-mentioned routing table items into the above-mentioned first target address segment, and the above-mentioned NP chip only needs to receive the above-mentioned routing table items. Therefore, the application of the solution provided by the embodiment of the present invention can make the above-mentioned routing table items directly transmitted from the above-mentioned master CPU to the above-mentioned NP chip, simplifying the above-mentioned routing table item transmission path and improving the routing table item transmission efficiency.

[0192] In one embodiment of the present invention, compared with the embodiment including the receiving module I, it further includes the following second updating module J.

[0193] The second updating module J is used to update the window to a position including the first target address segment upon receiving the window updating notification sent by the master CPU.

[0194] The window update notification is a notification indicating the update of the window position sent by the main control CPU to the NP chip when the first target address segment is not located in the original window.

[0195] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned NP chip updates the above-mentioned window to a position including the above-mentioned first target address segment. Since the manner of establishing a mapping relationship between the preset memory space accessible to the above-mentioned master CPU and the above-mentioned window remains unchanged before and after the above-mentioned window is updated, the above-mentioned master CPU can continue to write routing table items into its own memory space after the above-mentioned window is updated, thereby transmitting the routing table items to the updated window. That is, by adjusting the position of the window, the master CPU can write routing table items into various positions in the NP chip, reflecting the flexibility of transmitting the above-mentioned routing table items. Moreover, no matter where the window is located, the master CPU can realize the transmission of the routing table items by writing routing table items into its own memory space. Therefore, the window update has little impact on the master CPU, and this process is imperceptible to the master CPU.

[0196] In one embodiment of the present invention, the second update module J is specifically used for:

[0197] The first register of the system is queried to obtain a parameter indicating the position to which the window is to be updated.

[0198] The above parameters are written by the above master CPU.

[0199] Update the above window to the position indicated by the above parameters according to the above parameters.

[0200] The target mark is written into the second register thereof, so that the master control CPU determines that the NP chip has updated the window to a position including the first target address segment.

[0201] The target mark indicates that the NP chip has updated the window to a position including the first target address segment.

[0202] It can be seen from the above that in the solution provided by the embodiment of the present invention, the above-mentioned NP chip updates the above-mentioned window according to the above-mentioned parameters, and after completing the update of the above-mentioned window, writes the above-mentioned target mark in the above-mentioned second register, so that the above-mentioned master CPU can confirm that the above-mentioned NP chip has completed the update of the above-mentioned window, and can ensure that in the subsequent process of the above-mentioned master CPU transmitting the above-mentioned routing table entry, the above-mentioned routing table entry can be accurately written into the specified position of the above-mentioned NP chip.

[0203] Corresponding to the aforementioned routing table entry transmission method applied to the main control CPU and the NP chip, an embodiment of the present invention further provides an electronic device.

[0204] See also Fig.12 , is a structural diagram of an electronic device provided by an embodiment of the present invention, comprising a main control CPU 1201 and an NP chip 1202, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space in the main control CPU 1201 and a window in a memory block of the NP chip 1202, the window is: a continuous memory space in the memory block of the NP chip 1202, and the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window;

[0205] The main control CPU 1201 is used to determine the first target address segment to be written into the routing table entry in the NP chip 1202; if the first target address segment is within the window, determine the second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship; write the routing table entry into the second target address segment in the preset memory space; based on the preset memory mapping protocol, write the routing table entry into the first target address segment in the window of the NP chip 1202;

[0206] The NP chip 1202 is used to receive the routing table entry written into the first target address segment in the window and sent by the main control CPU 1201 based on the preset memory mapping protocol.

[0207] As can be seen from the above, in the solution provided by the embodiment of the present invention, if it is determined that the first target address segment of the above-mentioned routing table item is located within the above-mentioned window, the second target address segment of the above-mentioned routing table item in the above-mentioned preset memory space can be determined according to the above-mentioned mapping relationship, and then the routing table item written into the above-mentioned second target address segment can be directly transmitted to the above-mentioned NP chip based on the above-mentioned preset memory mapping protocol, and written into the above-mentioned first target address segment. Therefore, the solution provided by the embodiment of the present invention can make the above-mentioned routing table item be directly transmitted from the above-mentioned main control CPU to the above-mentioned NP chip, simplifying the transmission path of the above-mentioned routing table item and improving the transmission efficiency of the routing table item.

[0208] In one embodiment of the present invention, the main control CPU 1201 is further used for:

[0209] If the first target address segment is outside the window, a window update notification is sent to the NP chip 1202;

[0210] The NP chip 1202 is also used for:

[0211] Upon receiving the window update notification sent by the master CPU 1201, updating the window to a position including the first target address segment;

[0212] The main control CPU 1201 is also used for:

[0213] Continue to execute the step of determining the second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship.

[0214] As can be seen from the above, in the solution provided by the embodiment of the present invention, if the above-mentioned master CPU determines that the above-mentioned first target address segment is outside the current position range of the above-mentioned window, the above-mentioned master CPU can control the above-mentioned NP chip to update the above-mentioned window to a position including the above-mentioned first target address segment. After the above-mentioned window updates the position, the above-mentioned master CPU can continue to write routing table entries into its own memory space, thereby transmitting the routing table entries to the updated window. That is, by adjusting the position of the window, the master CPU can write routing table entries into various positions in the NP chip, reflecting the flexibility of the transmission of the above-mentioned routing table entries. Moreover, no matter where the window is located, the master CPU can realize the transmission of the routing table entries by writing routing table entries into its own memory space, so the window update has little impact on the master CPU, and this process is imperceptible to the master CPU.

[0215] In one embodiment of the present invention, the main control CPU 1201 is specifically used for:

[0216] If the first target address segment is outside the window, writing a parameter indicating the position to which the window is to be updated into the first register of the NP chip 1202; sending a window update notification to the NP chip 1202;

[0217] The NP chip 1202 is specifically used for:

[0218] When receiving the window update notification sent by the main control CPU 1201, query its own first register to obtain the parameter indicating the position to which the window is to be updated; update the window to the position indicated by the parameter according to the parameter; write a target mark into its own second register, the target mark indicating that the NP chip 1202 has updated the window to the position including the first target address segment;

[0219] The main control CPU 1201 is also specifically used for:

[0220] When the main control CPU 1201 finds the target mark in the second register, it is determined that the NP chip 1202 has updated the window to a position including the first target address segment.

[0221] It can be seen from the above that in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU will inform the above-mentioned NP chip of the parameters representing the position to which the above-mentioned window is to be updated, so that the above-mentioned NP chip updates the above-mentioned window according to the parameters, and the above-mentioned NP chip writes the above-mentioned target mark in the above-mentioned second register. When the above-mentioned main control CPU queries the above-mentioned target mark, it confirms that the above-mentioned NP chip has completed the update of the above-mentioned window, which can ensure the reliability of the above-mentioned window update result, and also ensure that in the subsequent process of the above-mentioned main control CPU transmitting the above-mentioned routing table entry, the above-mentioned routing table entry can be accurately written into the specified position of the above-mentioned NP chip.

[0222] In one embodiment of the present invention, the first target address segment is represented by the identifier of the target memory block, the entry offset of the routing table entry and the data length of the routing table entry, wherein the target memory block is: the memory block in the NP chip 1202 to which the routing table entry is to be written, and the entry offset is: the difference between the starting write address of the routing table entry and the starting address of the target memory block. The main control CPU 1201 is further used to:

[0223] When the identifier of the target memory block is different from the identifier of the memory block where the window is located, it is determined that the first target address segment is not located in the window; when the identifier of the target memory block is the same as the identifier of the memory block where the window is located, if the sum of the table entry offset and the data length is greater than the sum of the window offset and the size of the window, it is determined that the first target address segment is not located in the window.

[0224] The window offset is the difference between the start address of the window and the start address of the memory block where the window is located.

[0225] As can be seen from the above, in the solution provided by the embodiment of the present invention, the above-mentioned main control CPU first determines whether the identifier of the above-mentioned target memory block is the same as the identifier of the memory block where the above-mentioned window is located. If they are different, it is determined that the above-mentioned first target address segment is not located in the above-mentioned window; if they are the same, the sum of the above-mentioned table entry offset and the above-mentioned data length, and the sum of the above-mentioned window offset and the size of the above-mentioned window are calculated, and the above-mentioned first target address segment is determined by comparing the sizes of the two. Therefore, the above-mentioned main control CPU can simply and quickly determine whether the above-mentioned first target address segment is located in the above-mentioned window.

[0226] In one embodiment of the present invention, a mapping relationship based on a preset memory mapping protocol is established between the preset memory space in the master control CPU 1201 and each window in the NP chip 1202, and each window is located in a different memory block of the NP chip 1202. The master control CPU 1201 is specifically used to:

[0227] If there is a target window including the first target address segment among the windows, then the second target address segment in the preset memory space corresponding to the first target address segment is determined according to the mapping relationship corresponding to the target window.

[0228] As can be seen from the above, in the scheme proposed in the embodiment of the present invention, the above-mentioned master control CPU will establish the above-mentioned mapping relationship with the multiple windows in the above-mentioned NP chip, thereby increasing the possibility that the above-mentioned first target address segment is included in each current window of the above-mentioned NP chip, thereby reducing the possibility of controlling the above-mentioned NP chip to update the window, thereby saving the computing resources of the above-mentioned master control CPU and the above-mentioned NP chip as much as possible. In addition, each window can be distinguished according to the memory block where each window is located, and the CPU can map multiple windows with one space, without occupying additional CPU space.

[0229] In another embodiment provided by the present invention, a computer-readable storage medium is also provided, in which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned routing table item transmission methods applied to the above-mentioned master CPU or NP chip is implemented.

[0230] When the computer program stored in the computer-readable storage medium provided by the embodiment of the present invention is used to transmit routing table items, if it is determined that the first target address segment of the routing table item is located within the window, the second target address segment of the routing table item in the preset memory space can be determined according to the mapping relationship, and then the routing table item written into the second target address segment can be directly transmitted to the NP chip based on the preset memory mapping protocol, and written into the first target address segment. Therefore, the solution provided by the embodiment of the present invention can enable the routing table item to be directly transmitted from the master control CPU to the NP chip, simplifying the routing table item transmission path and improving the routing table item transmission efficiency.

[0231] In another embodiment provided by the present invention, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any of the routing table item transmission methods applied to the above-mentioned master control CPU or NP chip in the above-mentioned embodiments.

[0232] When the computer program product provided by the embodiment of the present invention is used to transmit routing table items, if it is determined that the first target address segment of the routing table item is located within the window, the second target address segment of the routing table item in the preset memory space can be determined according to the mapping relationship, and then the routing table item written into the second target address segment can be directly transmitted to the NP chip based on the preset memory mapping protocol, and written into the first target address segment. Therefore, the solution provided by the embodiment of the present invention can enable the routing table item to be directly transmitted from the main control CPU to the NP chip, simplifying the routing table item transmission path and improving the routing table item transmission efficiency.

[0233] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0234] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0235] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, computer-readable storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0236] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for transmitting routing table entries, characterized in that: Applied to a master control CPU, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the master control CPU and a window in a memory block of a network processor NP chip, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window, the method comprises: Determine a first target address segment of a routing table entry to be written in the NP chip; If the first target address segment is within the window, determining, according to the mapping relationship, a second target address segment in the preset memory space corresponding to the first target address segment; Writing the routing table entry into the second target address segment in the preset memory space; Based on the preset memory mapping protocol, the routing table entry is written into the first target address segment in the window of the NP chip.

2. The method according to claim 1, characterized in that The method further comprises: If the first target address segment is outside the window, a window update notification is sent to the NP chip to control the NP chip to update the window to a position including the first target address segment, and continue to execute the step of determining the second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship.

3. The method according to claim 2, characterized in that The sending of a window update notification to the NP chip to control the NP chip to update the window to a position including the first target address segment includes: Writing a parameter representing the position to which the window is to be updated into a first register of the NP chip; Sending a window update notification to the NP chip, so that the NP chip queries the first register, obtains the parameter, updates the window to the position indicated by the parameter, and writes a target mark to its second register, wherein the target mark indicates that the NP chip has completed the position update of the window; When the master CPU finds the target tag in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

4. The method according to any one of claims 1 to 3, characterized in that The first target address segment is represented by the identifier of the target memory block, the entry offset of the routing table entry and the data length of the routing table entry, wherein the target memory block is: the memory block in the NP chip to which the routing table entry is to be written, and the entry offset is: the difference between the start write address of the routing table entry and the start address of the target memory block. Whether the first target address segment is located in the window is determined by the following method: When the identifier of the target memory block is different from the identifier of the memory block where the window is located, determining that the first target address segment is not located in the window; When the identifier of the target memory block is the same as the identifier of the memory block where the window is located, if the sum of the table entry offset and the data length is greater than the sum of the window offset and the size of the window, it is determined that the first target address segment is not located in the window, wherein the window offset is: the difference between the starting address of the window and the starting address of the memory block where the window is located.

5. The method according to claim 1, characterized in that A mapping relationship based on a preset memory mapping protocol is established between the preset memory space accessible by the main control CPU and each window in the NP chip, each window is located in a different memory block of the NP chip, and if the first target address segment is located in the window, a second target address segment in the preset memory space corresponding to the first target address segment is determined according to the mapping relationship, including: If there is a target window including the first target address segment among the windows, a second target address segment in the preset memory space corresponding to the first target address segment is determined according to a mapping relationship corresponding to the target window.

6. A method for transmitting routing table entries, characterized in that: Applied to a network processor NP chip, a mapping relationship based on a preset memory mapping protocol is established between a window in a memory block of the NP chip and a preset memory space accessible to a main control CPU, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the window and an address of the preset memory space, the method comprises: Receive a routing table entry written into the first target address segment within the window and sent by the master CPU based on the preset memory mapping protocol, wherein the routing table entry is: a routing table entry written by the master CPU into the second target address segment within the preset memory space, and the second target address segment is: when the first target address segment is located within the window, the master CPU determines based on the mapping relationship and corresponds to the first target address segment.

7. The method according to claim 6, characterized in that The method further comprises: Upon receiving a window update notification sent by the master CPU, the window is updated to a position including the first target address segment, wherein the window update notification is: when the first target address segment is not located in the original window, the master CPU sends a notification indicating an update window position to the NP chip.

8. The method according to claim 7, characterized in that The updating the window to a position including the first target address segment comprises: querying its own first register to obtain a parameter indicating the position to which the window is to be updated, wherein the parameter is written by the main control CPU; updating the window to a position indicated by the parameter according to the parameter; A target mark is written into its own second register so that the master CPU determines that the NP chip has updated the window to a position including the first target address segment, wherein the target mark indicates that the NP chip has updated the window to a position including the first target address segment.

9. A routing table entry transmission device, characterized in that: Applied to a master control CPU, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the master control CPU and a window in a memory block of a network processor NP chip, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the preset memory space and an address of the window, the device comprises: A first determining module, used to determine a first target address segment to be written into the routing table entry in the NP chip; a second determining module, configured to determine, if the first target address segment is within the window, a second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship; A writing module, used for writing the routing table entry into the second target address segment in the preset memory space; A transmission module is used to write the routing table entry into the first target address segment in the window of the NP chip based on the preset memory mapping protocol.

10. A routing table entry transmission device, characterized in that: Applied to a network processor NP chip, a mapping relationship based on a preset memory mapping protocol is established between a window in a memory block of the NP chip and a preset memory space accessible to a main control CPU, the window is: a continuous memory space in the memory block of the NP chip, the mapping relationship is: a one-to-one mapping relationship between an address of the window and an address of the preset memory space, the device comprises: A receiving module is used to receive a routing table entry written into the first target address segment within the window and sent by the master CPU based on the preset memory mapping protocol, wherein the routing table entry is: a routing table entry written by the master CPU into the second target address segment within the preset memory space, and the second target address segment is: when the first target address segment is located within the window, the master CPU determines based on the mapping relationship and corresponds to the first target address segment.

11. An electronic device, characterized in that: include: A master control CPU and a network processor NP chip, a mapping relationship based on a preset memory mapping protocol is established between a preset memory space accessible by the master control CPU and a window in a memory block of the NP chip, the window being: a continuous memory space in the memory block of the NP chip, and the mapping relationship being: a one-to-one mapping relationship between an address of the preset memory space and an address of the window; The main control CPU is used to determine a first target address segment to be written into the routing table entry in the NP chip; if the first target address segment is within the window, determine a second target address segment in the preset memory space corresponding to the first target address segment according to the mapping relationship; Writing the routing table entry into the second target address segment in the preset memory space; Based on the preset memory mapping protocol, writing the routing table entry into the first target address segment in the window of the NP chip; The NP chip is used to receive the routing table entry written into the first target address segment in the window and sent by the main control CPU based on the preset memory mapping protocol.

12. The electronic device according to claim 11, characterized in that: The main control CPU is also used for: If the first target address segment is outside the window, sending a window update notification to the NP chip; The NP chip is also used for: Upon receiving a window update notification sent by the master CPU, updating the window to a position including the first target address segment; The main control CPU is also used for: Continue to execute the step of determining, according to the mapping relationship, a second target address segment in the preset memory space corresponding to the first target address segment.

13. The electronic device according to claim 12, characterized in that: The main control CPU is specifically used for: If the first target address segment is outside the window, writing a parameter indicating the position to which the window is to be updated into a first register of the NP chip; sending a window update notification to the NP chip; The NP chip is specifically used for: Upon receiving the window update notification sent by the master CPU, query its own first register to obtain a parameter indicating the position to which the window is to be updated; update the window to the position indicated by the parameter according to the parameter; write a target mark into its own second register, wherein the target mark indicates that the NP chip has updated the window to the position including the first target address segment; The main control CPU is also specifically used for: When the master CPU finds the target tag in the second register, it is determined that the NP chip has updated the window to a position including the first target address segment.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1-5 or 6-8 are implemented.

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