Method for accessing system memory and processing circuit arranged on network card

Abstract

The present invention discloses a method for accessing a system memory, which includes the following steps: reading a description unit from the system memory, wherein the description unit includes a buffer start address field and a buffer size field, wherein the buffer start address field includes the start address of the buffer in the system memory, and the buffer size field includes the size of the buffer; receiving a plurality of data packets, and writing the plurality of data packets into the buffer; modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the plurality of data packets or does not include information of any of the plurality of data packets; and writing the modified description unit into the system memory.

Description

Technical Field

[0001] The present invention relates to a method for accessing a system memory. Background Art

[0002] When an electronic device receives a network data packet from an external source, it temporarily stores the data packet and related parsing information in system memory for subsequent processing. There are two main approaches to storing parsing information: one is to allocate a complete, contiguous memory space within the system memory and store the parsing information for each data packet as a header within this memory space. However, since each data packet must be stored contiguously within this memory space, and the rapid increase in network connection speeds has led to an increase in the number of data packets to be processed, finding a complete, contiguous, and large-capacity memory space within the system memory is difficult. To address the issues with the first approach, a second approach uses multiple descriptors to describe multiple data packets. Each data packet can be stored at a different address within the system memory, and the processor can determine the address of the data packet within the system memory through a pointer to the corresponding descriptor. However, while the second approach eliminates the need for a complete, contiguous memory space within the system memory, receiving a large number of small data packets results in excessive read and write operations on the descriptor, resulting in wasted bandwidth and insufficient bandwidth, making it impossible to efficiently transmit data packets. Summary of the Invention

[0003] Therefore, one of the objects of the present invention is to propose a method for accessing system memory, which can effectively reduce the number of read and write times of using description units without the need to configure a complete continuous memory space in the system memory, so as to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a method for accessing a system memory is disclosed, comprising the following steps: reading a description unit from the system memory, wherein the description unit comprises a buffer start address field and a buffer size field, wherein the buffer start address field comprises a start address of the buffer in the system memory, and the buffer size field comprises the size of the buffer; receiving a plurality of data packets and writing the plurality of data packets into the buffer; modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit comprises information of only a portion of the plurality of data packets or does not comprise information of any of the plurality of data packets; and writing the modified description unit into the system memory.

[0005] In one embodiment of the present invention, a processing circuit disposed on a network card is disclosed, which is used to perform the following operations: read a description unit from a system memory external to the network card, wherein the description unit includes a buffer start address field and a buffer size field, wherein the buffer start address field includes the start address of the buffer in the system memory, and the buffer size field includes the size of the buffer; receive multiple data packets and write the multiple data packets into the buffer; modify the description unit according to the multiple data packets written to the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the multiple data packets or does not include information of any of the multiple data packets; and write the modified description unit to the system memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 Schematic diagram of a description unit prepared for a central processing unit and a modified description unit generated by a processing circuit.

[0008] Figure 3 Schematic diagram of a modified description unit and a corresponding buffer zone according to an embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a schematic diagram of a modified description unit and a corresponding buffer zone according to another embodiment of the present invention.

[0010] Figure 5 A method for accessing a system memory according to an embodiment of the present invention is provided. DETAILED DESCRIPTION

[0011] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1As shown, the electronic device 100 includes a network card 110, a system memory 120, a central processing unit 130, and a storage unit 140. The network card 110 includes a processing circuit 112 and a network connector 114, and the network connector 114 is used to connect to the network cable 102. The system memory 120 can be implemented using static random access memory (SRAM) or dynamic random access memory (DRAM). The system memory 120 includes multiple areas, one of which is used to store multiple description units 122_1-122_N, and each description unit 122_1-122_N is used to point to multiple buffers 124_1-124_N. The storage unit 140 includes at least one driver 142, wherein the driver 142 is used to perform operations related to the network card 110. In this embodiment, the electronic device 100 may be any electronic device that requires network functionality, such as a desktop computer, a laptop computer, etc., and the network card 110 may be built-in or externally connected to the electronic device 100 .

[0012] In this embodiment, each of the description units 122_1-122_N has a fixed size, such as 16 bytes or 32 bytes. In one embodiment, the description units 122_1-122_N are located at fixed addresses in the system memory 120, and the memory addresses of the description units 122_1-122_N are consecutive, but the present invention is not limited to this. In another embodiment, the description units 122_1-122_N do not necessarily have fixed addresses in the system memory 120, nor do they necessarily have consecutive memory addresses. As long as the description unit can indicate the memory address of the next description unit, for example, description unit 122_1 contains information pointing to the starting memory address of description unit 122_2. Furthermore, the addresses of the multiple buffers 124_1-124_N in the system memory 120 are not fixed, and the memory addresses of the buffers 124_1-124_N may be discontinuous.

[0013] During the operation of the electronic device 100, the central processing unit 130 reads the driver 142 from the storage unit 140 and executes the driver 142 to begin operations related to the network card 110, namely, receiving data packets received from the network card 110 via the network cable 102, or transmitting data to other electronic devices via the network card 110. In addition, the system memory 120 is used to temporarily store network data packets from the outside, data that needs to be transmitted to other electronic devices via the network card 110, or other system data. Since the focus of the present invention is to provide a method for storing data packets and related information, the following embodiments will only describe the content of the network data packets received by the electronic device 100 from the outside and stored in the system memory 120.

[0014] First, the CPU 130 prepares the contents of the description units 122_1 to 122_N in the system memory 120, wherein the description units 122_1 to 122_N are used to describe the information of the corresponding buffers 124_1 to 124_N. Figure 2 The diagram of description unit 122_1 is shown. Description unit 122_1 includes at least three fields: a control bit field, a buffer start address field, and a buffer size field. The control bit field indicates whether description unit 122_1 is currently available for use by network card 110. For example, the CPU 130 sets the control bit to "0" to indicate that network card 110 can currently use description unit 122_1 and the corresponding buffer 124_1. The buffer start address field indicates the starting address of buffer 124_1 in system memory 120, and the buffer size field indicates the capacity of buffer 124_1. Similarly, each of the remaining description units 122_2 to 122_N can also have the same structure. For example, description unit 122_2 includes a control bit, a buffer start address, and a buffer size corresponding to buffer 124_2, and so on.

[0015] In one embodiment, buffers 124_1-124_N do not have fixed addresses. For example, the next time the CPU 130 prepares the contents of the description unit 122_1, the buffer 124_1 may have a different address, and the starting address of the buffer within the description unit 122_1 may also be different. In one embodiment, the size of each buffer 124_1-124_N is greater than or equal to the maximum data size of an Ethernet packet, such as 1.5 kilobytes (KB), but the present invention is not limited to this. In other embodiments, the size of each buffer 124_1-124_N may be less than the maximum data size of an Ethernet packet.

[0016] Next, when the processing circuit 112 of the network card 110 receives one or more external data packets, the processing circuit 112 sequentially reads the descriptor units 122_1-122_N to determine which descriptor unit is available for processing circuit 112 to use. For example, the processing circuit 112 sequentially reads the control bits in the descriptor units 122_1-122_N and selects the descriptor unit with a control bit of "0" to perform subsequent operations. For ease of description, the following embodiment assumes that the processing circuit 112 selects the descriptor unit 122_1.

[0017] After reading the description unit 122_1, the processing circuit 112 determines how many currently received data packets the buffer 124_1 can store based on the buffer size of the buffer 124_1 recorded in the description unit 122_1. Figure 3 For example, assuming that data packets #0 to #2 are currently received, and if the total data size of data packets #0 to #2 plus the corresponding headers #0 to #2 is less than the size of the buffer 124_1, the processing circuit 112 may create a corresponding header for each data packet to record the information of the data packet, and write the header and the data packets into the buffer 124_1 in sequence. Specifically, the processing circuit 112 may create a header #0 for data packet #0, where header #0 records the size and related information of data packet #0, such as an error checking code (ECC) such as a checksum, and sequentially and continuously write header #0 and data packet #0 to the buffer 124_1. Next, the processing circuit 112 may create a header #1 for data packet #1, where header #1 records the size and related information of data packet #1, and sequentially and continuously write header #1 and data packet #1 to the buffer 124_1, with header #1 immediately following data packet #0. Next, the processing circuit 112 may create a header #2 for data packet #2, where header #2 records the size and related information of data packet #2, and sequentially and continuously write header #2 and data packet #2 to the buffer 124_1, with header #2 immediately following data packet #1.

[0018] In this embodiment, since the size of the next data packet received by the processing circuit 112 is larger than the remaining space of the buffer 124_1 , the processing circuit 112 does not continue to store the next data packet in the buffer 124_1 . The remaining space of the buffer 124_1 may remain blank without storing any data or may store invalid data.

[0019] After data packets #0-#2 are written into the buffer 124_1, the processing circuit 112 modifies the read content of the description unit 122_1 so that the modified description unit 112_1_A includes at least four fields: a control bit field, a first packet information field, a multi-packet tag field, and a total data amount / total number of packets field. In this embodiment, the control bit may be "1" to indicate that the corresponding buffer 124_1 has stored a data packet and may also be used to inform the CPU 130 that the data packet content can be read from the buffer 124_1. The first packet information field may include the starting address of header #0 of data packet #0, i.e., the starting address of the buffer 124_1. The multi-packet tag field is used to indicate whether the buffer 124_1 stores multiple data packets. For example, the multi-packet tag may be represented by a single bit. A multi-packet tag of "1" indicates that the buffer 124_1 currently stores two or more data packets, while a multi-packet tag of "0" indicates that the buffer 124_1 currently stores only one data packet. The total data size / total number of data packets field records the amount of all data currently stored in the buffer 124_1, or the number of stored data packets. Figure 3 The buffer 124_1 shown stores three data packets.

[0020] After the processing circuit 112 modifies the description unit 122_1 , the processing circuit 112 stores the modified description unit 112_1_A back to the original address of the description unit 122_1 in the system memory 120 . That is, the processing circuit 112 uses the modified description unit 112_1_A to overwrite the description unit 122_1 .

[0021] Next, the CPU 130 reads and analyzes the control bits in the descriptors 122_1-122_N and reads the descriptors whose control bits are set to "1." In this embodiment, the CPU 130 reads the modified descriptor 112_1_A and, based on the information in the modified descriptor 112_1_A, sequentially reads header #0, packet #0, header #1, packet #1, header #2, and packet #2 from the buffer 124_1 for subsequent processing. In this embodiment, because the modified descriptor 112_1_A provides a multi-packet tag field and a total data size / total number of packets field, the CPU 130 accurately determines the amount of data or packets to read from the buffer 124_1.

[0022] After the CPU 130 successfully reads the data in the buffer 124_1 , the CPU 130 may modify the modified description unit 112_1_A back to the description unit 112_1 , for example, by using the original description unit 112_1 to overwrite the modified description unit 112_1_A for use by the processing circuit 112 of the network card 110 when storing subsequent data packets.

[0023] In the above embodiment, since the buffer pointed to by a single descriptor unit can store multiple data packets, the central processor 130 does not need to prepare an excessive number of descriptor units 122_1-122_N in the system memory 120 to accommodate the reception of a large number of small data packets. Consequently, the space allocated within the system memory 120 specifically for storing descriptor units 122_1-122_N can be significantly reduced. Furthermore, although a single buffer can store multiple data packets, since the relevant information about the data packets (i.e., the header) is also stored in the buffer, the descriptor unit does not need to describe the relevant information about every data packet in the buffer. This effectively reduces the size of the descriptor unit, thereby avoiding excessive space in the system memory 120.

[0024] exist Figure 2 、 Figure 3 In the embodiment of FIG, the buffer 124_1 stores header #0, data packet #0, header #1, data packet #1, header #2, and data packet #2 in sequence, and the first data packet information in the modified description unit 112_1_A indicates the starting address of header #0. However, in other embodiments, referring to FIG. Figure 4 As shown, after the modification, the first packet information field in description unit 112_1_A can directly include relevant information about packet #0, such as the size and error checking code of packet #0. Buffer 124_1 no longer needs to store relevant information about packet #0. In other words, buffer 124_1 stores packet #0, header #1, packet #1, header #2, and packet #2 in sequence. These design changes are within the scope of the present invention.

[0025] Figure 5 A method for accessing a system memory according to an embodiment of the present invention, with reference to the contents described in the above embodiments, Figure 5 The process is as follows.

[0026] Step 500: The process starts.

[0027] Step 502: The CPU allocates a plurality of description units and corresponding plurality of buffers in the system memory.

[0028] Step 504: The processing circuit of the network card reads one of the description units.

[0029] Step 506: The processing circuit stores the one or more data packets and their headers into the buffer corresponding to the description unit.

[0030] Step 508: The processing circuit modifies the description unit according to the one or more data packets stored in the buffer to generate a modified description unit.

[0031] Step 510: The processing circuit writes the modified description unit into the system memory.

[0032] The above description is only a preferred embodiment of the present invention. Any equivalent changes and improvements made in accordance with the claims of the present invention shall fall within the scope of protection of the present invention.

[0033] Description of reference numerals:

[0034] 100: Electronic devices

[0035] 102: Network cable

[0036] 110: Network card

[0037] 112: Processing circuit

[0038] 114: Network connector

[0039] 120: System memory

[0040] 122_1~122_N: description unit

[0041] 122_1_A: Modified description unit

[0042] 124_1~124_N: buffer zone

[0043] 130:CPU

[0044] 140: Storage unit

[0045] 142: Driver

Claims

1. A method for accessing a system memory, comprising: Reading a description unit from the system memory, wherein the description unit comprises a buffer start address field and a buffer size field, wherein the buffer start address field comprises a start address of a buffer in the system memory, and the buffer size field comprises a size of the buffer; receiving a plurality of data packets, and writing the plurality of data packets into the buffer; modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the plurality of data packets or does not include information of any of the plurality of data packets; as well as The modified description unit is written to the system memory.

2. The method of claim 1 , wherein the step of receiving a plurality of data packets and writing the plurality of data packets into the buffer comprises: generating headers for the plurality of data packets respectively, wherein the header of each data packet includes information of the data packet; and The plurality of data packets, together with the corresponding headers, are sequentially written into the buffer.

3. The method of claim 2 , wherein the step of modifying the description unit according to the plurality of data packets written to the buffer to generate the modified description unit comprises: The description unit is modified according to the multiple data packets written to the buffer to add a first data packet information field and a total data volume / total number of data packets field to generate the modified description unit, wherein the first data packet information field includes the starting address of the buffer in the system memory or the address of the header of the first data packet among the multiple data packets; and the total data volume / total number of data packets field records the total amount of data stored in the buffer or the number of the multiple data packets.

4. The method of claim 3, wherein the modified description unit further comprises a multi-packet tag field, wherein the multi-packet tag field records whether the buffer stores multiple packets or only stores one packet. The method of claim 2 , wherein the information of the data packet includes the size of the data packet.

6. The method of claim 1 , wherein the plurality of data packets include a first data packet and at least one second data packet, and the step of receiving the plurality of data packets and writing the plurality of data packets into the buffer comprises: respectively generating a header for each of the at least one second data packet, wherein the header of each of the at least one second data packet comprises information of the second data packet; and The first data packet, the at least one second data packet and the corresponding headers are sequentially written into the buffer.

7. The method of claim 6 , wherein the step of modifying the description unit according to the plurality of data packets written to the buffer to generate the modified description unit comprises: The description unit is modified according to the multiple data packets written to the buffer to add a first data packet information field and a total data volume / total data packet number field to generate the modified description unit, wherein the first data packet information field includes information of the first data packet and the address of the first data packet in the system memory; and the total data volume / total data packet number field records the total data volume stored in the buffer or the number of the multiple data packets.

8. The method of claim 7, wherein the information of the first data packet includes a size of the first data packet, and the information of the second data packet includes a size of the second data packet.

9. The method according to claim 3 or 7, wherein the modified description unit further comprises a multi-packet tag field, wherein the multi-packet tag field records whether the buffer stores multiple data packets or only stores one data packet.

10. A processing circuit provided on a network card, configured to perform the following operations: Reading a description unit from a system memory external to the network card, wherein the description unit includes a buffer start address field and a buffer size field, wherein the buffer start address field includes a start address of a buffer in the system memory, and the buffer size field includes a size of the buffer; receiving a plurality of data packets, and writing the plurality of data packets into the buffer; modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the plurality of data packets or does not include information of any of the plurality of data packets; as well as The modified description unit is written to the system memory.

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