Packet processing accelerator

Abstract

A packet processing acceleration device includes a central processing unit (CPU), a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write-back circuit. The BD prefetch circuit reads a receive BD from a receive BD ring of a memory (DRAM) and writes it to the receive packet information ring of the TCM. The BD prefetch circuit also reads receive header data from a packet buffer of the DRAM and writes it to the receive packet information ring. The CPU accesses the TCM to read and process the receive BD and the receive header data, generating a transmit BD and transmit header data, and then writing them to the transmit packet information ring of the TCM. The BD write-back circuit reads the transmit BD from the transmit packet information ring and writes it to the transmit BD ring of the DRAM. The BD write-back circuit also reads the transmit header data from the transmit packet information ring and writes it to the packet buffer. The CPU accesses the TCM instead of the DRAM, thereby reducing latency.

Description

Technical Field

[0001] The present invention relates to a data packet processing device, and more particularly to a data packet processing acceleration device. Background Art

[0002] Figure 1 A general-purpose data packet processing device (e.g., a home gateway, a WiFi access point, and a 5G base station) is shown. Figure 1 The packet processing device 100 includes a central processing unit (CPU) 110, a cache 120, a multiplexer / demultiplexer 130, dynamic random access memory (DRAM) 140, a first network interface card (NIC 1) 150, and a second network interface card (NIC 2) 160. The first network interface card 150 stores received packets in the DRAM 140 via its receiver direct memory access (RX DMA) controller (not shown). The CPU 110 accesses the DRAM 140 to read and process at least a portion of the received packets (e.g., buffer descriptors (BDs) and packet header data), and writes the processed data back to the DRAM 140. The second network interface card 160 accesses the DRAM 140 via its transmitter direct memory access (TX DMA) controller (not shown), reads the processed packets as transmit packets, and outputs them.

[0003] As described above, the CPU 110 must access the DRAM 140 to obtain at least a portion of the received data packets, and must also access the read / write index of the RX DMA controller of the first network interface card 150 to determine whether there is data packet data waiting to be read from the DRAM 140. To increase processing efficiency, the CPU 110 accesses data packet data using cached access and uncached access. Uncached access is inefficient, while cached access requires additional processing of cache coherency and cache pollution. In addition, the CPU 110 experiences long latency when accessing the read / write index of the RX DMA controller or TX DMA controller of the first network interface card 150.

[0004] To solve Figure 1 One solution to the performance bottleneck encountered by the packet processing device 100 is to replace the static random access memory (SRAM) with Figure 1 DRAM 140. However, this solution is costly, and in certain situations (e.g., network congestion), insufficient SRAM space can lead to increased packet drop rates, thus affecting the user experience. Furthermore, this solution still suffers from long latency when accessing the read and write indexes of the RX DMA controller or TX DMA controller of the first network interface card 150.

[0005] Another solution is to Figure 1 In the packet processing device 100, an input and output consistency unit (IO Coherency Unit) is added, such as Figure 2 As shown. The input-output consistency unit 210 can snoop on the first network interface card 150's access to the DRAM 140 to automatically write a portion of the data (for example, buffer descriptors and packet header data) into the cache 120, so that the CPU can have the lowest latency when using cache access. In addition, when the second network interface card 160 wants to read processed data (for example, buffer descriptors or transmit data packets), the input-output consistency unit 210 can automatically write the data in the cache 120 back to the DRAM 140 after detecting this intention, so that the second network interface card 160 can obtain the latest data. The above solution has good performance, but the input-output consistency unit 210 is complex and costly, and requires the network interface card to work in conjunction with it. In addition, this solution still has the aforementioned cache pollution problem and cannot avoid the aforementioned long latency problem. Summary of the Invention

[0006] One of the objectives of the present disclosure is to provide a data packet processing acceleration device to avoid the problems of the prior art.

[0007] An embodiment of the packet processing acceleration device disclosed herein includes a central processing unit (CPU), a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write-back circuit.

[0008] The TCM is coupled to the CPU and is a first type of memory (e.g., static random access memory (SRAM)). The BD prefetch circuit is coupled to the TCM and is configured to read multiple sets of received BD data stored in a receive BD ring according to a BD extraction map and then write the multiple sets of received BD data to a receive packet information ring, wherein the receive BD ring is included in system memory (e.g., dynamic random access memory (DRAM)), and the receive packet information ring is included in the TCM. The BD prefetch circuit is further configured to read multiple sets of receive header data stored in a packet buffer according to a buffer extraction map and then write the multiple sets of receive header data to the receive packet information ring, wherein the packet buffer is included in the system memory. The CPU is configured to access the receive packet information ring to read and process the multiple sets of received BD data and the multiple sets of receive header data, and generate multiple sets of transmit BD data and multiple sets of transmit header data. The CPU is further configured to write the multiple sets of transmit BD data and the multiple sets of transmit header data to a transmit packet information ring, wherein the transmit packet information ring is included in the TCM. The BD write-back circuit is coupled to the TCM and is configured to read the plurality of sets of transmitted BD data stored in the transmit data packet information ring and write the plurality of sets of transmitted BD data into a transmit BD ring, wherein the transmit BD ring is included in the system memory. The BD write-back circuit is further configured to read the plurality of sets of transmit header data stored in the transmit data packet information ring and write the plurality of sets of transmit header data into the data packet buffer.

[0009] Another embodiment of the packet processing acceleration device disclosed herein includes a central processing unit (CPU) and a tightly coupled memory. The tightly coupled memory is coupled to the CPU. The CPU is configured to perform a BD prefetch operation. The BD prefetch operation includes: the CPU reading multiple sets of received BD data stored in a receive BD ring according to a buffer descriptor (BD) extraction map, and then writing the multiple sets of received BD data to a receive packet information ring; the CPU is further configured to read multiple sets of receive header data stored in a packet buffer according to the buffer extraction map, and then writing the multiple sets of receive header data to the receive packet information ring. The receive BD ring and the packet buffer are both included in a system memory, and the receive packet information ring is included in the tightly coupled memory. The CPU is configured to perform a BD processing operation, which includes: the CPU accessing the receive packet information ring to read and process the multiple sets of receive BD data and the multiple sets of receive header data, and generating multiple sets of transmit BD data and multiple sets of transmit header data; the CPU further configured to write the multiple sets of transmit BD data and the multiple sets of transmit header data into the transmit packet information ring, wherein the transmit packet information ring is included in the tightly coupled memory. The CPU is configured to perform a BD write-back operation, which includes: the CPU reading the multiple sets of transmit BD data stored in the transmit packet information ring and then writing the multiple sets of transmit BD data into the transmit BD ring; the CPU further configured to read the multiple sets of transmit header data stored in the transmit packet information ring and then writing the multiple sets of transmit header data into the packet buffer, wherein the transmit BD ring is included in the system memory.

[0010] The features, implementations and effects of the present invention are described in detail below with reference to preferred embodiments with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A known data packet processing device is shown;

[0012] Figure 2 Another known data packet processing device is shown;

[0013] Figure 3 An embodiment of the data packet processing acceleration device disclosed in the present invention is shown;

[0014] Figure 4 Shown Figure 3 An embodiment of a BDP circuit accessing a receive BD ring, a data packet buffer, and a receive data packet information ring;

[0015] Figure 5 Shown Figure 3 An embodiment of a BDW circuit accessing a transmit packet information ring, a transmit BD ring and a packet buffer;

[0016] Figure 6 Another embodiment of the data packet processing acceleration device disclosed in the present invention is shown;

[0017] Figure 7 Shown Figure 6 An embodiment of how the free buffer manager manages buffer addresses; and

[0018] Figure 8 A multi-channel embodiment of the data packet processing acceleration device disclosed in the present invention is shown. DETAILED DESCRIPTION

[0019] This specification discloses a data packet processing acceleration device. The data packet processing acceleration device disclosed herein does not need to use a cache, and can avoid cache coherency and cache pollution problems. The central processor of the data packet processing acceleration device disclosed herein does not need to access the read and write indexes of the direct memory access (DMA) controller of the network interface card, and can avoid the long latency problem. As shown in this specification, "A and / or B" and "at least one of A and B" refer to any combination of one or more of the listed associated items (A, B) (for example, A, B, or a combination of A and B).

[0020] Figure 3 An embodiment of the data packet processing acceleration device disclosed in the present invention is shown. Figure 3 The packet processing acceleration device 300 includes a central processing unit (CPU) 310, a tightly coupled memory (TCM) 320, a buffer descriptor (BD) prefetch circuit 330 (BDP circuit 330), and a BD write-back circuit 340 (BDW circuit 340). These circuits are described below.

[0021] Figure 3 An exemplary application of the packet processing acceleration device 300 is also shown; in this application, the packet processing acceleration device 300 is included in a packet forwarding device 30, and the packet forwarding device 30 also includes a first network interface control circuit 32 (referred to as NIC 32) (for example: Ethernet interface control circuit), a second network interface control circuit 34 (referred to as NIC34) (for example: wireless network interface control circuit) and a system memory 36 (for example: dynamic random access memory (DRAM)).

[0022] Please refer to Figure 3TCM 320 is coupled to CPU 310, BDP circuit 330, and BDW circuit 340, respectively. In one embodiment, TCM 320 is a static random access memory (SRAM). In one embodiment, TCM 320 is directly coupled to CPU 310, enabling CPU 310 to quickly access TCM 320. In one embodiment, TCM 320 is different from a cache and therefore does not include a cache controller.

[0023] Please refer to Figure 3 The BDP circuit 330 is configured to read multiple sets of received BD data stored in the reception-end (RX) BD ring 302 according to a BD extraction map, and then write the multiple sets of received BD data to the RX packet information ring 322. The RX BD ring 302 is included in the system memory 36 and is used to serve the RX direct memory access (RX DMA) controller (not shown) of the NIC 32. The RX packet information ring 322 is included in the TCM 320. The BD extraction map is a basis for BD extraction that depends on implementation and / or usage requirements; the method for determining the BD extraction map is beyond the scope of this disclosure. In one embodiment, the multiple sets of received BD data carry buffer information (e.g., buffer address and buffer length). The BDP circuit 330 can obtain the buffer address of at least one received packet based on the multiple sets of received BD data, and then read the data of the at least one received packet from the system memory 36 based on the buffer address. In one embodiment, the receiving BD ring 302 is a storage unit array with a fixed / adjustable length, and the receiving data packet information ring 322 is also a storage unit array with a fixed / adjustable length.

[0024] Please refer to Figure 3 BDP circuit 330 is further configured to read multiple sets of receive header data stored in packet buffer 304 according to a buffer extraction map, and then write the multiple sets of receive header data to receive packet information ring 322. The buffer extraction map is a buffer data extraction basis determined by implementation and / or usage requirements; the method for determining the buffer extraction map is beyond the scope of this disclosure.

[0025] Please refer to Figure 3. The CPU 310 is used to access the receive data packet information ring 322 to read and process the multiple sets of receive BD data and the multiple sets of receive header data, and generate multiple sets of transmit BD data and multiple sets of transmit header data. The CPU 310 is further used to write the multiple sets of transmit BD data and the multiple sets of transmit header data into the transmit data packet information ring 324 (TX packet information ring). The transmit data packet information ring 324 is included in the TCM 320. The way in which the CPU 310 processes the multiple sets of receive BD data and the multiple sets of receive header data depends on the implementation / application requirements and can be implemented by known / self-developed technologies. The details are not within the scope of discussion of this disclosure. It is worth noting that the CPU 310 accesses the TCM 320 without having to access the receive BD ring 302, the data packet buffer 304 and the transmit BD ring 306 described later, thereby reducing access delay. It is also worth noting that the CPU 310 can access the system memory 36 according to operational requirements.

[0026] Please refer to Figure 3 The BDW circuit 340 is used to read the multiple sets of transmit BD data stored in the transmit packet information ring 324 and then write the multiple sets of transmit BD data to the transmit BD ring 306 (TX BD ring). The transmit BD ring 306 is included in the system memory 36 and is used to serve the transmit direct memory access (TX DMA) controller (not shown) of the NIC 34. The BDW circuit 340 is also used to read the multiple sets of transmit header data stored in the transmit packet information ring 324 and then write the multiple sets of transmit header data to the packet buffer 304. In one embodiment, the multiple sets of transmit BD data carry buffer information (e.g., buffer address and buffer length). The BDW circuit 340 can obtain the buffer address of at least one transmit packet based on the multiple sets of transmit BD data and then update the data of the at least one transmit packet with the multiple sets of transmit header data based on the buffer address.

[0027] Figure 4 Shown Figure 3 The BDP circuit 330 accesses the receive BD ring 302, the packet buffer 304 and the receive packet information ring 322. Figure 4 As shown, the BDP circuit 330 determines whether there is BD data to be read based on whether the RX DMA write pointer 410 of the receiving BD ring 302 is different from the BDP read pointer 420, and then extracts the BD data (i.e., Figure 4 BD DW0, BD DW1, BD DW2, BD DW3) to select the multiple groups of received BD data (ie: Figure 4BD DW0, BD DW1, and BD DW3) are read from the received BD data. Based on the multiple sets of received BD data, the BDP circuit 330 determines the buffer address of at least one received data packet including the multiple sets of received header data. Based on the buffer address and the aforementioned buffer extraction map, the BDP circuit 330 selects and reads the multiple sets of received header data (i.e., PKT_BUF_DW0, PKT_BUF_DW1, PKT_BUF_DW2, PKT_BUF_DW3, PKT_BUF_DW4, PKT_BUF_DW5, ..., PKT_BUF_DW15) from the header data in the packet buffer 304. The BDP circuit 330 also writes the multiple sets of received BD data and subsequent sets of received header data into the received packet information ring 322 according to the BDP write pointer 430. The RX DMA write pointer 410 is controlled by the RX DMA controller of the NIC 32. The BDP read pointer 420 and the BDP write pointer 430 are controlled by the BDP circuit 330. Figure 4 In the receive BD ring 302 / data packet buffer 304 / received data packet information ring 322, each unit represents a storage unit, the size of which can be determined according to implementation requirements; each storage unit is used to store an item (for example, a BD item or a data packet information item), or is an empty storage unit.

[0028] Please refer to Figure 3-4 The CPU 310 determines whether there is data to be read based on whether the BDP write pointer 430 of the received data packet information ring 322 is different from the CPU read pointer 440, and further determines whether to read the multiple sets of received BD data and the multiple sets of received header data from the received data packet information ring 322. Figure 5 Shown Figure 3 In an embodiment of the invention, the BDW circuit 340 accesses the transmit data packet information ring 324, the transmit BD ring 306, and the data packet buffer 304, wherein the CPU 310 writes the multiple sets of transmit BD data and the multiple sets of transmit header data into the transmit data packet information ring 324 according to the CPU write pointer 510, and the CPU read pointer 440 and the CPU write pointer 510 are controlled by the CPU 310.

[0029] Please refer to Figure 3 and Figure 5 The BDW circuit 340 determines whether there is data to be read based on whether the CPU write pointer 510 of the transmission data packet information ring 324 is different from the BDW circuit read pointer 520, and then determines whether to read the multiple sets of transmission BD data (i.e.: Figure 5BD DW0, BD DW1, ..., BD DW7) and the multiple sets of transmission header data (ie: Figure 5 PKT_BUF_DW0, PKT_BUF_DW1, ..., PKT_BUF_DW15). The BDW circuit 340 also writes the multiple groups of transmission BD data into the transmission BD ring 306 according to the BDW circuit write pointer 530. The BDW circuit 340 also obtains the buffer address of at least one transmission data packet including the multiple groups of transmission header data based on the multiple groups of transmission BD data, and writes the multiple groups of transmission header data into the data packet buffer 304 according to the buffer address to update the at least one transmission data packet. The TX DMA controller of the NIC34 reads the at least one data packet according to the TX DMA read pointer 540, but this is not within the scope of discussion of this disclosure. It is worth noting that Figure 5 In the figure, each unit of the transmit data packet information ring 324 / transmit BD ring 306 / data packet buffer 304 represents a storage unit, the size of which can be determined according to implementation requirements; each storage unit is used to store an item (for example, a BD item or a data packet information item), or is an empty storage unit.

[0030] Figure 6 Another embodiment of the packet processing acceleration device disclosed in the present invention is shown. Figure 3 , Figure 6 The packet processing acceleration device 600 further includes a free buffer manager (FBM) 610. The FBM 610 is used to reclaim N buffer addresses of N transmission-complete spaces (N transmission-complete space(s)) in the transmit BD ring 306 through the BDP circuit 330, wherein the buffer data corresponding to the N buffer addresses (i.e., the data stored in the N transmission-complete spaces) have been read by the TX DMA controller of the NIC 34, where N is a positive integer. More specifically, the transmit BD ring 306 includes: storage units (i.e., Figure 6 , the filled-in diagonal squares of the BD ring 306); the storage units that have been read by the TX DMA controller (ie: Figure 6 , the grid of filled points of the BD ring 306 is transmitted), whose buffer address has not been recycled; and the storage unit whose buffer address has been recycled by the BDP circuit 330 (ie: Figure 6 , transmitting the blank square of the BD ring 306). It is worth noting that the FBM 610 can also be used to recycle one of the multiple receiving BD rings through the BDP circuit 330 (for example: Figure 8The buffer address of the receive BD ring 302-1 is retrieved. In this case, this receive BD ring is used by the TX DMA controller of the NIC 34. The details of the above operation can be deduced from the previous description and will not be repeated here. It is also worth noting that the CPU 310 can notify the BDP circuit 330 to perform a buffer address reclamation operation based on the request of the DMA controller of the NIC 32 / 34. It is also worth noting that the reclamation operation can be performed by the CPU 310 instead.

[0031] Please refer to Figure 6 The FBM 610 is further used to refill M buffer addresses to M reading-complete spaces (Mreading-complete space(s)) in the receiving BD ring 302 through the BDW circuit 340, wherein the buffer data corresponding to the M buffer addresses (i.e., the data stored in the M reading-complete spaces) have been read by the CPU 310, and M is a positive integer. More specifically, the receiving BD ring 302 includes: storage units waiting to be read by the BDP circuit 330 (i.e., Figure 6 , receiving the filled-in diagonal squares of the BD ring 302); the storage unit that has been read by the BDP circuit 330 (ie: Figure 6 , receiving the filled-in grid of the BD ring 302), whose buffer address has not been refilled; and the storage unit whose buffer address has been refilled by the BDW circuit 340 (ie: Figure 6 , receiving BD ring 302). It is worth noting that FBM 610 can also be used to refill the buffer address to one of the multiple transmitting BD rings (e.g., Figure 8 The buffer space of the transmit BD ring 306-1 is used by the NIC 32's RX DMA controller. The details of the above operation can be deduced from the previous description and will not be repeated here. It is also worth noting that the CPU 310 can notify the BDW circuit 340 to perform a buffer address refill operation based on the request of the NIC 32 / 34's DMA controller. It is also worth noting that the refill operation can be performed by the CPU 310 instead.

[0032] Figure 7 Shown Figure 6 An embodiment of how the FBM 610 manages buffer addresses. Figure 7 As shown, FBM 610 stores K buffer addresses (i.e.: Figure 7BUF_Add_1, BUF_Add_2, BUF_Add_3, ..., BUF_Add_K) are considered a stack of buffer addresses, where K is an integer greater than one. When the FBM 610 refills a buffer address into the read space in the receive BD ring 302, the FBM 610 provides the top address of the stack of buffer addresses as the buffer address. When the FBM 610 reclaims a buffer address from the transmitted space in the transmit BD ring 306, the FBM 610 uses the buffer address as the top address of the stack of buffer addresses.

[0033] Figure 8 A multi-channel embodiment of the data packet processing acceleration device disclosed in the present invention is shown. Figure 8 In the packet processing acceleration device 800, the BDP circuit 330 supports eight BDP channels, each of which corresponds to a receive BD ring 302 and a receive packet information ring 322. Part or all of the receive BD ring 302 is controlled by an RX DMA controller (not shown in the figure) and is also controlled by the FBM 610 (e.g., via the BDW circuit 340). Figure 8 BDW circuit 340 supports 8 BDW channels, each BDW channel corresponds to the transmit BD ring 306 and the transmit data packet information ring 324, and part or all of the transmit BD ring 306 is controlled by the TX DMA controller (not shown in the figure) and is also controlled by the FBM 610 (as shown in the figure) through the BDP circuit 330. Figure 8 As shown by the dotted arrow). Since ordinary technicians in this field can refer to Figure 3-7 The disclosure of the embodiments of the present invention will help you understand Figure 8 The details and variations of the embodiments, repeated and redundant descriptions are omitted here.

[0034] In an alternative embodiment, Figure 3 The CPU 310 executes the program to implement Figure 3 In an alternative embodiment, Figure 6 The CPU 310 executes the program to achieve Figure 6The functions of the BDP circuit 330, BDW circuit 340 and FBM 610 are implemented. In an alternative embodiment, the CPU 310 is a multi-core processor, that is, the CPU 310 may include two or more independent central processing units, and these cores can independently execute program instructions to perform multitasking, using the power of parallel computing to speed up program execution. More specifically, the CPU 310 performs at least one of BD prefetching, BD processing, BD write-back, recycling and refilling operations in a multitasking manner. In an embodiment, Figure 6 The functions of at least one part of the BDP circuit 330, the BDW circuit 340 and the FBM 610 are implemented by the independent central processing unit of the CPU 310. Figure 3-8 The details and variations of the above embodiments can be understood through the disclosure of the embodiments, and repeated and redundant descriptions are omitted here.

[0035] Please note that, under the premise of being feasible, ordinary technicians in this technical field may selectively implement some or all of the technical features in any of the aforementioned embodiments, or selectively implement a combination of some or all of the technical features in the aforementioned multiple embodiments, so as to increase the flexibility in the implementation of the present invention.

[0036] In summary, the data packet processing acceleration device disclosed in the present invention can avoid cache consistency and cache pollution problems, and can also avoid long delay problems.

[0037] Although the embodiments and examples of the present invention are described above, these embodiments and examples are not intended to limit the present invention. A person skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be based on the scope of the patent application defined in this specification.

[0038]

Explanation of symbols

[0039] 100: Data packet processing device

[0040] 110: CPU (Central Processing Unit)

[0041] 120: Cache

[0042] 130: Multiplexer / Demultiplexer

[0043] 140: DRAM (Dynamic Random Access Memory)

[0044] 150: NIC1 (first network interface card)

[0045] 160: NIC2 (second network interface card)

[0046] 210: Input and Output Consistency Unit

[0047] 30: Data packet forwarding device

[0048] 32: NIC (network interface control circuit)

[0049] 34: NIC (Network Interface Control Circuit)

[0050] 36: System memory

[0051] 300: Packet processing accelerator

[0052] 310: CPU (Central Processing Unit)

[0053] 320: TCM (tightly coupled memory)

[0054] 330: BDP circuit (buffer descriptor prefetch circuit)

[0055] 340: BDW circuit (buffer descriptor write back circuit)

[0056] 302: Receive BD Ring (Receive Buffer Descriptor Ring)

[0057] 304: Packet Buffer

[0058] 306: Transmit BD Ring (Transmit Buffer Descriptor Ring)

[0059] 322: Receive data packet information ring

[0060] 324: Transmit data packet information ring

[0061] 410: RX DMA write pointer (receive direct memory access controller write pointer)

[0062] 420: BDP read pointer

[0063] 430: BDP write pointer

[0064] 440: CPU reads pointer

[0065] BD DW0, BD DW1, BD DW2, BD DW3: Receive BD

[0066] PKT_BUF_DW0, PKT_BUF_DW1, PKT_BUF_DW2, PKT_BUF_DW3, PKT_BUF_DW4, PKT_BUF_DW5, ..., PKT_BUF_DW15: Receive header data

[0067] 510: CPU write pointer

[0068] 520: BDW circuit read pointer

[0069] 530: BDW circuit write pointer

[0070] 540: TX DMA read pointer (transmit direct memory access controller read pointer)

[0071] BD DW0, BD DW1, ..., BD DW7: Transmit BD

[0072] PKT_BUF_DW0, PKT_BUF_DW1, ..., PKT_BUF_DW15: transmit header data

[0073] 600: Packet processing accelerator

[0074] 610: FBM (Free Buffer Manager)

[0075] BUF_Add_1, BUF_Add_2, BUF_Add_3, ..., BUF_Add_K: buffer addresses

[0076] 800: Packet processing accelerator

[0077] 302-1: Receive BD Ring (Receive Buffer Descriptor Ring)

[0078] 306-1: Transmit BD Ring (Transmit Buffer Descriptor Ring)

Claims

1. A data packet processing acceleration device, comprising a central processing unit (CPU), a tightly coupled memory, a buffer descriptor (buffer descriptor; BD) pre-fetch circuit and BD write-back circuit, wherein: The tightly coupled memory is coupled to the CPU; The BD prefetch circuit is coupled to the tightly coupled memory and is configured to read multiple sets of received BD data stored in a receive BD ring according to a BD extraction map, and then write the multiple sets of received BD data into a receive packet information ring. The BD prefetch circuit is also configured to read multiple sets of received header data stored in a packet buffer according to a buffer extraction map, and then write the multiple sets of received header data into the receive packet information ring, wherein the receive BD ring and the packet buffer are both included in a system memory, and the receive packet information ring is included in the tightly coupled memory. The CPU is used to access the receive data packet information ring to read and process the multiple sets of receive BD data and the multiple sets of receive header data, and generate multiple sets of transmit BD data and multiple sets of transmit header data. The CPU is further used to write the multiple sets of transmit BD data and the multiple sets of transmit header data into the transmit data packet information ring, wherein the transmit data packet information ring is included in the tightly coupled memory; and The BD write-back circuit is coupled to the tightly coupled memory and is used to read the multiple sets of transmission BD data stored in the transmission data packet information ring and then write the multiple sets of transmission BD data into the transmission BD ring; The BD write-back circuit is further configured to read the multiple sets of transmission header data stored in the transmission data packet information ring and then write the multiple sets of transmission header data into the data packet buffer, wherein the transmission BD ring is included in the system memory. 2 . The packet processing acceleration device according to claim 1 , wherein the CPU does not access the receiving BD ring and the transmitting BD ring.

3. The packet processing acceleration device according to claim 1, wherein the BD prefetch circuit determines whether to read the multiple sets of received BD data from the receive BD ring based on whether there is a difference between a receive direct memory access controller write pointer and a BD prefetch circuit read pointer of the receive BD ring; the BD prefetch circuit obtains at least one buffer address of at least one data packet including the multiple sets of received header data based on the multiple sets of received BD data, and reads the multiple sets of received header data from the data packet buffer accordingly; the BD prefetch circuit writes the multiple sets of received BD data and the multiple sets of received header data into the receive packet information ring based on the BD prefetch circuit write pointer; the receive direct memory access write pointer is controlled by the receive direct memory access controller; the BD prefetch circuit read pointer and the BD prefetch circuit write pointer are controlled by the BD prefetch circuit.

4. The packet processing acceleration device according to claim 1, wherein the CPU determines whether to read the multiple groups of received BD data and the multiple groups of received header data from the received packet information ring based on whether there is a difference between the BD prefetch circuit write pointer and the CPU read pointer of the received packet information ring; the CPU writes the multiple groups of transmitted BD data and the multiple groups of transmitted header data into the transmitted packet information ring based on the CPU write pointer; the BD prefetch circuit write pointer is controlled by the BD prefetch circuit; the CPU read pointer and the CPU write pointer are controlled by the CPU.

5. The packet processing acceleration device according to claim 1, wherein the BD write-back circuit determines whether to read the multiple sets of transmission BD data and the multiple sets of transmission header data based on whether there is a difference between the CPU write pointer and the BD write-back circuit read pointer of the transmission packet information ring; the BD write-back circuit writes the multiple sets of transmission BD data into the transmission BD ring based on the BD write-back circuit write pointer; the BD write-back circuit also obtains at least one buffer address of at least one data packet including the multiple sets of transmission header data based on the multiple sets of transmission BD data, and writes the multiple sets of transmission header data into the packet buffer accordingly.

6. The packet processing acceleration device according to claim 1 further includes a free buffer manager, which is used to reclaim N buffer addresses of N transmitted spaces in the transmitting BD ring through the BD prefetch circuit, where N is a positive integer; the free buffer manager is also used to refill M buffer addresses to M read spaces in the receiving BD ring through the BD write-back circuit, where M is a positive integer.

7. The data packet processing acceleration device according to claim 6, wherein the free buffer manager regards K buffer addresses as a stack of buffer addresses, where K is an integer greater than one; when the free buffer manager wants to refill the first buffer address to the first read space in the receiving BD ring, the free buffer manager uses the topmost address of the stack of buffer addresses as the first buffer address; when the free buffer manager reclaims the first transmitted address of the first transmitted space in the transmitting BD ring, the free buffer manager uses the first transmitted address as the topmost address of the stack of buffer addresses.

8. The packet processing acceleration device according to claim 1, wherein the packet processing acceleration device and the system memory are included in a packet forwarding device, the receiving BD ring is used to serve the first network interface control circuit of the packet forwarding device, and the transmitting BD ring is used to serve the second network interface control circuit of the packet forwarding device.

9. A packet processing acceleration device comprising a central processing unit (CPU) and a tightly coupled memory, wherein: The tightly coupled memory is coupled to the CPU; The CPU is configured to perform a BD prefetch operation, the BD prefetch operation comprising: the CPU reading multiple sets of received BD data stored in a receive BD ring according to a buffer descriptor (BD) extraction map, and then writing the multiple sets of received BD data into a receive packet information ring; the CPU also reading multiple sets of receive header data stored in a packet buffer according to the buffer extraction map, and then writing the multiple sets of receive header data into the receive packet information ring, wherein the receive BD ring and the packet buffer are both included in a system memory, and the receive packet information ring is included in the tightly coupled memory; The CPU is used to perform a BD processing operation, which includes: the CPU accessing the receive data packet information ring to read and process the multiple sets of receive BD data and the multiple sets of receive header data, and generating multiple sets of transmit BD data and multiple sets of transmit header data; the CPU further writing the multiple sets of transmit BD data and the multiple sets of transmit header data into the transmit data packet information ring, wherein the transmit data packet information ring is included in the tightly coupled memory; and The CPU is used to perform a BD write-back operation, which includes: the CPU reading the multiple sets of BD data stored in the transmission data packet information ring, and then writing the multiple sets of BD data into the transmission BD ring; the CPU also reads the multiple sets of transmission header data stored in the transmission data packet information ring, and then writes the multiple sets of transmission header data into the data packet buffer, wherein the transmission BD ring is included in the system memory.

10. The data packet processing acceleration device according to claim 9, wherein the CPU is further used to perform a recycling operation to recycle N buffer addresses of N transmitted spaces in the transmitting BD ring, where N is a positive integer; the CPU is also used to perform a refilling operation to refill M buffer addresses to M read spaces in the receiving BD ring, where M is a positive integer.

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