Method, system, terminal and medium for modeling electrical characteristics of three-dimensional stacked structure modules
By setting blind vias and through vias in the three-dimensional stacked structure module, and combining shell and ground, simulation can be performed directly in a single model, solving the problem of long simulation time in existing technologies. This achieves an efficient and reliable three-dimensional interconnect structure simulation model, improving signal integrity and product quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN MICROELECTRONICS TECH INST
- Filing Date
- 2023-03-27
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies cannot easily and conveniently establish simulation models of three-dimensional interconnected POP modules, cannot truly reflect the signal integrity of the modules, and the simulation process is time-consuming.
By setting blind and through holes in the three-dimensional stacked structure module, and combining the top shell and side shell of the module, a virtual model is established and optimized, and simulation is performed directly in one model, omitting complicated steps such as HFSS simulation and substrate link construction.
It enables the establishment of efficient and reliable three-dimensional interconnect structure simulation models, saving time, accurately reflecting the module signal quality, shortening the development cycle, and improving product quality.
Smart Images
Figure CN116245069B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of three-dimensional integrated system simulation modeling technology, specifically to a method, system, terminal, and medium for modeling the electrical characteristics of a three-dimensional stacked structure module. Background Technology
[0002] Modern electronic devices are increasingly demanding miniaturization and high-density integration. Three-dimensional integration technology can significantly shorten signal line lengths and reduce the area occupied by electronic devices, making it a key technology for achieving high performance, high reliability, miniaturization, and lightweight design. However, the vertical module structure is relatively complex, requiring multiple simulation steps using various simulation software for different parts of the module, generating a large amount of data and consuming considerable time. Furthermore, the presence of numerous and diverse side interconnect channels and the module's shell further complicates model building. Therefore, it is necessary to explore a simple, convenient, and template-based method to establish a simulation model of a three-dimensional interconnect structure POP module, enabling simulation analysis of the module's electrical characteristics and providing practical and effective design suggestions for subsequent product applications. Existing technologies cannot easily and conveniently establish a simulation model of a three-dimensional interconnect structure POP module, nor can they realistically simulate the complex and diverse side interconnect channels and irregular large-area shells.
[0003] Existing modeling methods involve separately modeling the substrate and side interconnects, requiring HFSS simulation of vertical interconnect channels. This necessitates repeated simulations of the substrate and interconnect channels, resulting in significant time consumption. After obtaining S-parameters, interlayer substrate links are then constructed for timing analysis. When modeling the side interconnects separately, the existence of the shell / ground is ignored, failing to accurately reflect the module's signal integrity. Furthermore, since S-parameters for these substrates and interconnect channels are extracted separately, complete module S-parameters cannot be provided to users, impacting subsequent system-level simulations. Summary of the Invention
[0004] In order to overcome the shortcomings of the existing technology, the present invention aims to provide a method, system, terminal and medium for electrical characteristic modeling of a three-dimensional stacked structure module, so as to solve the technical problem that the existing technology requires repeated simulation analysis of the substrate and interconnect channel, which consumes a lot of time and cannot truly reflect the signal integrity of the module.
[0005] This invention is achieved through the following technical solution:
[0006] A method for modeling the electrical characteristics of a three-dimensional stacked structure module includes the following steps:
[0007] Based on the required module stacking structure, the multilayer substrate layout file is preprocessed to obtain a module layout file containing the stacked structure. Based on the position of the floating interconnect leads of the multilayer substrate, multiple blind and buried vias are set on the side interconnect channels along the length of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0008] The virtual model of the three-dimensional stacked structure module is optimized to obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0009] Preferably, the process of preprocessing multiple substrate layout files to obtain the layout stack-up structure is as follows:
[0010] The modules are placed sequentially from bottom to top within the same layout project file according to their internal stacking order, thus obtaining a module layout file containing a stacked structure.
[0011] Preferably, multiple blind vias are placed at the positions of the suspended interconnect leads of multiple substrates to simulate the side interconnect channels along the length of the module, wherein the size of the blind vias is consistent with the width of the module interconnect channels, and the depth of the blind vias penetrates different dielectric layers according to the depth of the interconnect channels.
[0012] Furthermore, the width of the blind via is set according to the network attributes of the side interconnection channel along the length of the module. If the network attributes of the module interconnection channels are different, the width of the blind via is the same as the width of the module interconnection channel. If the network attributes of the module interconnection channels are the same, the width of the blind via is the width of the interconnection channel occupied by adjacent modules with the same network attributes.
[0013] Preferably, a conductive layer is provided on the top layer of the module to simulate the top shell of the module. The irregular shell on the side of the module along its length direction consists of multiple blind and buried vias and through-holes provided along the side of the module along its length direction. The blind and buried vias are located on the top layer of the interconnect channels on the side of the module along its length direction. The width of the blind and buried vias is the sum of the widths of the interconnect channels, and the depth is from the surface of the top substrate to the surface of the module. The through-holes are located on both sides of the interconnect channels. The width of the through-holes is the width of both sides of the interconnect channels on the side of the module along its length direction, and the depth is from the bottom plate of the module to the surface of the module.
[0014] Preferably, a through hole is provided on the side of the module from the bottom to the top of the module along the width direction of the module. The width of the through hole is the dimension of the module width direction, and the depth is from the bottom surface of the module to the surface of the module.
[0015] Preferably, the three-dimensional interconnect signals of the substrate are led out through suspended interconnect leads. The suspended interconnect leads are ground according to the module body size, that is, part of the structure of the suspended interconnect leads is left in the module and part of the structure is ground away. The blind buried vias are set according to the outer dimensions of the module and the grinding position of the suspended interconnect leads on the substrate. The specific number, position, width and depth of the blind buried vias are designed according to the direction of the interconnect channel in the final three-dimensional interconnect structure simulation model.
[0016] A system for modeling the electrical characteristics of a three-dimensional stacked structural module, comprising:
[0017] The layout design software processing module is used to preprocess the multilayer substrate layout file according to the required module stacking structure to obtain the module layout file containing the stacking structure, and according to the position of the floating interconnect leads of the multilayer substrate, set multiple blind and buried vias on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0018] The simulation model processing module is used to optimize the virtual model of the three-dimensional stacked structure module, obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0019] A mobile terminal includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the electrical characteristic modeling method for a three-dimensional stacked structure module as described above.
[0020] A computer-readable storage medium storing a computer program, characterized in that, when executed by a processor, the computer program implements the steps of the electrical characteristic modeling method for a three-dimensional stacked structure module as described above.
[0021] Compared with the prior art, the present invention has the following beneficial technical effects:
[0022] This invention provides a method for modeling the electrical characteristics of a three-dimensional stacked structure module. Utilizing a two-step approach, it efficiently and reliably establishes a simulation model with relatively low time cost. Through interactive design between layout software and simulation software, it quickly and conveniently builds a simulation model of the three-dimensional interconnect structure, omitting complex and redundant steps such as HFSS simulation of vertical interconnect channels and 3D layout construction of interlayer substrate links. By combining or separating blind and buried vias of different widths and depths, different simulation models can be quickly and effectively built using a template-based "building block" approach. By directly establishing the substrate and side interconnects within a single model, separate simulations and link construction are unnecessary, saving the time consumed by repeated simulations in the aforementioned methods, simplifying the process and saving time.
[0023] Furthermore, by establishing the substrate and side interconnects within a single model, separate simulations and interconnect construction are eliminated, saving time previously spent on separate modeling of the substrate and side interconnects. This simplifies the process and reduces time. Considering the presence of the module's shell, a model closely resembling the module's actual structure is created. The irregular shell along the module's length provides a return path for transmitted signals, reduces crosstalk between adjacent signal lines, and reliably simulates signal quality during module operation. This significantly shortens the overall module development cycle, improves product quality, and provides accurate and complete S-parameters for the module, offering convenience to users. Attached Figure Description
[0024] Figure 1 This is a flowchart of the electrical characteristic modeling method for the three-dimensional stacked structure module in this invention;
[0025] Figure 2 This is a schematic diagram of the POP module stacking structure according to an embodiment of the present invention;
[0026] Figure 3 This is a diagram showing the internal stacking of the POP module according to an embodiment of the present invention;
[0027] Figure 4 This is a stack-up diagram of the POP substrate layout data according to an embodiment of the present invention;
[0028] Figure 5 This is a processing diagram of a blind burial hole according to an embodiment of the present invention;
[0029] Figure 6 This is a physical diagram of a single-sided interconnection channel of the POP module according to an embodiment of the present invention;
[0030] Figure 7 This is a physical diagram of the POP module according to an embodiment of the present invention;
[0031] Figure 8 This is a simulation model diagram of the POP module in an embodiment of the present invention. Detailed Implementation
[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0033] The present invention will now be described in further detail with reference to the accompanying drawings:
[0034] The purpose of this invention is to provide a method, system, terminal, and medium for modeling the electrical characteristics of a three-dimensional stacked structure module, in order to solve the technical problem in the prior art where repeated simulation analysis of the substrate and interconnect channels consumes a lot of time and cannot truly reflect the signal integrity of the module.
[0035] Specifically, according to Figure 1 As shown, the electrical characteristic modeling method of this three-dimensional stacked structure module includes the following process:
[0036] S1. Based on the required module stacking structure, the multilayer substrate layout file is preprocessed to obtain a module layout file containing the stacked structure. Based on the position of the floating interconnect leads of the multilayer substrate, multiple blind and buried vias are set on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0037] S2. Optimize the virtual model of the three-dimensional stacked structure module to obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. Connect them to obtain the three-dimensional interconnect structure simulation model. In the three-dimensional interconnect structure simulation model, combine it with the multilayer substrate to form an electrical conductivity layer, and complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0038] Specifically, the process of preprocessing multiple substrate layout files to obtain the layout stack-up structure is as follows:
[0039] The modules are placed sequentially from bottom to top within the same layout project file according to their internal stacking order, thus obtaining a module layout file containing a stacked structure.
[0040] Specifically, multiple blind vias are placed at the locations of the suspended interconnect leads on multiple substrates to simulate the side interconnect channels along the length of the module. The size of the blind vias is consistent with the width of the module interconnect channels, and the depth of the blind vias penetrates different dielectric layers according to the depth of the interconnect channels.
[0041] The width of the blind via is set according to the network attributes of the side interconnection channel along the length of the module. If the network attributes of the module interconnection channels are different, the width of the blind via is the same as the width of the module interconnection channel. If the network attributes of the module interconnection channels are the same, the width of the blind via is the width of the interconnection channel occupied by adjacent modules with the same network attributes.
[0042] Specifically, a conductive layer is set on the top layer of the module to simulate the top shell of the module. The irregular shell on the side along the length of the module consists of multiple blind and buried vias and through-holes. The blind and buried vias are located on the top layer of the interconnect channels on the side along the length of the module. The width of the blind and buried vias is the sum of the widths of the interconnect channels, and the depth is from the surface of the top substrate to the surface of the module. The through-holes are located on both sides of the interconnect channels. The width of the through-holes is the width of both sides of the interconnect channels, and the depth is from the bottom plate of the module to the surface of the module.
[0043] Specifically, through holes are provided on the side of the module from the bottom to the top of the module along the width direction. The width of the through holes is the same as the width of the module, and the depth is from the bottom surface of the module to the surface of the module.
[0044] Specifically, the three-dimensional interconnect signals of the substrate are led out through suspended interconnect leads. The suspended interconnect leads are ground according to the module body size, that is, part of the structure of the suspended interconnect leads is left in the module and part of the structure is ground away. The blind and buried vias are set according to the outer dimensions of the module and the grinding position of the suspended interconnect leads on the substrate. The specific number, position, width and depth of the blind and buried vias are designed according to the direction of the interconnect channel in the final three-dimensional interconnect structure simulation model.
[0045] Example 1
[0046] This embodiment provides a method for modeling the electrical characteristics of a three-dimensional stacked structure module, and the specific steps are as follows:
[0047] Step 1: Preprocess the module layout file, set the stacking order, and place blind vias;
[0048] This step can be divided into two stages:
[0049] Phase 1: According to the required module stacking structure diagram, such as... Figure 2 As shown, the layout files of the substrates used in the module are placed in the same layout design project file, and the layout stack-up structure is set according to the stacking order, such as... Figure 3 and Figure 4 As shown.
[0050] Phase 2: The three-dimensional interconnect signals on the substrate rely on suspended interconnect leads. This part of the structure is ground away during subsequent module processing according to the module's dimensions; that is, a portion of the structure remains inside the module. Since the remaining portion is ground away, blind / buried vias simulating the side (length direction) interconnects need to be placed, referencing the module's external dimensions and the subsequent grinding positions of the suspended interconnect leads. Figure 5 As shown. The specific quantity, location, width, and hole depth are designed according to the orientation of the interconnect channels in the final three-dimensional interconnect structure, such as... Figure 6 As shown, there are some irregular shell-to-ground channels on the side of the module. Considering the via stacking limitations of the layout design software, these shell-to-ground channels will be set in the subsequent simulation software.
[0051] Step 2: Using simulation software, simulate the top shell and remaining irregular shell channels on the sides of the 3D interconnected POP module. After importing the simulation software, set a separate large-area layer on the top surface of the module to simulate the shell. Following the direction of the side shell channels, place blind holes between specific layers and connect them to the large-area layer on the top surface to build the module model. The module has a total of 4 planes on its sides. The module has two planes without interconnect channels (in the width direction). These two planes will become the shell of the module in subsequent processing; therefore, through holes need to be placed on these two planes to simulate the shell on the sides of the module. Figure 7 and Figure 8 As shown.
[0052] In this invention, the layout design software can be any one of Cadence Allegro, Mentor, or Altium Designer. The simulation software can be any one of 3D Layout or SIWAVE.
[0053] This invention provides a method for modeling the electrical characteristics of a three-dimensional stacked structure module. Based on the interactive design of layout design software and simulation software, it allows for the rapid and convenient creation of simulation models of the three-dimensional interconnect structure. The method eliminates complex and redundant steps, such as HFSS simulation of vertical interconnect channels and 3D layout for building interlayer substrate links. By combining or separating blind and buried vias of different widths and depths, different simulation models can be quickly and effectively created using a template-based approach, similar to "building blocks." Therefore, this module modeling method not only creates models that closely match the actual module and reliably simulates the signal quality during module operation, but also significantly reduces the overall module development cycle, improves product quality, and has broad application prospects.
[0054] By combining or separating blind vias of different widths and depths, different simulation models can be quickly and effectively built, much like "building blocks," ultimately resulting in a realistic and reliable 3D interconnected structure simulation model. This method is powerful, efficient, stable, and simple in structure, significantly reducing model building time, improving simulation efficiency, and shortening module development cycles, thus possessing significant strategic importance and social benefits.
[0055] The present invention also provides an electrical characteristic modeling system for a three-dimensional stacked structure module, including...
[0056] The layout design software processing module is used to preprocess the multilayer substrate layout file according to the required module stacking structure to obtain the module layout file containing the stacking structure, and according to the position of the floating interconnect leads of the multilayer substrate, set multiple blind and buried vias on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0057] The simulation model processing module is used to optimize the virtual model of the three-dimensional stacked structure module, obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0058] The present invention also provides a mobile terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, such as an electrical characteristic modeling program for a three-dimensional stacked structure module.
[0059] When the processor executes the computer program, it implements the steps of the above-described method for modeling the electrical characteristics of the three-dimensional stacked structure module, for example:
[0060] Based on the required module stacking structure, the multilayer substrate layout file is preprocessed to obtain a module layout file containing the stacked structure. Based on the position of the floating interconnect leads of the multilayer substrate, multiple blind and buried vias are set on the side interconnect channels along the length of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0061] The virtual model of the three-dimensional stacked structure module is optimized to obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0062] Alternatively, when the processor executes the computer program, it implements the functions of each module in the above system, for example:
[0063] The layout design software processing module is used to preprocess the multilayer substrate layout file according to the required module stacking structure to obtain the module layout file containing the stacking structure, and according to the position of the floating interconnect leads of the multilayer substrate, set multiple blind and buried vias on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0064] The simulation model processing module is used to optimize the virtual model of the three-dimensional stacked structure module, obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0065] For example, the computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the mobile terminal. For example, the computer program can be divided into a layout file processing module and a simulation model processing module; the specific functions of each module are as follows:
[0066] The layout design software processing module is used to preprocess the multilayer substrate layout file according to the required module stacking structure to obtain the module layout file containing the stacking structure, and according to the position of the floating interconnect leads of the multilayer substrate, set multiple blind and buried vias on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module.
[0067] The simulation model processing module is used to optimize the virtual model of the three-dimensional stacked structure module, obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
[0068] The mobile terminal can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The mobile terminal may include, but is not limited to, a processor and a memory.
[0069] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. This processor is the control center of the mobile terminal, connecting all parts of the mobile terminal via various interfaces and lines.
[0070] The memory can be used to store the computer program and / or module. The processor implements various functions of the mobile terminal by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory.
[0071] The memory may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function (such as sound playback or image playback). The data storage area may store data created based on the use of the phone (such as audio data or a phonebook). Furthermore, the memory may include high-speed random access memory (RAM) and non-volatile memory, such as hard disks, RAM, plug-in hard disks, SmartMediaCards (SMC), Secure Digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.
[0072] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the electrical characteristic modeling method for a three-dimensional stacked structure module.
[0073] If the modules / units integrated in the mobile terminal are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
[0074] Based on this understanding, all or part of the processes in the above method can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of the above-described method for modeling the electrical characteristics of the three-dimensional stacked structure module. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate form.
[0075] The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.
[0076] It should be noted that the content contained in the computer-readable medium may be appropriately added to or subtracted from the content as required by the legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium may not include electrical carrier signals and telecommunication signals.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A method for modeling the electrical characteristics of a three-dimensional stacked structure module, characterized in that, The process includes the following: Based on the required module stacking structure, the multilayer substrate layout file is preprocessed to obtain a module layout file containing the stacked structure. Based on the position of the floating interconnect leads of the multilayer substrate, multiple blind and buried vias are set on the side interconnect channels along the length of the module to obtain a virtual model of the three-dimensional stacked structure module. The virtual model of the three-dimensional stacked structure module is optimized to obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module. In this process, multiple blind vias are placed at the positions of the suspended interconnect leads of multiple substrates to simulate the side interconnect channels along the length of the module. The size of the blind vias is consistent with the width of the module interconnect channels, and the depth of the blind vias penetrates different dielectric layers according to the depth of the interconnect channels. The module has a conductive layer on top to simulate the top shell of the module. The irregular shell on the side along the length of the module consists of multiple blind and buried vias and through-holes. The blind vias are located on the top layer of the interconnect channels on the side along the length of the module. The width of the blind vias is the sum of the widths of the interconnect channels, and the depth is from the surface of the top substrate to the surface of the module. The through-holes are located on both sides of the interconnect channels. The width of the through-holes is the width of both sides of the interconnect channels, and the depth is from the bottom plate of the module to the surface of the module.
2. The method for modeling the electrical characteristics of a three-dimensional stacked structure module according to claim 1, characterized in that, The specific process of preprocessing multiple substrate layout files to obtain the layout stack-up structure is as follows: The modules are placed sequentially from bottom to top within the same layout project file according to their internal stacking order, thus obtaining a module layout file containing a stacked structure.
3. The method for modeling the electrical characteristics of a three-dimensional stacked structure module according to claim 1, characterized in that, The width of the blind via is set according to the network attributes of the side interconnection channel along the length of the module. If the network attributes of the module interconnection channels are different, the width of the blind via is the same as the width of the module interconnection channel. If the network attributes of the module interconnection channels are the same, the width of the blind via is the width of the interconnection channel occupied by adjacent modules with the same network attributes.
4. The method for modeling the electrical characteristics of a three-dimensional stacked structure module according to claim 1, characterized in that, A through hole is provided on the side of the module from the bottom to the top of the module along the width direction. The width of the through hole is the dimension of the module width direction, and the depth is from the bottom surface of the module to the surface of the module.
5. The method for modeling the electrical characteristics of a three-dimensional stacked structure module according to claim 1, characterized in that, The three-dimensional interconnect signals of the substrate are led out through floating interconnect leads. The floating interconnect leads are ground according to the module body size, that is, part of the structure of the floating interconnect leads is left in the module and part of the structure is ground away. The blind and buried vias are set according to the outer size of the module and the grinding position of the floating interconnect leads on the substrate. The specific number, position, width and depth of the blind and buried vias are designed according to the direction of the interconnect channel in the final three-dimensional interconnect structure simulation model.
6. A system for modeling the electrical characteristics of a three-dimensional stacked structure module, characterized in that, A method for modeling the electrical characteristics of a three-dimensional stacked structure module as described in any one of claims 1-5, comprising: The layout design software processing module is used to preprocess the multilayer substrate layout file according to the required module stacking structure to obtain the module layout file containing the stacking structure, and according to the position of the floating interconnect leads of the multilayer substrate, set multiple blind and buried vias on the side interconnect channels in the length direction of the module to obtain a virtual model of the three-dimensional stacked structure module. The simulation model processing module is used to optimize the virtual model of the three-dimensional stacked structure module, obtain the top shell of the module, the side shell in the width direction of the module, and the irregular side shell in the length direction of the module. After connecting them, a three-dimensional interconnect structure simulation model is obtained. Then, an electrical conductivity layer is combined with the multilayer substrate in the three-dimensional interconnect structure simulation model to complete the electrical characteristic modeling of the three-dimensional stacked structure module.
7. A mobile terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the electrical characteristic modeling method for a three-dimensional stacked structure module as described in any one of claims 1 to 5.
8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the electrical characteristic modeling method for a three-dimensional stacked structure module as described in any one of claims 1-5.