Method, device, equipment, medium and product for checking input pending error

Abstract

The present disclosure provides a check method, device and equipment for input dangling error, medium and product, relates to the technical field of computers, in particular to the technical field of chips, artificial intelligence, electronic design automation, semiconductor device manufacturing and integrated circuit design. The specific implementation scheme is: determining a target module in a target chip that is verified to have an input dangling error; if the target module is a first type of module, determining a superior driving module that drives the input end of the target module in the target chip; wherein the first type of module is a chip module with complete layout data; determining the authenticity of the input dangling error according to the module type of the superior driving module; wherein the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data. The present disclosure improves the checking efficiency and accuracy of input dangling errors in the chip physical verification scenario.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of chips, artificial intelligence, electronic design automation, semiconductor device manufacturing and integrated circuit design, and especially to a method, apparatus, device, medium and product for verifying input floating errors. Background Technology

[0002] Floating input errors are a typical problem in chip physical verification, referring to the lack of a valid signal drive at the input terminal of a module in the chip. If such errors are not corrected in time, they may lead to malfunctions in logic functions, abnormal power consumption, or even chip failure. Therefore, accurately verifying floating input errors is a critical step in ensuring the quality of chip design.

[0003] As chip scale increases and integration levels rise, the number of intellectual property cores required for chip design also increases. Since these intellectual property cores are core secrets of each company, suppliers often only provide partial layout data to protect their intellectual property. This leads to design rule checking tools generating numerous false alarms due to the inability to see the complete layout data within the intellectual property cores.

[0004] In existing technologies, input dangling errors are usually checked manually. Summary of the Invention

[0005] This disclosure provides a method, apparatus, device, medium, and product for verifying input dangling errors to improve the efficiency and accuracy of input dangling error verification.

[0006] According to one aspect of this disclosure, a method for validating input dangling errors is provided, comprising:

[0007] Identify the target module in the target chip that has been verified to have an input floating error;

[0008] If the target module is a first type of module, then the upper-level driver module that drives the input terminal of the target module in the target chip is determined; wherein, the first type of module is a chip module with complete layout data;

[0009] The authenticity of the input floating error is determined based on the module type of the upper-level driving module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data.

[0010] According to another aspect of this disclosure, an input dangling error verification device is provided, comprising:

[0011] The target module determination module is used to determine the target modules in the target chip that have been verified to have input floating errors.

[0012] The upper-level driver module determination module is used to determine the upper-level driver module that drives the input terminal of the target module in the target chip if the target module is a first type of module; wherein, the first type of module is a chip module with complete layout data;

[0013] The authenticity verification module is used to determine the authenticity of the input floating error based on the module type of the upper-level driving module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data.

[0014] According to another aspect of this disclosure, an electronic device is provided, comprising:

[0015] At least one processor; and

[0016] A memory that is communicatively connected to at least one processor; wherein,

[0017] The memory stores instructions that can be executed by at least one processor to enable the at least one processor to perform any of the methods of this disclosure.

[0018] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform any of the methods of this disclosure.

[0019] According to another aspect of this disclosure, a computer program product is provided, including a computer program and a method for the computer program to be executed by a processor according to any of the methods disclosed herein.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0021] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0022] Figure 1 This is a flowchart of a method for verifying input dangling errors according to an embodiment of the present disclosure;

[0023] Figure 2 This is a flowchart of another method for verifying input dangling errors provided according to an embodiment of this disclosure;

[0024] Figure 3 This is a schematic diagram of the structure of an input dangling error verification device provided according to an embodiment of the present disclosure;

[0025] Figure 4This is a block diagram of an electronic device used to implement the input dangling error verification method of the embodiments of this disclosure. Detailed Implementation

[0026] As chip scale continues to expand and integration levels increase, the number of intellectual property cores required for integration is also growing. For example, large-scale high-performance AI chips integrate as many as a dozen to twenty intellectual property cores, resulting in tens of thousands of false input errors caused by missing layout data for these cores. Especially during the project approval phase, which requires multiple rounds of iterative verification, the traditional method of manual, one-by-one checking is extremely labor-intensive, time-consuming, risky, and prone to overlooking genuine errors.

[0027] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0028] Figure 1 This is a flowchart illustrating a method for verifying input floating errors according to an embodiment of this disclosure. This embodiment is applicable to chip physical verification scenarios where false positives / false negatives are verified for input floating errors. The method can be executed by an input floating error verification device, which can be implemented in hardware and / or software and can be configured in an electronic device. (Reference) Figure 1 The method specifically includes the following:

[0029] S101. Identify the target module in the target chip that has been verified to have an input floating error.

[0030] S102. If the target module is a first type of module, then determine the upper-level driver module that drives the input terminal of the target module in the target chip; wherein, the first type of module is a chip module with complete layout data.

[0031] S103. Determine the authenticity of the input floating error based on the module type of the upper-level driver module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is the chip module with incomplete layout data.

[0032] In S101, the target chip refers to the entire integrated circuit chip that is being physically verified. In the physical verification process, the target chip is the object to be inspected; it contains multiple chip modules that together constitute the complete chip functionality. The layout data of the target chip is the input to the design rule checking tool, used to check for any design rule violations.

[0033] Floating input errors, also known as input faults, refer to a specific type of error reported by design rule checking tools during physical verification. Essentially, a floating input error occurs when the input terminal of a module in the chip logically lacks a valid drive signal; that is, the input terminal appears "floating" at the layout level, not connected to any signal source. In physical verification, floating input errors can occur in two ways: one is a genuine design flaw, meaning the input terminal is indeed not driven; the other is a false alarm caused by incomplete layout data, meaning the input terminal actually has a drive, but due to incomplete layout data, the design rule checking tool is unaware of the module's internal connections and mistakenly identifies it as floating.

[0034] A target module refers to one or more specific chip modules in a target chip that are marked by the design rule checking tool as having input dangling errors. Target modules can be any type of module in the chip, including modules with complete layout data (Type 1 modules) or modules with incomplete layout data (Type 2 modules).

[0035] In one implementation of S101, a verification result file generated by the target chip during the physical verification phase is obtained. This verification result file contains error markers corresponding to all input dangling errors reported by the design rule checking tool, and each error marker records the specific location coordinates of the error in the chip layout.

[0036] By parsing the verification result file, the position coordinates of each error marker are extracted, and the specific chip module to which each error marker is located can be determined by reverse searching in the layout data based on these position coordinates. This module is then used as the target module to be verified as having an input floating error.

[0037] In another implementation of S101, firstly, an input floating error report output by the design rule checking tool is obtained. This report contains the logic node information corresponding to each input floating error. During operation, the design rule checking tool establishes a mapping relationship between the chip layout and the logic netlist. For each input floating error, the design rule checking tool records the identifier of the logic node associated with that error.

[0038] Subsequently, by parsing the input dangling error report, the logical node identifier corresponding to each input dangling error is extracted.

[0039] Finally, the target chip's logic netlist file is loaded. This netlist file fully records the module identifiers, port connections, and network connection information of all chip modules. Based on the extracted logic node identifiers, the chip module connected to the logic node identifier is queried in the logic netlist file, and that module is selected as the target module to be verified for input dangling errors.

[0040] In S102, the first type of module refers to a chip module with complete layout data. During physical verification, all layout layers of this type of module, such as transistor layers, metal interconnect layers, and via layers, are fully visible, allowing the design rule checking tool to comprehensively examine its internal connections. Because the layout data of the first type of module is complete, the design rule checking tool can accurately determine whether its input ports actually contain drive signals.

[0041] The input terminal of a target module refers to the physical port on the target module used to receive external signals. In chip design, each module is connected to the upper-level driver module through its input terminal to receive signal inputs from the upper-level driver module. The connection status of the input terminal is an important object of design rule checking in physical verification: if the input terminal is logically lacking a valid drive signal, it will be reported as an input floating error.

[0042] A higher-level driver module refers to a chip module that provides drive signals to the input terminal of a target module in a logical connection relationship. In chip design, signal transmission between modules is directional, and the output terminal of the higher-level driver module is connected to the input terminal of the lower-level module through a wire. In this embodiment of the present disclosure, when the target module is a first-type module, it is necessary to trace the higher-level driver module connected to its input terminal and determine whether the floating input error of the target module is a genuine design defect or a false error caused by incomplete layout data of the higher-level driver module, based on the layout data integrity type of the higher-level driver module.

[0043] Layout data refers to graphical data describing the physical implementation of a chip. It contains information about all the physical layers required to construct the chip, such as active area layers, polysilicon layers, metal interconnect layers, and via layers. Each layer consists of several geometric shapes, the shape, size, and position of which collectively determine the layout of transistors on the chip, the routing of interconnects, and the physical connections between modules. Layout data is the basis for chip manufacturing in wafer fabs and is also the object of design rule checking tools.

[0044] Complete layout data means that the chip module's layout data contains all necessary layer information, with no internal layers omitted or left blank. For modules with complete layout data, design rule checking tools can identify their internal connections, enabling comprehensive design rule checks on the module and its surrounding connections. In this embodiment, input dangling errors in the first type of module with complete layout data may be genuine design defects; however, for the second type of module with incomplete layout data, due to the missing internal layers, the design rule checking tool cannot see the internal connections. Therefore, input dangling errors in this module itself, or those caused by it acting as a higher-level driving module, are often false errors.

[0045] In one implementation of S102, a pre-established list of module types is queried, and the target module is identified as belonging to either a first-type module or a second-type module based on its module name or module identifier. If the identification result indicates that the target module is a first-type module, the input dangling error flag generated by the design rule checking tool is imported into the place-and-route tool. The place-and-route tool internally stores the complete logical connection relationship of the target chip, which records the signal driving and driven relationships between each chip module in the form of a netlist.

[0046] By calling the connection query function provided by the placement and routing tool, specifying the module name of the target module and its input pin identifier, the tool traverses and searches according to the internal logical connection relationship, and finally outputs the module name of the parent module driving the input, and then determines the parent driving module based on the module name.

[0047] In another implementation of S102, a pre-established list of module types is queried, and the target module is identified as belonging to the first type of module or the second type of module based on the module name or module identifier of the target module.

[0048] If the identification result indicates that the target module is a first-class module, then the logic netlist file generated during the placement and routing stage of the target chip is obtained. By parsing the logic netlist file, a directed graph model is established with modules as nodes and signal connections as edges.

[0049] Subsequently, starting with the target module's module name and input pin identifier, a reverse search algorithm is executed in the directed graph model to find all possible source nodes that can provide signals to the input terminal. Then, based on the source nodes found, the corresponding module is determined as the upper-level driver module.

[0050] In S103, the module type refers to the category of the chip module based on the completeness of its layout data. In this embodiment, the module type specifically includes a first type of module and a second type of module: the first type of module is a chip module with complete layout data, in which all layer information is fully visible; the second type of module is a chip module with incomplete layout data, in which the core layers are omitted or empty, and only necessary interface information such as boundaries and pins is retained.

[0051] The authenticity of input floating errors refers to whether the error is a genuine design flaw or a false alarm caused by incomplete layout data. A "genuine error" means that the target module's input actually lacks a valid drive signal, constituting a design flaw that needs fixing. A "false error" means that the target module's input actually has a drive signal, but due to incomplete layout data from the upstream drive module, the design rule checking tool mistakenly identifies it as floating; this is a false error that does not require processing.

[0052] The second type of module refers to chip modules with incomplete layout data. During the physical verification phase, the core layers of these modules are omitted or left blank, with only interface information such as boundary layers and pin layers retained.

[0053] Incomplete layout data refers to the missing essential layer information in the chip module's layout data. Specifically, the module may only retain external interface information such as boundary layers and pin layers, while internal core layers, such as active area layers, polysilicon layers, and internal metal interconnect layers, may be intentionally omitted or left blank. This data format is typically a technical measure taken by module suppliers to protect their intellectual property.

[0054] In one embodiment of S103, the module type of the upper-level driving module is determined. If the module type of the upper-level driving module is a first-class module, that is, the upper-level driving module is a chip module with complete layout data, it indicates that the upper-level driving module itself has complete internal connection relationship, but its output terminal fails to provide a valid driving signal to the input terminal of the target module. Therefore, the floating input error of the target module is determined to be a real design defect, that is, a real error.

[0055] If the upper-level driver module is a second-type module, that is, a chip module with incomplete layout data, it means that the input terminal of the target module is actually connected to a black box module whose internal structure is not visible. The design rule checking tool falsely reports a floating input because it cannot see the internal connection relationship of the second-type module. Therefore, the error is determined to be a false error.

[0056] This disclosure embodiment identifies a target module in a target chip that has been verified to have an input floating error; if the target module is a first type of module, then it identifies an upper-level driving module in the target chip that drives the input terminal of the target module; wherein, the first type of module is a chip module with complete layout data; the authenticity of the input floating error is determined according to the module type of the upper-level driving module; wherein, the module type includes the first type of module and a second type of module, and the second type of module is a chip module with incomplete layout data. The beneficial effects are:

[0057] Firstly, by automating the identification of target modules and their superior driving modules, and by determining the authenticity of input floating errors based on the module type of the superior driving module, the tedious process of manually analyzing input floating errors one by one is avoided, the verification time is shortened, the verification efficiency is improved, and the need for multiple rounds of rapid iterative verification in the later stages of chip design can be effectively supported.

[0058] Secondly, by judging the authenticity of the layout data based on the integrity of the module, false errors caused by incomplete layout data can be accurately identified, avoiding the omission of real design defects due to fatigue or negligence in manual methods. This improves the accuracy of input floating error verification, thereby reducing the risk of chip tape-out and ensuring chip design quality.

[0059] Figure 2 This is a flowchart of another method for verifying input dangling errors according to an embodiment of this disclosure. It can be used to further optimize and extend the above technical solution, and can be combined with the various optional implementation methods described above. (Reference) Figure 2 The method specifically includes the following:

[0060] S201. Obtain the physical verification result corresponding to the target chip, and determine the error mark position corresponding to the input floating error in the target chip based on the physical verification result; determine the target module in the target chip that has been verified to have an input floating error based on the error mark position.

[0061] S202. If the target module is a first-type module, then execute S204; if the target module is a second-type module, then execute S203.

[0062] S203. Determine that the input dangling error is a pseudo error.

[0063] S204. Determine the logical connection relationship between each chip module in the target chip; based on the logical connection relationship, determine the signal source driving the input terminal of the target module, and take the chip module corresponding to the signal source as the upper-level driving module.

[0064] S205. If the module type of the upper-level driver module is a first-class module, then the input floating error is determined to be a true error; if the module type of the upper-level driver module is a second-class module, then the input floating error is determined to be a false error.

[0065] In S201, the physical verification result refers to the output data obtained after physically verifying the target chip. Specifically, after verifying the layout data of the target chip using the design rule checking tool, the tool generates a physical verification result. The physical verification result records all detected design rule violations, including but not limited to the type of violation (such as input dangling errors, spacing violations, width violations, etc.), the location information of the violation, and the severity of the violation.

[0066] Error marker location refers to the specific location information recorded in the physical verification results for each input dangling error. During the operation of the design rule checking tool, when an input dangling error is detected, the tool generates a corresponding error marker in the chip layout. This marker typically graphically indicates the area where the error occurred, along with the error marker location. The error marker location can be a point coordinate, a rectangular area, or a polygonal range, indicating the specific location of the target module in the chip layout.

[0067] In one implementation of S201, a physical verification result file is obtained, and the error marker position corresponding to each input dangling error is parsed. The layout data of the target chip is loaded, and the error marker positions are spatially compared with the boundary coordinates of each module. Modules that overlap or contain the error marker positions are identified, and these modules are determined as the target modules verified to have input dangling errors.

[0068] In another implementation of S201, a physical verification result file is obtained, and the error marker position corresponding to each input dangling error is parsed. The layout database of the target chip is loaded, and a reverse query is performed using the spatial query interface provided by the database, with the error marker position as the input condition. The module associated with the error marker position is retrieved, and the module is identified as the target module verified to have an input dangling error.

[0069] By obtaining the physical verification results corresponding to the target chip, and determining the error marker location corresponding to the input floating error in the target chip based on the physical verification results; and by determining the target module in the target chip that has been verified to have an input floating error based on the error marker location, the beneficial effects are:

[0070] Firstly, by automatically parsing the physical verification result file, the error marker position corresponding to each input dangling error is directly extracted, and the corresponding module is automatically matched based on the error marker position. This transforms the process that originally required manual searching one by one into automatic machine execution, shortening the error location time.

[0071] Secondly, by automatically matching the corresponding module based on the error mark location, it ensures that each input dangling error can be accurately located to its true module, avoiding visual errors or misjudgments that may occur during manual searching, and providing a basic guarantee for the accuracy of the entire verification process.

[0072] In S203, the input floating error is a false error, meaning that the input floating error is not a real design defect, but a false alarm caused by incomplete layout data of the second type of module.

[0073] Specifically, in the physical verification phase, the second type of module only provides interface information such as boundaries and pins, while its internal core layers are intentionally omitted or left blank. When the target module itself belongs to the second type, the design rule checking tool, unable to see the complete internal connections of the module, will misjudge the module's input as "floating." However, in reality, the module may have been driven normally at the logic design level; the design rule checking tool simply cannot verify this fact due to missing data. Therefore, this type of error is a false alarm and requires no correction.

[0074] By determining that an input dangling error is a pseudo-error if the target module is a second type of module, the beneficial effect is that:

[0075] Firstly, by introducing a pre-judgment mechanism: once the target module is identified as a second-type module, the error is immediately determined to be a pseudo-error, eliminating the need for subsequent tracing of the parent driver module and type determination. This pre-filtering mechanism directly skips complex analysis steps for a large number of target modules whose layout data is incomplete, reducing unnecessary computational overhead and processing time.

[0076] Secondly, addressing the root cause of the problem directly, the invisibility of the second type of module itself determines the unverifiable nature of its related errors, thus directly classifying them as pseudo-errors. This judgment logic avoids invalid analysis based on missing layout data, ensuring the rationality and efficiency of the processing.

[0077] In S204, logical connection relationships refer to the logical path description of signal transmission between modules in the chip design, reflecting the original intent of the circuit design. Specifically, logical connection relationships exist in the form of a netlist, recording the module name, pin definitions, and signal connection topology between each chip module. For example, in the logical connection relationships, the output pin of module A is defined as connected to the input pin of module B, which is essentially a signal flow convention at the design level.

[0078] A signal source is the starting point in a logical connection relationship that provides drive signals to the input terminal of a target module. A signal source can be the output terminal of a chip module or an input port of a chip. In circuit design, each signal has a definite initiation point and a receiving point; the signal source is the initiation point of the signal, driving the signal along the connection path to the subsequent module.

[0079] The chip module corresponding to the signal source refers to the instance of the chip module where the signal source is located. Once the signal source is located, it is necessary to further determine which specific chip module it belongs to. For example, if the signal source is an output pin of module C, then the "chip module corresponding to the signal source" is module C itself.

[0080] In one implementation of S204, the input floating error flags generated by the design rule checking tool are imported into the place-and-route tool. The place-and-route tool internally stores the complete logical connection relationship of the target chip, which is recorded in the form of a netlist of signal driving and driven relationships between modules.

[0081] By invoking the connection lookup function provided by the placement and routing tool, starting from the input terminal of the target module and tracing backwards, the tool will automatically find and return the signal source driving that input terminal, i.e., the output terminal of an upstream module or the input port of a chip. Based on the lookup results, the chip module to which the signal source belongs is determined as the superior driver module.

[0082] By determining the logical connection relationships between the chip modules in the target chip, and based on these relationships, identifying the signal sources driving the input terminals of the target modules, and using the chip modules corresponding to these signal sources as the higher-level driving modules, the following advantages are achieved:

[0083] Firstly, by obtaining the complete logical connection relationship of the chip in advance, the signal source is automatically searched in reverse from the input end of the target module, transforming manual tracking into automated execution and improving processing efficiency.

[0084] Secondly, tracing is based on clear logical connections to ensure the consistency and accuracy of each tracing result. Regardless of who executes it or how many times it is executed, the input of the same target module can always be traced back to the same signal source, avoiding identification errors caused by human factors.

[0085] In S205, a floating input error is a true error, indicating that the target module's input lacks a valid drive signal at the logic design level, representing a design flaw that needs to be corrected. Specifically, when the upper-level driver module is identified as a Class I module, it means that the upper-level driver module itself has complete layout data, but its output fails to provide a signal to the target module's input, indicating a connection deficiency in the logic design or physical implementation. For example, the connection between the upper-level driver module's output and the target module's input may have been omitted in the design, or the upper-level driver module itself may not be correctly configured as an output.

[0086] A floating input error is a false error. It means that the target module's input actually has a valid drive signal, but the design rule checking tool misjudges it as floating due to incomplete layout data of the upper-level driver module. This is a false error that does not need to be processed. Specifically, when the upper-level driver module is identified as a second-type module, the core layer inside this module is omitted or set to empty, and only interface information such as boundaries and pins is retained. Because the design rule checking tool cannot see the internal connection relationship of the second-type module, it mistakenly believes that the target module's input is not connected to any signal source, thus reporting a floating input error. However, in reality, in the logic design and physical implementation, the target module's input may be driven by the upper-level driver module; it's just that the layout data prevents the design rule checking tool from checking it.

[0087] In one implementation of S205, the module type information of the upper-level driver module is obtained. Specifically, it can be determined whether it belongs to the first type module or the second type module by querying a preset module type list or parsing the integrity of the layout data of the upper-level driver module.

[0088] If the upper-level driver module is identified as a first-class module, i.e. a chip module with complete layout data, then the input floating error of the target module is determined to be a true error.

[0089] If the upper-level driver module is identified as a second-type module, i.e. a chip module with incomplete layout data, then the input floating error of the target module is determined to be a pseudo-error.

[0090] By determining that a floating input error is a true error if the parent driver module is of type 1, and a floating input error is a false error if the parent driver module is of type 2, the beneficial effect is:

[0091] Firstly, by establishing clear judgment rules: if the superior driving module is a first-type module, it is judged as a true error; if it is a second-type module, it is judged as a false error. This transforms the judgment of true and false errors from a reliance on subjective experience to an objective rule-driven approach. This module-type-based judgment logic avoids interference from human factors, ensures that each error is handled according to a unified standard, and effectively reduces the risk of misjudgment.

[0092] Secondly, it transforms manual analysis into automated batch processing, eliminating the need for individual manual intervention and improving processing efficiency.

[0093] Optionally, after determining the authenticity of the dangling input error, the following steps are also included:

[0094] A1. If the input dangling error is determined to be a true error, then determine the module attribute information corresponding to the target module.

[0095] Module attribute information refers to a set of data describing the characteristics and state of the target module, used to provide detailed background information about the module after a true error is identified. Module attribute information includes at least one of the following: module name, module location, and module logical connection information.

[0096] The module name is a unique identifier for the target module in the chip design, used to distinguish and identify different module instances. Including the module name in error alarm messages allows engineers to directly identify which specific module experienced the true error, eliminating the need for further investigation to determine the module's identity.

[0097] Module location refers to the physical coordinates or region information of the target module within the chip layout, indicating its specific placement on the chip. Including the module location in error alarm information allows engineers to quickly jump to the error area directly in the layout editing tool, visually view the physical environment around the module, and facilitate analysis of the error cause and repair.

[0098] Module logical connection information describes the connection relationships between the target module and other modules at the logical design level. This includes, but is not limited to, which upper-level driver modules are connected to the module's input ports, which lower-level modules are driven by its output ports, and the network names associated with each port. Including module logical connection information in error alarm messages helps engineers understand the target module's role and context in the logical design, determine the signal paths that a true error might affect, and thus formulate accurate repair solutions.

[0099] B1. Generate error alarm information corresponding to input dangling errors based on module attribute information.

[0100] Error alarm messages refer to comprehensive reports generated for input dangling errors that are determined to be true errors. These reports convey key information about the error to engineers and provide troubleshooting guidance. Error alarm messages typically integrate multiple module attribute information, such as module name, module location, and module logical connection information, and are presented in a structured or easy-to-read format.

[0101] In one implementation, when the input dangling error of the target module is determined to be a true error based on the module type of the upper-level driver module, the module attribute information of the target module is extracted from the design database of the target chip. Specifically, this includes the module name, module location, and module logical connection information. The module name can be obtained by querying the design instantiation list, the module location can be read from the layout database using the module's bounding box coordinates, and the module logical connection information is obtained by parsing the logic netlist.

[0102] The module attribute information obtained above is integrated and formatted to generate structured error alarm information. In addition to including a unique identifier of the true error, the time of occurrence, a complete description of the target module, and suggested repair guidelines, the error alarm information is output in text form to an error report file or displayed directly in the verification tool interface, allowing engineers to quickly locate and repair the true error.

[0103] If the input dangling error is determined to be a true error, then the module attribute information corresponding to the target module is determined; and an error alarm message corresponding to the input dangling error is generated based on the module attribute information. The beneficial effects are:

[0104] Firstly, while identifying genuine errors, the system automatically extracts the module name, module location, and module logical connection information, and aggregates these scattered attribute information into a complete error alarm message. Engineers no longer need to search manually and can directly carry out repair work based on the alarm message, which greatly shortens the time cycle from error identification to error repair.

[0105] Secondly, the generated error alarm information not only includes the location of the error but also the logical connection relationship of the module, enabling engineers to intuitively understand the input source and output destination of the module and determine the signal path and functional modules that a true error may affect. This complete error context helps engineers make repair decisions quickly, select the optimal repair solution, and avoid incorrect or missed repairs due to incomplete information.

[0106] Optionally, after determining the authenticity of the dangling input error, the following steps are also included:

[0107] If the input floating error is determined to be a false error, then the input floating error is filtered out from the physical verification results corresponding to the target chip.

[0108] Filtering out dangling input errors refers to the operation of removing or ignoring dangling input error markers that have been determined to be false errors in the physical verification results. Specifically, once an input dangling error is determined to be a false error by the scheme of this embodiment, the error is no longer considered a design defect that needs to be fixed, and therefore needs to be filtered out from the final physical verification results to avoid interfering with engineers.

[0109] In one implementation, when the input dangling error of the target module is determined to be a pseudo-error based on the module type of the upper-level driver module, the error flag corresponding to the pseudo-error is obtained. This error flag is then matched against the physical verification result file of the target chip, locating the record entry corresponding to the pseudo-error within the verification result file. Subsequently, a filtering operation is performed on this record entry. Specifically, this can be done by deleting the error record from the verification result file or marking the error record as "ignored" and setting it not to be displayed in the final report. After the filtering operation is completed, the physical verification result file is updated, generating a filtered verification report containing only true errors.

[0110] If an input floating error is determined to be a spurious error, then filtering out the input floating error from the physical verification results corresponding to the target chip has the following advantages:

[0111] Firstly, after identifying false errors, they can be directly filtered out from the physical verification results. Engineers no longer need to deal with a massive number of false errors and can directly obtain a verification report containing only true errors, allowing them to focus their energy entirely on the design flaws that need to be fixed.

[0112] Secondly, by accurately identifying and filtering out false errors, the possibility of ineffective repairs targeting false errors is fundamentally eliminated, ensuring that every repair effort targets real design flaws and maximizes the efficiency of project resource utilization.

[0113] Optionally, determine the logical connection relationships between the chip modules in the target chip, including:

[0114] Obtain the netlist file saved in the placement and routing tool for the target chip; determine the logical connection relationships between the chip modules in the target chip based on the netlist file.

[0115] Placement and routing tools refer to electronic design automation software used for chip physical design, responsible for placing logic modules on the layout and completing the physical connections between modules. In this embodiment, the placement and routing tool is the source of the netlist file, as it simultaneously stores the chip's logic design information and physical implementation information.

[0116] A netlist file is a design document that records the logical connection relationships of chips in text format. It includes module names, pin definitions, and signal connection topologies between modules. The netlist file is the direct basis for determining logical connection relationships. Even if the layout data of some modules is incomplete, the netlist still records the connection relationships between that module and other modules completely.

[0117] In one implementation, the netlist file saved by the placement and routing tool used by the target chip is read. Based on the network connection relationships described in the netlist file, the module connected to each signal network and its port correspondence are established, thereby determining which output of the superior module drives the input of each module, and which input of the subordinate modules is driven by the output of each module. Through the above parsing process, the complete logical connection relationship between the chip modules in the target chip can be obtained.

[0118] By obtaining the netlist file saved in the placement and routing tool for the target chip, and determining the logical connection relationships between the chip modules in the target chip based on the netlist file, the beneficial effects are:

[0119] By directly reading the netlist file saved in the placement and routing tool and determining the logical connection relationship between chip modules based on the netlist file, the extraction and construction of the entire chip's logical connection relationship can be completed quickly, providing efficient data support for subsequent tracing of the upper-level driver module.

[0120] Optionally, the first type of module includes the basic unit in the target chip; the second type of module includes the intellectual property core in the target chip.

[0121] In chip design, a basic cell refers to the smallest pre-designed circuit unit that implements the most basic logic functions; it is also commonly referred to as a standard cell. Basic cells include, but are not limited to, basic logic gates such as AND gates, OR gates, NOT gates, flip-flops, and buffers. These cells are pre-developed and stored by chip design manufacturers or foundries, and have standardized dimensions, heights, and interface specifications. The layout data of basic cells is complete, containing all necessary layer information, and design rule checking tools can perform a complete check of their internal connections.

[0122] Intellectual property cores refer to complex, reusable circuit modules with independent functions in chip design. These are typically developed by specialized companies and licensed as intellectual property products. To protect their core technologies, suppliers of intellectual property cores often only provide partial layout data, retaining only interface information such as boundaries and pins, while hiding the internal core layers.

[0123] By setting the first type of module to include the basic units in the target chip and the second type of module to include the intellectual property core in the target chip, the beneficial effects are:

[0124] Basic cells and intellectual property cores are common building blocks in all integrated circuit designs, unrestricted by specific chip types, process nodes, or design styles. Defining the first type of module and the second type of module as these two general-purpose modules allows the solutions in this disclosure to be applied to any chip design project using standard cell libraries and intellectual property cores, exhibiting good versatility and portability without requiring customized adjustments for different designs.

[0125] Figure 3 This is a schematic diagram of a device for verifying input floating errors according to an embodiment of the present disclosure. It is applicable to chip physical verification scenarios for verifying false positives of input floating errors. The device in this embodiment can be implemented in software and / or hardware and can be integrated into any electronic device with computing capabilities.

[0126] like Figure 3 As shown, the input dangling error verification device 30 disclosed in this embodiment may include a target module determination module 31, a higher-level driving module determination module 32, and a authenticity verification module 33, wherein:

[0127] Target module determination module 31 is used to determine the target module in the target chip that has been verified to have an input floating error;

[0128] The upper-level driver module determination module 32 is used to determine the upper-level driver module that drives the input terminal of the target module in the target chip if the target module is a first type of module; wherein, the first type of module is a chip module with complete layout data;

[0129] The authenticity verification module 33 is used to determine the authenticity of the input floating error based on the module type of the upper-level driving module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data.

[0130] Optionally, the upper-level driver module determining module 32 is specifically used for:

[0131] Determine the logical connection relationships between the chip modules in the target chip;

[0132] Based on the logical connection relationship, the signal source driving the input terminal of the target module is determined, and the chip module corresponding to the signal source is used as the upper-level driving module.

[0133] Optionally, the authenticity verification module 33 is specifically used for:

[0134] If the module type of the upper-level driver module is the first type of module, then the input dangling error is determined to be a true error;

[0135] If the module type of the upper-level driver module is the second type of module, then the input dangling error is determined to be a pseudo error.

[0136] Optionally, the device further includes a pseudo-error identification module, specifically used for:

[0137] If the target module is the second type of module, then the input dangling error is determined to be a pseudo-error.

[0138] Optionally, the target module determining module 31 is specifically used for:

[0139] Obtain the physical verification result corresponding to the target chip, and determine the error marker position corresponding to the input dangling error in the target chip based on the physical verification result;

[0140] The target module in the target chip that is verified to have the input floating error is determined based on the error mark location.

[0141] Optionally, the device further includes an error alarm information generation module, specifically used for:

[0142] If the input dangling error is determined to be a true error, then the module attribute information corresponding to the target module is determined; wherein, the module attribute information includes at least one of module name, module location, and module logical connection information;

[0143] Based on the module attribute information, generate error alarm information corresponding to the input dangling error.

[0144] Optionally, the device further includes an error filtering module, specifically used for:

[0145] If the input dangling error is determined to be a false error, then the input dangling error is filtered out from the physical verification results corresponding to the target chip.

[0146] Optionally, the upper-level driver module determining module 32 is further used for:

[0147] Obtain the netlist file of the target chip saved in the placement and routing tool;

[0148] The logical connection relationships between the chip modules in the target chip are determined based on the netlist file.

[0149] Optionally, the first type of module includes the basic unit in the target chip; the second type of module includes the intellectual property core in the target chip.

[0150] The input dangling error verification device 30 disclosed in this embodiment can execute the input dangling error verification method disclosed in this embodiment, and has the corresponding functional modules and beneficial effects of the method execution. Content not described in detail in this embodiment can be referred to the description in the method embodiments of this disclosure.

[0151] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0152] Figure 4A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0153] like Figure 4 As shown, device 400 includes a computing unit 401, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 402 or a computer program loaded from storage unit 408 into random access memory (RAM) 403. RAM 403 may also store various programs and data required for the operation of device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via bus 404. Input / output (I / O) interface 405 is also connected to bus 404.

[0154] Multiple components in device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of monitors, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0155] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as the input dangling error verification method. For example, in some embodiments, the input dangling error verification method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the input dangling error verification method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the input dangling error verification method by any other suitable means (e.g., by means of firmware).

[0156] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0157] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0158] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0159] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0160] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0161] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and weak business scalability inherent in traditional physical hosting and VPS services. Servers can also be servers for distributed systems or servers integrated with blockchain technology.

[0162] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0163] Cloud computing refers to a technology system that enables access to a shared pool of physical or virtual resources via a network. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on demand and in a self-service manner. Cloud computing technology can provide efficient and powerful data processing capabilities for applications such as artificial intelligence and blockchain, as well as for model training.

[0164] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution provided in this disclosure can be achieved, and this is not limited herein.

[0165] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for verifying input dangling errors, comprising: Identify the target module in the target chip that has been verified to have an input floating error; If the target module is a first type of module, then the upper-level driver module that drives the input terminal of the target module in the target chip is determined; wherein, the first type of module is a chip module with complete layout data; The authenticity of the input floating error is determined based on the module type of the upper-level driving module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data.

2. The method according to claim 1, wherein, The step of determining the upper-level driver module that drives the input terminal of the target module in the target chip includes: Determine the logical connection relationships between the chip modules in the target chip; Based on the logical connection relationship, the signal source driving the input terminal of the target module is determined, and the chip module corresponding to the signal source is used as the upper-level driving module.

3. The method according to claim 1, wherein, Determining the authenticity of the input dangling error based on the module type of the upper-level driver module includes: If the module type of the upper-level driver module is the first type of module, then the input dangling error is determined to be a true error; If the module type of the upper-level driver module is the second type of module, then the input dangling error is determined to be a pseudo error.

4. The method according to claim 1, further comprising, after determining the target module in the target chip that has been verified to have an input dangling error: If the target module is the second type of module, then the input dangling error is determined to be a pseudo-error.

5. The method according to claim 1, wherein, The target module in the target chip that has been verified to have an input dangling error includes: Obtain the physical verification result corresponding to the target chip, and determine the error marker position corresponding to the input dangling error in the target chip based on the physical verification result; The target module in the target chip that is verified to have the input floating error is determined based on the error mark location.

6. The method according to claim 1, further comprising, after determining the authenticity of the input dangling error: If the input dangling error is determined to be a true error, then the module attribute information corresponding to the target module is determined; wherein, the module attribute information includes at least one of module name, module location, and module logical connection information; Based on the module attribute information, generate error alarm information corresponding to the input dangling error.

7. The method according to claim 1, further comprising, after determining the authenticity of the input dangling error: If the input dangling error is determined to be a false error, then the input dangling error is filtered out from the physical verification results corresponding to the target chip.

8. The method according to claim 2, wherein, Determining the logical connection relationships between the chip modules in the target chip includes: Obtain the netlist file of the target chip saved in the placement and routing tool; The logical connection relationships between the chip modules in the target chip are determined based on the netlist file.

9. The method according to any one of claims 1-8, wherein, The first type of module includes the basic unit in the target chip; the second type of module includes the intellectual property core in the target chip.

10. A device for verifying input dangling errors, comprising: The target module determination module is used to determine the target modules in the target chip that have been verified to have input floating errors. The upper-level driver module determination module is used to determine the upper-level driver module that drives the input terminal of the target module in the target chip if the target module is a first type of module; wherein, the first type of module is a chip module with complete layout data; The authenticity verification module is used to determine the authenticity of the input floating error based on the module type of the upper-level driving module; wherein, the module type includes the first type of module and the second type of module, and the second type of module is a chip module with incomplete layout data.

11. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-9.

13. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the method according to any one of claims 1-9.

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