A system-level software simulation and verification method for a UART interface of an SoC chip

Abstract

The application discloses a kind of SoC chip UART interface system level software simulation verification methods, it is related to chip design verification technical field, the method includes: constructing UART peripheral virtual behavior model;The sending port of the UART interface to be verified in the SoC chip to be tested is connected with the receiving port of UART peripheral virtual behavior model, the receiving port of the UART interface to be verified is connected with the sending port of UART peripheral virtual behavior model, to constitute a closed loop simulation verification environment;Based on closed loop simulation verification environment, by running test program on the SoC chip to be tested, drive the UART interface to be verified and UART peripheral virtual behavior model carry out data interaction, based on data interaction result, the system level function of the UART interface to be verified is verified.The application can realize high multiplexing and high simulation verification efficiency simultaneously, and simplify UART interface verification environment.

Description

Technical Field

[0001] This invention relates to the field of chip design verification technology, and in particular to a system-level software simulation verification method for the UART interface of a SoC chip. Background Technology

[0002] In the development of SoC (System on Chip) chips, UART (Universal Asynchronous Receiver / Transmitter), as a basic and widely used low-speed serial communication interface, is often used for key functions such as debugging information output and connecting external sensors. Therefore, it is crucial to conduct thorough and efficient simulation verification of the UART interface function before tape-out. Currently, the industry mainly relies on the following two methods for UART interface simulation verification: The first method utilizes multiple UART modules integrated within the SoC chip under test for interconnection verification. For example, the input and output of the first UART module are interconnected with the input and output of the second UART module to form a self-transmitting and self-receiving closed loop, thereby enabling mutual communication to verify basic functional points. However, although this method is simple and easy to implement, its application prerequisite is that the SoC chip must integrate at least two UART modules. It is not applicable to chips that only integrate a single UART module, and has obvious limitations. The second method uses a module-level verification environment built based on UVM (Universal Verification Methodology) and VIP (Verification Intellectual Property). This verification environment typically includes multiple complex components such as stimulus generators, monitors, reference models, and scoring boards, enabling detailed verification of various functionalities within the UART module. However, when applying this method to chip system-level verification, which focuses on interface interaction, data flow control, and interrupt response, especially in bare-metal software environment simulations, the verification environment becomes overly redundant and cumbersome. The complex component hierarchy leads to reduced simulation efficiency, increased environment setup and maintenance costs, and a mismatch between the verification focus and the needs of system-level verification, resulting in wasted verification resources and efficiency bottlenecks.

[0003] Therefore, it is necessary to provide a system-level software simulation verification method for the UART interface of a SoC chip that can simultaneously achieve high reusability and high simulation verification efficiency, and simplify the UART interface verification environment. Summary of the Invention

[0004] To address some or all of the technical problems existing in the prior art, this invention provides a system-level software simulation verification method for SoC chip UART interface, which can simultaneously achieve high reusability and high simulation verification efficiency, and simplify the UART interface verification environment.

[0005] The technical solution of the present invention is as follows: A system-level software simulation and verification method for a SoC chip UART interface is provided, the method comprising: A virtual behavior model for a UART peripheral device is constructed. The virtual behavior model for a UART peripheral device has a transmit port and a receive port. The virtual behavior model for a UART peripheral device is used to simulate the behavior of an external UART device. Connect the transmitting port of the UART interface to be verified in the SoC chip under test to the receiving port of the UART peripheral virtual behavior model, and connect the receiving port of the UART interface to be verified to the transmitting port of the UART peripheral virtual behavior model to form a closed-loop simulation verification environment. Based on the closed-loop simulation verification environment, by running a test program on the SoC chip under test, the UART interface to be verified is driven to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level functions of the UART interface to be verified are verified. The SoC chip under test includes at least one UART interface, and the UART interface in the SoC chip under test reuses the UART peripheral virtual behavior model.

[0006] Furthermore, in some embodiments, the system-level functions of the UART interface to be verified include at least: data transmission and reception functions.

[0007] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is a data transmission and reception function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: Test data is sent from the core of the SoC chip under test to the UART interface to be verified. Test data is sent to the UART peripheral virtual behavior model through the transmit port of the UART interface to be verified. After receiving the data, the UART peripheral virtual behavior model sends the data back to the UART interface to be verified via the sending port of the UART peripheral virtual behavior model. Data is read from the UART interface to be verified through the core of the SoC chip under test; Compare the test data sent by the core of the SoC chip under test with the data read by the core of the SoC chip under test from the UART interface to be verified. If they are consistent, the data transmission and reception function of the UART interface to be verified is determined to be correct.

[0008] Furthermore, in some embodiments, the system-level functions of the UART interface to be verified include at least: interrupt response function.

[0009] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is an interrupt response function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: By controlling the data interaction between the UART peripheral virtual behavior model and the UART interface to be verified, an interrupt triggering condition is constructed to cause the UART interface to be verified to generate an interrupt request. Check the status of the interrupt enable register. If the enable bit corresponding to the interrupt request is valid, the interrupt request is recorded in the interrupt identification register and reported to the core of the SoC chip under test, so that the core of the SoC chip under test executes the preset interrupt service routine to process the interrupt request. Verify whether the interrupt service routine has responded correctly to the interrupt triggering condition; If the response is correct, the interrupt response function of the UART interface to be verified is determined to be correct.

[0010] Furthermore, in some embodiments, the system-level functions of the UART interface to be verified include at least: register read / write functions.

[0011] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is a register read / write function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: If the register is a readable and writable register, the core of the SoC chip under test performs a read operation on the readable and writable register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the readable and writable register through the core of the SoC chip under test; The third value is obtained by performing a read operation on the readable and writable register again through the core of the SoC chip under test; Compare the second value with the third value. If they are equal, then the register read / write function of the UART interface to be verified is determined to be correct.

[0012] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is a register read / write function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: If the register is a read-only register, the core of the SoC chip under test performs a read operation on the read-only register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the read-only register through the core of the SoC chip under test; The read-only register is read again through the core of the SoC chip under test to obtain a third value; Compare the first value with the third value. If they are equal, then the register read / write function of the UART interface to be verified is determined to be correct.

[0013] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is a register read / write function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: If the register is a write-only register, the core of the SoC chip under test performs a read operation on the write-only register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the write-only register through the core of the SoC chip under test; The write-only register is read again through the core of the SoC chip under test to obtain a third value; Compare the first value with the third value to see if they are not equal. If they are, then the register read / write function of the UART interface to be verified is determined to be correct.

[0014] Furthermore, in some implementations, when the system-level function of the UART interface to be verified is a register read / write function, the process of verifying the system-level function of the UART interface to be verified by running a test program on the SoC chip under test based on the closed-loop simulation verification environment, driving the UART interface to be verified to interact with the UART peripheral virtual behavior model, and verifying the system-level function of the UART interface to be verified based on the data interaction results includes: If the register is a register group with associated access logic, configure a specific control bit of the first control register to a first value to enable the access window of the first group of target registers. Under the enabled access window of the first group of target registers, perform a first verification operation on the first group of target registers to confirm whether its access attributes meet the first expectation. Configure the specific control bit of the first control register to a second value to close the access window of the first group of target registers and enable the access window of the second group of target registers. With the access window of the second group of target registers enabled, perform a second verification operation on the second group of target registers to confirm whether its access attributes meet the second expectation. The first control register, together with the first group of target registers and the second group of target registers, constitutes a register group with associated access logic. The first group of target registers and the second group of target registers are mapped to the same or associated hardware address, and their accessibility is uniquely determined by the state of the first control register.

[0015] The main advantages of the technical solution of this invention are as follows: The present invention provides a system-level software simulation verification method for UART interfaces of SoC chips. By constructing a reusable virtual behavior model of UART peripherals and cross-interconnecting it with the UART interface of the SoC chip under test to form a closed-loop simulation verification environment, this method effectively overcomes the limitations of traditional multi-UART interface interconnection verification methods and the redundancy problem of module-level verification methods based on UVM and VIP in system-level applications. It can significantly simplify the verification environment and improve the simulation verification efficiency. At the same time, thanks to the high reusability of the virtual behavior model of UART peripherals, it can flexibly support system-level functional verification of any number of UART interfaces in the chip, enhancing the universality and portability of the verification process. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1A flowchart illustrating a system-level software simulation verification method for a SoC chip UART interface provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of a system-level software simulation verification method for a SoC chip UART interface provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0018] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] refer to Figure 1-2 This invention provides a system-level software simulation verification method for the UART interface of a SoC chip, which includes the following steps: Step 1: Construct a virtual behavior model for UART peripherals. The virtual behavior model for UART peripherals has a transmit port and a receive port. The virtual behavior model for UART peripherals is used to simulate the behavior of external UART devices. Step 2: Connect the transmit port of the UART interface to be verified in the SoC chip under test to the receive port of the UART peripheral virtual behavior model, and connect the receive port of the UART interface to be verified to the transmit port of the UART peripheral virtual behavior model to form a closed-loop simulation verification environment. Step 3: Based on the closed-loop simulation verification environment, the test program is run on the SoC chip under test to drive the UART interface to be verified to interact with the virtual behavior model of the UART peripheral. Based on the data interaction results, the system-level functions of the UART interface to be verified are verified. The SoC chip under test includes at least one UART interface, and the UART interface in the SoC chip under test reuses the UART peripheral virtual behavior model.

[0020] In this embodiment of the invention, different UART interfaces in a SoC chip can reuse the same UART peripheral virtual behavior model. When it is necessary to verify the system-level function of a certain UART interface in the SoC chip, the transmit port (tx pin) of the UART interface to be verified is connected to the receive port (rx pin) of the UART peripheral virtual behavior model, and the receive port (rx pin) of the UART interface to be verified is connected to the transmit port (tx pin) of the UART peripheral virtual behavior model, thereby forming a closed-loop simulation verification environment. Then, based on the closed-loop simulation verification environment, a test program is run on the core of the SoC chip to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model, and the data interaction results are collected, compared and analyzed to verify whether the system-level function of the UART interface is correct.

[0021] The present invention provides a system-level software simulation verification method for UART interfaces of SoC chips. By constructing a reusable virtual behavior model of UART peripherals and cross-interconnecting it with the UART interface of the SoC chip under test to form a closed-loop simulation verification environment, this method effectively overcomes the limitations of traditional multi-UART interface interconnection verification methods and the redundancy problem of module-level verification methods based on UVM and VIP in system-level applications. It can significantly simplify the verification environment and improve the simulation verification efficiency. At the same time, thanks to the high reusability of the virtual behavior model of UART peripherals, it can flexibly support system-level functional verification of any number of UART interfaces in the chip, enhancing the universality and portability of the verification process.

[0022] Furthermore, in this embodiment of the invention, when verifying the system-level functions of the UART interface, the system-level functions of the UART interface may include: data transmission and reception functions.

[0023] In this embodiment of the invention, when the system-level function of the UART interface to be verified is a data transmission and reception function, step 3 further includes: Test data is sent from the core of the SoC chip under test to the UART interface to be verified. Test data is sent to the UART peripheral virtual behavior model via the transmit port of the UART interface to be verified. After the UART peripheral virtual behavior model receives the data, it sends the data back to the UART interface to be verified via the sending port of the UART peripheral virtual behavior model. Data is read from the UART interface to be verified through the core of the SoC chip under test; Compare the test data sent by the core of the SoC chip under test with the data read by the core of the SoC chip under test from the UART interface to be verified. If they are consistent, the data transmission and reception function of the UART interface to be verified is determined to be correct.

[0024] In this embodiment of the invention, the test data can be a string.

[0025] In this embodiment of the invention, the above-mentioned data transmission and reception function verification operation constructs a complete data loop path consisting of a core, a UART interface, and a virtual behavior model of UART peripherals. This achieves closed-loop, self-testing verification of the UART interface's transmission and reception path, significantly simplifying the verification process and result judgment logic. It does not rely on external real devices or complex monitoring mechanisms. By directly comparing the data consistency between the source and the destination through the core, it can deterministically and efficiently verify the integrity of the data throughout the entire transmission link, thereby ensuring the correctness of the UART interface's data transmission and reception function verification results.

[0026] Furthermore, in this embodiment of the invention, when verifying the system-level functions of the UART interface, the system-level functions of the UART interface may include: interrupt response function.

[0027] In this embodiment of the invention, when the system-level function of the UART interface to be verified is an interrupt response function, step 3 further includes: By controlling the data interaction between the UART peripheral virtual behavior model and the UART interface to be verified, an interrupt triggering condition is constructed to make the UART interface to be verified generate an interrupt request. Check the status of the interrupt enable register (IER). If the enable bit corresponding to the interrupt request is valid, the interrupt request is recorded in the interrupt discrimination register (IIR) and reported to the core of the SoC chip under test, so that the core of the SoC chip under test executes the preset interrupt service routine to handle the interrupt request. Verify that the interrupt service routine has responded correctly to the interrupt trigger condition; If the response is correct, the interrupt response function of the UART interface to be verified is determined to be correct.

[0028] In this embodiment of the invention, interrupt triggering conditions are constructed by controlling the data interaction between the UART peripheral virtual behavior model and the UART interface to be verified. Specifically, the data interaction rhythm between the UART peripheral virtual behavior model and the UART interface to be verified is controlled, and an interrupt is triggered when the transmit holding register (THR) or the transmit FIFO (first-in, first-out queue) is empty or full, and the UART interface generates an interrupt request.

[0029] In this embodiment of the invention, when the UART interface generates an interrupt request, each interrupt request has an enable bit in the interrupt enable register and is recorded in the interrupt discrimination register. If an interrupt occurs and the corresponding enable bit is 1, that is, the enable bit corresponding to the interrupt request is valid, the interrupt request will be recorded in the interrupt discrimination register and transmitted to the core of the SoC chip under test; if an interrupt occurs and the corresponding enable bit is 0, that is, the enable bit corresponding to the interrupt request is invalid, the interrupt request is ignored.

[0030] In this embodiment of the invention, after receiving an interrupt request, the core of the SoC chip under test executes a preset interrupt service routine to process the interrupt request and verify whether the interrupt service routine correctly responds to the interrupt triggering condition. If it responds correctly, the interrupt response function of the UART interface under test is determined to be correct. Specifically, for example, if the interrupt request generated by the UART interface is caused by a transmit interrupt, it indicates that the transmit FIFO is empty or full. The core of the SoC chip under test writes 1 byte of data to the transmit holding register, indicating that the interrupt response function of the UART interface is correct.

[0031] In this embodiment of the invention, the above-mentioned interrupt response function verification operation constructs an interrupt scenario through a software-controllable UART peripheral virtual behavior model, realizing closed-loop verification of the complete interrupt path of the UART interface from condition triggering, enable judgment, status recording to SoC chip response and processing. It can transform the internal interrupt mechanism that is difficult to observe directly into a clear process that can be indirectly verified through program behavior, significantly improving the controllability and observability of interrupt response function verification, thereby ensuring the correctness of the interrupt response function verification results of the UART interface.

[0032] Furthermore, in this embodiment of the invention, when verifying the system-level functions of the UART interface, the system-level functions of the UART interface may include: register read / write functions.

[0033] In this embodiment of the invention, when the system-level function of the UART interface to be verified is a register read / write function, step 3 further includes: If the register is a readable and writable register, the core of the SoC chip under test performs a read operation on the readable and writable register in the UART interface to be verified to obtain the first value; Modify the first value to obtain the second value, and write the second value into a readable and writable register through the core of the SoC chip under test; The third value is obtained by performing a read operation on the readable and writable registers again through the core of the SoC chip under test; Compare the second and third values ​​to see if they are equal. If they are, then the register read / write function of the UART interface to be verified is correct.

[0034] In this embodiment of the invention, when modifying the first value, for example, one of the digits of the first value can be modified to obtain the second value.

[0035] In embodiments of the present invention, readable and writable registers include, for example, the Line Control Register (LCR), the Modem Control Register (MCR), and the Scratchpad Register (SPR).

[0036] In this embodiment of the invention, the above-mentioned register read / write function verification operation adopts a standardized "read-modify-write-read again" closed-loop process. By directly operating and comparing the register values, the read / write function of the readable and writable register can be verified deterministically.

[0037] Furthermore, in this embodiment of the invention, when the system-level function of the UART interface to be verified is a register read / write function, step 3 further includes: If the register is a read-only register, the core of the SoC chip under test performs a read operation on the read-only register in the UART interface to be verified to obtain the first value; Modify the first value to obtain the second value, and write the second value into the read-only register through the core of the SoC chip under test; The third value is obtained by performing a read operation on the read-only register again through the core of the SoC chip under test; Compare the first value with the third value. If they are equal, the register read / write function of the UART interface to be verified is determined to be correct.

[0038] In this embodiment of the invention, when modifying the first value, for example, one of the digits of the first value can be modified to obtain the second value.

[0039] In this embodiment of the invention, a read-only register is, for example, a line status register (LSR).

[0040] In this embodiment of the invention, the above-mentioned register read / write function verification operation adopts a standardized "read-modify-write-read again" closed-loop process. By directly operating and comparing the register values, the read / write function of the read-only register can be verified deterministically.

[0041] Furthermore, in this embodiment of the invention, when the system-level function of the UART interface to be verified is a register read / write function, step 3 further includes: If the register is a write-only register, the first value is obtained by performing a read operation on the write-only register in the UART interface to be verified through the core of the SoC chip under test; Modify the first value to obtain the second value, and write the second value into the write-only register through the core of the SoC chip under test; The third value is obtained by performing a read operation on the write-only register again through the core of the SoC chip under test; Compare the first value with the third value to see if they are not equal. If they are, then the register read / write function of the UART interface to be verified is correct.

[0042] In this embodiment of the invention, when modifying the first value, for example, one of the digits of the first value can be modified to obtain the second value.

[0043] In this embodiment of the invention, only write registers are used, such as the Transmit Holding Register (THR) and the FIFO Control Register (FCR).

[0044] In this embodiment of the invention, the above-mentioned register read / write function verification operation adopts a standardized "read-modify-write-read again" closed-loop process. By directly operating and comparing the register values, the read / write function of writing only registers can be verified deterministically.

[0045] Furthermore, in this embodiment of the invention, when the system-level function of the UART interface to be verified is a register read / write function, step 3 further includes: If the register is a register group with associated access logic, configure a specific control bit of the first control register to a first value to enable the access window of the first group of target registers. Under the enabled access window of the first group of target registers, perform a first verification operation on the first group of target registers to confirm whether its access attributes meet the first expectation. Configure a specific control bit of the first control register to a second value to close the access window of the first group of target registers and enable the access window of the second group of target registers. With the access window of the second group of target registers enabled, perform a second verification operation on the second group of target registers to confirm whether their access attributes meet the second expectation. The first control register, together with the first group of target registers and the second group of target registers, constitutes a register group with associated access logic. The first group of target registers and the second group of target registers are mapped to the same or associated hardware address, and their accessibility is uniquely determined by the state of the first control register.

[0046] In this embodiment of the invention, the first control register, the first set of target registers, and the second set of target registers are determined according to actual conditions. For example, the first control register is a line control register, the first set of target registers is the high byte of the divisor latch (DLH) and the low byte of the divisor latch (DLL), and the second set of target registers is a receive buffer register (RBR).

[0047] Taking the aforementioned first control register, first group of target registers, and second group of target registers as examples, when verifying the register read / write function, the 7th bit of the line control register is configured to 1 to allow access to the baud rate divisor latch; read / write verification is performed on the low byte and high byte of the divisor latch, confirming that when the 7th bit of the line control register is configured to 1, the low byte and high byte of the divisor latch behave as readable and writable registers; then, the 7th bit of the line control register is configured to 0 to disable access to the baud rate divisor latch and allow access to the receive buffer register; read / write verification is performed on the receive buffer register, confirming that when the 7th bit of the line control register is configured to 0, the receive buffer register behaves as a read-only register.

[0048] In this embodiment of the invention, the high byte and low byte of the divisor latch overlap with part or all of the address of the receive buffer register, and the switching of the physical access object is controlled by the status of the 7th bit of the line control register.

[0049] In this embodiment of the invention, the above-mentioned verification operation for the read and write functions of register groups with associated access logic, through systematically testing the dynamic impact of control register state switching on the access permissions of target registers, achieves in-depth verification of the complex address reuse and access control mechanism inside the UART interface. It can accurately verify the correctness of dynamic dependencies and control logic in hardware design, ensuring that the software can reliably access the correct register set in different working modes, fundamentally eliminating configuration failures or functional abnormalities caused by register mapping or enable logic errors, and significantly improving the system-level verification's coverage of complex interactive logic inside the chip and the verification credibility.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, the terms "front," "back," "left," "right," "upper," and "lower" in this document refer to the placement shown in the accompanying drawings.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system-level software simulation and verification method for a SoC chip UART interface, characterized in that, include: A virtual behavior model for a UART peripheral device is constructed. The virtual behavior model for a UART peripheral device has a transmit port and a receive port. The virtual behavior model for a UART peripheral device is used to simulate the behavior of an external UART device. Connect the transmitting port of the UART interface to be verified in the SoC chip under test to the receiving port of the UART peripheral virtual behavior model, and connect the receiving port of the UART interface to be verified to the transmitting port of the UART peripheral virtual behavior model to form a closed-loop simulation verification environment. Based on the closed-loop simulation verification environment, by running a test program on the SoC chip under test, the UART interface to be verified is driven to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level functions of the UART interface to be verified are verified. The SoC chip under test includes at least one UART interface, and the UART interface in the SoC chip under test reuses the UART peripheral virtual behavior model.

2. The system-level software simulation verification method for a SoC chip UART interface according to claim 1, characterized in that, The system-level functions of the UART interface to be verified include at least: data transmission and reception functions.

3. The system-level software simulation verification method for a SoC chip UART interface according to claim 2, characterized in that, When the system-level function of the UART interface to be verified is data transmission and reception, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: Test data is sent from the core of the SoC chip under test to the UART interface to be verified. Test data is sent to the UART peripheral virtual behavior model through the transmit port of the UART interface to be verified. After receiving the data, the UART peripheral virtual behavior model sends the data back to the UART interface to be verified via the sending port of the UART peripheral virtual behavior model. Data is read from the UART interface to be verified through the core of the SoC chip under test; Compare the test data sent by the core of the SoC chip under test with the data read by the core of the SoC chip under test from the UART interface to be verified. If they are consistent, the data transmission and reception function of the UART interface to be verified is determined to be correct.

4. The system-level software simulation verification method for a SoC chip UART interface according to claim 1, characterized in that, The system-level functions of the UART interface to be verified include at least the interrupt response function.

5. The system-level software simulation verification method for a SoC chip UART interface according to claim 4, characterized in that, When the system-level function of the UART interface to be verified is an interrupt response function, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: By controlling the data interaction between the UART peripheral virtual behavior model and the UART interface to be verified, an interrupt triggering condition is constructed to cause the UART interface to be verified to generate an interrupt request. Check the status of the interrupt enable register. If the enable bit corresponding to the interrupt request is valid, the interrupt request is recorded in the interrupt identification register and reported to the core of the SoC chip under test, so that the core of the SoC chip under test executes the preset interrupt service routine to process the interrupt request. Verify whether the interrupt service routine has responded correctly to the interrupt triggering condition; If the response is correct, the interrupt response function of the UART interface to be verified is determined to be correct.

6. The system-level software simulation verification method for a SoC chip UART interface according to claim 1, characterized in that, The system-level functions of the UART interface to be verified include at least: register read / write functionality.

7. The system-level software simulation verification method for a SoC chip UART interface according to claim 6, characterized in that, When the system-level function of the UART interface to be verified is a register read / write function, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: If the register is a readable and writable register, the core of the SoC chip under test performs a read operation on the readable and writable register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the readable and writable register through the core of the SoC chip under test; The third value is obtained by performing a read operation on the readable and writable register again through the core of the SoC chip under test; Compare the second value with the third value. If they are equal, then the register read / write function of the UART interface to be verified is determined to be correct.

8. The system-level software simulation verification method for a SoC chip UART interface according to claim 6, characterized in that, When the system-level function of the UART interface to be verified is a register read / write function, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: If the register is a read-only register, the core of the SoC chip under test performs a read operation on the read-only register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the read-only register through the core of the SoC chip under test; The read-only register is read again through the core of the SoC chip under test to obtain a third value; Compare the first value with the third value. If they are equal, then the register read / write function of the UART interface to be verified is determined to be correct.

9. A system-level software simulation verification method for a SoC chip UART interface according to claim 6, characterized in that, When the system-level function of the UART interface to be verified is a register read / write function, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: If the register is a write-only register, the core of the SoC chip under test performs a read operation on the write-only register in the UART interface to be verified to obtain the first value; The first value is modified to obtain the second value, and the second value is written into the write-only register through the core of the SoC chip under test; The write-only register is read again through the core of the SoC chip under test to obtain a third value; Compare the first value with the third value to see if they are not equal. If they are, then the register read / write function of the UART interface to be verified is determined to be correct.

10. A system-level software simulation verification method for a SoC chip UART interface according to claim 6, characterized in that, When the system-level function of the UART interface to be verified is a register read / write function, the process involves running a test program on the SoC chip under test based on the closed-loop simulation verification environment to drive the UART interface to be verified to interact with the UART peripheral virtual behavior model. Based on the data interaction results, the system-level function of the UART interface to be verified is verified, including: If the register is a register group with associated access logic, configure a specific control bit of the first control register to a first value to enable the access window of the first group of target registers. Under the enabled access window of the first group of target registers, perform a first verification operation on the first group of target registers to confirm whether its access attributes meet the first expectation. Configure the specific control bit of the first control register to a second value to close the access window of the first group of target registers and enable the access window of the second group of target registers. With the access window of the second group of target registers enabled, perform a second verification operation on the second group of target registers to confirm whether its access attributes meet the second expectation. The first control register, together with the first group of target registers and the second group of target registers, constitutes a register group with associated access logic. The first group of target registers and the second group of target registers are mapped to the same or associated hardware address, and their accessibility is uniquely determined by the state of the first control register.

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