A distributed deployment inference method of a deep pulse neural network and a related device
By splitting deep spiking neural networks into sub-neural networks and gradually deploying them on neuromorphic chips, the problems of storage resources and computing power limitations were solved, enabling large-scale deep spiking neural network inference on neuromorphic chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PENG CHENG LAB
- Filing Date
- 2023-02-09
- Publication Date
- 2026-05-29
AI Technical Summary
Deep spiking neural networks cannot be deployed on neuromorphic chips due to limitations in storage resources and computing power, which restricts their applications.
By breaking down deep spiking neural networks into several sub-neural networks, compiling and deploying them on a neuromorphic chip, and performing inference step by step through these sub-neural networks, the application scope of deep spiking neural networks is expanded.
It enables large-scale deep spiking neural network model inference on neuromorphic chips, expanding its application scope.
Smart Images
Figure CN116245182B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a distributed deployment inference method and related apparatus for deep spiking neural networks. Background Technology
[0002] Spiking Neural Networks (SNNs), as third-generation neural networks, possess a high degree of biological realism, achieving efficient computation by simulating the connection patterns of the brain's neural networks and incorporating temporal information. Due to their low-power characteristics, SNNs have attracted significant attention in the field of neural network research.
[0003] In recent years, significant progress has been made in the research of neuromorphic chips both domestically and internationally. For example, IBM's TrueNorth, Intel's Loihi 1 / 2, Tsinghua University's Tianji Chip II, and Zhejiang University's Darwin I / II have achieved ultra-low power consumption by utilizing the sparsity, impulse summation, and asynchronous event-driven characteristics of neuromorphic spiking computation. Currently, neuromorphic chips support model inference. However, with the rapid development of artificial intelligence, the demand for model performance is growing exponentially, and model complexity is increasing rapidly. Due to the limitations of storage resources and computing power in neuromorphic chips, deep spiking neural networks cannot be deployed on them, which greatly restricts their application.
[0004] Therefore, existing technologies still need to be improved and enhanced. Summary of the Invention
[0005] The technical problem to be solved by this application is to provide a distributed deployment inference method and related apparatus for deep spiking neural networks, addressing the shortcomings of existing technologies.
[0006] To address the aforementioned technical problems, the first aspect of this application provides a distributed deployment inference method for deep spiking neural networks, the method further comprising:
[0007] Obtain the deep spiking neural network to be deployed, and split the deep spiking neural network into several sub-neural networks. In any two adjacent sub-neural networks, the output of the preceding sub-neural network is the input of the following sub-neural network.
[0008] Each sub-neural network in the several sub-neural networks is compiled to obtain the corresponding generated model file for each sub-neural network;
[0009] The generative model files corresponding to several sub-neural networks are sequentially deployed on the neuromorphic chip so that the input data can be inferred step by step through several sub-neural networks to obtain the output data corresponding to the input data.
[0010] The distributed deployment inference method for the deep spiking neural network, wherein splitting the deep spiking neural network into several sub-neural networks specifically includes:
[0011] Obtain the storage space corresponding to the neuromorphic chip;
[0012] The deep spiking neural network is divided into several sub-neural networks based on the storage space, wherein the storage space required by each sub-neural network is smaller than the storage space corresponding to the neuromorphic chip.
[0013] The distributed deployment inference method for the deep spiking neural network, wherein compiling each sub-neural network in the plurality of sub-neural networks specifically comprises:
[0014] The compiler software corresponding to the neuromorphic chip is used to compile each of the several sub-neural networks. When compiling each sub-neural network, the input of the sub-neural network carries the membrane potential state.
[0015] The distributed deployment inference method of the deep spiking neural network includes the following steps during the compilation of each sub-neural network: the batch size dimension and channel dimension of the input data are merged to obtain target input data; the target data is passed through the spiking computation layer of the sub-neural network to obtain candidate output data; the batch size dimension and channel dimension of the candidate output data are split; and the split batch size dimension and modulus potential state dimension are merged to obtain reference output data; finally, the reference output data is input into the target computation unit of the sub-neural network to obtain output data. The target computation unit includes convolutional layers and / or pooling layers.
[0016] The distributed deployment and inference method for the deep spiking neural network, wherein the step of sequentially deploying the generated model files corresponding to several sub-neural networks on a neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes:
[0017] When several sub-neural networks are deployed on a single neuromorphic chip, the generative model file of the first sub-neural network is deployed on the neuromorphic chip, and the input data is input into the first sub-neural network to obtain the first output data.
[0018] The neuromorphic chip is controlled to delete the first sub-neural network and deploy the generation model file of the second sub-neural network on the neuromorphic chip, and input the first output data into the second sub-neural network to obtain the second output data;
[0019] This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
[0020] The distributed deployment and inference method for the deep spiking neural network, wherein the step of sequentially deploying the generated model files corresponding to several sub-neural networks on a neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes:
[0021] When several sub-neural networks are deployed on multiple neuromorphic chips, the generated model files of each sub-neural network are deployed on different chips respectively.
[0022] Input data is fed into one of a series of neuromorphic chips that are deployed in the first sub-neural network, and the first output data is output through the first sub-neural network.
[0023] The first output data is input into another chip among multiple neuromorphic chips deployed in the second sub-neural network, and the second output data is output through the second sub-neural network.
[0024] This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
[0025] The distributed deployment inference method of the deep spiking neural network is described, wherein the neuromorphic chips deployed in each of the several sub-neural networks are different.
[0026] A second aspect of this application provides a distributed deployment inference system for a deep spiking neural network, the system comprising:
[0027] The acquisition module is used to acquire the deep spiking neural network to be deployed and split the deep spiking neural network into several sub-neural networks, wherein, in any two adjacent sub-neural networks, the output of the preceding sub-neural network is the input of the following sub-neural network.
[0028] The compilation module is used to compile each sub-neural network in a number of sub-neural networks to obtain the corresponding generated model file for each sub-neural network;
[0029] The deployment module is used to sequentially deploy the generated model files corresponding to several sub-neural networks onto the neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data.
[0030] A third aspect of this application provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps in the distributed deployment inference method for deep spiking neural networks as described above.
[0031] A fourth aspect of this application provides a terminal device, which includes: a processor, a memory, and a communication bus; the memory stores a computer-readable program that can be executed by the processor;
[0032] The communication bus enables communication between the processor and the memory;
[0033] When the processor executes the computer-readable program, it implements the steps in the distributed deployment inference method for deep spiking neural networks as described above.
[0034] Beneficial Effects: Compared with existing technologies, this application provides a distributed deployment inference method and related apparatus for deep spiking neural networks. The method includes acquiring a deep spiking neural network to be deployed and splitting the deep spiking neural network into several sub-neural networks; compiling each sub-neural network to obtain a corresponding generative model file; and sequentially deploying the generative model files corresponding to the sub-neural networks onto a neuromorphic chip to perform inference on the input data step by step through the sub-neural networks to obtain the corresponding output data. By splitting the deep spiking network into several sub-neural networks and compiling and deploying each sub-neural network separately, this application allows the deep spiking neural network to be deployed on a neuromorphic chip, enabling the neuromorphic chip to use large-scale deep spiking neural networks for model inference, thus expanding the application scope of deep spiking neural networks. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 A flowchart of the distributed deployment inference method for the deep spiking neural network provided in this application.
[0037] Figure 2 A schematic diagram of the time-dimensional pulse sequence calculation process for compilation and deployment.
[0038] Figure 3 Deploy a data transformation graph for inference.
[0039] Figure 4 This is a schematic diagram of the deep spiking neural network inference process for a single type of brain chip.
[0040] Figure 5 This is a schematic diagram of the deep spiking neural network inference process for various types of brain chips.
[0041] Figure 6 The schematic diagram of the distributed deployment inference method for deep spiking neural networks provided in this application.
[0042] Figure 7 A schematic diagram of the terminal device provided in this application. Detailed Implementation
[0043] This application provides a distributed deployment inference method and related apparatus for deep spiking neural networks. To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.
[0044] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.
[0045] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.
[0046] It should be understood that the sequence number and size of each step in this embodiment do not imply the order of execution. The execution order of each process is determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.
[0047] Research has shown that Spiking Neural Networks (SNNs), as a third-generation neural network, possess a high degree of biological realism, achieving efficient computation by simulating the connection patterns of the brain's neural networks and incorporating temporal information. Due to their low-power characteristics, SNNs have attracted significant attention in the field of neural network research.
[0048] In recent years, significant progress has been made in the research of neuromorphic chips both domestically and internationally. For example, IBM's TrueNorth, Intel's Loihi 1 / 2, Tsinghua University's Tianji Chip II, and Zhejiang University's Darwin I / II have achieved ultra-low power consumption by utilizing the sparsity, impulse summation, and asynchronous event-driven characteristics of neuromorphic spiking computation. Currently, neuromorphic chips support model inference. However, with the rapid development of artificial intelligence, the demand for model performance is growing exponentially, and model complexity is increasing rapidly. Due to the limitations of storage resources and computing power in neuromorphic chips, deep spiking neural networks cannot be deployed on them, which greatly restricts their application.
[0049] To address the aforementioned issues, in this embodiment, a deep spiking neural network (DSN) to be deployed is obtained and then divided into several sub-neural networks. Each sub-neural network is compiled to obtain a corresponding generative model file. These generative model files are then sequentially deployed onto a neuromorphic chip. This allows the input data to be inferred step-by-step through the sub-neural networks to obtain the corresponding output data. By dividing the deep spiking network into several sub-neural networks and compiling and deploying each sub-neural network separately, the deep spiking neural network can be deployed on a neuromorphic chip, enabling the chip to use a large-scale deep spiking neural network for model inference and expanding the application scope of deep spiking neural networks.
[0050] The application content will be further explained below with reference to the accompanying drawings and the description of the embodiments.
[0051] This embodiment provides a distributed deployment inference method for deep spiking neural networks, such as... Figure 1 As shown, the method includes:
[0052] S10. Obtain the deep spiking neural network to be deployed, and split the deep spiking neural network into several sub-neural networks.
[0053] Specifically, the deep spiking neural network (DSNN) is a trained spiking neural network. For example, it could be a ResNet152-based DNN containing over 20 million neurons, trained iteratively 100 times on a V100 cluster platform. Understandably, before deploying the DNN on a neuromorphic chip, it's necessary to construct the DNN and train it on a learning platform to obtain a pre-trained DNN; this pre-trained DNN is then used as the DNN to be deployed.
[0054] Each sub-neural network in a plurality of sub-neural networks is a part of a deep spiking neural network (DSN). These sub-neural networks do not overlap and are concatenated according to their positional order within the DSN to form the DSN. Specifically, for any two adjacent sub-neural networks, the output of the preceding sub-neural network becomes the input of the following sub-neural network. Adjacent sub-neural networks are those whose positions within the DSN are adjacent. For example, the DSN can be divided into sub-neural networks 1, 2, ..., N, where the indices are determined by their positional order within the DSN. Sub-neural network 1 precedes sub-neural network 2, sub-neural network 2 precedes sub-neural network 3, and so on, with sub-neural network N being the last sub-neural network.
[0055] In one implementation, to enable the divided sub-neural networks to be deployed on a neuromorphic chip, where the neuromorphic chip is pre-determined to accommodate the deep spiking neural network, the deep spiking neural network needs to be divided according to the storage space of the neuromorphic chip. Based on this, the specific steps of dividing the deep spiking neural network into several sub-neural networks include:
[0056] Obtain the storage space corresponding to the neuromorphic chip;
[0057] The deep spiking neural network is divided into several sub-neural networks based on the storage space.
[0058] Specifically, the storage space of the neuromorphic chip refers to the available storage space of the neuromorphic chip, and the storage space required by the sub-neural network refers to the storage slots occupied by the sub-neural network deployed on the neuromorphic chip. The storage space required by the sub-neural network is less than the storage space of the neuromorphic chip, thus allowing the sub-neural network to be deployed on the neuromorphic chip. In one implementation, to ensure that each sub-neural network can be deployed on the neuromorphic chip, when splitting the deep spiking neural network into several sub-neural networks according to the storage space, it is necessary to statistically analyze the number of neurons, parameters, and input data size of each layer of the deep spiking neural network to determine the required storage space for each layer. Then, based on the storage space of the neuromorphic chip, the deep spiking neural network is split into several sub-neural networks using a layer-by-layer splitting method, where the output of the previous sub-neural network becomes the input of the next sub-neural network. For example, a deep spiking neural network built based on ResNet152 can be split into 52 sub-neural networks, meaning each bottleneck is a sub-neural network.
[0059] S20. Compile each sub-neural network in the several sub-neural networks to obtain the corresponding generated model file for each sub-neural network.
[0060] Specifically, after obtaining each sub-neural network, it needs to be compiled so that it can be used with the neuromorphic chip. That is, after obtaining the sub-neural network, the compilation software of the neuromorphic chip is used to compile and deploy each sub-network to obtain the corresponding generated model file. The generated model file can be loaded onto the neuromorphic chip, and the sub-neural network corresponding to the generated model file can be deployed on the neuromorphic chip.
[0061] Furthermore, since the deep spiking network model adds a time-dimensional cumulative calculation during the computation process, the time dimension needs to be considered during the compilation of the sub-neural networks. It is understandable that, because the calculation of the pulse sequence during the inference process of the deep spiking network depends on the modulus potential state in the time dimension, i.e., the membrane potential at time T-1 is an influencing factor at time T, and the membrane potential is the determining factor of the pulse sequence of the deep spiking network SNN layer, it is necessary to save the membrane potential state value at each time T during the compilation and deployment process and carry it into the calculation of the next time step. Based on this, the specific compilation of each sub-neural network in the several sub-neural networks is as follows:
[0062] The compiler software corresponding to the neuromorphic chip is used to compile each of the several sub-neural networks. When compiling each sub-neural network, the input of the sub-neural network carries the membrane potential state.
[0063] Specifically, for each sub-neural network, the modulus potential state v is used as both the input and output during the sub-neural network's compilation. That is, both the input and output terms of the sub-neural network carry the modulus potential state v. In other words, the modulus potential state v_outT at time T-1, along with the input inference data, serves as the input at time T. This method achieves time-dependent iteration in the deployment of the SNN model. For example, setting T to 4, such as... Figure 2 As shown, the output of neuron T=0 includes the membrane potential state v_out1. The membrane potential state v_out1 of neuron T=0 is the input of neuron 1. The output of neuron T=1 includes the membrane potential state v_out2, and so on. The output of neuron T=3 includes the membrane potential state v_out4.
[0064] Furthermore, because a membrane potential state dimension is added during the compilation process, each deep spiking neural network (DSN) data layer gains a time dimension T, making the DSN data five-dimensional. However, neuromorphic storage chips do not support five-dimensional data, thus requiring dimensionality transformation of the input data during DSN layer computation. Based on this, as... Figure 3 As shown, during the compilation process of each sub-neural network, the batch size dimension N and the channel dimension C in the input data [T,N,C,H,W] are merged to obtain the target input data [T,NC,H,W]. The target data is passed through the pulse computation layer of the sub-neural network to obtain the candidate output data [T,NC,H,W]. The batch size dimension N and the channel dimension C in the candidate output data [T,NC,H,W] are split, and the split batch size dimension N is merged with the modulus potential state dimension T to obtain the reference output data [TN,C,H,W]. Finally, the reference output data is input into the target computation unit of the sub-neural network to obtain the output data. The target computation unit includes a convolutional layer and / or a pooling layer, where T represents the modulus potential state dimension, N represents the batch size dimension, C represents the channel dimension, H represents the height dimension, and W represents the width dimension. For example, taking the compilation process of SNN-ResNet152 as an example, the input data at the beginning of inference is [4,2,3,224,224]. Before entering the SNN layer for computation, the data is transformed from [4,2,3,224,224] into [4,2*3,224,224]. After the SNN layer computation is completed, the data is transformed from [4,2*3,224,224] into [4*2,3,224,224] for convolution, pooling and other operations.
[0065] S30. The generative model files corresponding to several sub-neural networks are sequentially deployed on the neuromorphic chip so as to gradually reason about the input data through several sub-neural networks to obtain the output data corresponding to the input data.
[0066] Specifically, a neuromorphic chip deploys one sub-neural network. That is, when several sub-neural networks are deployed sequentially on the same neuromorphic chip, the previous neural network needs to be deleted after the previous sub-neural network has completed its inference before the next sub-neural network is deployed. When several sub-neural networks are deployed on multiple neuromorphic chips, each neuromorphic chip deploys one sub-neural network.
[0067] In one implementation, the step of sequentially deploying the generative model files corresponding to several sub-neural networks onto a neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes:
[0068] When several sub-neural networks are deployed on a single neuromorphic chip, the generative model file of the first sub-neural network is deployed on the neuromorphic chip, and the input data is input into the first sub-neural network to obtain the first output data.
[0069] The neuromorphic chip is controlled to delete the first sub-neural network and deploy the generation model file of the second sub-neural network on the neuromorphic chip, and input the first output data into the second sub-neural network to obtain the second output data;
[0070] This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
[0071] Specifically, deploying several sub-neural networks on a single neuromorphic chip refers to using a single neuromorphic chip for model inference, such as... Figure 4 As shown, the process of model inference by a single neuromorphic chip can be as follows: First, the foremost sub-neural network is loaded into the neuromorphic chip, and the input data is input into the foremost sub-neural network for inference calculation to obtain the first output data. Then, the first output data is saved and the foremost sub-neural network is deleted so that the free storage space of the neuromorphic chip can meet the needs of the second sub-neural network. Second, the second sub-neural network is loaded into the neuromorphic neural network, and the first output data is used as input data to the second sub-neural network for inference calculation. This process is repeated to complete the inference calculation of several sub-neural networks. The output data of the last sub-neural network is the output data of the deep spiking neural network.
[0072] In one implementation, the step of sequentially deploying the generative model files corresponding to several sub-neural networks onto a neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes:
[0073] When several sub-neural networks are deployed on multiple neuromorphic chips, the generated model files of each sub-neural network are deployed on different chips respectively.
[0074] Input data is fed into one of a series of neuromorphic chips that are deployed in the first sub-neural network, and the first output data is output through the first sub-neural network.
[0075] The first output data is input into another chip among multiple neuromorphic chips deployed in the second sub-neural network, and the second output data is output through the second sub-neural network.
[0076] This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
[0077] Specifically, deploying several sub-neural networks on multiple neuromorphic chips refers to deep spiking neural networks performing model inference through multiple types of neuromorphic chips. In this case, such as... Figure 5 As shown, each sub-neural network is loaded onto a neuromorphic chip, and each sub-neural network corresponds to a different neuromorphic chip. That is, the number of neuromorphic chips used for model inference is greater than or equal to the number of sub-neural networks. This allows each sub-neural network to be configured with its own neuromorphic chip. After the first sub-neural network determines its first output data, it can be directly transmitted to the neuromorphic chip containing the second sub-neural network. Inference computation is then performed through the second sub-neural network, without waiting for the neuromorphic chip to remove the first sub-neural network and then load the second sub-neural network, thus improving model inference speed. For example, for an SNN network built on ResNet152, a multi-process pipelined parallel approach was designed to accelerate SNN model inference. The 52 sub-models are loaded onto 52 computing chips. After chip 1 completes one inference computation, chip 2 receives the output data from chip 1 and begins the inference computation of sub-network 2. Simultaneously, chip 1 begins the next round of inference computation, and so on, until chip 52 completes its final inference, ending the process.
[0078] Of course, in practical applications, when using multiple types of brain chips for inference, the number of multiple types of brain chips may be less than the number of several sub-neural networks. In this case, based on the first number of multiple types of brain chips, a first number of sub-neural networks can be selected from several sub-neural networks according to their position order in the deep spiking neural network. Each selected sub-neural network is assigned a brain-like chip, and then each sub-neural network is loaded onto its corresponding brain-like chip and inference calculation is performed. After the inference of the last sub-neural network in the selected sub-neural network is completed, the output data of the last sub-neural network in the selected sub-neural network is saved, and the sub-neural networks in each type of brain chip are deleted. Thus, the above selection, loading, and inference process continues until the output data of the last sub-neural network is obtained.
[0079] In summary, this embodiment provides a distributed deployment and inference method for deep spiking neural networks. The method includes acquiring a deep spiking neural network to be deployed and splitting it into several sub-neural networks; compiling each sub-neural network to obtain a corresponding generated model file; and sequentially deploying the generated model files of the sub-neural networks onto a neuromorphic chip to progressively infer input data through the sub-neural networks to obtain output data corresponding to the input data. This application, by splitting the deep spiking network into several sub-neural networks and compiling and deploying each sub-neural network separately, allows the deep spiking neural network to be deployed on a neuromorphic chip, enabling the neuromorphic chip to use large-scale deep spiking neural networks for model inference, thus expanding the application scope of deep spiking neural networks.
[0080] Based on the above-described distributed deployment inference method using deep spiking neural networks, this embodiment provides a distributed deployment inference system for deep spiking neural networks, such as... Figure 6 As shown, the system includes:
[0081] The acquisition module 100 is used to acquire the deep spiking neural network to be deployed and split the deep spiking neural network into several sub-neural networks, wherein, in any two adjacent sub-neural networks, the output of the preceding sub-neural network is the input of the following sub-neural network.
[0082] The compilation module 200 is used to compile each sub-neural network in several sub-neural networks to obtain the corresponding generated model file for each sub-neural network;
[0083] The deployment module 300 is used to sequentially deploy the generated model files corresponding to several sub-neural networks onto the neuromorphic chip, so as to gradually infer the input data through several sub-neural networks to obtain the output data corresponding to the input data.
[0084] Based on the distributed deployment inference method of deep spiking neural networks described above, this embodiment provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps in the distributed deployment inference method of deep spiking neural networks as described in the above embodiment.
[0085] Based on the distributed deployment inference method of the aforementioned deep spiking neural network, this application also provides a terminal device, such as... Figure 7As shown, it includes at least one processor 20; a display screen 21; and a memory 22, and may also include a communications interface 23 and a bus 24. The processor 20, display screen 21, memory 22, and communications interface 23 can communicate with each other via the bus 24. The display screen 21 is configured to display a preset user guide interface in the initial setup mode. The communications interface 23 can transmit information. The processor 20 can invoke logical instructions in the memory 22 to execute the methods described in the above embodiments.
[0086] Furthermore, the logical instructions in the aforementioned memory 22 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0087] The memory 22, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, such as program instructions or modules corresponding to the methods in the embodiments of this disclosure. The processor 20 executes functional applications and data processing by running the software programs, instructions, or modules stored in the memory 22, thereby implementing the methods in the above embodiments.
[0088] The memory 22 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 22 may include high-speed random access memory (RAM) and non-volatile memory. Examples include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks; these can also be transient storage media.
[0089] Furthermore, the specific process of loading and executing multiple instruction processors in the aforementioned storage medium and terminal device has been described in detail in the above method, and will not be repeated here.
[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A distributed deployment inference method for deep spiking neural networks, characterized in that, The method further includes: Obtain the deep spiking neural network to be deployed, and split the deep spiking neural network into several sub-neural networks. In any two adjacent sub-neural networks, the output of the preceding sub-neural network is the input of the following sub-neural network. Each sub-neural network in the several sub-neural networks is compiled to obtain the corresponding generated model file for each sub-neural network; The generative model files corresponding to several sub-neural networks are sequentially deployed on the neuromorphic chip so that the input data can be inferred step by step through several sub-neural networks to obtain the output data corresponding to the input data. Specifically, compiling each sub-neural network within the plurality of sub-neural networks involves: The brain-like chip's corresponding compilation software compiles each of the several sub-neural networks. When compiling each sub-neural network, the input of the sub-neural network carries the membrane potential state, and the output of the sub-neural network carries the membrane potential state. During the compilation process of each sub-neural network, the batch size dimension and channel dimension of the input data are merged to obtain the target input data. The target input data is passed through the pulse calculation layer of the sub-neural network to obtain candidate output data. The batch size dimension and channel dimension of the candidate output data are split, and the split batch size dimension and the modulus potential state dimension are merged to obtain the reference output data. Finally, the reference output data is input into the target calculation unit of the sub-neural network to obtain the output data.
2. The distributed deployment inference method for deep spiking neural networks according to claim 1, characterized in that, The step of splitting the deep spiking neural network into several sub-neural networks specifically includes: Obtain the storage space corresponding to the neuromorphic chip; The deep spiking neural network is divided into several sub-neural networks based on the storage space, wherein the storage space required by each sub-neural network is smaller than the storage space corresponding to the neuromorphic chip.
3. The distributed deployment inference method for deep spiking neural networks according to claim 1, characterized in that, The target computing unit includes convolutional layers and / or pooling layers.
4. The distributed deployment inference method for deep spiking neural networks according to claim 1, characterized in that, The step of sequentially deploying the generative model files corresponding to several sub-neural networks onto a neuromorphic chip, so as to gradually reason about the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes: When several sub-neural networks are deployed on a single neuromorphic chip, the generative model file of the first sub-neural network is deployed on the neuromorphic chip, and the input data is input into the first sub-neural network to obtain the first output data. The neuromorphic chip is controlled to delete the first sub-neural network and deploy the generation model file of the second sub-neural network on the neuromorphic chip, and input the first output data into the second sub-neural network to obtain the second output data; This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
5. The distributed deployment inference method for deep spiking neural networks according to claim 1, characterized in that, The step of sequentially deploying the generative model files corresponding to several sub-neural networks onto a neuromorphic chip, so as to gradually reason about the input data through several sub-neural networks to obtain the output data corresponding to the input data, specifically includes: When several sub-neural networks are deployed on multiple neuromorphic chips, the generated model files of each sub-neural network are deployed on different chips respectively. Input data is fed into one of a series of neuromorphic chips that are deployed in the first sub-neural network, and the first output data is output through the first sub-neural network. The first output data is input into another chip among multiple neuromorphic chips deployed in the second sub-neural network, and the second output data is output through the second sub-neural network. This process continues until the final sub-neural network is reached, in order to obtain the output data corresponding to the input data.
6. The distributed deployment inference method for deep spiking neural networks according to claim 5, characterized in that, The neuromorphic chips deployed in each of the several sub-neural networks are different.
7. A distributed deployment inference system for a deep spiking neural network, characterized in that, The system includes: The acquisition module is used to acquire the deep spiking neural network to be deployed and split the deep spiking neural network into several sub-neural networks. In any two adjacent sub-neural networks, the output of the first sub-neural network is the input of the second sub-neural network. The compilation module is used to compile each sub-neural network in a series of sub-neural networks to obtain the corresponding generated model file for each sub-neural network. The deployment module is used to sequentially deploy the generated model files corresponding to several sub-neural networks onto the neuromorphic chip, so as to gradually reason about the input data through several sub-neural networks to obtain the output data corresponding to the input data; Specifically, compiling each sub-neural network within the plurality of sub-neural networks involves: The brain-like chip's corresponding compilation software compiles each of the several sub-neural networks. When compiling each sub-neural network, the input of the sub-neural network carries the membrane potential state, and the output of the sub-neural network carries the membrane potential state. During the compilation process of each sub-neural network, the batch size dimension and channel dimension of the input data are merged to obtain the target input data. The target input data is passed through the pulse calculation layer of the sub-neural network to obtain candidate output data. The batch size dimension and channel dimension of the candidate output data are split, and the split batch size dimension and the modulus potential state dimension are merged to obtain the reference output data. Finally, the reference output data is input into the target calculation unit of the sub-neural network to obtain the output data.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the steps in the distributed deployment inference method for deep spiking neural networks as described in any one of claims 1-6.
9. A terminal device, characterized in that, include: Processor, memory, and communication bus; the memory stores a computer-readable program that can be executed by the processor; The communication bus enables communication between the processor and the memory; When the processor executes the computer-readable program, it implements the steps in the distributed deployment inference method for a deep spiking neural network as described in any one of claims 1-6.