Display device

Abstract

According to one aspect of the disclosure, a display device includes a display panel including a sub-pixel composed of an upper sub-pixel and a lower sub-pixel adjacent to each other by a common data line, and a data driver converting only image data corresponding to any one of even and odd gray levels among 10-bit image data into a data voltage and supplying the converted data voltage to the sub-pixel, wherein, when the data driver converts only image data of even gray levels into a data voltage and the sub-pixel displays X (X is an odd number) gray levels, the data driver supplies data voltage of X-1 gray levels to the upper sub-pixel and supplies data voltage of X+1 gray levels to the lower sub-pixel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0174685, filed with the Korean Intellectual Property Office on December 8, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of reducing the size of a data driver and lowering manufacturing costs by synthesizing the grayscale of subpixels. Background Technology

[0004] As display devices used for computer, television, or mobile phone displays, there are organic light-emitting display (OLED) devices that are self-emissive and liquid crystal display (LCD) devices that require a separate light source.

[0005] Display devices have a wide range of applications, including personal digital assistants, computer and television displays, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Meanwhile, the data driver includes a digital-to-analog converter (DAC) that converts image data, which is a digital signal input from an external source, into analog data voltages. However, in recent years, there have been issues such as the increasing bit depth of image data with increasing resolution and DAC size, as well as the increasing manufacturing cost of the data driver used to convert image data. Summary of the Invention

[0007] One objective of this disclosure is to provide a display device that increases the grayscale range to be represented by synthesizing the grayscale values ​​of two sub-pixels.

[0008] Another objective of this disclosure is to provide a display device capable of displaying 10-bit image data by synthesizing the grayscale of subpixels when using a DAC capable of converting 9-bit image data.

[0009] Another objective of this disclosure is to provide a display device that can maintain display quality while changing the DAC of the data driver to a lower specification.

[0010] Another objective of this disclosure is to provide a display device that increases the number of subpixels connected to a data line to minimize the degradation of display quality when synthesizing grayscale.

[0011] Another objective of this disclosure is to provide a display device that ensures driving time through overlapping driving between vertically adjacent subpixels.

[0012] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above can be clearly understood by those skilled in the art from the following description.

[0013] To achieve the above objectives, according to one aspect of this disclosure, a display device includes: a display panel comprising sub-pixels consisting of upper and lower sub-pixels sharing a common data line and adjacent to each other; and a data driver that converts only image data corresponding to either an even-numbered gray level or an odd-numbered gray level from 10-bit image data into data voltages and supplies the converted data voltages to the sub-pixels. Specifically, when the data driver converts only even-numbered gray-level image data into data voltages, and the sub-pixel displays a gray level X (where X is an odd number), the data driver supplies a data voltage of gray level X-1 to the upper sub-pixel and a data voltage of gray level X+1 to the lower sub-pixel. Therefore, according to this disclosure, various gray levels can be displayed by combining different gray levels displayed in the upper and lower sub-pixels, thus enabling the display of high-resolution images even using a low-specification data driver.

[0014] According to another aspect of this disclosure, a display device includes: a display panel comprising subpixels consisting of upper and lower subpixels sharing a common data line and adjacent to each other, and displaying an image based on n-bit image data (n being a natural number) input from the outside, wherein only a portion of the externally input n-bit image data is converted into m-bit image data (m being a natural number less than n) and output to the upper and lower subpixels, and the subpixels consisting of the upper and lower subpixels display a grayscale corresponding to the n-bit image data. Therefore, according to this disclosure, although only the data voltage of the m-bit image data is output to the display panel, the grayscale displayed in the upper and lower subpixels is synthesized to display a grayscale corresponding to the n-bit image data.

[0015] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0016] According to this disclosure, grayscale values ​​displayed in adjacent sub-pixels are synthesized to represent various grayscale values.

[0017] According to this disclosure, when using a DAC capable of converting up to 9-bit digital signals, the grayscale values ​​of the upper and lower subpixels are synthesized to display 10-bit image data.

[0018] According to this disclosure, the display quality of the display device can be maintained even if the DAC of the data driver is changed to a lower specification.

[0019] According to this disclosure, the number of sub-pixels connected to a data line is increased to suppress the degradation of display quality due to composite grayscale.

[0020] According to this disclosure, the overlapping-driven subpixels are connected to a single data line, ensuring sufficient driving time for each subpixel even as the number of subpixels increases.

[0021] The effects of this disclosure are not limited to those illustrated above, and many more effects are included in this specification. Attached Figure Description

[0022] The above and other aspects, features, and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figures 2A to 2B This is a schematic diagram illustrating a grayscale representation method of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 3 This is a circuit diagram of the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 4 This is a timing diagram of the driving of the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 5A and Figure 5B This is a view used to illustrate the process of inputting data voltages to the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 6 This is a circuit diagram of the upper and lower sub-pixels of a display device according to another exemplary embodiment of the present disclosure;

[0029] Figure 7 This is a timing diagram of the driving of the upper and lower sub-pixels of a display device according to another exemplary embodiment of the present disclosure;

[0030] Figure 8A This is a view used to illustrate the connection of the upper and lower sub-pixels to different light emission control signal lines;

[0031] Figure 8B This is a view used to illustrate the situation where the upper and lower sub-pixels are connected to the same light emission control signal line;

[0032] Figure 9 This is a circuit diagram of the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure;

[0033] Figure 10 This is a timing diagram showing the driving of the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure; and

[0034] Figure 11A and Figure 11B This is a view used to illustrate the process of inputting data voltages to the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0035] The advantages and features of this disclosure and its implementation methods will become clear from the exemplary embodiments described in detail below and the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0036] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0037] Even if not explicitly stated, components are interpreted as including a normal error range.

[0038] When using terms such as “on top of,” “above,” “below,” and “beside,” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used in conjunction with the terms “closely” or “directly.”

[0039] When one element or layer is placed "on" another element or layer, another layer or element can be directly inserted on the other element or between the two elements.

[0040] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be a second component under the technical concept of this disclosure.

[0041] Throughout the specification, similar reference numerals generally denote similar elements.

[0042] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, but this disclosure is not limited to the dimensions and thickness of the components shown.

[0043] Features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0044] In the following, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of description, only the display panel 110, gate driver 120, data driver 130, and timing controller 140 are shown among the various components of the display device 100.

[0046] refer to Figure 1 The display device 100 includes a display panel 110 containing a plurality of sub-pixels SP, a gate driver 120 and a data driver 130 supplying various signals to the display panel 110, and a timing controller 140 controlling the gate driver 120 and the data driver 130.

[0047] Gate driver 120 supplies scan signals to multiple scan lines SL according to multiple gate control signals GCS supplied from timing controller 140. Although in Figure 1 The diagram shows a gate driver 120 configured to be spaced apart from one side of the display panel 110, but the number of gate drivers 120 and their arrangement are not limited thereto.

[0048] The data driver 130 uses gamma voltage to convert image data RGB input from the timing controller 140 into a data voltage Vdata based on multiple data control signals DCS supplied from the timing controller 140. The data driver 130 receives gamma voltage from the gamma unit, selects the gamma voltage from the received gamma voltage that corresponds to the grayscale of the image data RGB, so as to generate the data voltage Vdata, and supplies the generated data voltage Vdata to multiple data lines DL.

[0049] Timing controller 140 aligns externally input image data (RGB) to supply the image data to data driver 130. Timing controller 140 can generate a gate control signal GCS and a data control signal DCS using synchronization signals from external inputs, such as a dot clock signal, a data enable signal, and a horizontal / vertical sync signal. Timing controller 140 supplies the generated gate control signal GCS and data control signal DCS to gate driver 120 and data driver 130, respectively, to control gate driver 120 and data driver 130.

[0050] Display panel 110 is configured to display an image to a user and includes multiple subpixels SP. In display panel 110, multiple scan lines SL and multiple data lines DL intersect each other, and the multiple subpixels SP are respectively connected to the scan lines SL and data lines DL. Furthermore, high-potential power supply voltage and low-potential power supply voltage can be supplied, as will be referred to below. Figure 3 Each of the multiple sub-pixels SP is described in more detail.

[0051] Multiple subpixels (SPs) are the smallest units that constitute an image, and several subpixels (SPs) are grouped together to form a pixel. Each of the multiple subpixels (SPs) includes a light-emitting element and pixel circuitry for driving the light-emitting element. The multiple light-emitting elements can be defined in different ways depending on the type of display panel 110. For example, when the display panel 110 is an OLED panel, the light-emitting element can be an OLED element that includes an anode, an organic light-emitting layer, and a cathode. Alternatively, light-emitting diodes (LEDs) or quantum dot light-emitting diodes (QLEDs) containing quantum dots (QDs) can be further used as light-emitting elements.

[0052] Simultaneously, based on the number of bits of the digital signal that can be converted into a data voltage Vdata in the digital-to-analog converter (DAC), the grayscale level to be displayed in the display panel 110 can be determined within a predetermined range. For example, when the DAC converts 9-bit image data RGB into an analog data voltage Vdata, the display panel 110 can display grayscale levels from 0 to 511, which can be represented by 9 bits. For example, when the DAC converts 10-bit image data RGB into an analog data voltage Vdata, the display panel 110 can display grayscale levels from 0 to 1023, which can be represented by 10 bits.

[0053] At this time, the display device 100 according to an exemplary embodiment of the present disclosure can represent more gray levels than can be represented by m bits, even when using a digital-to-analog converter (DAC) capable of converting to an m-bit digital signal (m is a natural number). Specifically, when the image data RGB input from the outside to the display device 100 is n-bit image data RGB (n is a natural number), the data driver 130 includes a DAC capable of converting to an m-bit digital signal (m is a natural number less than n). In this case, only a portion of the n-bit image data RGB is converted to m-bit image data RGB and supplied to the data driver 130 and the sub-pixel SP for conversion of the data voltage Vdata in the data driver 130. Furthermore, the gray levels represented in each sub-pixel SP are synthesized to represent more gray levels than can be represented by m bits. For example, when the DAC is capable of converting up to 9 bits of digital signal to an analog data voltage Vdata, the gray levels displayed in the sub-pixel SP are synthesized to represent more gray levels than 0 gray levels to 511 gray levels. Therefore, the display device 100 according to an exemplary embodiment of the present disclosure can display various grayscale images without using a high-specification digital-to-analog converter (DAC) that converts digital signals with more bits, and can reduce the size of the data driver 130 and lower its cost.

[0054] At this point, in order to synthesize the grayscale of multiple subpixels SP without reducing the resolution of the display panel 110, each subpixel SP consists of a pair of upper and lower subpixels. Only a portion of the n-bit image data RGB input from the outside is converted into m-bit image data RGB and output to each of the upper and lower subpixels. The subpixel SP composed of the upper and lower subpixels synthesizes the grayscale of the upper and lower subpixels to display the grayscale corresponding to the n-bit image data.

[0055] Since a subpixel SP is composed of an upper subpixel and a lower subpixel to synthesize grayscale and increase the overall number of subpixel SPs, the upper and lower subpixels are driven in an overlapping manner to ensure the driving time of each subpixel SP. This will be described in detail below.

[0056] In the following text, for ease of description, it is assumed that the digital-to-analog converter (DAC) converts 9-bit image data RGB, and the display panel 110 displays gray levels from 0 to 1023 that can be represented by 10 bits, but is not limited thereto.

[0057] Next, we will refer to Figure 2A and Figure 2B This describes a driving method for displaying various gray levels by synthesizing the gray levels of two sub-pixels SP.

[0058] Figure 2A and Figure 2BThis is a schematic diagram illustrating a grayscale representation method of a display device according to an exemplary embodiment of the present disclosure.

[0059] refer to Figure 2A The 10-bit image data RGB is input from an external source to the timing controller 140. The timing controller 140 converts the 10-bit image data RGB to 9-bit image data RGB and supplies the converted 9-bit image data RGB to the digital-to-analog converter DAC of the data driver 130.

[0060] At this point, 9-bit image data RGB, which only represents gray levels 0 to 511, cannot represent gray levels 0 to 1023. However, a display device 100 according to an exemplary embodiment of this disclosure may represent only the even or odd gray levels from gray levels 0 to 1023 as gray levels 0 to 511 of a 9-bit signal. For example, each of the even gray levels 0, 2, 4, ..., 1020 and 1022 from gray levels 0 to 1023 can match each of the gray levels 0 to 511 of the 9-bit image data RGB. In the gray levels 0 to 1023, there are a total of 512 even gray levels and a total of 512 odd gray levels. Therefore, 9-bit image data RGB, representing 512 gray levels from 0 to 511 gray levels, can represent either 512 even gray levels or 512 odd gray levels. Each of the 512 even or 512 odd gray levels corresponding to 0 to 1023 gray levels in 10-bit image data RGB is converted to each of the 0 to 511 gray levels in 9-bit image data RGB and output to data driver 130. Therefore, timing controller 140 converts externally input 10-bit image data into 9-bit image data RGB and supplies the converted 9-bit image data to data driver 130.

[0061] However, 10-bit image data RGB is supplied from timing controller 140 to data driver 130, and the 10-bit image data RGB is converted into 9-bit image data RGB in data driver 130 to be supplied to digital-to-analog converter DAC, but is not limited thereto.

[0062] Therefore, among the gray levels from 0 to 1023 represented by 10 bits, only odd or even gray levels are converted into 9-bit image data RGB to be supplied to the data driver 130, and the digital-to-analog converter DAC can convert the 9-bit image data RGB into analog data voltage Vdata.

[0063] For ease of description, it is assumed that the even gray levels in the 10-bit image data RGB match the 9-bit image data RGB.

[0064] Simultaneously, each of the multiple sub-pixels SP can be composed of an upper sub-pixel SPPa and a lower sub-pixel SPb to synthesize grayscale. The grayscale values ​​of adjacent upper sub-pixels SPPa and lower sub-pixels SPb are synthesized to represent grayscale levels from 0 to 1023.

[0065] The upper subpixel Spa and the lower subpixel SPb are connected to the same data line DL and are set to be adjacent to each other. The upper subpixel Spa is the subpixel that receives the data voltage Vdata before the lower subpixel SPb, and the lower subpixel SPb is the subpixel that receives the data voltage Vdata after the upper subpixel Spa. The upper subpixel Spa and the lower subpixel SPb are subpixels that emit light of the same color, and even gray levels and odd gray levels can be represented using the gray levels represented by each of the upper subpixel Spa and the lower subpixel SPb.

[0066] refer to Figure 2A When X is an even number of gray levels, the image data RGB representing the X gray level can be input to a digital-to-analog converter (DAC). The DAC converts the image data representing the X gray level into an analog data voltage Vdata and supplies the converted analog data voltage Vdata to each of the multiple sub-pixels SP. The data voltage Vdata for displaying the X gray level can be input from the DAC to the upper sub-pixel SPa and the lower sub-pixel SPb. Therefore, both the upper sub-pixel SPa and the lower sub-pixel SPb represent the X gray level, allowing an image of the X gray level to be displayed on the display device 100.

[0067] refer to Figure 2B When X is an odd number of gray levels, gray levels smaller than X and larger than X can be displayed in the upper sub-pixel SPb and the lower sub-pixel SPb, respectively, to display gray level X.

[0068] First, the 9-bit signal that can be converted by the digital-to-analog converter (DAC) includes gray levels 0 to 511, and gray levels 0 to 511 only match even gray levels from 0 to 1023. Therefore, gray levels 0 to 511 of the 9-bit signal transmitted to the DAC cannot convert the odd-numbered gray level X into the analog data voltage Vdata. Therefore, the 9-bit signal corresponding to gray levels X-1 (less than X) and X+1 (greater than X) can be supplied to the DAC. In other words, instead of the odd-numbered gray levels of the RGB image data to be displayed, even-numbered gray levels before and after the odd-numbered gray levels of the RGB image data can be supplied to the DAC.

[0069] The digital-to-analog converter (DAC) outputs the data voltage Vdata for grayscale level X-1 to the upper sub-pixel SPa. The DAC also outputs the data voltage Vdata for grayscale level X+1 to the lower sub-pixel SPb. Since the upper sub-pixel SPa displays grayscale level X-1 and the lower sub-pixel SPb displays grayscale level X+1, the X-1 and X+1 grayscale levels are combined to display grayscale level X. For example, when displaying 9 grayscale levels, the DAC outputs the data voltage Vdata corresponding to grayscale level 8 to the upper sub-pixel SPa. Furthermore, the DAC can output the data voltage Vdata corresponding to grayscale level 10 to the lower sub-pixel SPb. Finally, the 8 grayscale level of the upper sub-pixel SPa and the 10 grayscale level of the lower sub-pixel SPb are combined, resulting in a single sub-pixel SP displaying 9 grayscale levels.

[0070] Conversely, when the digital-to-analog converter (DAC) is designed to output only the data voltage Vdata for odd-numbered gray levels, even-numbered and odd-numbered gray levels can be represented using the same method described above. Specifically, when representing odd-numbered gray levels, the DAC outputs the data voltage Vdata for the odd-numbered gray levels to the upper sub-pixel SPa and the lower sub-pixel SPb. When representing even-numbered gray levels, the DAC outputs the data voltage Vdata for odd-numbered gray levels that is smaller than the even-numbered gray levels to the upper sub-pixel SPa, and outputs the data voltage Vdata for odd-numbered gray levels that is larger than the even-numbered gray levels to the lower sub-pixel SPb.

[0071] Therefore, when the display device 100 according to an exemplary embodiment of the present disclosure uses a digital-to-analog converter (DAC) capable of converting 9-bit image data RGB, in order to display 10-bit image data RGB, it outputs a data voltage Vdata for either the even-numbered gray levels from 0 gray level to 1023 gray level. Furthermore, the gray levels of each of the upper sub-pixel SPa and the lower sub-pixel SPb are synthesized to represent all gray levels from 0 gray level to 1023 gray level of the 10-bit image data RGB.

[0072] Meanwhile, even and odd gray levels are represented by synthesizing the gray levels of the upper sub-pixel SPa and the lower sub-pixel SPb. Therefore, it is necessary to increase the number of sub-pixels SP connected to a single data line DL to achieve the image quality of the related technology. If a digital-to-analog converter (DAC) capable of converting 10-bit digital signals is used, a single sub-pixel SP can display one of the gray levels from 0 to 1023. However, as in the display device 100 according to an exemplary embodiment of this disclosure, when the DAC represents gray levels from 0 to 1023 corresponding to 10-bit image data RGB, the upper sub-pixel SPa and the lower sub-pixel SPb represent the same gray level. Therefore, the display quality is not degraded only when the number of sub-pixels SP connected to a single data line DL is doubled.

[0073] However, when the number of sub-pixels SP or scan lines connected to a single data line DL is doubled, the scan signal output time and the time for inputting signals to each of the multiple sub-pixels SP inevitably decrease in order to maintain the driving speed of the display device 100. Therefore, it may be difficult to perform internal compensation for each sub-pixel SP. Therefore, in a display device 100 according to an exemplary embodiment of this disclosure, the upper sub-pixel SPa and the lower sub-pixel SPb are driven in an overlapping manner to ensure that the driving time required to input various signals to each of the multiple sub-pixels SP and to compensate for various deviations is sufficient.

[0074] In the following text, reference will be made to Figures 3 to 5B Describe in detail the driving method for multiple sub-pixels (SPs).

[0075] Figure 3 This is a circuit diagram of the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 4 This is a timing diagram of the driving of the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 4 In such Figure 2B The diagram shows the timing sequence when synthesizing grayscale values ​​greater than a specific grayscale and grayscale values ​​less than that specific grayscale to represent that specific grayscale. In other words, Figure 4 This is a timing diagram showing the input of the lower grayscale data voltage LVdata to the upper sub-pixel SPPa and the input of the upper grayscale data voltage HVdata to the lower sub-pixel SPb.

[0076] refer to Figure 3A subpixel SP comprises an upper subpixel SPA and a lower subpixel SPb. The upper subpixel SPA and the lower subpixel SPb are connected to a data line DL and are positioned adjacent to each other. The upper subpixel SPA may be charged with a data voltage Vdata before the lower subpixel SPb. The grayscale values ​​displayed in each of the upper and lower subpixels SPA and SPb are composited to represent grayscale levels from 0 to 1023.

[0077] In the following text, for ease of description, it is assumed that the upper sub-pixel SPPa is set in row n and the lower sub-pixel SPb is set in row n+1.

[0078] Each of the upper sub-pixel Spa in the nth row and the lower sub-pixel SPb in the (n+1)th row is connected to the scan line SL, the light emission control signal line EM, the initialization line, the data line DL, the high-potential power supply line, and the low-potential power supply line. Furthermore, each of the upper sub-pixel Spa and the lower sub-pixel SPb is provided with a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a driving transistor DTR, a storage capacitor Cst, and a light-emitting diode EL.

[0079] First, the driving transistor DTR for the upper sub-pixel SPa in the nth row includes a gate, a source, and a drain. The gate is connected to the second node N2, the source is connected to the first node N1, and the drain is connected to the third node N3. The driving transistor DTR can control the driving current flowing in the light-emitting diode EL.

[0080] The first transistor TR1 includes a gate, a source, and a drain. The gate of the first transistor TR1 is connected to the scan line SL(n) of the nth row, the source is connected to the second node N2, and the drain is connected to the third node N3. The first transistor TR1 is turned on to connect the second node N2 and the third node N3.

[0081] The second transistor TR2 includes a gate, a source, and a drain. The gate of the second transistor TR2 is connected to the scan line SL(n) of the nth row, the source is connected to the data line DL, and the drain is connected to the first node N1. The second transistor TR2 transmits the data voltage Vdata from the data line DL to the first node N1 based on the scan signal of the scan line SL(n) of the nth row.

[0082] The third transistor TR3 includes a gate, a source, and a drain. The gate of the third transistor TR3 is connected to the light-emitting control signal line EM(n) in the nth row, the source is connected to the high-potential power supply line, and the drain is connected to the first node N1. The third transistor TR3 can transmit the high-potential power supply voltage VDD to the first node N1 based on the light-emitting control signal of the light-emitting control signal line EM(n) in the nth row.

[0083] The fourth transistor TR4 includes a gate, a source, and a drain. The gate of the fourth transistor TR4 is connected to the light-emitting control signal line EM(n) in the nth row, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The fourth transistor TR4 can transfer drive current from the driving transistor DTR to the light-emitting diode EL based on the light-emitting control signal of the light-emitting control signal line EM(n) in the nth row.

[0084] The fifth transistor TR5 includes a gate, a source, and a drain. The gate of the fifth transistor TR5 is connected to the scan line SL(n-2) in the (n-2)th row, the source is connected to the initialization line, and the drain is connected to the second node N2. The fifth transistor TR5 can reset the second node N2 to the initialization voltage Vini from the initialization line based on the scan signal of the scan line SL(n-2) in the (n-2)th row.

[0085] The sixth transistor TR6 includes a gate, a source, and a drain. The gate of the sixth transistor TR6 is connected to the scan line SL(n) of the nth row, the source is connected to the initialization line, and the drain is connected to the fourth node N4. The sixth transistor TR6 can reset the fourth node N4 to the initialization voltage Vini from the initialization line based on the scan signal of the scan line SL(n) of the nth row.

[0086] The storage capacitor Cst comprises multiple capacitor electrodes. A portion of these electrodes are connected to a high-potential power supply line, while the others are connected to a second node N2. A data voltage Vdata, compensated by the threshold voltage Vth of the driving transistor DTR, is charged into the storage capacitor Cst to sample the data voltage Vdata and compensate for deviations in the driving transistor DTR of each of the multiple sub-pixels SP.

[0087] The light-emitting diode (LED) EL includes a first electrode and a second electrode. The first electrode of the LED EL is connected to the fourth node N4, and the second electrode is connected to the low-potential power line supplied with a low-potential power supply voltage VSS. The LED EL can emit light through the drive current from the driving transistor DTR.

[0088] Except that the lower sub-pixel SPb in row n+1 is connected to the scan line SL(n-1) in row n-1, the scan line SL(n+1) in row n+1, and the light emission control signal line EM(n+1) in row n+1, the other configurations of the lower sub-pixel SPb in row n+1 are basically the same as those of the upper sub-pixel SPa in row n.

[0089] Specifically, the gate of each of the first transistor TR1, the second transistor TR2, and the sixth transistor TR6 of the lower sub-pixel SPb is connected to the scan line SL(n+1) of the (n+1)th row. The gate of the fifth transistor TR5 is connected to the scan line SL(n-1) of the (n-1)th row, and the gate of the fourth transistor TR4 is connected to the light emission control signal line EM(n+1) of the (n+1)th row.

[0090] Let's refer to each other. Figure 4 A low-level scan signal is output to scan line SL(n-2) of row n-2 at the first time t1. The fifth transistor TR5 of the upper sub-pixel SPa can be turned on by the scan signal of scan line SL(n-2) of row n-2. The gate of the second node N2 of the upper sub-pixel SPa and the driving transistor DTR can be initialized to the initialization voltage Vini by the turned-on fifth transistor TR5.

[0091] Next, a low-level scan signal is output to scan line SL(n-1) of row n-1 at time t2. The fifth transistor TR5 of the lower sub-pixel SPb can be turned on by the scan signal of scan line SL(n-1) of row n-1. Therefore, the gate of the second node N2 of the lower sub-pixel SPb and the driving transistor DTR can be initialized to the initialization voltage Vini from time t2.

[0092] A low-level scan signal is output to the scan line SL(n) of the nth row at the third time t3. Therefore, the first transistor TR1, the second transistor TR2, and the sixth transistor TR6 connected to the upper sub-pixel SPa of the scan line SL(n) of the nth row can be turned on.

[0093] The low grayscale data voltage LVdata can be transmitted from the data line DL to the first node N1 of the upper sub-pixel SPa through the conducting second transistor TR2 at the third time t3. At this time, the output low grayscale data voltage LVdata is as referenced. Figure 2B The described digital-to-analog converter (DAC) outputs the data voltage Vdata to the upper sub-pixel SPa.

[0094] The gate and drain of the driving transistor DTR are shorted through the conducting first transistor TR1 to form a diode connection. At this time, the low-grayscale data voltage LVdata, transmitted through the second transistor TR2, is transferred to the driving transistor DTR, causing the voltage at the second node N2 to change from the initialization voltage Vini to the sum of the low-grayscale data voltage LVdata and the threshold voltage Vth. In other words, the low-grayscale data voltage LVdata charges the upper sub-pixel SPa, and then the upper sub-pixel SPa can emit light of a grayscale corresponding to the low-grayscale data voltage LVdata.

[0095] The voltage at the fourth node N4 can be reset to the initial voltage Vini from the initialization line by the conducting sixth transistor TR6.

[0096] Next, a low-level scan signal is output to the scan line SL(n+1) of the (n+1)th row at the fourth time t4, which enables the first transistor TR1, the second transistor TR2, and the sixth transistor TR6 of the lower sub-pixel SPb to conduct.

[0097] The low grayscale data voltage LVdata can be transmitted from the data line DL to the first node N1 of the lower sub-pixel SPb through the conducting second transistor TR2. At this time, the output low grayscale data voltage LVdata is the voltage corresponding to the grayscale to be displayed in the upper sub-pixel SPa. That is to say, from the fourth time t4 to the fifth time t5, the low grayscale data voltage LVdata charged into the upper sub-pixel SPa can also be charged into the lower sub-pixel SPb.

[0098] Starting from time t5, the digital-to-analog converter (DAC) outputs a high grayscale data voltage HVdata corresponding to the grayscale to be displayed in the lower sub-pixel SPb. At this time, even if the high grayscale data voltage HVdata is output to the data line DL, starting from time t5, the scan signal of the scan line SL(n) of the nth row becomes high, causing the second transistor TR2 of the upper sub-pixel SPa to be turned off, and then the high grayscale data voltage HVdata is not transmitted to the upper sub-pixel SPa.

[0099] After time t5, the high grayscale data voltage HVdata corresponding to the grayscale to be displayed in the lower sub-pixel SPb begins to charge only into the lower sub-pixel SPb. From time t4 to time t5, the same low grayscale data voltage LVdata charges the gate of the driving transistor DTR in both the lower sub-pixel SPb and the upper sub-pixel SPa. Starting from time t5, the high grayscale data voltage HVdata can charge only into the gate of the driving transistor DTR in the lower sub-pixel SPb.

[0100] In summary, from time t3 to time t5, the low grayscale data voltage LVdata is charged into the upper sub-pixel SPb and the lower sub-pixel SPb. Furthermore, from time t5 to time t6, overlapping driving of the lower sub-pixel SPb by charging it with the high grayscale data voltage HVdata can be performed. From time t5 to time t6, the gate voltage of the driving transistor DTR of the lower sub-pixel SPb can be increased from the sum of the low grayscale data voltage LVdata and the threshold voltage Vth to the sum of the high grayscale data voltage HVdata and the threshold voltage Vth.

[0101] Next, when the charging of the low grayscale data voltage LVdata in the upper sub-pixel SPPa and the high grayscale data voltage HVdata in the lower sub-pixel SPb is complete, the light emission control signal is output to each of the upper sub-pixel SPPa and the lower sub-pixel SPb to make the light-emitting diode EL emit light.

[0102] Specifically, a low-level light emission control signal is output to the light emission control signal line EM(n) of the nth row at time t7. The fourth transistor TR4 of the upper sub-pixel SPa can be turned on by the light emission control signal, and the driving current can flow to the light-emitting diode EL through the turned-on fourth transistor TR4. Therefore, in the upper sub-pixel SPa, the light-emitting diode EL starts to emit light from time t7, enabling it to represent the gray level corresponding to the low grayscale data voltage LVdata.

[0103] Next, a low-level light emission control signal is output to the light emission control signal line EM(n+1) of the (n+1)th row at time t8. The fourth transistor TR4 of the lower sub-pixel SPb is turned on by the light emission control signal to transfer the drive current to the light-emitting diode EL. Therefore, in the lower sub-pixel SPb, the light-emitting diode EL starts emitting light from time t8, enabling the representation of grayscale corresponding to the high grayscale data voltage HVdata.

[0104] Meanwhile, in a display device 100 according to an exemplary embodiment of the present disclosure, when two different grayscale values ​​are synthesized, the upper sub-pixel Spa is charged with a low grayscale data voltage LVdata, and the lower sub-pixel SPb is charged with a high grayscale data voltage HVdata. In the upper sub-pixel Spa and the lower sub-pixel SPb, which share a single data line DL, the charging times of the data voltage (Vdata) can partially overlap through overlapping driving. When the high grayscale data voltage HVdata is charged into the upper sub-pixel Spa, which was charged with data voltage Vdata earlier, it is difficult for the low grayscale data voltage LVdata to be charged into the lower sub-pixel SPb, which was charged with data voltage Vdata later. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the low grayscale data voltage LVdata is charged into the upper sub-pixel Spa, which was charged with data voltage Vdata earlier, and the high grayscale data voltage HVdata is charged into the lower sub-pixel SPb, which was charged later. In this way, the data voltage Vdata can be charged normally into the upper sub-pixel Spa and the lower sub-pixel SPb, which will refer to... Figure 5A and Figure 5B To describe in more detail.

[0105] Figure 5A and Figure 5B This is a view used to illustrate the process of inputting data voltages to the upper and lower sub-pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 5AThis is a view used to illustrate the process of inputting high grayscale data voltage HVdata to the upward sub-pixel SPB and low grayscale data voltage LVdata to the downward sub-pixel SPb. Figure 5B This is a view used to illustrate the process of inputting low grayscale data voltage LVdata to the upward sub-pixel SPPa and high grayscale data voltage HVdata to the downward sub-pixel SPb.

[0106] Let's refer to each other. Figure 3 , Figure 4 and Figure 5A At time t3, the first transistor TR1 of the upper sub-pixel SPa is turned on by the scan signal of the scan line SL(n) of the nth row. In the driving transistor DTR of the upper sub-pixel SPa, the gate and drain can be connected through the turned-on first transistor TR1.

[0107] When the high grayscale data voltage HVdata is applied to the upper sub-pixel SPa, the gate voltage of the driving transistor DTR can be increased from the initialization voltage Vini to the sum of the high grayscale data voltage HVdata and the threshold voltage Vth. Charging can continue at the high grayscale data voltage HVdata until the difference between the gate-source voltage Vgs and the threshold voltage Vth of the driving transistor DTR becomes zero. In other words, the high grayscale data voltage HVdata can be applied until the gate voltage of the driving transistor DTR becomes the sum of the high grayscale data voltage HVdata and the threshold voltage Vth.

[0108] Next, at the fourth time t4, the first transistor TR1 of the lower sub-pixel SPb is turned on by the scan signal of the scan line SL(n+1) of the n+1th row, and the gate and drain of the driving transistor DTR are connected through the first transistor TR1 to be in a diode connection state as a diode.

[0109] At this time, at the fourth time t4, the high grayscale data voltage HVdata can also be applied to the lower sub-pixel SPb. From the fourth time t4 to the fifth time t5, the high grayscale data voltage HVdata is applied to the lower sub-pixel SPb, so that the gate voltage of the driving transistor DTR can increase from the initial voltage Vini to the sum of the high grayscale data voltage HVdata and the threshold voltage Vth.

[0110] Next, starting from time t5, the low grayscale data voltage LVdata can be applied to the lower sub-pixel SPb. Only when the gate voltage of the driving transistor DTR changes from the sum of the high grayscale data voltage HVdata and the threshold voltage Vth to the sum of the low grayscale data voltage LVdata and the threshold voltage Vth, can the lower sub-pixel SPb represent the grayscale corresponding to the low grayscale data voltage LVdata.

[0111] However, the gate voltage of the driving transistor DTR is already charged with the sum of the high grayscale data voltage HVdata and the threshold voltage Vth. Therefore, when the low grayscale data voltage LVdata is applied to the source of the driving transistor DTR, the difference between the gate-source voltage Vgs and the threshold voltage Vth may be greater than 0. In this case, the driving transistor DTR of the lower sub-pixel SPb is turned off, causing the data voltage Vdata compensated by the threshold voltage Vth of the driving transistor DTR to not be properly charged into the storage capacitor Cst, and it may not be able to properly compensate for the deviation of the lower sub-pixel SPb.

[0112] Therefore, when the high grayscale data voltage HVdata is first supplied to the upper sub-pixel SPb and the lower sub-pixel SPb, and the low grayscale data voltage LVdata is supplied to the lower sub-pixel SPb after a pre-time interval, the driving transistor DTR of the lower sub-pixel SPb is turned off. This may fail to compensate for the deviation in the threshold voltage Vth, and the low grayscale data voltage LVdata may not be properly input to the lower sub-pixel SPb.

[0113] Conversely, refer to Figure 5B According to an exemplary embodiment of the present disclosure, the display device 100 charges the upper sub-pixel SPPa and the lower sub-pixel SPb with a low grayscale data voltage LVdata. In this case, the gate voltage of the driving transistor DTR of each of the upper sub-pixel SPPa and the lower sub-pixel SPb can be changed from the initialization voltage Vini to the sum of the low grayscale data voltage LVdata and the threshold voltage Vth.

[0114] Next, starting from time t5, the high grayscale data voltage HVdata is supplied to the lower sub-pixel SPb. The gate voltage of the driving transistor DTR of the lower sub-pixel SPb can change from the sum of the low grayscale data voltage LVdata and the threshold voltage Vth to the sum of the high grayscale data voltage HVdata and the threshold voltage Vth. In this case, the high grayscale data voltage HVdata is input to the source of the driving transistor DTR, making the difference between the gate-source voltage Vgs and the threshold voltage Vth of the driving transistor DTR less than 0. Therefore, when the high grayscale data voltage HVdata is input, the driving transistor DTR can remain continuously turned on.

[0115] Therefore, the driving transistor DTR of the lower sub-pixel SPb can remain on until the gate voltage becomes the sum of the high grayscale data voltage HVdata and the threshold voltage Vth. The data voltage Vdata, after threshold voltage Vth compensation, can then be properly charged into the storage capacitor Cst.

[0116] Therefore, when the low grayscale data voltage LVdata is input to the upper sub-pixel SPPa and the high grayscale data voltage HVdata is input to the lower sub-pixel SPb, the overlap driving of the upper sub-pixel SPPa and the lower sub-pixel SPb is possible, and the internal compensation of the upper sub-pixel SPPa and the lower sub-pixel SPb can be performed normally.

[0117] Therefore, the display device 100 according to an exemplary embodiment of this disclosure synthesizes the gray levels displayed in each of the upper sub-pixel SPa and the lower sub-pixel SPb to represent more gray levels than the number of bits that the digital-to-analog converter (DAC) can convert. Specifically, when using a DAC capable of converting 9-bit image data RGB, only gray levels 0 to 511 can be displayed. However, each of the 9-bit gray levels 0 to 511 can be set to an even or odd gray level corresponding to the 0 to 1023 gray levels of 10-bit image data RGB. If an even gray level from 0 to 1023 matches each of the 9-bit gray levels 0 to 511, the 9-bit signal is converted as is to a data voltage Vdata, which is then output to the sub-pixel SP to display the even gray level. When displaying an odd number of gray levels, an even number of gray levels smaller than the odd number of gray levels is displayed in the upper sub-pixel Spa, and an even number of gray levels larger than the odd number of gray levels can be displayed in the lower sub-pixel SPb. Therefore, the gray levels of the upper sub-pixel Spa and the lower sub-pixel SPb are combined to display an odd number of gray levels. Thus, in the display device 100 according to an exemplary embodiment of the present disclosure, although a digital-to-analog converter (DAC) capable of converting 9-bit digital signals is used, the gray levels of the upper sub-pixel Spa and the lower sub-pixel SPb are combined to easily display 10-bit image data RGB.

[0118] In a display device 100 according to an exemplary embodiment of the present disclosure, the overlapping driving of the upper sub-pixel SPa and the lower sub-pixel SPb enables the synthesis of grayscale and ensures the driving time of each sub-pixel SP. To display intermediate grayscale by synthesizing even and odd grayscale levels, a sub-pixel SP can be composed of an upper sub-pixel SPa and a lower sub-pixel SPb. In this case, the number of sub-pixel SPs connected to a single data line DL is doubled, but the driving time given to each sub-pixel SP is inevitably reduced. Therefore, the time required for internal compensation of deviations in each sub-pixel SP can be ensured by the overlapping driving of the upper sub-pixel SPa and the lower sub-pixel SPb. During the overlapping driving, the time period during which the data voltage Vdata is input to the upper sub-pixel SPa can partially overlap with the time period during which the data voltage Vdata is input to the lower sub-pixel SPb. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the overlapping driving of the upper sub-pixel SPa and the lower sub-pixel SPb ensures that the signal is input to each of the plurality of sub-pixels SP and the driving time required for compensation of deviations.

[0119] In a display device 100 according to an exemplary embodiment of the present disclosure, when different grayscale values ​​are synthesized, a low grayscale data voltage LVdata is input to the upper sub-pixel SPa of a sub-pixel SP, and a high grayscale data voltage HVdata is input to the lower sub-pixel SPb. This allows for internal compensation of one sub-pixel SP. Initially, the time periods of the input data voltages Vdata to the upper sub-pixel SPa and the lower sub-pixel SPb partially overlap. For example, from time t4 to time t5, the low grayscale data voltage LVdata is input to both the upper sub-pixel SPa and the lower sub-pixel SPb. Starting from time t5, only the high grayscale data voltage HVdata is input to the lower sub-pixel SPb. At this time, when the high grayscale data voltage HVdata is first input to the upper sub-pixel SPa, the gate voltage of the driving transistor DTR of each of the upper sub-pixel SPa and the lower sub-pixel SPb can be charged by the sum of the high grayscale data voltage HVdata and the threshold voltage Vth. When the low grayscale data voltage LVdata is input to the lower sub-pixel SPb, the difference between the voltage Vgs between the gate and source of the driving transistor DTR of the lower sub-pixel SPb and the threshold voltage Vth is greater than 0, which may cause the driving transistor DTR to be turned off. Therefore, the data voltage Vdata compensated by the threshold voltage Vth may not be properly charged into the storage capacitor Cst. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the low grayscale data voltage LVdata is charged into the upper sub-pixel SPa, and the high grayscale data voltage HVdata is charged into the lower sub-pixel SPb. Therefore, the upper sub-pixel SPa and the lower sub-pixel SPb can be driven normally.

[0120] Figure 6This is a circuit diagram of the upper and lower sub-pixels of a display device according to another exemplary embodiment of the present disclosure. Figure 7 This is a timing diagram of the driving of the upper and lower sub-pixels of a display device according to another exemplary embodiment of the present disclosure. Figure 8A This is a view used to illustrate the connection of the upper and lower sub-pixels to different light emission control signal lines. Figure 8B This is a view used to illustrate the situation where the upper and lower sub-pixels are connected to the same light emission control signal line. Figure 6 and Figure 7 The display device 600 and Figures 1 to 4 The only difference between the display devices 100 is the light emission control signal line EM(n / n+1), but the other configurations are basically the same, so repeated descriptions will be omitted.

[0121] refer to Figure 6 The upper sub-pixel SPPa and the lower sub-pixel SPb are connected to the same common light emission control signal line EM(n / n+1). Each of the fourth transistor TR4 of the upper sub-pixel SPPa and the fourth transistor TR4 of the lower sub-pixel SPb can be simultaneously turned on based on the light emission control signal from the common light emission control signal line EM(n / n+1). The upper sub-pixel SPPa and the lower sub-pixel SPb are connected to the common light emission control signal line EM(n / n+1) to emit light simultaneously.

[0122] refer to Figure 7 At time t7, a low-level light emission control signal is applied to the common light emission control signal line EM(n / n+1). In this case, the LEDs EL of both the upper sub-pixel SPPa and the lower sub-pixel SPb can start emitting light from time t7. Therefore, the upper sub-pixel SPPa and the lower sub-pixel SPb can emit light simultaneously by sharing a single common light emission control signal line EM(n / n+1).

[0123] Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, the upper sub-pixel SPPa and the lower sub-pixel SPb share a common light emission control signal line EM(n / n+1) to simplify the structure of the display device 600.

[0124] Specifically, refer to Figure 8A and Figure 8B The light emission control signals output to the light emission control lines can be generated from the light emission control drivers EST connected to each light emission control signal line. Each of the multiple light emission control drivers EST can be formed by multiple transistors and storage capacitors, and outputs light emission control signals sequentially. However, as the number of multiple light emission control drivers EST increases, the structure of the display device 600 becomes more complex, and the bezel area may increase.

[0125] For example, refer to Figure 8A Each of the upper sub-pixels SPa and lower sub-pixels SPb can be connected to a different light-emitting control driver EST. The upper sub-pixel SPa in row n-2 is connected to the light-emitting control driver EST in row n-2. The lower sub-pixel SPb in row n-1 can be connected to the light-emitting control driver EST in row n-1. The upper sub-pixel SPa in row n is connected to the light-emitting control driver EST in row n. The lower sub-pixel SPb in row n+1 can be connected to the light-emitting control driver EST in row n+1. In summary, the light-emitting control drivers EST are configured to correspond to each of rows n-2, n-1, n, and n+1 to drive multiple sub-pixels SP.

[0126] Conversely, refer to Figure 8B In a display device 600 according to another exemplary embodiment of the present disclosure, the upper sub-pixel SPPa and the lower sub-pixel SPb can be connected to a light-emitting control driver EST. The upper sub-pixel SPPa in the (n-2)th row and the lower sub-pixel SPb in the (n-1)th row are connected to a light-emitting control driver EST. The upper sub-pixel SPPa in the nth row and the lower sub-pixel SPb in the (n+1)th row are connected to a light-emitting control driver EST. In this case, adjacent upper sub-pixels SPPa and lower sub-pixels SPb share the light-emitting control driver EST, thereby reducing the number of light-emitting control drivers EST and simplifying the structure of the display device 600.

[0127] Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, a pair of upper sub-pixels SPa and lower sub-pixels SPb share a common light emission control signal line EM(n / n+1), thereby reducing the number of light emission control signal lines by half. Furthermore, the number of light emission control drivers EST connected to each light emission control signal line is simplified. Thus, in a display device 600 according to another exemplary embodiment of the present disclosure, the upper sub-pixel SPa and lower sub-pixel SPb share a common light emission control signal line EM(n / n+1), thereby eliminating, for example, a portion of the configuration of the light emission control drivers EST, and simplifying the structure of the display device 600.

[0128] Figure 9 This is a circuit diagram of the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 10 This is a timing diagram of the driving of the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 11A and Figure 11B This is a view used to illustrate the process of inputting data voltages to the upper and lower sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 10 In such Figure 2BThe diagram shows the timing when a low grayscale data voltage LVdata is input to the upward sub-pixel SPB and a high grayscale data voltage HVdata is input to the downward sub-pixel SPb. Figure 11A This is a view used to illustrate the process of inputting a high grayscale data voltage HVdata to the upward sub-pixel SPB and a low grayscale data voltage LVdata to the downward sub-pixel SPb. Figure 11B This is a view used to illustrate the process of inputting a low grayscale data voltage LVdata to the upward sub-pixel SPB and a high grayscale data voltage HVdata to the downward sub-pixel SPb. Figure 9 and Figure 10 Display device 900 and Figures 1 to 4 The only difference between the display devices 100 is the circuitry of each sub-pixel SP, but the other configurations are basically the same, so repeated descriptions will be omitted.

[0129] refer to Figure 9 A subpixel SP consists of an upper subpixel SPA and a lower subpixel SPb. The upper subpixel SPA and the lower subpixel SPb are connected to a data line DL and are positioned adjacent to each other. The upper subpixel SPA can be charged with a data voltage Vdata before the lower subpixel SPb. The grayscale values ​​displayed in each of the upper and lower subpixels SPA and SPb are composited to represent grayscale levels from 0 to 1023.

[0130] For ease of description, it is assumed that the upper sub-pixel SPA is set in row n and the lower sub-pixel SPb is set in row n+1.

[0131] Each of the upper sub-pixel Spa in the nth row and the lower sub-pixel SPb in the (n+1)th row is connected to the scan line SL, the light emission control signal line, the reference line, the data line DL, the high-potential power supply line, and the low-potential power supply line. Furthermore, each of the upper sub-pixel Spa and the lower sub-pixel SPb is provided with a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a driving transistor DTR, a storage capacitor Cst, and a light-emitting diode EL.

[0132] The driving transistor DTR for the upper sub-pixel SPa in row n includes a gate, a source, and a drain. The gate is connected to the second node N2, the source is connected to the high-potential power supply line, and the drain is connected to the third node N3. The driving transistor DTR controls the driving current flowing in the light-emitting diode EL.

[0133] The first transistor TR1 includes a gate, a source, and a drain. The gate of the first transistor TR1 is connected to the first scan line SL1(n) of the nth row, the source is connected to the data line DL, and the drain is connected to the first node N1. The first transistor TR1 can transmit the data voltage Vdata from the data line DL to the first node N1 based on the scan signal of the first scan line SL1(n) of the nth row.

[0134] The second transistor TR2 includes a gate, a source, and a drain. The gate of the second transistor TR2 is connected to the second scan line SL2(n) of the nth row, the source is connected to the second node N2, and the drain is connected to the third node N3. The second transistor TR2 is turned on to connect between the gate and drain of the driving transistor DTR, that is, between the second node N2 and the third node N3.

[0135] The third transistor TR3 includes a gate, a source, and a drain. The gate of the third transistor TR3 is connected to the light-emitting control signal line EM(n) in the nth row, and the source and drain are connected between the first node N1 and the reference line. The third transistor TR3 is turned on by the light-emitting control signal to supply the reference voltage Vref to the first node N1.

[0136] The fourth transistor T4 includes a gate, a source, and a drain. The gate of the fourth transistor T4 is connected to the light-emitting control signal line EM(n) in the nth row, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The fourth transistor T4 is turned on by the light-emitting control signal to transfer the drive current from the driving transistor DTR to the light-emitting diode EL.

[0137] The fifth transistor TR5 includes a gate, a source, and a drain. The gate of the fifth transistor TR5 is connected to the second scan line SL2(n) of the nth row, and the source and drain are connected between the reference line and the fourth node N4. The fifth transistor TR5 can transmit the reference voltage Vref to the fourth node N4 based on the scan signal of the second scan line SL2(n) of the nth row.

[0138] The storage capacitor Cst includes multiple capacitive electrodes connected to each of the first node N1 and the second node N2. The storage capacitor Cst can continuously maintain the data voltage Vdata supplied through the first transistor TR1 for one frame. The storage capacitor Cst can continuously maintain the voltage Vgs between the gate and source of the driving transistor DTR.

[0139] The light-emitting diode (LED) EL includes a first electrode and a second electrode. The first electrode of the LED EL is connected to the fourth node N4, and the second electrode is connected to the low-potential power supply voltage VSS. The LED EL can emit light through a drive current from the driving transistor DTR.

[0140] Except that the lower sub-pixel SPb is connected to the first scan line SL1(n+1) of the n+1th row, the second scan line SL2(n+1) of the n+1th row, and the light emission control signal line EM(n+1) of the n+1th row, the other configurations of the lower sub-pixel SPb are basically the same as those of the upper sub-pixel SPa.

[0141] Specifically, the gate of the first transistor TR1 of the lower sub-pixel SPb is connected to the first scan line SL1(n+1) of the (n+1)th row, and the gates of the second transistor TR2 and the fifth transistor TR5 are connected to the second scan line SL2(n+1) of the (n+1)th row. In addition, the gates of the third transistor TR3 and the fourth transistor TR4 are connected to the light emission control signal line EM(n+1) of the (n+1)th row.

[0142] Let's refer to each other. Figure 9 The upper sub-pixel SPPa and the lower sub-pixel SPb can be driven in an overlapping manner. During the overlapping drive, the period during which the data voltage Vdata is supplied to the upper sub-pixel SPPa can partially overlap with the period during which the data voltage Vdata is supplied to the lower sub-pixel SPb.

[0143] First, at the first time t1, a low-level scan signal is output to the second scan line SL2(n) of the nth row. The second transistor TR2 and the fifth transistor TR5 of the upper sub-pixel SPa can be turned on by the scan signal of the second scan line SL2(n) of the nth row. The fourth node N4 of the upper sub-pixel SPa can be initialized to the reference voltage Vref by the turned-on fifth transistor TR5. The second node N2 and the third node N3 of the upper sub-pixel SPa can be connected by the turned-on second transistor TR2.

[0144] Next, a low-level scan signal is output to the second scan line SL2(n+1) of the (n+1)th row at time t2. The second transistor TR2 and the fifth transistor TR5 of the lower sub-pixel SPb can be turned on by the scan signal of the second scan line SL2(n+1) of the (n+1)th row. The fourth node N4 of the lower sub-pixel SPb can be initialized to the reference voltage Vref through the turned-on fifth transistor TR5. The second node N2 and the third node N3 of the lower sub-pixel SPb can be connected through the turned-on second transistor TR2.

[0145] At time t3, a low-level scan signal is output to the first scan line SL1(n) of the nth row, and a high-level light emission control signal is output to the light emission control signal line EM(n) of the nth row. Low grayscale data voltage LVdata or high grayscale data voltage HVdata is output to the data line DL. The first transistor TR1 of the upper sub-pixel Spa is turned on by the scan signal of the first scan line SL1(n) of the nth row. The third transistor TR3 and the fourth transistor TR4 of the upper sub-pixel Spa are turned off by the light emission control signal of the light emission control signal line EM(n) of the nth row. The first transistor TR1 is turned on to transmit the low grayscale data voltage LVdata or high grayscale data voltage HVdata from the data line DL to the first node N1 of the upper sub-pixel Spa. Therefore, the low grayscale data voltage LVdata or high grayscale data voltage HVdata can be charged into the upper sub-pixel Spa, and when the light-emitting diode EL emits light, the upper sub-pixel Spa can exhibit low grayscale.

[0146] At time t4, a low-level scan signal is output to the first scan line SL1(n+1) of row n+1, and a high-level light emission control signal is output to the light emission control signal line EM(n+1) of row n+1. The first transistor TR1 of the lower sub-pixel SPb is turned on by the scan signal of the first scan line SL1(n+1) of row n+1. The third transistor TR3 and the fourth transistor TR4 of the lower sub-pixel SPb are turned off by the light emission control signal of the light emission control signal line EM(n+1) of row n+1. The first transistor TR1 is turned on from time t4 to transmit the low grayscale data voltage LVdata or the high grayscale data voltage HVdata from the data line DL to the first node N1 of the lower sub-pixel SPb.

[0147] From time t3 to time t5, either the low grayscale data voltage LVdata or the high grayscale data voltage HVdata is output to data line DL. From time t5 to time t6, the other of the low grayscale data voltage LVdata and the high grayscale data voltage HVdata is output to data line DL. Therefore, starting from time t5, the first transistor TR1 can transmit either the low grayscale data voltage LVdata or the high grayscale data voltage HVdata from data line DL to the first node N1 of the next sub-pixel SPb.

[0148] In summary, from time t3 to time t5, the low grayscale data voltage LVdata or the high grayscale data voltage HVdata is charged into the storage capacitor Cst in the upper sub-pixel SPa. Furthermore, the gate voltage of the driving transistor DTR of the upper sub-pixel SPa can be charged from the reference voltage Vref to the sum of the high-potential power supply voltage VDD and the threshold voltage Vth via the conducting second transistor TR2.

[0149] From time t4 to time t5, one of the low grayscale data voltage LVdata and the high grayscale data voltage HVdata is charged into the storage capacitor Cst of the lower sub-pixel SPb. From time t5 to time t6, the other of the low grayscale data voltage LVdata and the high grayscale data voltage HVdata is charged into the storage capacitor Cst of the lower sub-pixel SPb. Therefore, from time t4 to time t5, the gate voltage of the driving transistor DTR of the lower sub-pixel SPb can be charged from the reference voltage Vref to the sum of the high-potential power supply voltage VDD and the threshold voltage Vth. Furthermore, from time t5 to time t6, either the low grayscale data voltage LVdata or the high grayscale data voltage HVdata is charged into the storage capacitor Cst of the lower sub-pixel SPb. However, the gate of the driving transistor DTR can be continuously charged with the sum of the high-potential power supply voltage VDD and the threshold voltage Vth.

[0150] Finally, at time t7, a low-level light-emitting control signal is output to the light-emitting control signal line EM(n) of row n, and at time t8, a low-level light-emitting control signal is output to the light-emitting control signal line EM(n+1) of row n+1. Starting from time t7, the third transistor TR3 and the fourth transistor TR4 of the upper sub-pixel SPb are turned on to transfer drive current to the light-emitting diode EL. Starting from time t8, the third transistor TR3 and the fourth transistor TR4 of the lower sub-pixel SPb are turned on to transfer drive current to the light-emitting diode EL. Therefore, starting from time t7, the light-emitting diode EL of the upper sub-pixel SPb can emit light, and starting from time t8, the light-emitting diode EL of the lower sub-pixel SPb can emit light. Thus, the upper sub-pixel SPb causes the light-emitting diode EL to emit light from time t7 to display the gray level corresponding to one of the low grayscale data voltage LVdata and the high grayscale data voltage HVdata. The lower sub-pixel SPb causes the light-emitting diode EL to emit light from time t8 to display the gray level corresponding to the other of the low gray-scale data voltage LVdata and the high gray-scale data voltage HVdata.

[0151] At the same time, Figure 9 and Figure 10 The text has already described how the upper subpixel SPa and the lower subpixel SPb emit light at different times. However, as in the reference... Figure 6 and Figure 7 The description states that the upper sub-pixel SPa and the lower sub-pixel SPb are connected to the same common light emission control signal line EM(n / n+1) to emit light simultaneously, but are not limited to this.

[0152] Meanwhile, in a display device 900 according to yet another exemplary embodiment of the present disclosure, when a sub-pixel SP includes six transistors and a storage capacitor Cst, the upper sub-pixel SPa and the lower sub-pixel SPb can be driven without being limited to the output order of the low grayscale data voltage LVdata and the high grayscale data voltage HVdata.

[0153] Specifically, refer to Figure 11A The high grayscale data voltage HVdata is first charged into the upper sub-pixel SPB, and then the low grayscale data voltage LVdata can be easily charged into the lower sub-pixel SPb.

[0154] First, at the third time t3, a low-level scan signal is output to the first scan line SL1(n) of the nth row to output the high grayscale data voltage HVdata to the first node N1 of the upper sub-pixel SPa. Therefore, the voltage of the first node N1 of the upper sub-pixel SPa can be charged from the reference voltage Vref to the high grayscale data voltage HVdata. Simultaneously, the gate voltage of the driving transistor DTR of the upper sub-pixel SPa can be charged by the conducting second transistor TR2 with the sum of the high-potential power supply voltage VDD and the threshold voltage Vth.

[0155] Next, at time t4, a low-level scan signal is output to the first scan line SL1(n+1) of the (n+1)th row to output the high grayscale data voltage HVdata to the first node N1 of the next sub-pixel SPb. The voltage of the first node N1 of the next sub-pixel SPb is charged from the reference voltage Vref to the high grayscale data voltage HVdata. The gate voltage of the driving transistor DTR of the next sub-pixel SPb can be charged by the sum of the high-potential supply voltage VDD and the threshold voltage Vth.

[0156] Next, the low grayscale data voltage LVdata is output to the data line DL starting from time t5, so that the low grayscale data voltage LVdata is output to the first node N1 of the lower sub-pixel SPb. Therefore, the voltage of the first node N1 of the lower sub-pixel SPb changes from the reference voltage Vref to the high grayscale data voltage HVdata, and then from the high grayscale data voltage HVdata to the low grayscale data voltage LVdata. However, even if the data voltage Vdata applied to the first node N1 changes, the voltage of the gate of the driving transistor DTR can remain at the sum of the high potential supply voltage VDD and the threshold voltage Vth. Therefore, even if the high grayscale data voltage HVdata is output first, and then the low grayscale data voltage LVdata is output, the threshold voltage Vth of the driving transistor DTR of each of the upper sub-pixel SPb can be sampled normally.

[0157] Next, refer to Figure 11B The low grayscale data voltage LVdata is first charged into the upper sub-pixel SPPa, and then the high grayscale data voltage HVdata can be easily charged into the lower sub-pixel SPb.

[0158] At the third time t3, a low-level scan signal is output to the first scan line SL1(n) of the nth row, causing the voltage of the first node N1 of the upper sub-pixel SPa to be charged from the reference voltage Vref to the low grayscale data voltage LVdata. Simultaneously, the gate voltage of the driving transistor DTR of the upper sub-pixel SPa can be charged by the conducting second transistor TR2 with the sum of the high-potential power supply voltage VDD and the threshold voltage Vth.

[0159] Next, at time t4, a low-level scan signal is output to the first scan line SL1(n+1) of the (n+1)th row to output the low grayscale data voltage LVdata to the first node N1 of the next sub-pixel SPb. The voltage of the first node N1 of the next sub-pixel SPb is charged from the reference voltage Vref to the low grayscale data voltage LVdata. The gate voltage of the driving transistor DTR of the next sub-pixel SPb can be charged by the sum of the high-potential supply voltage VDD and the threshold voltage Vth.

[0160] Next, the high grayscale data voltage HVdata is output to the data line DL starting from time t5, so that the high grayscale data voltage HVdata is output to the first node N1 of the lower sub-pixel SPb. Therefore, the voltage of the first node N1 of the lower sub-pixel SPb changes from the reference voltage Vref to the low grayscale data voltage LVdata, and then from the low grayscale data voltage LVdata to the high grayscale data voltage HVdata. However, even if the data voltage Vdata applied to the first node N1 changes, the gate voltage of the driving transistor DTR remains at the sum of the high potential supply voltage VDD and the threshold voltage Vth. Therefore, even if the low grayscale data voltage LVdata is output first and then the high grayscale data voltage HVdata is output, the threshold voltage Vth of the driving transistor DTR of each of the upper sub-pixel SPb can be sampled normally.

[0161] Therefore, in a display device 900 according to yet another exemplary embodiment of the present disclosure, the circuitry of each sub-pixel SP is configured to charge the gate voltage of the driving transistor DTR with the sum of the high-potential power supply voltage VDD and the threshold voltage Vth. Thus, the upper sub-pixel SPa and the lower sub-pixel SPb can be driven without being limited by the input order of the high grayscale data voltage HVdata and the low grayscale data voltage LVdata. First, each of the upper sub-pixel SPa and the lower sub-pixel SPb includes a circuit consisting of six transistors and a storage capacitor Cst. At this time, when the input data voltage Vdata is applied, the gate voltage of the driving transistor DTR is charged with the sum of the high-potential power supply voltage VDD and the threshold voltage Vth. Therefore, it is possible to prevent the driving transistor DTR from being turned off according to the output order of the high grayscale data voltage HVdata and the low grayscale data voltage LVdata. Therefore, in a display device 900 according to another exemplary embodiment of the present disclosure, when two grayscale values ​​are combined to display one grayscale value, the upper sub-pixel SPPa and the lower sub-pixel SPb can be driven normally without being restricted by the output order of the high grayscale data voltage HVdata and the low grayscale data voltage LVdata.

[0162] Exemplary embodiments of this disclosure can also be described as follows:

[0163] According to one aspect of this disclosure, a display device is provided. The display device includes: a display panel comprising sub-pixels consisting of upper and lower sub-pixels sharing a common data line and adjacent to each other; and a data driver that converts only image data corresponding to either even-numbered or odd-numbered gray levels from 10-bit image data into data voltages and supplies the converted data voltages to the sub-pixels. When the data driver converts only even-numbered gray-level image data into data voltages, and the sub-pixel displays a gray level X (where X is odd), the data driver supplies the data voltage of gray level X-1 to the upper sub-pixel and the data voltage of gray level X+1 to the lower sub-pixel.

[0164] When the data driver converts image data of even gray levels to data voltages only and the subpixels display even gray levels, the data driver can supply even gray level data voltages to the upper and lower subpixels.

[0165] When the data driver converts image data of odd gray levels to data voltages only and the sub-pixel displays a gray level of Y (where Y is an even number), the data driver can supply the data voltage of gray level Y-1 to the upper sub-pixel and the data voltage of gray level Y+1 to the lower sub-pixel.

[0166] Data drivers may include digital-to-analog converters that convert 9-bit digital signals into data voltages.

[0167] The 9-bit digital signal converted in the digital-to-analog converter can correspond to either the even-numbered gray-level image data or the odd-numbered gray-level image data in the 10-bit image data.

[0168] Subpixels can display gray levels from 0 to 1023, obtained by combining the gray levels displayed in the upper subpixel and the gray levels displayed in the lower subpixel.

[0169] The time period during which the data voltage is input to the upper sub-pixel and the time period during which the data voltage is input to the lower sub-pixel can partially overlap.

[0170] The display device may further include a driving transistor disposed in each of the upper and lower sub-pixels. When a data voltage of gray level X-1 is input to the upper sub-pixel and a data voltage of gray level X+1 is input to the lower sub-pixel, the gate voltage of the driving transistor of the upper sub-pixel can be the sum of the data voltage of gray level X-1 and the threshold voltage, and the gate voltage of the driving transistor of the lower sub-pixel can change from the sum of the data voltage of gray level X-1 and the threshold voltage to the sum of the data voltage of gray level X+1 and the threshold voltage.

[0171] The data driver can input only the X-1 gray level data voltage to the upper and lower sub-pixels, and then input the X+1 gray level data voltage to the lower sub-pixel.

[0172] The display device may further include a driving transistor disposed in each of the upper and lower sub-pixels. When the data voltage of gray level X-1 is input to the upper sub-pixel and the data voltage of gray level X+1 is input to the lower sub-pixel, the gate voltage of the driving transistor of the upper sub-pixel may be the sum of the high-potential power supply voltage and the threshold voltage, and the gate voltage of the driving transistor of the lower sub-pixel may be the sum of the high-potential power supply voltage and the threshold voltage.

[0173] The display device may further include storage capacitors connected to the gates of the driving transistors in the upper and lower sub-pixels. When the data voltage of gray level X-1 is input to the upper sub-pixel and the data voltage of gray level X+1 is input to the lower sub-pixel, the data voltage of gray level X-1 can be input to one end of the storage capacitor of the upper sub-pixel, and after the data voltage of gray level X-1 is input to one end of the storage capacitor of the lower sub-pixel, the data voltage of gray level X+1 can be input.

[0174] The display device may further include light emission control signal lines connected to each of the upper and lower sub-pixels. The light emission control signal line connected to the upper sub-pixel may output a light emission control signal before the light emission control signal line connected to the lower sub-pixel.

[0175] The display device may further include a common light emission control signal line that is connected to both the upper and lower sub-pixels. The upper and lower sub-pixels may emit light simultaneously based on a light emission control signal from the common light emission control signal line.

[0176] According to another aspect of this disclosure, a display device is provided. The display device includes: a display panel comprising subpixels consisting of upper and lower subpixels sharing a common data line and adjacent to each other, and displaying an image based on n-bit image data (n is a natural number) input from the outside. Only a portion of the externally input n-bit image data is converted into m-bit image data (m is a natural number less than n) and output to the upper and lower subpixels, and the subpixels consisting of the upper and lower subpixels display a grayscale corresponding to the n-bit image data.

[0177] A specific gray level can be displayed in a subpixel when each of the upper and lower subpixels displays a specific gray level.

[0178] When the upper sub-pixel displays a gray level less than a specific gray level and the lower sub-pixel displays a gray level greater than a specific gray level, the lower and upper gray levels can be combined to display the specific gray level in the sub-pixel.

[0179] n-bit image data can be 10-bit image data, and m-bit image data can be 9-bit image data.

[0180] Each of the 512 even gray levels from gray level 0 to gray level 1023 corresponding to 10-bit image data can be converted to each of the gray levels from gray level 0 to gray level 511 of 9-bit image data and output to the upper and lower sub-pixels.

[0181] When a sub-pixel displays an odd gray level from 0 to 1023 corresponding to 10-bit image data, the data voltage of an even gray level less than the odd gray level can be output to the upper sub-pixel, and the data voltage of an even gray level greater than the odd gray level can be output to the lower sub-pixel.

[0182] Specifically, each of the 512 odd gray levels from gray level 0 to gray level 1023 corresponding to 10-bit image data can be converted into each of the gray levels from gray level 0 to gray level 511 of 9-bit image data and output to the upper and lower sub-pixels.

[0183] When a sub-pixel displays an even gray level from 0 to 1023 corresponding to 10-bit image data, the data voltage of the odd gray level that is less than the even gray level can be output to the upper sub-pixel, and the data voltage of the odd gray level that is greater than the even gray level can be output to the lower sub-pixel.

[0184] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within the equivalent scope of these claims should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: The display panel includes sub-pixels consisting of upper and lower sub-pixels that are adjacent to each other; as well as A data driver that converts only the image data corresponding to either an even-numbered or an odd-numbered gray level from the 10-bit image data into a data voltage, and supplies the converted data voltage to the sub-pixel. Specifically, when the data driver converts only the image data of the even-number gray levels into the data voltage and the sub-pixel displays gray level X, the data driver supplies the data voltage of gray level X-1 to the upper sub-pixel and the data voltage of gray level X+1 to the lower sub-pixel, where X is an odd number.

2. The display device according to claim 1, wherein, When the data driver converts only the image data of the even gray level into the data voltage and the sub-pixel displays the even gray level, the data driver supplies the data voltage of the even gray level to the upper sub-pixel and the lower sub-pixel.

3. The display device according to claim 1, wherein, When the data driver converts only the image data of the odd gray levels into the data voltage and the sub-pixel displays the Y gray level, the data driver supplies the data voltage of the Y-1 gray level to the upper sub-pixel and the data voltage of the Y+1 gray level to the lower sub-pixel, where Y is an even number.

4. The display device according to claim 1, wherein, The data driver includes a digital-to-analog converter that converts a 9-bit digital signal into the data voltage.

5. The display device according to claim 4, wherein, The 9-bit digital signal converted in the digital-to-analog converter corresponds to either the even-numbered grayscale image data or the odd-numbered grayscale image data in the 10-bit image data.

6. The display device according to claim 4, wherein, The sub-pixel display achieves gray levels from 0 to 1023 by combining the gray levels displayed in the upper sub-pixel and the gray levels displayed in the lower sub-pixel.

7. The display device according to claim 1, wherein, The time period during which the data voltage is input to the upper sub-pixel and the time period during which the data voltage is input to the lower sub-pixel partially overlap.

8. The display device according to claim 7, further comprising: The driving transistor is disposed in each of the upper sub-pixel and the lower sub-pixel. Specifically, when the data voltage of gray level X-1 is input to the upper sub-pixel and the data voltage of gray level X+1 is input to the lower sub-pixel, the voltage of the gate of the driving transistor of the upper sub-pixel is the sum of the data voltage of gray level X-1 and the threshold voltage, and the voltage of the gate of the driving transistor of the lower sub-pixel changes from the sum of the data voltage of gray level X-1 and the threshold voltage to the sum of the data voltage of gray level X+1 and the threshold voltage.

9. The display device according to claim 8, wherein, The data driver inputs the data voltage of the X-1 gray level to the upper sub-pixel and the lower sub-pixel, and then inputs the data voltage of the X+1 gray level only to the lower sub-pixel.

10. The display device according to claim 7, further comprising: The driving transistor is disposed in each of the upper sub-pixel and the lower sub-pixel. Specifically, when the data voltage of gray level X-1 is input to the upper sub-pixel and the data voltage of gray level X+1 is input to the lower sub-pixel, the gate voltage of the driving transistor of the upper sub-pixel is the sum of the high-potential power supply voltage and the threshold voltage, and the gate voltage of the driving transistor of the lower sub-pixel is the sum of the high-potential power supply voltage and the threshold voltage.

11. The display device according to claim 10, further comprising: A storage capacitor connected to the gate of the driving transistor in each of the upper and lower sub-pixels. Specifically, when the data voltage of gray level X-1 is input to the upper sub-pixel and the data voltage of gray level X+1 is input to the lower sub-pixel, the data voltage of gray level X-1 is input to one end of the storage capacitor of the upper sub-pixel, and the data voltage of gray level X+1 is input after the data voltage of gray level X-1 is input to one end of the storage capacitor of the lower sub-pixel.

12. The display device according to claim 1, further comprising: Light emission control signal lines connected to each of the upper and lower sub-pixels. Specifically, the light emission control signal line connected to the upper sub-pixel outputs a light emission control signal before the light emission control signal line connected to the lower sub-pixel.

13. The display device according to claim 1, further comprising: A common light emission control signal line is connected to both the upper and lower sub-pixels. The upper sub-pixel and the lower sub-pixel emit light simultaneously based on the light emission control signal from the common light emission control signal line.

14. A display device, comprising: The display panel includes subpixels consisting of upper and lower subpixels that are adjacent to each other, and displays an image based on an n-bit image data input from an external source, where n is a natural number. In this process, only a portion of the n-bit image data input from the outside is converted into m-bit image data and output to the upper sub-pixel and the lower sub-pixel. The sub-pixel formed by the upper and lower sub-pixels displays the grayscale corresponding to the n-bit image data, where m is a natural number less than n. Specifically, when the upper sub-pixel displays a gray level less than a specific gray level and the lower sub-pixel displays a gray level greater than the specific gray level, the lower gray level and the upper gray level are combined to display the specific gray level in the sub-pixel.

15. The display device according to claim 14, wherein, The specific grayscale is displayed in the sub-pixel when each of the upper and lower sub-pixels displays a specific grayscale.

16. The display device according to claim 14, wherein, The n-bit image data is 10-bit image data, and the m-bit image data is 9-bit image data.

17. The display device according to claim 16, wherein, Each of the 512 even gray levels from gray level 0 to gray level 1023 corresponding to the 10-bit image data is converted to each of the gray levels from gray level 0 to gray level 511 of the 9-bit image data and output to the upper sub-pixel and the lower sub-pixel.

18. The display device according to claim 17, wherein, When the sub-pixel displays an odd gray level from 0 to 1023 corresponding to the 10-bit image data, the data voltage of the even gray level that is less than the odd gray level is output to the upper sub-pixel, and the data voltage of the even gray level that is greater than the odd gray level is output to the lower sub-pixel.

19. The display device according to claim 16, wherein, Each of the 512 odd gray levels from gray level 0 to gray level 1023 corresponding to the 10-bit image data is converted to each of the gray levels from gray level 0 to gray level 511 of the 9-bit image data and output to the upper sub-pixel and the lower sub-pixel.

20. The display device according to claim 19, wherein, When the sub-pixel displays an even gray level from 0 to 1023 corresponding to the 10-bit image data, the data voltage of the odd gray level that is less than the even gray level is output to the upper sub-pixel, and the data voltage of the odd gray level that is greater than the even gray level is output to the lower sub-pixel.

Images