Ic device and method of manufacturing the same

Abstract

Embodiments of the present application provide an IC device, comprising: a first power rail and a second power rail extending along a first direction and carrying one of a power supply and a reference voltage; a third power rail extending between the first power rail and the second power rail and carrying the other of the power supply and the reference voltage; and a plurality of transistors comprising a first active region to a fourth active region extending between the first power rail and the second power rail, a plurality of gate structures extending perpendicular to the first direction, and a first conductive segment and a second conductive segment extending through the third power rail in a second direction. Each of the second active region and the third active region is adjacent to the third power rail, each of the first conductive segment and the second conductive segment is electrically connected to an S / D structure in each of the second active region and the third active region, and the plurality of transistors is configured as one of an AOI, an OAI, and a four-input NAND. Embodiments of the present application also provide a method of manufacturing an IC device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of electronic circuits, and more specifically, to IC devices and methods of manufacturing the same. Background Technology

[0002] The ongoing trend towards miniaturization in integrated circuits (ICs) is enabling devices to become smaller, consume less power, and deliver more functionality at a higher speed than earlier technologies. This miniaturization is achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify semiconductor device designs while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] One aspect of the present invention provides an integrated circuit (IC) device, comprising: a first power rail and a second power rail extending along a first direction, wherein each of the first power rail and the second power rail is configured to carry a power supply voltage and a power supply reference voltage; a third power rail extending along the first direction between the first power rail and the second power rail, wherein the third power rail is configured to carry the other of the power supply voltage and the power supply reference voltage; and a plurality of transistors, including: a first active region to a fourth active region extending along the first direction between the first power rail and the second power rail, wherein each of the second active region and the third active region is adjacent to the third power rail; a plurality of gate structures extending along a second direction perpendicular to the first direction; and a first conductive segment and a second conductive segment extending through the third power rail in the second direction, wherein each of the first conductive segment and the second conductive segment is electrically connected to a source / drain S / D structure in each of the second active region and the third active region, wherein the plurality of transistors are configured as one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), or a four-input NAND.

[0004] Another aspect of the present invention provides an integrated circuit (IC) device, comprising: a first row of transistors, including: a first active region and a second active region, extending along a first direction and adjacent to corresponding first and second power rails, each of the first and second active regions including a plurality of source / drain S / D structures; and a first plurality of gate structures extending between the first and second power rails along a second direction perpendicular to the first direction, wherein the first row of transistors is configured to receive a first subset of a plurality of input signals; a second row of transistors including: a third active region and a fourth active region, extending along the first direction and adjacent to the second and third power rails respectively, the third active region and the fourth active region... Each of the source regions includes a plurality of S / D structures; and a second plurality of gate structures extending along the second direction between the second power rail and the third power rail, wherein the second row of transistors is configured to receive a second subset of the plurality of input signals; and a first conductive segment and a second conductive segment extending through the second power rail in the second direction, wherein each of the first conductive segment and the second conductive segment is electrically connected to the S / D structure of the plurality of S / D structures in each of the second active region and the third active region, and the first row of transistors and the second row of transistors, as well as the first conductive segment and the second conductive segment, are configured as one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND gate.

[0005] Another aspect of the present invention provides a method for manufacturing an integrated circuit (IC) device, the method comprising: forming, in a semiconductor substrate, a first active region and a second active region in a first row extending along a first direction, and a third active region and a fourth active region in a second row adjacent to the first row, wherein each active region includes a plurality of source / drain S / D structures; constructing a first conductive segment and a second conductive segment extending along a second direction, wherein each of the first conductive segment and the second conductive segment covers and is electrically connected to the S / D structures in each of the second active region and the third active region; and constructing additional conductive segments, a plurality of gate structures, and a plurality of vias. The structure forms one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND device, including the first conductive segment and the second conductive segment and pull-up and pull-down transistors in each of the first and second rows; and constructs a first power rail to a third power rail extending along the first direction, wherein the first power rail and the second power rail are aligned with the first row, the second power rail and the third power rail are aligned with the second row, and each of the first conductive segment and the second conductive segment passes through a plane perpendicular to the first conductive segment and the second conductive segment and including the second power rail. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A-1C This is a schematic diagram of an IC logic device according to some embodiments.

[0008] Figure 2A This is a schematic diagram of an IC logic device according to some embodiments.

[0009] Figure 2B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0010] Figure 2C These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0011] Figure 2D These are IC layout diagrams and cross-sectional views of corresponding IC logic devices based on some embodiments.

[0012] Figure 2E These are IC layout diagrams and cross-sectional views of corresponding IC logic devices based on some embodiments.

[0013] Figure 3A This is a schematic diagram of an IC logic device according to some embodiments.

[0014] Figure 3B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0015] Figure 4A This is a schematic diagram of an IC logic device according to some embodiments.

[0016] Figure 4B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0017] Figure 5A This is a schematic diagram of an IC logic device according to some embodiments.

[0018] Figure 5B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0019] Figure 6A This is a schematic diagram of an IC logic device according to some embodiments.

[0020] Figure 6B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0021] Figure 7A This is a schematic diagram of an IC logic device according to some embodiments.

[0022] Figure 7B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0023] Figure 8A This is a schematic diagram of an IC logic device according to some embodiments.

[0024] Figure 8B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0025] Figure 9A This is a schematic diagram of an IC logic device according to some embodiments.

[0026] Figure 9B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0027] Figure 10A This is a schematic diagram of an IC logic device according to some embodiments.

[0028] Figure 10B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0029] Figure 11A This is a schematic diagram of an IC logic device according to some embodiments.

[0030] Figure 11B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0031] Figure 12A This is a schematic diagram of an IC logic device according to some embodiments.

[0032] Figure 12B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0033] Figure 13A These are schematic diagrams of IC logic devices according to some embodiments.

[0034] Figure 13B These are IC layout diagrams and corresponding IC logic device planar diagrams based on some embodiments.

[0035] Figure 14 This is a flowchart of a method for operating an IC logic device according to some embodiments.

[0036] Figure 15This is a flowchart of a method for manufacturing an IC logic device according to some embodiments.

[0037] Figure 16 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0038] Figure 17 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0039] Figure 18 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0040] This invention provides numerous different embodiments or instances for implementing various components of this disclosure. Specific embodiments of components and arrangements are described below to simplify the invention. Of course, these are merely embodiments and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0041] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0042] In various embodiments, the IC device based on the IC layout includes three power rails and multiple transistors, each transistor including four active regions, multiple gates, and a first conductive segment and a second conductive segment extending across an intermediate power rail. Each of the first and second conductive segments is electrically connected to a source / drain (S / D) structure in each of the second and third active regions, and the multiple transistors are configured as logic devices, such as an AND-OR-NOT gate (AOI), an OR-NAND gate (OAI), or a four-input NAND gate. Compared to methods of configuring such logic devices in other ways (e.g., based on a total of two power rails), the conductive segment length and therefore the speed degradation and reliability risks based on electromigration are reduced.

[0043] As described below, Figures 1A-1C The top-level circuit morphology was described. Figures 2A-13A Each of these is a schematic diagram of a logic circuit embodiment, and Figures 2B-2E and Figures 3B-13B Each of these figures depicts a plan view or cross-sectional view of the corresponding device / layout embodiment, wherein reference numerals denote IC device components and those used in the manufacturing process (e.g., below regarding...). Figure 15 The methods discussed are 1500 and / or related to the following: Figure 18 The IC manufacturing system 1800 discussed (related to IC manufacturing processes) at least partially defines the IC layout components of the corresponding IC device components. In some embodiments, Figures 2B-2E or Figures 3B-13B One or more of them are, for example, using the following about Figure 17 The system 1700 under discussion, through the execution of the following... Figure 16 The discussed method 1600 generates some or all of the IC layout diagrams through some or all of its operations. Therefore, Figures 2B-2E and Figures 3B-13B Each of these represents a layout diagram of the IC and a plan view of the corresponding IC device.

[0044] For illustrative purposes, each figure in this article has been simplified, for example... Figures 1A-13B These figures are views of the IC structure and device, in which various components are included and excluded for the purpose of the discussion below. In various embodiments, except... Figures 1A-13B The components depicted, IC structures, devices, and / or layout diagrams include one or more components corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, S / D structures, bulk connections, or other transistor elements, isolation structures, etc.

[0045] Figures 1A-1C This is a top-level diagram of an IC logic device according to some embodiments. Figure 1A The pull-up configuration 100A is described. Figure 1B The dropdown configuration 100B is described, and Figure 1C A device / layout diagram 100C corresponding to configurations 100A and 100B is depicted and includes the X and Y directions. In some embodiments, the device / layout diagram 100C is referred to as cell 100C.

[0046] Each of the pull-up configuration 100A and pull-down configuration 100B includes pull-up (PMOS) transistor groups PU1 and PU2 and pull-down (NMOS) transistor groups PD1 and PD2 arranged between the power supply voltage VDD and the power supply reference voltage VSS. The gates of pull-up transistor group PU1 and pull-down transistor group PD1 are configured to receive input signal A1-input signal Z1, and the gates of pull-up transistor group PU2 and pull-down transistor group PD2 are configured to receive input signal A2-input signal Z2. Each of the pull-up configuration 100A and pull-down configuration 100B includes an output terminal OUT connected between the pull-up transistor group PU1 / PU2 and the pull-down transistor group PD1 / PD2 and configured to carry an output signal ZN based on the corresponding configuration of the input signals A1-input signal Z1 and A2-input signal Z2 and the pull-up transistor group PU1 / PU2 and the pull-down transistor group PD1 / PD2.

[0047] The pull-up configuration 100A includes two entities, each of pull-up transistor groups PU1 and PU2, configured to selectively connect the output signal ZN to the power supply voltage VDD, and a single entity, each of pull-down transistor groups PD1 and PD2, configured to selectively connect the output signal ZN to the power supply reference voltage VSS.

[0048] The pull-down configuration 100B includes a single entity of each of the pull-up transistor groups PU1 and PU2 configured to selectively connect the output terminal OUT to the power supply voltage VDD, and two entities of each of the pull-down transistor groups PD1 and PD2 configured to selectively connect the output terminal OUT to the power supply reference voltage VSS.

[0049] Device / layout diagram 100C includes power rails PR1-PR3 extending along the X direction, row R1 extending along the X direction between power rails PR1 and PR2, and row R2 extending along the X direction between power rails PR2 and PR3.

[0050] Power rails PR1-PR3 correspond to metal regions / segments. A metal region / segment is a region included in the IC layout diagram as part of a manufacturing process defining a metal segment structure. This metal segment structure includes one or more conductive materials in a given metal layer of the manufacturing process, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. In various embodiments, one or more of power rails PR1-PR3 correspond to a first metal layer (also referred to in some embodiments as a metal zero layer), a second or higher metal layer, a buried metal layer, or a back metal layer in the manufacturing process.

[0051] In some embodiments, power rails PR1 and PR3 are configured to carry the power supply voltage VDD and power rail PR2 is configured to carry the power supply reference voltage VSS, or power rails PR1 and PR3 are configured to carry the power supply reference voltage VSS and power rail PR2 is configured to carry the power supply voltage VDD.

[0052] Rows R1 and R2 are jointly defined by a boundary PRb, which in some embodiments is also referred to as the cell boundary or layout and wiring boundary PRb. The boundary PRb includes a segment (unlabeled) extending along the X direction and aligned with power rails PR1 and PR3 in the Z direction (not shown) perpendicular to the X and Y directions, and a segment extending along the Y direction and aligned with the gate region / structure (…) in the Z direction… Figure 1C Not shown in the text, for example, the following about Figures 2B-2E and Figures 3B-13B The segment (unlabeled) aligned with one of the gate regions / structures G1 and G10, G12 and G14 discussed.

[0053] Each of rows R1 and R2 has a height CH in the Y direction. In some embodiments, the height CH corresponds to the pitch of power rails PR1-PR3. In some embodiments, the height CH is referred to as the cell height CH, and the device / layout diagram 100C is referred to as a dual-height cell.

[0054] like Figure 1C As shown, each of the pull-up configuration 100A and pull-down configuration 100B is implemented to include a pull-up transistor group PU1 and a pull-down transistor group PD1 located in row R1 and a pull-up transistor group PU2 and a pull-down transistor group PD2 located in row R2. Row R1 is configured to receive input signal A1-input signal Z1, and row R2 is configured to receive input signal A2-input signal Z2.

[0055] As follows about Figures 2B-2E and Figures 3B-13B Further discussion reveals that device / layout diagram 100C also includes two or more conductive regions / segments extending along the Y direction from row R1 to row R2, thus crossing power rail PR2. Figure 1C (Not shown in the diagram). Each of two or more conductive regions / segments is electrically connected to the S / D structure of one or more transistors in the pull-up transistor group PU1 and pull-down transistor group PD1 included in row R1, and electrically connected to the S / D structure of one or more transistors in the pull-up transistor group PU2 and pull-down transistor group PD2 included in row R2. Two or more conductive regions are considered to extend across the power rail PR2 by overlapping with the power rail PR2 in the layout diagram, and two or more conductive segments are considered to extend through the power rail PR2 by intersecting with the XZ plane (not shown) where the power rail PR2 is located.

[0056] By including two or more conductive regions / segments in one of the pull-up configurations 100A and 100B, the device / layout diagram 100C includes conductive components that are shorter in length than those in which the corresponding logic devices are otherwise configured (e.g., based on a total of two power rails), thus reducing speed degradation and reliability risks based on electromigration.

[0057] Figures 1A-1C The transistor group configurations depicted are provided for illustrative purposes and are not limiting examples. In some embodiments, device / layout diagram 100C is further configured to include two or more conductive regions / segments extending across power rail PR2. In some embodiments, pull-up configuration 100A implemented as device / layout diagram 100C includes entities of more than two of the following transistor groups: one or both of pull-up transistor groups PU1 and PU2 corresponding to row R1 or R2; one or more pull-up transistor groups other than pull-up transistor groups PU1 and PU2 in a given row of row R1 and row R2; and / or pull-up transistor groups configured to receive unequal numbers of input signals (e.g., input signal A1-input signal Z1 and input signal A2-input signal Z2). In some embodiments, the pull-down configuration 100B implemented as device / layout diagram 100C includes entities comprising more than two of the following transistor groups: one or both of pull-down transistor groups PD1 and PD2; one or more pull-down transistor groups other than pull-down transistor groups PD1 and PD2 in corresponding rows R1 or R2; and / or pull-down transistor groups configured to receive unequal numbers of input signals in a given row of rows R1 and R2.

[0058] Figures 2A-13A This is a schematic diagram of corresponding IC logic devices 200-1300 according to some embodiments. Each of IC logic devices 200-1300 is a non-limiting example of one of pull-up configurations 100A and pull-down configurations 100B implemented as a device / layout diagram 100C. In some embodiments, the device / layout diagram is also referred to as cell 200-1, cell 200-2, and cell 300-1300. Figures 2A-13A and corresponding Figures 2B-2E as well as Figures 3B-13B Each of the figures depicts an entity of pull-up and pull-down transistors (e.g., pull-up transistors PU1 and PU2 and / or pull-down transistors PD1 and PD2), wherein, for clarity, these transistors are not individually or collectively labeled.

[0059] exist Figures 2A-13AIn each of the depicted devices 200-1300, the pull-up transistor includes a PMOS transistor connected between the power supply voltage VDD and the output terminal OUT and configured to receive an input signal, while the pull-down transistor includes an NMOS transistor connected between the output terminal OUT and the power supply reference voltage VSS and configured to receive an input signal. A first subset of each of the pull-up and pull-down transistors is located in row R1, and a second subset of each of the pull-up and pull-down transistors is located in row R2, as described below and in the corresponding... Figures 2B-2E and Figures 3B-13B As shown in the image.

[0060] Figure 2A The device 200 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of eight PMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight PMOS transistors in row R2 configured to receive input signals A1 and A2; and the pull-down transistors include a total of eight NMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 200 includes conductive paths 210-240 configured to electrically connect the shared S / D terminal of the pull-up transistors in row R1 to the shared S / D terminal of the pull-up transistors in row R2, as described below. Figures 2B-2E The AOI device discussed here, and thus configured to generate an output signal ZN in response to input signals A1, A2, B1, and B2, is referred to as AOI22D4 in some embodiments.

[0061] Figure 3A The device 300 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of two PMOS transistors in row R1 configured to receive input signals A3 and A4, and a total of two PMOS transistors in row R2 configured to receive input signals A1 and A2; the pull-down transistors include a total of eight NMOS transistors in row R1 configured to receive input signals A3 and A4, and a total of eight NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 300 includes conductive paths 310 and 320 configured to electrically connect the shared S / D terminal of the pull-down transistors in row R1 to the shared S / D terminal of the pull-down transistors in row R2, as described below. Figure 3B The discussed, and thus configured, four-input NAND device is capable of generating an output signal ZN in response to input signals A1, A2, A3, and A4. In some embodiments, device 300 is referred to as an ND4D4 device.

[0062] Figure 4A The device 400 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of eight PMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight PMOS transistors in row R2 configured to receive input signals A1 and A2; and the pull-down transistors include a total of six NMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of six NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 400 includes conductive paths 410-440 configured to electrically connect the shared S / D terminal of the pull-up transistors in row R1 to the shared S / D terminal of the pull-up transistors in row R2, as described below. Figure 4B The discussed and thus configured skew cell AOI device is capable of generating an output signal ZN in response to input signals A1, A2, B1, and B2. In some embodiments, device 400 is referred to as AOI22SKRD4 device.

[0063] Figure 5A The device 500 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of six PMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of six PMOS transistors in row R2 configured to receive input signals A1 and A2; and the pull-down transistors include a total of eight NMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 500 includes conductive paths 510-540 configured to electrically connect the shared S / D terminal of the pull-down transistors in row R1 to the shared S / D terminal of the pull-down transistors in row R2, as described below. Figure 5B The discussed device, and thus configured to generate an output signal ZN in response to input signals A1, A2, B1, and B2, is a skew unit OAI device. In some embodiments, device 500 is referred to as OAI22SKFD4 device.

[0064] Figure 6AThe device 600 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of four PMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of four PMOS transistors in row R2 configured to receive input signals A1 and A2; and the pull-down transistors include a total of four NMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 600 includes conductive paths 610 and 620 configured to electrically connect the shared S / D terminal of the pull-up transistors in row R1 to the shared S / D terminal of the pull-up transistors in row R2, as described below. Figure 6B The AOI device discussed therein, and thus configured to generate an output signal ZN in response to input signals A1, A2, B1, and B2, is referred to as AOI22OPTPAD4 in some embodiments.

[0065] Figure 7A The device 700 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of four PMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of eight PMOS transistors in row R2 configured to receive input signals A1 and A2; and the pull-down transistors include a total of four NMOS transistors in row R1 configured to receive input signals B1 and B2, and a total of four NMOS transistors in row R2 configured to receive input signals A1 and A2. Device 700 includes conductive paths 710 and 720 configured to electrically connect the shared S / D terminal of the pull-down transistors in row R1 to the shared S / D terminal of the pull-down transistors in row R2, as described below. Figure 7B The OAI device discussed here, and thus configured to generate an output signal ZN in response to input signals A1, A2, B1, and B2. In some embodiments, device 700 is referred to as OAI22OPTPAD4 device.

[0066] Figure 8AThe device 800 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of ten PMOS transistors in row R1 configured to receive input signals B1, B2, and C, and a total of ten PMOS transistors in row R2 configured to receive input signals A1, A2, and C; and the pull-down transistors include a total of nine NMOS transistors in row R1 configured to receive input signals B1, B2, and C, and a total of nine NMOS transistors in row R2 configured to receive input signals A1, A2, and C. Device 800 includes conductive paths 810-870, wherein conductive paths 810-840 are configured to electrically connect the shared S / D terminals of the pull-up transistors in row R1 to the shared S / D terminals of the pull-up transistors in row R2, as described below. Figure 8B The discussed AOI device is configured to generate an output signal ZN in response to input signals A1, A2, B1, B2, and C. In some embodiments, device 800 is referred to as AOI221D4 device.

[0067] Figure 9A The device 900 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of eight PMOS transistors in row R1 configured to receive input signals A1-A3 and input signal B, and a total of eight PMOS transistors in row R2 configured to receive input signals A1-A3 and input signal B; and the pull-down transistors include a total of seven NMOS transistors in row R1 configured to receive input signals A1-A3 and input signal B, and a total of seven NMOS transistors in row R2 configured to receive input signals A1-A3 and input signal B. Device 900 includes conductive paths 910-930 configured to electrically connect the shared S / D terminal of the pull-up transistors in row R1 to the shared S / D terminal of the pull-up transistors in row R2, as described below. Figure 9B The discussed AOI device is configured to generate an output signal ZN in response to input signals A1-A3 and input signal B. In some embodiments, device 900 is referred to as AOI31D4 device.

[0068] Figure 10AThe device 1000 depicted is a non-limiting example of a pull-up configuration 100A, wherein the pull-up transistors include a total of 10 PMOS transistors in row R1 configured to receive input signals A1-A3, input signal B, and input signal C, and a total of 10 PMOS transistors in row R2 configured to receive input signals A1-A3, input signal B, and input signal C; and the pull-down transistors include a total of 8 NMOS transistors in row R1 configured to receive input signals A1-A3, input signal B, and input signal C, and a total of 8 NMOS transistors in row R2 configured to receive input signals A1-A3, input signal B, and input signal C. Device 1000 includes conductive paths 1010-1030 configured to electrically connect the shared S / D terminal of the pull-up transistors in row R1 to the shared S / D terminal of the pull-up transistors in row R2, as described below. Figure 10B The device 1000 discussed herein is configured to generate an output signal ZN in response to input signals A1-A3, input signal B, and input signal C. In some embodiments, the device 1000 is referred to as an AOI311D4 device.

[0069] Figure 11A The device 1100 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of nine PMOS transistors in row R1 configured to receive input signals B1, B2, and C, and a total of nine PMOS transistors in row R2 configured to receive input signals A1, A2, and C; and the pull-down transistors include a total of ten NMOS transistors in row R1 configured to receive input signals B1, B2, and C, and a total of ten NMOS transistors in row R2 configured to receive input signals A1, A2, and C. Device 1100 includes conductive paths 1110-1170, wherein paths 1110-1140 are configured to connect the shared S / D terminals of the pull-down transistors in row R1 to the shared S / D terminals of the pull-down transistors in row R2, as described below. Figure 11B The discussed device 1100 is thus configured to generate an output signal ZN in response to input signals A1, A2, B1, B2, and C. In some embodiments, device 1100 is referred to as an OAI221D4 device.

[0070] Figure 12AThe device 1200 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of seven PMOS transistors in row R1 configured to receive input signals A1-A3 and B, and a total of seven PMOS transistors in row R2 configured to receive input signals A1-A3 and B; and the pull-down transistors include a total of eight NMOS transistors in row R1 configured to receive input signals A1-A3 and B, and a total of eight NMOS transistors in row R2 configured to receive input signals A1-A3 and B. Device 1200 includes conductive paths 1210-1230 configured to electrically connect the shared S / D terminal of the pull-down transistors in row R1 to the shared S / D terminal of the pull-down transistors in row R2, as described below. Figure 12B The device 1200 discussed herein is thus configured to be an OAI device capable of generating an output signal ZN in response to input signals A1-A3 and input signal B. In some embodiments, the device 1200 is referred to as an OAI31D4 device.

[0071] Figure 13A The device 1300 depicted is a non-limiting example of a pull-down configuration 100B, wherein the pull-up transistors include a total of eight PMOS transistors in row R1 configured to receive input signals A1-A3, B, and C, and a total of eight PMOS transistors in row R2 configured to receive input signals A1-A3, B, and C; and the pull-down transistors include a total of ten NMOS transistors in row R1 configured to receive input signals A1-A3, B, and C, and a total of ten NMOS transistors in row R2 configured to receive input signals A1-A3, B, and C. Device 1300 includes conductive paths 1310-1330 configured to electrically connect the shared S / D terminal of the pull-down transistors in row R1 to the shared S / D terminal of the pull-down transistors in row R2, as described below. Figure 13B The device 1300 discussed herein is thus configured as an AOI device capable of generating an output signal ZN in response to input signals A1-A3, B, and C. In some embodiments, the device 1300 is referred to as the OAI311D4 device.

[0072] Figure 2B , Figure 2C and Figures 3B-13B It is based on some embodiments corresponding to Figures 2A-13A The schematic diagrams depicted are corresponding IC layout diagrams / device plan views 200-1, 200-2 and 300-1300 (including X and Y directions). Figure 2D This is the IC layout diagram / device 200-1 in the... Figure 2BThe cross-sectional view in the YZ plane indicated by line A-A' is shown in the figure. Figure 2E This is IC layout diagram / device 200-2 in... Figure 2C The line B-B' indicates the cross-sectional view in the YZ plane. Figure 2D and Figure 2E The cross-section depicted is a non-limiting example provided to illustrate a conductive segment extending across the intermediate power rail.

[0073] like Figures 2B-2E and Figures 3B-13B As shown, each schematic / device 200-1, 200-2 and 300-1300 includes: a semiconductor substrate SUB (only on the semiconductor substrate SUB) Figure 2D and 2E The active regions / regions AA1-AA4 extending along the X direction (marked in the middle); some or all of the multiple metal-like defined (MD) regions / segments MD1-MD13 extending along the Y direction; some or all of the multiple gate regions / structures G1-Gate regions / structures G14 extending along the Y direction; and power rails PR1-PR3. Active regions / regions AA1 and AA2 are located between power rails PR1 and PR2 in row R1, and active regions / regions AA3 and AA4 are located between power rails PR2 and PR3 in row R2. All the multiple MD regions / segments MD1-MD13 and all the multiple gate regions / structures G1-Gate regions / structures G14 are aligned along the Y direction.

[0074] The overlapping / covering of multiple MD regions / segments MD1-MD13 with active regions / regions AA1-AA4 corresponds to the S / D structure of one or more transistors, which include adjacent portions of multiple gate regions / structures G1-G14. For clarity, in Figures 2B-2E and Figures 3B-13B There are no separate markers for the location and transistors.

[0075] Each schematic / device 200-1, 200-2, and 300-1300 also includes the solid form of a metal region / segment MS extending in the X and Y directions, as well as the solid form of vias VD, VG, and V0, each of which is labeled for clarity. See below for reference. Figures 2B-2E and Figures 3B-13B The arrangement of the mentioned components according to various embodiments is discussed.

[0076] An active region / area, such as active regions / areas AA1-AA4, is a region included in the IC layout diagram in the manufacturing process that defines the active region. It is also referred to as oxide diffusion or definition (OD) in the semiconductor substrate, directly located within an n-well region / area or a p-well region / area (not shown for clarity), and one or more IC device components, such as S / D structures, are formed within the active region / area. In some embodiments, the active region is an n-type or p-type active region of a planar transistor, a FinFET, or a gate-all-around (GAA) transistor. In various embodiments, the active region (structure) includes: one or more semiconductor materials, such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.; and dopant materials, such as boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials.

[0077] In some embodiments, the active region is a region included in an IC layout diagram in a manufacturing process that defines a nanosheet structure, for example, a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0078] exist Figures 2B-2E and Figures 3B-13B In the embodiments depicted, active regions AA1 and AA4 are n-type active regions adjacent to the corresponding power rails PR1 and PR3 configured to carry the power supply reference voltage VSS, and active regions AA2 and AA3 are p-type active regions adjacent to the power rail PR2 configured to carry the power supply reference voltage VDD. Alternatively, active regions AA1 and AA4 are p-type active regions adjacent to the corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, and active regions AA2 and AA3 are n-type active regions adjacent to the power rail PR2 configured to carry the power supply reference voltage VSS.

[0079] A MD region / segment, for example, one of a plurality of MD regions / segments MD1-MD regions / segments MD13, is a conductive region included in an IC layout diagram in a manufacturing process that defines a portion of the MD segment. Also referred to as a conductive segment or MD conductive line or trace, it is located in and / or on a semiconductor substrate. In some embodiments, the MD segment includes a portion of at least one metal layer, such as a contact layer, that covers and contacts the substrate and has a sufficiently small thickness to allow an insulating layer to be formed between the MD segment and an overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), another metal, and materials suitable for providing low-resistance electrical connections between IC structural elements (i.e., resistance levels below a predetermined threshold corresponding to one or more tolerance levels based on the effect of resistance on circuit performance).

[0080] In various embodiments, the MD segment comprises a portion in a semiconductor substrate and / or epitaxial layer having a doping level, for example, sufficient based on an implantation process, to give the segment a low resistance level. In various embodiments, the doped MD segment comprises one or more segments having a doping concentration of about 1 × 10⁻⁶. 16 per cubic centimeter (cm- 3 (or larger doped materials).

[0081] In some embodiments, the manufacturing process includes two MD layers, and the MD region / segment in the plurality of MD regions / segments MD1-MD region / segment MD13 refers to any one of the two MD layers in the manufacturing process.

[0082] exist Figures 2B-2E and Figures 3B-13B In the embodiments depicted, each of the plurality of MD regions / segments MD1-MD13 overlaps with one or more active regions / regions AA1-AA4. In various embodiments, one or more MD segments, for example, some or all of the plurality of MD segments MD1-MD13, are adjacent to or include some or all of one or more S / D structures corresponding to one or more active regions.

[0083] The MD regions / segments among the multiple MD regions / segments MD1-MD13 have a configuration along the Y direction according to the cut-MD region (also referred to as the cut-metal region in some embodiments, not depicted for clarity). The cut-MD region is a region in the IC layout diagram included in the manufacturing process as a portion defining the discontinuity in a given MD segment, thereby electrically isolating corresponding adjacent MD segments from each other.

[0084] A gate region / structure, such as the gate regions / structures G1-G14, is a region included in the IC layout diagram in the manufacturing process that defines the gate structure. The gate structure is a volume comprising one or more conductive segments, such as gate electrodes, comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, and is substantially surrounded by one or more insulating materials, whereby the one or more conductive segments are configured to control the voltage supplied to the adjacent gate dielectric layer.

[0085] The dielectric layer, such as the gate dielectric layer, is a bulk comprising one or more insulating materials (e.g., silicon dioxide, silicon nitride (Si3N4)) and / or one or more other suitable materials (such as low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8 or 7.0, e.g., alumina (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2)) suitable for providing high resistance between IC structure elements (i.e., resistance levels above a predetermined threshold corresponding to one or more tolerance levels based on the effect of resistance on circuit performance).

[0086] Multiple gate regions / structures G1 and G14 have a configuration along the Y direction according to diced-gate regions (also referred to in some embodiments as diced-polysilicon regions, not depicted for clarity). A diced-gate region is a region included in the IC layout diagram in the manufacturing process as a portion of the discontinuity of the gate electrode defining a given gate structure, thereby electrically isolating corresponding adjacent portions of the gate electrode from each other.

[0087] exist Figures 2B-2E and Figures 3B-13B In the embodiments depicted, each of the plurality of gate regions / structures G1 and the largest of the plurality of gate regions / structures G1-G14 (e.g., the plurality of gate regions / structures G10, G12, or G14) includes a first gate region / structure having endpoints above / below power rails PR1 and PR2, and a second gate region / structure having endpoints above / below power rails PR2 and PR3. The corresponding gate regions / structures, also referred to in some embodiments as dummy gate regions / structures, are not included in the active circuitry and are depicted along the Y-direction boundaries of schematic diagrams / devices 200-1, 200-2, and 300-1300.

[0088] In some embodiments, one or both of the largest numbered gate regions / structures G1 and G1-G14 are otherwise configured to depict the boundaries of schematic / device 200-1, 200-2 and 300-1300, for example, by including a single region / segment having endpoints above / below power rails PR1 and PR3 or by including more than two regions / segments extending between power rails PR1 and PR3.

[0089] A metal region / segment MS is an entity encompassing a region in an IC layout diagram within a manufacturing process, defined as a portion of a metal segment extending in the X or Y direction within a given metal layer of the manufacturing process. Figures 2B-2E and Figures 3B-13B In the embodiments depicted, the metal region / segment MS extends in the X direction in the first metal layer, while the metal region / segment MS extends in the Y direction in the second metal layer (also referred to as metal layer 1 in some embodiments). In some embodiments, the metal region / segment MS extends in the X and Y directions in other ways, for example, by extending in the Y direction in the first metal layer and in the X direction in the second metal layer.

[0090] A via region / structure, such as via region / structure VD, VG, or V0, is a region included in an IC layout diagram in a manufacturing process that defines a via structure. It comprises one or more conductive materials and is configured to provide an electrical connection between an upper conductive structure (e.g., power rails PR1-PR3 or a metal segment MS) and a lower conductive structure. In the case of via region / structure VD, the lower conductive structure corresponds to an MD segment or an S / D structure; in the case of via region / structure VG, the lower conductive structure corresponds to a gate electrode; and in the case of via region / structure V0, the lower conductive structure corresponds to a first metal layer region / segment, such as a metal region / segment MS.

[0091] like Figures 2B-2E and Figures 3B-13B As shown, each schematic / device 200-1, 200-2, and 300-1300 includes a solid of a plurality of MD regions / segments MD1-MD13, which overlaps / covers one of the active regions / regions AA1, AA2, and AA4 and is located above / below one of the power rails PR1-PR3 at the location corresponding to the solid of the via region / structure VD. Each such location thus depicts the electrical connection between the S / D structure in the corresponding active region AA1, AA2, or AA4 and the adjacent power rail PR1-power rail PR3.

[0092] Each schematic / device 200-1, 200-2 and 300-1300 also includes an entity of a metal region / segment MS that extends along the X direction in a first metal layer in either row R1 or row R2 and overlaps / covers one or more MD regions / segments MD1-MD13 at the location corresponding to the entity of the via region / structure VD, such that the location of the entity of each such via region / structure VD depicts the electrical connection between the S / D structure in the corresponding active region AA1-active region AA4 and the entity of the overlying metal region / segment MS.

[0093] Each schematic / device 200-1, 200-2 and 300-1300 also includes an entity of a metal region / segment MS that extends along the X direction in the first metal layer of either row R1 or row R2 and overlaps / covers one or more MD regions / segments MD1-MD13 at the location corresponding to the entity of the via region / structure VG, each such location thereby depicting the electrical connection between the corresponding gate structure and the entity of the overlying metal region / segment MS.

[0094] Each schematic / device 200-1, 200-2, and 300-1300 also includes one or more entities extending in the Y direction in the second metal layer and overlapping / covering the metal region / segment MS in the first metal layer at the location of the entity corresponding to the via region / structure V0, the location of the entity of each via region / structure V0 thereby depicting the electrical connection between the corresponding entities of the metal region / segment MS in the first and second metal layers. For example... Figure 2B , Figure 2C and Figures 3B-13B Each of the depicted metal regions / segments MS in the second metal layer corresponds to at least one such entity as the output terminal OUT.

[0095] Therefore, according to Figures 2A-13A The diagram depicted in the middle and further based on Figures 2B-2E and Figures 3B-13B Each corresponding schematic / device depicted in the diagram, including active regions AA1-AA4, multiple MD regions / segments MD1-MD regions / segments MD13 and gate regions / structures G1-G14, as well as the physical entities of metal regions / segments MS and via regions / structures VD, VG and V0, are configured as multiple pull-up transistors and pull-down transistors, as discussed below.

[0096] Figure 2B and Figure 2D The schematic diagram / device 200-1 depicted in the diagram and Figure 2C and Figure 2EThe schematic diagram / device 200-2 depicted includes n-type active regions AA1 and AA4 adjacent to the corresponding power rails PR1 and PR3 configured to carry the power supply reference voltage VSS, p-type active regions AA2 and AA3 adjacent to the power rail PR2 configured to carry the power supply voltage VDD, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. A physical entity of a metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD3 and MD7 is configured as the output terminal OUT.

[0097] In schematic / device 200-1, multiple MD regions / segments MD2, MD4, MD6, and MD8 include corresponding MD regions / segments 210-1 to 240-1 located above / below power rail PR2 and above / below active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 210-1 to 240-1 (in some embodiments, also referred to as conductive paths 210-1 to 240-1). The component corresponding to conductive path 210-1 is... Figure 2D It is depicted in an example cross-sectional view.

[0098] In schematic / device 200-2, the physical entities of the metal regions / segments MS, namely metal regions / segments 210-2 to 240-2, overlap / cover power rails PR2 and each of active regions / regions AA2 and AA3 at positions corresponding to the via regions / structures VD and V0 entities and the metal region / segment MS entities extending in the X direction, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through metal regions / segments 210-2 to 240-2 (also referred to in some embodiments as conductive paths 210-2 to 240-2). The component corresponding to conductive path 210-2 is... Figure 2E It is depicted in an example cross-sectional view.

[0099] The portion of the active region / region AA2 and the plurality of gate regions G2-G9 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R1, wherein the gate structure is configured to receive input signals B1 and B2, and the portion of the active region / region AA3 and the plurality of gate regions G2-G9 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding Figure 2A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as NMOS pull-down transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals B1 / B2 and A1 / A2. According to... Figure 2A The schematic diagram 200 depicted in the diagram shows that the MD regions / segments 210-1 to 240-1 and the metal regions / segments MS 210-2 to 240-2 are thus configured to correspond to the conductive regions / segments of AOI devices 200-1 and 200-2 that extend along the Y direction between rows R1 and R2 and cross the power rail PR2, thereby achieving the aforementioned benefits.

[0100] Figure 3B The schematic diagram / device 300 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. A physical entity of a metal region / segment MS extending along the Y direction and overlapping / covering multiple gate regions / structures G7 and MD regions / segments MD7 is configured as the output terminal OUT.

[0101] Multiple MD regions / segments MD3 and MD7 include corresponding MD regions / segments 310 and 320 located above / below power rail PR2 and above / below active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 310 and 320 (also referred to as conductive paths 310 and 320 in some embodiments).

[0102] The portion of the active region / region AA2 and the plurality of gate regions G3, G4, G7 and G8 adjacent to the corresponding S / D structure is configured as an NMOS pull-down transistor in row R1, wherein the gate structure is configured to receive input signal A3. The portion of the active region / region AA3 and the plurality of gate regions G3, G4, G7 and G8 adjacent to the corresponding S / D structure is configured as an NMOS pull-down transistor in row R2, wherein the gate structure is configured to receive input signal A2, as described above regarding... Figure 3A The active regions AA2 and AA3, and portions of the adjacent gate regions / structures G2, G5, G6, and G9, are configured as NMOS pull-down transistors in the corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals A4 and A1. The active regions AA1 and AA4, and portions of the adjacent gate regions G2-G9, are configured as PMOS pull-up transistors in the corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals A3 / A4 and A1 / A2. According to... Figure 3AThe schematic diagram shows that MD regions / segments 310 and 320 are thus configured as conductive regions / segments of NAND device 300, which extend along the Y direction between row R1 and row R2 and cross power rail PR2, thereby obtaining the benefits discussed above.

[0103] Figure 4B The schematic diagram / device 400 depicted includes n-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry a power supply reference voltage VSS, p-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry a power supply voltage VDD, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. A physical entity of a metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD2 and MD8 is configured as an output terminal OUT.

[0104] Multiple MD regions / segments MD2, MD4, MD6, and MD8 include corresponding MD regions / segments 410-440, which are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 410-MD regions / segments 440 (in some embodiments, also referred to as conductive path 410-conductive path 440).

[0105] The portion of the active region / region AA2 and the plurality of gate regions G2-G9 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R1, wherein the gate structure is configured to receive input signals B1 and B2, and the portion of the active region / region AA3 and the plurality of gate regions G2-G9 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding Figure 4A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as NMOS pull-down transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals B1 / B2 and A1 / A2. According to... Figure 4A The schematic diagram depicted shows that MD regions / segments 410-440 are thus configured as conductive regions / segments of AOI device 400, which extend along the Y direction between row R1 and row R2 and cross power rail PR2, thereby obtaining the benefits discussed above.

[0106] Figure 5BThe schematic diagram / device 500 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. An instance of a metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD2 and MD8 is configured as an output terminal OUT.

[0107] Multiple MD regions / segments MD2, MD4, MD6, and MD8 include corresponding MD regions / segments 510-540, which are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 510-540 (also referred to as conductive paths 510-540 in some embodiments).

[0108] The NMOS pull-down transistors in row R1 include portions of the active region / region AA2 and multiple gate regions G2-G9 adjacent to the corresponding S / D structure, wherein the gate structure is configured to receive input signals B1 and B2, and the NMOS pull-down transistors in row R2 include portions of the active region / region AA3 and multiple gate regions G2-G9 adjacent to the corresponding S / D structure, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding... Figure 5A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as PMOS pull-up transistors in the corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals B1 / B2 and A1 / A2. According to... Figure 5A The schematic diagram depicted shows that MD regions / segments 510-540 are thus configured as conductive regions / segments of the OAI device 500, which extend along the Y direction between rows R1 and R2 and cross the power rail PR2, thereby achieving the aforementioned benefits.

[0109] Figure 6B The schematic diagram / device 600 depicted includes n-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry a power supply reference voltage VSS, p-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry a power supply voltage VDD, multiple gate regions / structures G1-G14, and multiple MD regions / structures MD1-MD13. A physical entity of a metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD3 and MD11 is configured as an output terminal OUT.

[0110] Multiple MD regions / segments MD2, MD6, MD8, and MD12 include corresponding MD regions / segments, which are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3. Through the solid of the via region / structure VD, the solid of the metal region / segment MS extending in the X direction overlaps / covers and is electrically connected to each of the overlapping / covered MD regions / segments in multiple MD regions / segments MD2 and MD6, as well as the MD region / segment in multiple MD regions / segments MD4, thereby the components are collectively configured as a conductive path 610 between the corresponding S / D structures in active regions / regions AA2 and AA3. Through the solid of the via region / structure VD, the solid of the metal region / segment MS extending in the X direction overlaps / covers and is electrically connected to each of the overlapping / covered MD regions / segments in multiple MD regions / segments MD8 and MD12, as well as the MD region / segment in multiple MD regions / segments MD10, thereby the components are collectively configured as a conductive path 620 between the corresponding S / D structures in active regions / regions AA2 and AA3.

[0111] The portion of the active region / region AA2 and the plurality of gate regions G2-G13 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R1, wherein the gate structure is configured to receive input signals B1 and B2, and the portion of the active region / region AA3 and the plurality of gate regions G2-G13 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding Figure 6A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G13, are configured as NMOS pull-down transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals B1 / B2 and A1 / A2. According to... Figure 6A The schematic diagram depicted shows that the conductive paths 610 and 620 of the AOI device 600 are thus configured to include an MD region / segment extending in the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby obtaining the benefits discussed above.

[0112] Figure 7BThe schematic diagram / device 700 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G14, and multiple MD regions / structures MD1-MD13. A metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD3 and MD11 is configured as the output terminal OUT.

[0113] Multiple MD regions / segments MD2, MD6, MD8, and MD12 include corresponding MD regions / segments, which are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3. Through the solid of the via region / structure VD, the solid of the metal region / segment MS extending in the X direction overlaps / covers and is electrically connected to each of the overlapping / covered MD regions / segments in multiple MD regions / segments MD2 and MD6, as well as the MD region / segment in multiple MD regions / segments MD4, thereby the components are collectively configured as a conductive path 710 between the corresponding S / D structures in active regions / regions AA2 and AA3. Through the solid of the via region / structure VD, the solid of the metal region / segment MS extending in the X direction overlaps / covers and is electrically connected to each of the overlapping / covered MD regions / segments in multiple MD regions / segments MD8 and MD12, as well as the MD region / segment in multiple MD regions / segments MD10, thereby the components are collectively configured as a conductive path 720 between the corresponding S / D structures in active regions / regions AA2 and AA3.

[0114] The portion of the active region / region AA2 and the plurality of gate regions G2-G13 adjacent to the corresponding S / D structure is configured as an NMOS pull-down transistor in row R1, wherein the gate structure is configured to receive input signals B1 and B2, and the portion of the active region / region AA2 and the plurality of gate regions G2-G13 adjacent to the corresponding S / D structure is configured as an NMOS pull-down transistor in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding Figure 7A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G14, are configured as PMOS pull-up transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals B1 / B2 and A1 / A2. According to... Figure 7A The schematic diagram depicted shows that the conductive paths 710 and 720 of the OAI device 700 are thus configured to include an MD region / segment extending in the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby enabling the benefits discussed above to be obtained.

[0115] Figure 8B The schematic diagram / device 800 depicted includes n-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry a power supply reference voltage VSS, p-type active regions / regions AA2 and AA3 adjacent to a power rail PR2 configured to carry a power supply voltage VDD, multiple gate regions / structures G1-G12, and multiple MD regions / structures MD1-MD11. A metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD6 is configured as an output terminal OUT.

[0116] Multiple MD regions / segments MD2, MD5, MD7, and MD10 include corresponding MD regions / segments located above / below power rail PR2 and overlapping / covering active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 810-MD regions / segments 840 (also referred to in some embodiments as conductive paths 810-conductive paths 840).

[0117] The portion of the active region / region AA2 and the plurality of gate regions G2, G3, G5-G8, G10 and G11 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R1, wherein the gate structure is configured to receive input signals B1 and B2. The portion of the active region / region AA3 and the plurality of gate regions G2, G3, G5-G8, G10 and G11 adjacent to the corresponding S / D structure is configured as a PMOS pull-up transistor in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding... Figure 8A The active regions / regions AA1 and AA4 and portions of the adjacent multiple gate regions G2-G11 are configured as NMOS pull-down transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive corresponding input signals C, B1 / B2, and A1 / A2. According to... Figure 8A The schematic diagram depicted shows that the MD region / segment 810-840 is therefore configured as a conductive region / segment of the AOI device 800 extending along the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby obtaining the benefits discussed above.

[0118] The physical extensions of the metal region / segment MS in the X direction overlap / cover and are electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD1 and MD3 through the physical extensions of the via region / structure VD. Therefore, these components are collectively configured as a conductive path 850 between corresponding S / D structures in the active region / region AA3. The physical extensions of the metal region / segment MS in the X direction overlap / cover and are electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD4, MD6, and MD8 through the physical extensions of the via region / structure VD. Therefore, these components are collectively configured as a conductive path 860 between corresponding S / D structures in the active region / region AA2. The physical extensions of the metal region / segment MS in the X direction overlap / cover and are electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD9 and MD11 through the physical extensions of the via region / structure VD. Thus, these components are collectively configured as a conductive path 870 between corresponding S / D structures in the active region / region AA3.

[0119] The active regions AA2 and AA3, and portions of the multiple gate regions G2-G11 adjacent to the corresponding S / D structures, are configured as PMOS pull-up transistors in rows R1 and R2, wherein the gate structures are configured to receive input signals C, B1 / B2, and A1 / A2, as described above. Figure 8A The conductive paths 850-870 of the AOI device 800 are thus configured as a solid extending in the X direction, including a metal region / segment MS, with a length less than five times the gate pitch of the gate region / structure G1-G12. This reduces segment length, speed degradation, and electromigration-based reliability risks compared to some methods where the segment length is greater than five times the gate pitch.

[0120] Figure 9B The schematic diagram / device 900 depicted includes n-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply reference voltage VSS, p-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply voltage VDD, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. A metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD4 is configured as the output terminal OUT.

[0121] Multiple MD regions / segments MD1, MD5, and MD9 include corresponding MD regions / segments located above / below power rail PR2 and overlapping / covering active regions / regions AA2 and AA3. The solid, X-direction-extending solid of the metal region / segment MS overlaps / covers and is electrically connected via the via region / structure VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD1 and the MD regions / segments of multiple MD regions / segments MD3, thereby these components are collectively configured as a conductive path 910 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid, X-direction-extending solid of the metal region / segment MS overlaps / covers and is electrically connected via the via region / structure VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD5 and the MD regions / segments of multiple MD regions / segments MD3 and MD7, thereby these components are collectively configured as a conductive path 920 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid overlap / coverage of the metal region / segment MS extending in the X direction and the solid electrical connection of the overlapping / covered MD region / segment of the multiple MD region / segment MD9 and the MD region / segment of the multiple MD region / segment MD7 through the via region / structure VD, so that these components are collectively configured as a conductive path 930 between the corresponding S / D structures in the active region / region AA2 and AA3.

[0122] Figure 10B The schematic diagram / device 1000 depicted includes n-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry a power supply reference voltage VSS, p-type active regions / regions AA2 and AA3 adjacent to a power rail PR2 configured to carry a power supply voltage VDD, multiple gate regions / structures G1-G12, and multiple MD regions / structures MD1-MD11. A metal region / segment MS extending along the Y direction and overlapping / covering multiple MD regions / segments MD6 is configured as an output terminal OUT.

[0123] Multiple MD regions / segments MD1, MD6, and MD10 include corresponding MD regions / segments that overlap / are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD1 and the MD regions / segments of multiple MD regions / segments MD3, thereby these components are collectively configured as a conductive path 1010 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD6 and the MD regions / segments of multiple MD regions / segments MD4 and MD8, thereby these components are collectively configured as a conductive path 1020 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid overlap / cover of the metal region / segment MS extending along the X direction and the solid electrical connection of the overlapping / covered MD region / segment of the multiple MD region / segment MD11 and the MD region / segment of the multiple MD region / segment MD9 through the via region / structure VD, so that these components are collectively configured as conductive path 1030 between the corresponding S / D structures in the active region / region AA2 and AA3.

[0124] The active regions AA2 and AA3 adjacent to the corresponding S / D structure, as well as portions of multiple gate regions G2-G11, are configured as PMOS pull-up transistors in rows R1 and R2, wherein the gate structure is configured to receive input signals C, B, and A1-A3, as described above. Figure 10A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as NMOS pull-down transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive input signals C, B, and A1-A3. According to... Figure 10A The schematic diagram depicted shows that the conductive paths 1010-1030 of the AOI device 1000 are thus configured to include an MD region / segment extending in the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby obtaining the benefits discussed above.

[0125] Figure 11BThe schematic diagram / device 1100 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to corresponding power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G12, and multiple MD regions / structures MD1-MD11. A metal region / segment MS extending along the Y direction and overlapping / covering the entities of multiple MD regions / segments MD6 is configured as the output terminal OUT.

[0126] Multiple MD regions / segments MD2, MD5, MD7, and MD10 include corresponding MD regions / segments that are located above / below power rail PR2 and overlap / cover active regions / regions AA2 and AA3, thereby depicting the electrical connection between the corresponding S / D structures of active regions AA2 and AA3 through MD regions / segments 1110-1140 (also referred to as conductive paths 1110-1140 in some embodiments).

[0127] The portions of the active region / region AA2 and the multiple gate regions G2, G3, G5-G8, G10 and G11 adjacent to the corresponding S / D structure are configured as NMOS pull-down transistors in row R1, wherein the gate structure is configured to receive input signals B1 and B2. The portions of the active region / region AA3 and the multiple gate regions G2, G3, G5-G8, G10 and G11 adjacent to the corresponding S / D structure are configured as NMOS pull-down transistors in row R2, wherein the gate structure is configured to receive input signals A1 and A2, as described above regarding... Figure 11A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G11, are configured as PMOS pull-up transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive the corresponding input signals C, B1 / B2, and A1 / A2. According to... Figure 11A The schematic diagram depicted shows that the MD region / segment 1110-1140 is thus configured as a conductive region / segment of the OAI device 1100 extending along the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby enabling the aforementioned benefits to be obtained.

[0128] The solid extending in the X direction of the metal region / segment MS overlaps / covers and is electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD1 and MD3 through the solid of the via region / structure VD. Therefore, these components are collectively configured as a conductive path 1150 between corresponding S / D structures in the active region / region AA3. The solid extending in the X direction of the metal region / segment MS overlaps / covers and is electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD4, MD6 and MD8 through the solid of the via region / structure VD. Therefore, these components are collectively configured as a conductive path 1160 between corresponding S / D structures in the active region / region AA2. The solid extending in the X direction of the metal region / segment MS overlaps / covers and is electrically connected to the MD region / segment of each of the plurality of MD regions / segments MD9 and MD11 through the solid of the via region / structure VD. Thus, these components are collectively configured as a conductive path 1170 between corresponding S / D structures in the active region / region AA3.

[0129] The portion of the active regions AA2 and AA3 adjacent to the corresponding S / D structure, as well as the portions of multiple gate regions G2-G11, are configured as NMOS pull-down transistors in rows R1 and R2, wherein the gate structure is configured to receive input signals C, B1 / B2, and A1 / A2, as described above. Figure 11A The conductive paths 1150-1170 of the OAI device 1100 are thus configured to include a metal region / segment MS whose length in the X direction is less than five times the gate pitch of the gate region / structure G1-G12, thereby reducing segment length, speed degradation, and electromigration-based reliability risks compared to some methods where the segment length is greater than five times the gate pitch.

[0130] Figure 12B The schematic diagram / device 1200 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G10, and multiple MD regions / structures MD1-MD9. A metal region / segment MS extending along the Y direction and overlapping / covering the entities of multiple MD regions / segments MD4 is configured as the output terminal OUT.

[0131] Multiple MD regions / segments MD1, MD5, and MD9 include corresponding MD regions / segments located above / below power rail PR2 and overlapping / covering active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD1 and the MD regions / segments of multiple MD regions / segments MD3, thereby these components are collectively configured as a conductive path 1210 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD5 and the MD regions / segments of multiple MD regions / segments MD3 and MD7, thereby these components are collectively configured as a conductive path 1220 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid overlap / coverage of the metal region / segment MS extending in the X direction and the solid electrical connection of the overlapping / coverage of the MD region / segment of the multiple MD region / segment MD9 and the MD region / segment of the multiple MD region / segment MD7 through the via region / structure VD, so that these components are collectively configured as conductive path 1230 between the corresponding S / D structures in the active region / region AA2 and AA3.

[0132] The portions of the active regions AA2 and AA3 and the multiple gate regions G2-G9 are configured as NMOS pull-down transistors in rows R1 and R2, wherein the gate structure is configured to receive input signals B and A1-A3, as described above. Figure 12A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as PMOS pull-up transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive input signals B and A1-A3. According to... Figure 12A The schematic diagram depicted shows that the conductive paths 1210-1230 of the OAI device 1200 are thus configured to include an MD region / segment extending in the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby enabling the benefits discussed above to be obtained.

[0133] Figure 13BThe schematic diagram / device 1300 depicted includes p-type active regions / regions AA1 and AA4 adjacent to corresponding power rails PR1 and PR3 configured to carry the power supply voltage VDD, n-type active regions / regions AA2 and AA3 adjacent to power rail PR2 configured to carry the power supply reference voltage VSS, multiple gate regions / structures G1-G12, and multiple MD regions / structures MD1-MD11. A metal region / segment MS extending along the Y direction and overlapping / covering the entities of multiple MD regions / segments MD6 is configured as the output terminal OUT.

[0134] Multiple MD regions / segments MD1, MD6, and MD10 include corresponding MD regions / segments located above / below power rail PR2 and overlapping / covering active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD1 and the MD regions / segments of multiple MD regions / segments MD3, thereby these components are collectively configured as a conductive path 1310 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid bodies of the metal regions / segments MS extending in the X-direction overlap / cover and are electrically connected via via regions / structures VD to each of the overlapping / covered MD regions / segments of multiple MD regions / segments MD6 and the MD regions / segments of multiple MD regions / segments MD4 and MD8, thereby these components are collectively configured as a conductive path 1320 between corresponding S / D structures in active regions / regions AA2 and AA3. The solid overlap / cover of the metal region / segment MS extending along the X direction is electrically connected to each of the overlapping / covered MD regions / segments of the multiple MD regions / segments MD11 and the MD regions / segments of the multiple MD regions / segments MD9 through the solid via region / structure VD, so that these components are collectively configured as conductive paths 1330 between corresponding S / D structures in active regions / regions AA2 and AA3.

[0135] The portion of the active regions AA2 and AA3 adjacent to the corresponding S / D structure and the multiple gate regions G2-G11 is configured as NMOS pull-down transistors in rows R1 and R2, wherein the gate structure is configured to receive input signals C, B and A1-A3, as described above. Figure 13A The active regions / regions AA1 and AA4, as well as portions of the adjacent gate regions G2-G9, are configured as PMOS pull-up transistors in corresponding rows R1 and R2, wherein the gate structures are configured to receive input signals C, B, and A1-A3. According to... Figure 13AThe schematic diagram depicted shows that the conductive paths 1310-1330 of the OAI device 1300 are thus configured to include an MD region / segment extending in the Y direction between rows R1 and R2 and crossing the power rail PR2, thereby enabling the benefits discussed above to be obtained.

[0136] Figure 14 This is a flowchart of a method 1400 for operating a logic device according to one or more embodiments. Method 1400 can be used with logic devices, such as those described above. Figure 1A-13B The logic devices discussed are 100C, 200-1, 200-2, or 300-1300.

[0137] Figure 14 The order of operations of method 1400 described herein is for illustrative purposes only; the operation of method 1400 can be performed in a different manner. Figure 14 The sequential execution described herein. In some embodiments, in addition to Figure 14 Operations other than those described in the text Figure 14 The operations described herein are performed before, between, during, and / or after. In some embodiments, the operations of method 1400 are a subset of the operations of the methods operating the IC.

[0138] In operation 1410, multiple input signals are received at the logic device. In some embodiments, according to the above regarding... Figure 1A-13B The discussed embodiments include receiving multiple input signals, including receiving input signals A1-A4, B1, B2, B, or C at logic devices 100C, 200-1, 200-2, or 300-1300.

[0139] Receiving multiple signals includes receiving each signal having a logic high voltage level (e.g., a voltage level within a predetermined threshold of the voltage level of the power supply voltage VDD) or a logic low voltage level (e.g., a voltage level within a predetermined threshold of the voltage level of the power supply reference voltage VSS).

[0140] In operation 1420, an output signal is generated based on the configuration of multiple input signals and logic devices. Generating an output signal based on multiple input signals includes performing one of the following operations on the multiple input signals: AOI, OAI, and four-input NAND.

[0141] The configuration-based output signal generation based on the logic device includes: a logic device comprising first and second power rails extending along a first direction, each of the first and second power rails being configured to carry a power supply voltage and a power supply reference voltage; a third power rail extending along the first direction between the first and second power rails and being configured to carry the other of the power supply voltage and the power supply reference voltage; and a plurality of transistors. The plurality of transistors includes: first to fourth active regions extending along the first direction between the first and second power rails, each of the second and third active regions being adjacent to the third power rail; a plurality of gate structures extending in a second direction perpendicular to the first direction; and first and second conductive segments extending through the third power rail in the second direction, each of the first and second conductive segments being electrically connected to an S / D structure in each of the second and third active regions.

[0142] In some embodiments, generating output signals based on the configuration of logic devices includes, based on the above description... Figures 1A-13B The configurations of the logic devices 100C, 200-1, 200-2, or 300-1300 discussed generate output signals.

[0143] By performing the operation of method 1400, AOI, OAI, or NAND operations are performed using the dual-high cell configured as described above, thereby obtaining the benefits discussed above regarding logic devices 100C, 200-1, 200-2, and 300-1300.

[0144] Figure 15 This is a flowchart of a method 1500 for manufacturing an IC device according to some embodiments. Method 1500 is operable to form the above-mentioned... Figures 1A-13B One or more of the IC devices discussed are 100C, 200-1, 200-2, and 300-1300.

[0145] In some embodiments, the operation of method 1500 is as follows: Figure 15 The method is executed in the order shown. In some embodiments, the operation of method 1500 is different from that of the method shown. Figure 15 The operations are performed in the sequence shown. In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 1500. In some embodiments, performing some or all of the operations of method 1500 includes performing the following described below regarding IC manufacturing system 1800 and Figure 18 One or more operations are being discussed.

[0146] In operation 1510, in some embodiments, a first active region and a second active region are formed in a first row extending along a first direction, and a third active region and a fourth active region are formed in a second row adjacent to the first row, wherein each active region includes multiple S / D structures. Forming the third active region and the fourth active region in the second row adjacent to the first row includes forming a third active region adjacent to the second active region. In some embodiments, forming the first to fourth active regions includes forming the above-described... Figures 2B-2E and Figures 3B-13B The active regions AA1 to AA4 are discussed.

[0147] In various embodiments, forming each of the first and fourth active regions includes forming an n-type active region and forming each of the second and third active regions includes forming a p-type active region, or forming each of the first and fourth active regions includes forming a p-type active region and forming each of the second and third active regions includes forming an n-type active region. In some embodiments, forming the first to fourth plurality of active regions includes forming the first and fourth or second and third active regions in one or more n-wells.

[0148] In various embodiments, forming the first to fourth plurality of active regions includes performing one or more implantation processes in regions of the semiconductor substrate corresponding to the first to fourth plurality of active regions, thereby as described above regarding Figures 2B-2E and Figures 3B-13B The discussion focuses on achieving a predetermined doping concentration and type for one or more given dopants.

[0149] In some embodiments, forming the first to fourth active regions includes, for example, forming a plurality of corresponding S / D structures in and / or on portions of the first to fourth active regions by performing one or more implantation etching processes and / or deposition processes.

[0150] In operation 1520, the first conductive segment and the second conductive segment are configured to extend in a second direction perpendicular to the first direction, wherein each of the first and second conductive segments covers and is electrically connected to the S / D structure in each of the second and third active regions. In some embodiments, constructing the first and second conductive segments includes constructing two or more MD segments, as described above. Figure 2B , Figure 2D and Figures 3B-13B The discussion covers multiple MD segments, MD1-MD13. In some embodiments, constructing the first and second conductive segments includes constructing two or more metallic segments, as described above. Figure 2C and Figure 2E Two of the metal segments 210-2 to 240-2 are discussed.

[0151] In some embodiments, constructing the first and second conductive segments includes constructing a third and fourth conductive segment extending in a second direction, wherein each of the third and fourth conductive segments covers and is electrically connected to the S / D structure in each of the second and third active regions. In some embodiments, constructing the third and fourth conductive segments includes constructing two or more additional MD segments from a plurality of MD segments MD1-MD13, as described above. Figure 2B , 2D The 4B-8B and 11B discussed.

[0152] In various embodiments, constructing the first conductive segment and the second conductive segment includes performing a variety of manufacturing operations, such as photolithography, diffusion, deposition, etching, planarization, and one or more other operations, wherein the other operations are adapted to construct a structure configured to form as described above. Figures 2B-2E and Figures 3B-13B One or more conductive materials with a continuous low-resistance structure under discussion.

[0153] In operation 1530, additional conductive segments, multiple gate structures, and multiple via structures are constructed to form one of AOI, OAI, and four-input NAND devices, which include a first conductive segment and a second conductive segment in each of the first and second rows, as well as pull-up transistors and pull-down transistors.

[0154] In some embodiments, constructing the additional conductive segments, multiple gate structures, and multiple via structures includes constructing the physical form of the metal segment MS, some or all of the gate structures G1-G14, and the physical forms of the via structures VD, VG, and V0, each as described above. Figures 2B-2E and Figures 3B-13B A discussion was held.

[0155] In various embodiments, constructing additional conductive segments, multiple gate structures, and multiple via structures includes performing one or more of various manufacturing operations, such as photolithography, diffusion, deposition, etching, planarization, and others, wherein the other operations are adapted according to the above-mentioned... Figures 2B-2E and Figures 3B-13B The discussion covers the configurations used to build various components.

[0156] In some embodiments, one of the AOI, OAI, and four-input NAND devices comprising a first conductive segment and a second conductive segment in each of the first and second rows, as well as pull-up and pull-down transistors, includes, according to the above, […]. Figures 2A-13A The schematic diagrams 200-1300 discussed form one of the AOI, OAI, and four-input NAND devices.

[0157] In operation 1540, in some embodiments, a first power rail to a third power rail extending in a first direction is constructed, wherein the first and second power rails are aligned with a first row, the second and third power rails are aligned with a second row, and each of the first and second conductive segments passes through a plane perpendicular to the first and second conductive segments and including the second power rail.

[0158] In some embodiments, constructing the first power rail to the third power rail extending along the first direction includes constructing power rails PR1-PR3 extending along the X direction, as described above. Figure 1C , Figures 2B-2E and Figures 3B-13B The subject of discussion.

[0159] In some embodiments, each of the first and second conductive segments, passing through a plane perpendicular to the first and second conductive segments and including the second power rail, includes one or more additional conductive segments passing through the plane, for example, as described above regarding... Figures 2B-2E and Figure 4B-13B The subject of discussion.

[0160] In various embodiments, constructing the first to third power rails includes performing one or more of various manufacturing operations, such as photolithography, diffusion, deposition, etching, planarization, and others, wherein the other operations are adapted to construct metal segments covered or buried in and / or on the back side of the semiconductor substrate, as described above. Figures 2B-2E and Figures 3B-13B The subject of discussion.

[0161] By performing some or all of the operations of method 1500, an AOI, OAI, or four-input NAND IC device is manufactured, wherein the first and second conductive segments pass through a plane including a second power rail, thereby obtaining the IC devices 100C, 200-1, 200-2, and 300-1300 as described above. Figures 1A-13B Benefits of the discussion.

[0162] Figure 16 It is based on some embodiments to generate IC layout diagrams (e.g., the above regarding...). Figure 1A-13B The flowchart of method 1600 for discussing IC layout diagrams 100C, 200-1, 200-2 and / or 300-1300) is provided.

[0163] In some embodiments, generating an IC layout diagram includes generating a layout diagram corresponding to an IC device (e.g., the one mentioned above). Figure 1A-13B The discussion focuses on the IC layout diagrams of IC devices (100C, 200-1, 200-2 and / or 300-1300) manufactured based on the generated IC layout diagrams.

[0164] In some embodiments, some or all of method 1600 is executed by a computer processor, such as processor 1702 that generates system 1700 in the IC layout diagram, as described below. Figure 17 Discussed.

[0165] Some or all of the operations of method 1600 can be performed in the design room (e.g., as described below). Figure 18 The design process was carried out in part of the design room (1820) during the discussion.

[0166] In some embodiments, the operation of method 1600 is as follows: Figure 16 The operations are performed in the order shown. In some embodiments, the operations of method 1600 are performed simultaneously and / or in a manner different from that shown. Figure 16 The operations are performed in the order shown. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 1600.

[0167] In operation 1610, in some embodiments, the first to fourth active regions are arranged in an IC cell (also referred to in some embodiments as a dual-height cell). Arranging the first to fourth active regions in the IC cell includes arranging the first and second active regions in a first row and arranging the third and fourth active regions in a second row, as described above regarding... Figure 1C , Figures 2B-2E and Figures 3B-13B The discussion focuses on rows R1 and R2.

[0168] In some embodiments, arranging the first to fourth active regions in the IC cell includes based on the first to third power rails (e.g., as mentioned above regarding...). Figure 1C , Figures 2B-2E and Figures 3B-13B The unit dimensions of the power rails PR1-PR3 are used to arrange the first to fourth active regions.

[0169] In operation 1620, multiple MD regions, gate regions, via regions, and metal regions of the cell are arranged as one of AOI, OAI, and four-input NAND devices, which include a first conductive region and a second conductive region extending across a rail corresponding to a power rail and overlapping each of the second and third active regions.

[0170] The multiple MD regions, gate regions, via regions, and metal regions of the cell are arranged as one of the AOI, OAI, and four-input NAND devices, including pull-up and pull-down transistors configured in each of the first and second rows.

[0171] In some embodiments, the plurality of MD regions, gate regions, via regions, and metal regions of the cell are arranged as one of AOI, OAI, and quad-input NAND devices, including those described above regarding... Figures 2A-13A The schematic diagrams 200-1300 discussed show some or all of the following: multiple MD regions MD1-MD13, gate regions G1-G14, via regions VD, VG and V0, and metal region MS.

[0172] In some embodiments, the first and second conductive regions extending through the rails corresponding to the power rails include first and second MD regions, for example, as mentioned above. Figure 2B , 2D The MD regions MD1-MD13 discussed in 3B-13B. In some embodiments, the first and second conductive regions extending across the rails corresponding to the power rails include first and second metallic regions, for example, as mentioned above regarding... Figure 2C and Figure 2E Two of the metal regions 210-2 to 240-2 are discussed.

[0173] In some embodiments, the plurality of MD regions, gate regions, via regions, and metal regions of a cell are arranged as one of an AOI, OAI, and quad-input NAND devices including first and second conductive regions extending through tracks corresponding to power rails. This includes one of an AOI, OAI, and quad-input NAND devices arranged with additional conductive regions extending through one or more tracks corresponding to power rails, for example, as described above regarding... Figure 2B , 2D The 4B-8B and 11B discussed.

[0174] In some embodiments, the first and second conductive regions extending through the rails corresponding to the power rail include first, second, and any additional conductive regions extending through the rails corresponding to the power rail PR2, as described above. Figure 1C , Figures 2B-2E and Figures 3B-13B .

[0175] In some embodiments, the plurality of MD regions, gate regions, via regions, and metal regions of the cell are arranged to include first and second conductive regions overlapping each of the second and third active regions. One of the AOI, OAI, and four-input NAND devices includes first, second, and any additional conductive regions overlapping each of the second and third active regions at locations corresponding to the S / D regions, as described above regarding... Figures 2B-2E and Figures 3B-13B The subject of discussion.

[0176] In operation 1630, in some embodiments, an IC layout diagram including cells is stored in a storage device. In some embodiments, storing the IC layout diagram including cells in a storage device includes storing the cells in a cell library, such as cell library 1707 of the IC layout diagram generation system 1700, as follows regarding... Figure 17 The subject of discussion.

[0177] In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable storage medium and / or includes storing the IC layout diagram via a network, such as network 1714 of the IC layout diagram generation system 1700, as described below. Figure 17 Discussed.

[0178] In operation 1640, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on an IC layout diagram. For example, performing one or more manufacturing operations based on an IC layout diagram, such as one or more photolithographic exposures, as described above regarding... Figure 15 And the following about Figure 18 discuss.

[0179] By performing some or all of the operations of method 1600, an IC layout diagram corresponding to the IC device is generated, wherein the AOI, OAI, or quad-input NAND IC device includes first and second conductive segments that pass through a plane including a second power rail, thereby obtaining the IC devices 100C, 200-1, 200-2, and 300-1300 described above. Figure 1A-13B The benefits discussed.

[0180] Figure 17 This is a block diagram of an IC design system 1700 according to some embodiments. The design IC layout diagrams described herein according to one or more embodiments can be implemented, for example, using the IC design system 1700 according to some embodiments. In some embodiments, the IC design system 1700 is an APR system, includes an APR system, or is a portion of an APR system that can be used to perform APR methods.

[0181] In some embodiments, the IC layout generation system 1700 is a general-purpose computing device including a hardware processor 1702 and a non-transitory computer-readable storage medium 1704. The storage medium 1704, etc., is encoded to store computer program code 1706, i.e., a set of executable instructions. The execution of the instructions 1706 by the hardware processor 1702 represents (at least partially) the implementation of a portion or all of an EDA tool for a method, such as the IC layout generation method 500 described above with respect to FIG. 5 and / or the IC layout generation method 700 described above with respect to FIG. 7 (hereinafter, the processes and / or methods mentioned).

[0182] Processor 1702 is electrically connected to computer-readable storage medium 1704 via bus 1708. Processor 1702 is also electrically connected to input / output (I / O) interface 1710 via bus 1708. Network interface 1712 is also electrically connected to processor 1702 via bus 1708. Network interface 1712 is connected to network 1714 to enable processor 1702 and computer-readable storage medium 1704 to be connected to external components via network 1714. Processor 1702 is configured to execute computer program code 1706 encoded in computer-readable storage medium 1004 to enable IC design system 1700 to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0183] In one or more embodiments, the computer-readable storage medium 1704 is an electronic, magnetic, fiber-optic, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1704 includes semiconductor or solid-state memory, magnetic tape, mobile electronic disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes an optical disc read-only memory (CD-ROM), an optical disc read / write memory (CD-R / W), and / or a digital video optical disc (DVD).

[0184] In one or more embodiments, computer-readable storage medium 1704 stores computer program code 1706 configured to enable IC design system 1700 (where such execution represents, at least partially, an EDA tool) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1704 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1704 stores a cell library 1707 comprising cells as disclosed herein, such as those described above. Figure 1A-13B Units 100C, 200-1, 200-1 and 300-1300 are discussed.

[0185] IC design system 1700 includes I / O interface 1710. I / O interface 1710 is connected to external circuitry. In one or more embodiments, I / O interface 1710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1702.

[0186] The IC design system 1700 also includes a network interface 1712 connected to the processor 1702. The network interface 1712 allows the IC design system 1700 to communicate with a network 1714, to which one or more other computer systems are connected. The network interface 1712 includes a wireless network interface such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more IC design systems 1700.

[0187] IC design system 1700 is configured to receive information via I / O interface 1710. The information received via I / O interface 1710 includes one or more instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1702. The information is transmitted to processor 1702 via bus 1708. IC design system 1000 is configured to receive information associated with a user interface (UI) via I / O interface 1710. This information is stored as a user interface (UI) 1042 on computer-readable medium 1704.

[0188] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, part or all of the described processes and / or methods are implemented as part of a software application for an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an IC design system 1700. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO, available from CADENCEDESIGNSYSTEMS, Inc., or another suitable layout generation tool.

[0189] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or storage units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, and memory cards.

[0190] Figure 18This is a block diagram of an IC manufacturing system 1800 and an associated IC manufacturing process according to some embodiments. In some embodiments, the manufacturing system 1800 is used to manufacture at least one of the following, based on an IC layout diagram: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0191] exist Figure 18 In this IC manufacturing system 1800, entities interact with each other throughout the design, development, and manufacturing cycles, such as design studio 1820, mask room 1830, and IC manufacturer / producer (“fab”) 1850 and / or services related to the manufacture of IC devices 1860. The entities in system 1800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 1820, mask room 1830, and IC foundry 1850 are owned by a single larger company. In some embodiments, two or more of design studio 1820, mask room 1830, and IC foundry 1850 coexist in a shared facility and use shared resources.

[0192] Design studio (or design team) 1820 generates IC design layout 1822. IC design layout 1822 includes various geometric patterns, such as the IC layout discussed above. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various elements of the IC device 1860 to be manufactured. The various layers combine to form various IC components. For example, a portion of IC design layout 1822 includes various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on a semiconductor substrate. Design studio 1820 implements appropriate design procedures to form IC design layout 1822. Design processes include one or more of logic design, physical design, or placement and routing. IC design layout 1822 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 1822 may be represented in GDSII file format or DFII file format.

[0193] Mask chamber 1830 includes data preparation 1832 and mask fabrication 1844. Mask chamber 1830 uses an IC design layout 1822 to fabricate one or more masks 1845 to fabricate the various layers of an IC device 1860 according to the IC design layout 1822. Mask chamber 1830 performs mask data preparation 1832, in which the IC design layout 1822 is converted into a representative data file (RDF). Mask data preparation 1832 provides the RDF to mask fabrication 1844. Mask fabrication 1844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1845 or a semiconductor wafer 1853. The design layout 1822 is manipulated through mask data preparation 1832 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 1850. Figure 18 In this diagram, mask data preparation 1832 and mask manufacturing 1844 are shown as separate elements. In some embodiments, mask data preparation 1832 and mask manufacturing 1844 can be collectively referred to as mask data preparation.

[0194] In some embodiments, mask data preparation 1832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjusts the IC design layout (Figure 1822). In some embodiments, mask data preparation 1832 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0195] In some embodiments, mask data preparation 1832 includes a mask rule checker (MRC) that checks the IC design layout 1822, which has already been processed in the OPC, using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1822 to compensate for constraints during mask fabrication 1844, which can reverse some modifications performed by the OPC to satisfy the mask creation rules.

[0196] In some embodiments, mask data preparation 1832 includes a lithography process check (LPC), an LPC simulation performed by an IC foundry 1850 to manufacture an IC device 1860. The LPC simulates this process based on an IC design layout 1822 to create a simulated manufactured device, such as IC device 1860. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC check takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), and other suitable factors, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1822.

[0197] It should be understood that, for clarity, the above description of mask data preparation 1832 has been simplified. In some embodiments, data preparation 1832 includes additional components such as logic operations (LOPs) to modify the IC design layout 1822 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1822 during data preparation 1832 can be performed in various different sequences.

[0198] Following mask data preparation 1832 and during mask fabrication 1844, a mask 1845 or a set of masks 1845 is fabricated based on a modified IC design layout 1822. In some embodiments, mask fabrication 1844 includes performing one or more photolithographic exposures based on the IC design layout 1822. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 1845 according to the modified IC design layout 1822. The mask 1845 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1845. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) or EUV beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary intermediate mask of mask 1845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1845 is formed using a phase-shifting technique. In the phase-shifting mask (PSM) version of mask 1845, various components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be a decaying PSM or an alternating PSM. One or more masks generated by mask fabrication 1844 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1853, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0199] IC foundry 1850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC foundry 1850 is a semiconductor foundry. For example, there may be manufacturing devices for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing device can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing device may provide other services for casting operations.

[0200] IC foundry 1850 includes wafer fabrication tools 1852 configured to perform various fabrication operations on semiconductor wafers 1853, such that IC devices 1860 are fabricated according to one or more masks (e.g., mask 1845). In various embodiments, fabrication tools 1852 include one or more of the following: wafer stepper, ion implanter, coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication devices as discussed herein capable of performing one or more suitable fabrication processes.

[0201] IC foundry 1850 uses mask 1845, fabricated through mask chamber 1830, to fabricate IC device 1860. Therefore, IC foundry 1850 uses IC design layout 1822 at least indirectly to fabricate IC device 1860. In some embodiments, using mask 1845, IC foundry 1850 fabricates semiconductor wafer 1853 to form IC device 1860. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1822. Semiconductor wafer 1853 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon. Semiconductor wafer 1853 also includes one or more of various doped regions, dielectric components, and multilayer interconnects (formed in subsequent fabrication steps).

[0202] In some embodiments, the IC device includes: first and second power rails extending along a first direction, wherein each of the first and second power rails is configured to carry a power supply voltage and a power supply reference voltage; a third power rail extending along the first direction between the first and second power rails, wherein the third power rail is configured to carry the other of the power supply voltage and the power supply reference voltage; and a plurality of transistors including a first to a fourth active region extending along the first direction between the first and second power rails, wherein each of the second and third active regions is adjacent to the third power rail; a plurality of gate structures extending in a second direction perpendicular to the first direction; and a first conductive segment and a second conductive segment extending through the third power rail in the second direction. Each of the first and second conductive segments is electrically connected to an S / D structure in each of the second and third active regions, and the plurality of transistors is configured as one of an AOI, an OAI, and a four-input NAND gate. In some embodiments, the first and second conductive segments include corresponding first and second MD segments located below the third power rail and covering the corresponding S / D structures in the second and third active regions. In some embodiments, the IC device includes third and fourth metal segments located below a third power rail and covering corresponding S / D structures in the second and third active regions. In some embodiments, a first metal segment to a third metal segment extend along the first direction, wherein the first metal segment covers the first type of metal-defined segment and the second type of metal-defined segment and covers and is electrically connected to the fifth type of metal-defined segment to the seventh type of metal-defined segment, the fifth to the seventh type of metal-defined segment covers the corresponding S / D structure in the second active region, the second metal segment covers the third type of metal-defined segment and covers and is electrically connected to the eighth type of metal-defined segment and the ninth type of metal-defined segment covering the corresponding S / D structure in the third active region, and the third metal segment covers the fourth type of metal-defined segment and covers and is electrically connected to the tenth type of metal-defined segment and the eleventh type of metal-defined segment covering the corresponding S / D structure in the third active region. In some embodiments, the IC device includes a first conductive path comprising a first type of metal-defined segment and a first metal segment extending along the first direction and electrically connected to each of the first type of metal-defined segment and the third type of metal-defined segment covering a corresponding S / D structure in the second active region; and a second conductive path comprising a second type of metal-defined segment and a second metal segment extending along the first direction and electrically connected to each of the second type of metal-defined segment and the fourth type of metal-defined segment covering a corresponding S / D structure in the second active region.In some embodiments, the first conductive path further includes a fifth type of metal-defined segment extending through the third power rail in the second direction and electrically connected to the corresponding S / D structure in each of the first metal segment and the second active region and the third active region; and the second conductive path further includes a sixth type of metal-defined segment extending through the third power rail in the second direction and electrically connected to the corresponding S / D structure in each of the second active region and the third active region. In some embodiments, the IC device includes a third conductive path comprising: a fifth type of metal-defined segment extending through the third power rail in the second direction and electrically connected to the corresponding S / D structure in each of the second active region and the third active region; and a third metal segment extending in the first direction and electrically connected to each of the fifth type of metal-defined segment, the sixth type of metal-defined segment, and the seventh type of metal-defined segment covering the corresponding S / D structure in the third active region. In some embodiments, each of the first conductive segment and the second conductive segment includes a metal segment covering the third power rail and each of the corresponding S / D structures in the second active region and the third active region. In some embodiments, each of the first and second power rails is configured to carry a power supply voltage, and the third power rail is configured to carry the power supply reference voltage. Each of the first and fourth active regions includes a p-type active region, and each of the second and third active regions includes an n-type active region. In some embodiments, each of the first and second power rails is configured to carry a power supply reference voltage, the third power rail is configured to carry a power supply voltage, each of the first and fourth active regions is an n-type active region, and each of the second and third active regions is a p-type active region.

[0203] In some embodiments, the IC device includes a first row of transistors, comprising: a first active region and a second active region extending along a first direction and adjacent to corresponding first and second power rails, each of the first and second active regions including a plurality of source / drain S / D structures; and a first plurality of gate structures extending between the first and second power rails along a second direction perpendicular to the first direction, wherein the first row of transistors is configured to receive a first subset of a plurality of input signals; the second row of transistors includes: a third active region and a fourth active region extending along the first direction and adjacent to the second and third power rails respectively, each of the third and fourth active regions... Each includes multiple S / D structures; and a second plurality of gate structures extending along the second direction between the second power rail and the third power rail, wherein the second row of transistors is configured to receive a second subset of the plurality of input signals; and a first conductive segment and a second conductive segment extending through the second power rail in the second direction, wherein each of the first conductive segment and the second conductive segment is electrically connected to the S / D structure in each of the plurality of S / D structures in the second active region and the third active region, and the first row of transistors and the second row of transistors, as well as the first conductive segment and the second conductive segment, are configured as one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND gate. In some embodiments, the first row of transistors includes: a pull-up transistor including a first active region and configured to receive a first subset of the plurality of input signals; and a pull-down transistor including a second active region and configured to receive the first subset of the plurality of input signals. The second row of transistors includes: a pull-down transistor including the third active region and configured to receive the second subset of the plurality of input signals; and a pull-up transistor including the fourth active region and configured to receive the second subset of the plurality of input signals. In some embodiments, the first row of transistors includes: a pull-down transistor including the first active region and configured to receive the first subset of the plurality of input signals; and a pull-up transistor including the second active region and configured to receive the first subset of the plurality of input signals. The second row of transistors includes: a pull-up transistor including the third active region and configured to receive the second subset of the plurality of input signals; and a pull-down transistor including the fourth active region and configured to receive the second subset of the plurality of input signals. In some embodiments, each of the first and second rows of transistors is configured to receive a plurality of input signals comprising a total of two corresponding first or second subsets of the input signals. In some embodiments, each of the first and second rows of transistors is configured to receive an input signal from a plurality of input signals in addition to a first subset and a second subset of the plurality of input signals.In some embodiments, the IC device includes a metal segment that extends through the second power rail in a second direction and is configured to carry an output signal.

[0204] In some embodiments, a method of manufacturing an IC device includes forming, in a semiconductor substrate, a first active region and a second active region in a first row extending along a first direction, and a third active region and a fourth active region in a second row adjacent to the first row, wherein each active region includes a plurality of source / drain S / D structures; constructing a first conductive segment and a second conductive segment extending along a second direction, wherein each of the first conductive segment and the second conductive segment covers and is electrically connected to the S / D structures in each of the second active region and the third active region; constructing additional conductive segments, a plurality of gate structures, and a plurality of via structures to form one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND device including the first conductive segment and the second conductive segment and pull-up and pull-down transistors in each of the first row and the second row; and constructing a first power rail to a third power rail extending along the first direction, wherein the first power rail and the second power rail are aligned with the first row, the second power rail and the third power rail are aligned with the second row, and each of the first conductive segment and the second conductive segment passes through a plane perpendicular to the first conductive segment and the second conductive segment and including the second power rail. In some embodiments, constructing the first and second conductive segments includes constructing MD segments. In some embodiments, constructing the first and second conductive segments further includes constructing a third and fourth conductive segment extending along the second direction, wherein each of the third and fourth conductive segments covers and is electrically connected to the S / D structure in each of the second and third active regions. In some embodiments, forming each of the first and fourth active regions includes forming an n-type active region and forming each of the second and third active regions includes forming a p-type active region, or forming each of the first and fourth active regions includes forming a p-type active region and forming each of the second and third active regions includes forming an n-type active region.

[0205] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit (IC) device, comprising: A first power rail and a second power rail extend along a first direction, wherein each of the first power rail and the second power rail is configured to carry one of a power supply voltage and a power supply reference voltage. A third power rail extends along the first direction between the first power rail and the second power rail, wherein the third power rail is configured to carry another of the power supply voltage and the power supply reference voltage; and Multiple transistors, including: The first to fourth active regions extend along the first direction between the first power rail and the second power rail, wherein each of the second and third active regions is adjacent to the third power rail, each of the first and second active regions includes a plurality of first source / drain S / D structures, and each of the third and fourth active regions includes a plurality of second source / drain S / D structures. Multiple gate structures extend along a second direction perpendicular to the first direction; and A first conductive segment and a second conductive segment extend across the third power rail in the second direction, wherein each of the first conductive segment and the second conductive segment is electrically connected to the first source / drain S / D structure of the plurality of first source / drain S / D structures in the second active region and the second source / drain S / D structure of the plurality of second source / drain S / D structures in the third active region. The plurality of transistors are configured as one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), or a four-input NAND.

2. The integrated circuit (IC) device according to claim 1, wherein, The first conductive segment and the second conductive segment include corresponding first-type metal-defined segments and second-type metal-defined segments that both extend across the bottom of the third power rail and respectively cover the corresponding first source / drain S / D structure in the second active region and the corresponding second source / drain S / D structure in the third active region.

3. The integrated circuit (IC) device according to claim 2, further comprising: The third and fourth metal-limiting segments extend in the second direction and both extend below the third power rail, respectively covering the corresponding first source / drain S / D structure in the second active region and the corresponding second source / drain S / D structure in the third active region.

4. The integrated circuit (IC) device according to claim 3, further comprising: The first metal segment to the third metal segment extend along the first direction, wherein The first metal segment covers the first type of metal-defined segment and the second type of metal-defined segment, and covers and is electrically connected to the fifth to seventh type of metal-defined segments, wherein the fifth to seventh type of metal-defined segments cover the corresponding first source / drain S / D structure in the second active region. The second metal segment covers the third type of metal-defined segment and covers and is electrically connected to the eighth and ninth type of metal-defined segments of the corresponding second source / drain S / D structure in the third active region, and The third metal segment covers the fourth type of metal segment and covers and is electrically connected to the tenth and eleventh type of metal segments that cover the corresponding second source / drain S / D structure in the third active region.

5. The integrated circuit (IC) device according to claim 3, further comprising: The first conductive path includes a first type of metal-defined segment and a first metal segment extending along the first direction and electrically connected to each of the first type of metal-defined segment and the third type of metal-defined segment covering the first source / drain S / D structure in the second active region. as well as The second conductive path includes a second type of metal-defined segment and a second metal segment extending along the first direction and electrically connected to each of the second type of metal-defined segment and the fourth type of metal-defined segment covering the corresponding first source / drain S / D structure in the second active region.

6. The integrated circuit (IC) device according to claim 5, wherein... The first conductive path further includes a fifth type of metal segment extending in the second direction across the third power rail and electrically connected to the first metal segment and the fifth type of metal segment in the second active region corresponding to the first source / drain S / D structure and the third active region corresponding to the second source / drain S / D structure, and The second conductive path further includes a sixth type of metal segment extending in the second direction across the third power rail and electrically connected to the second metal segment and the sixth type of metal segment corresponding to the first source / drain S / D structure in the second active region and the second source / drain S / D structure in the third active region.

7. The integrated circuit (IC) device according to claim 5, further comprising: A third conductive path, the third conductive path comprising: A fifth type of metal-defined segment extends in the second direction across the third power rail and is electrically connected to the corresponding first source / drain S / D structure in the second active region and the corresponding second source / drain S / D structure in the third active region; and The third metal segment extends in the first direction and is electrically connected to each of the fifth, sixth, and seventh metal segments on the corresponding second source / drain S / D structure covering the third active region.

8. The integrated circuit (IC) device according to claim 1, wherein, Each of the first conductive segment and the second conductive segment includes a metal segment that covers the third power rail and the corresponding first source / drain S / D structure in the second active region and the corresponding second source / drain S / D structure in the third active region.

9. The integrated circuit (IC) device according to claim 1, wherein... Each of the first power rail and the second power rail is configured to carry a power supply voltage. The third power rail is configured to carry the power reference voltage. Each of the first active region and the fourth active region includes a p-type active region, and Each of the second active region and the third active region includes an n-type active region.

10. The integrated circuit (IC) device according to claim 1, wherein, Each of the first power rail and the second power rail is configured to carry the power reference voltage. The third power rail is configured to carry the power supply voltage. Each of the first active region and the fourth active region includes an n-type active region, and Each of the second and third active regions includes a p-type active region.

11. An integrated circuit (IC) device, comprising: The first row of transistors includes: a first active region and a second active region extending along a first direction and located between corresponding first and second power rails extending along the first direction, the second active region being adjacent to the second power rail, each of the first and second active regions including a plurality of first source / drain S / D structures; and a first plurality of gate structures extending between the first and second power rails along a second direction perpendicular to the first direction, wherein the first row of transistors is configured to receive a first subset of a plurality of input signals; The second row of transistors includes: a third active region and a fourth active region extending in the first direction and located between the second power rail and the third power rail extending in the first direction, the third active region being adjacent to the second power rail, each of the third and fourth active regions including a plurality of second source / drain S / D structures; and a second plurality of gate structures extending in the second direction between the second and third power rails, wherein the second row of transistors is configured to receive a second subset of the plurality of input signals; and The first conductive segment and the second conductive segment extend across the second power rail in the second direction. in Each of the first conductive segment and the second conductive segment is electrically connected to the first source / drain S / D structure of the plurality of first source / drain S / D structures in the second active region and the second source / drain S / D structure of the plurality of second source / drain S / D structures in the third active region. The first row transistors and the second row transistors, as well as the first conductive segment and the second conductive segment, are configured as one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND gate.

12. The integrated circuit (IC) device according to claim 11, wherein The first row of transistors includes: A pull-up transistor, including the first active region and configured to receive the first subset of the plurality of input signals; and a pull-down transistor, including the second active region and configured to receive the first subset of the plurality of input signals, and The second row of transistors includes: a pull-down transistor, which includes the third active region and is configured to receive the second subset of the plurality of input signals; and a pull-up transistor, including the fourth active region and configured to receive the second subset of the plurality of input signals.

13. The integrated circuit (IC) device according to claim 11, wherein The first row of transistors includes: pull-down A transistor, including the first active region and configured to receive the first subset of the plurality of input signals; and a pull-up transistor, including the second active region and configured to receive the first subset of the plurality of input signals, and The second row of transistors includes: a pull-up transistor, which includes the third active region and is configured to receive the second subset of the plurality of input signals; and a pull-down transistor, including the fourth active region and configured to receive the second subset of the plurality of input signals.

14. The integrated circuit (IC) device according to claim 11, wherein The first row of transistors and the second row of transistors are configured to receive a corresponding first subset or second subset of the plurality of input signals, each of the first subset and the second subset comprising two input signals.

15. The integrated circuit (IC) device according to claim 14, wherein... Each of the first row of transistors and the second row of transistors is also configured to receive other input signals from the plurality of input signals besides the first subset and the second subset.

16. The integrated circuit (IC) device according to claim 11, further comprising: A metal segment extends across the second power rail in the second direction and is configured to carry an output signal.

17. A method for manufacturing an integrated circuit (IC) device, the method comprising: In a semiconductor substrate, a first active region and a second active region are formed in a first row extending along a first direction, and a third active region and a fourth active region are formed in a second row adjacent to the first row. The first active region and the second active region each include a plurality of first source / drain S / D structures, and the third active region and the fourth active region each include a plurality of second source / drain S / D structures. Construct a first conductive segment and a second conductive segment extending along a second direction, wherein each of the first conductive segment and the second conductive segment covers and is electrically connected to the first source / drain S / D structure of the plurality of first source / drain S / D structures in the second active region and the second source / drain S / D structure of the plurality of second source / drain S / D structures in the third active region; Construct additional conductive segments, multiple gate structures, and multiple via structures to form one of an AND-OR-NOT gate (AOI), an OR-AND-NOT gate (OAI), and a four-input NAND device, including the first conductive segment and the second conductive segment, and pull-up and pull-down transistors in each of the first and second rows; and Construct a first power rail to a third power rail extending along the first direction. in The first row is located between the first power rail and the second power rail. The second row is located between the second power rail and the third power rail, and Each of the first conductive segment and the second conductive segment spans a plane perpendicular to the first conductive segment and the second conductive segment and including the second power rail.

18. The method according to claim 17, wherein, Constructing the first conductive segment and the second conductive segment includes constructing a metal-like defined segment.

19. The method of claim 17, wherein, Constructing the first conductive segment and the second conductive segment further includes: Construct a third conductive segment and a fourth conductive segment extending along the second direction, wherein each of the third conductive segment and the fourth conductive segment covers and is electrically connected to the first source / drain S / D structure of the plurality of first source / drain S / D structures in the second active region and the second source / drain S / D structure of the plurality of second source / drain S / D structures in the third active region.

20. The method of claim 17, wherein, Each of the formation of the first active region and the fourth active region includes forming an n-type active region, and each of the formation of the second active region and the third active region includes forming a p-type active region, or Forming each of the first active region and the fourth active region includes forming a p-type active region, and forming each of the second active region and the third active region includes forming an n-type active region.

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