A cascade H-bridge converter and a parallel branch modulation method and a pre-charge method thereof

Abstract

The application discloses a kind of cascade H bridge converter and parallel branch modulation method and pre-charging method thereof, on the basis of traditional cascade H bridge converter, and parallel branch is connected with the positive end and / or negative end of adjacent H bridge module capacitor;Positive parallel branch is connected to the positive end of capacitor, and negative parallel branch is connected to the negative end of capacitor;Parallel branch is composed of bidirectional switch.The application connects the positive and negative ends of each sub-module capacitor by parallel branch, realizes the balance of H bridge module capacitor in sequence by conducting parallel branch in the zero state of traditional cascade H bridge converter;The topology avoids the sampling of each module DC voltage, high-speed data transmission and high computational resource consumption capacitor voltage balancing control algorithm, with the advantages of simple circuit structure and control system, low cost, small size, good voltage-sharing effect, easy to expand, etc.

Description

Technical Field

[0001] This invention relates to the technical field, specifically to a cascaded H-bridge converter and its parallel branch modulation method and pre-charging method. Background Technology

[0002] Cascaded H-bridge converters (CHBCs) offer advantages such as high modularity and scalability, high reliability, low harmonics, and flexible control. They are widely used in active power filters, synchronous var compensators, and solid-state transformers, and are currently one of the preferred main circuit topologies for power electronics in medium and low voltage systems. However, because CHBCs contain multiple independent DC capacitors, voltage imbalances can occur due to factors such as inter-module losses, modulation, component parameters, and signal delays. This imbalance directly affects output waveform quality, switching voltage and current stress, and the converter's dynamic response speed. Extreme imbalances can even lead to system lockout or damage. Therefore, maintaining voltage balance among the CHBC's sub-module capacitors is crucial for its stable operation.

[0003] The submodule capacitor voltage equalization methods for CHBC can be mainly divided into two categories: software methods and hardware methods. The centralized control method based on multiple samplers is currently the most widely used and technologically mature software-based capacitor voltage equalization method. Its basic technical approach is as follows: DC capacitance of each module is collected, and high-bandwidth data is transmitted to the top-level controller. Control methods such as capacitor voltage sorting, bias voltage compensation, or power distribution are used to calculate the modulation wave or switching signal of each module, and then distributed to each submodule. This method has the advantages of simple structure and stable control, but as the number of modules increases, the complexity of the communication system and the computational pressure on the top-level controller will increase dramatically. With the development of sampling technology, in recent years, some scholars have proposed using high-precision repeated sampling of the CHBC output stepped wave to identify the DC capacitor voltage of each module, thus avoiding the use of a large number of DC samplers. However, as the number of modules increases, the sampling and identification of the stepped wave becomes particularly difficult, and this method still cannot solve the problem of high computational pressure on the top-level controller.

[0004] The basic idea of ​​hardware-based capacitor voltage self-balancing methods is to achieve capacitor voltage balancing by constructing parallel paths between modules. This type of method has advantages such as simple structure, no need for complex samplers and communication systems, and no pressure for voltage balancing calculations. The earliest dual H-bridge topology constructed parallel paths between modules, enabling local parallel balancing between the two H-bridge modules. Subsequent full-bridge, asymmetric half-bridge, and symmetric half-bridge H-bridge parallel topologies introduced additional parallel states beyond the series and bypass states of traditional CHBCs, making parallel connection of all sub-modules possible. However, the implementation of parallel states in these topologies requires additional switching devices, leading to increased system cost and more complex driving logic. To reduce the number of switches in parallel CHBCs, diodes can be used to replace IGBT switches, but the unidirectional conduction characteristic of diodes reduces balancing capability. Alternatively, the number of switches can be reduced by eliminating redundant switching states.

[0005] The magnitude of the inrush current during parallel balancing and the resulting losses are important indicators for evaluating the applicability of parallel CHBC topologies. To reduce the inrush current, methods such as appropriately designed current-limiting inductors and the addition of snubber circuits can be employed. However, current-limiting inductors are not always effective in suppressing the inrush current because resonance may occur between numerous LC circuits, leading to an increase in the parallel inrush current, a deterioration in the balancing effect, or even failure to operate. The modulation method of the parallel CHBC determines the state of each switch during the parallel connection process. In most existing modulation methods, the connection (charging or discharging) of capacitors and their parallel connection with adjacent capacitors may occur simultaneously. This will cause the normal operating current and the balancing inrush current to overlap, exceeding the maximum current stress of the switches. Furthermore, the complex wiring of parallel topologies makes it difficult to extend and upgrade hardware self-balancing methods on traditional HB-MMC and FB-MMC topologies. Summary of the Invention

[0006] To address the aforementioned problems, the present invention aims to provide a cascaded H-bridge converter and its parallel branch modulation and pre-charging methods. This avoids sampling the DC voltage of each module, high-speed data transmission, and computationally expensive capacitor voltage equalization control algorithms. It offers advantages such as simple circuit structure and control system, low cost, small size, good voltage equalization effect, and easy expansion. The technical solution is as follows:

[0007] A cascaded H-bridge converter with hardware parallel voltage equalization capability is based on the traditional cascaded H-bridge converter. Parallel branches connect the positive and / or negative terminals of the capacitors of adjacent H-bridge modules. The parallel branch connected to the positive terminal of the capacitor is the positive parallel branch, and the parallel branch connected to the negative terminal of the capacitor is the negative parallel branch. The parallel branches are composed of bidirectional switches.

[0008] Furthermore, the bidirectional switch includes two IGBTs connected in reverse series, with a diode connected in parallel between the collector and emitter of each IGBT, and the positive terminal of the diode connected to the collector of the IGBT.

[0009] Furthermore, the bidirectional switch comprises two IGBTs connected in anti-parallel.

[0010] Furthermore, the bidirectional switch includes a hybrid connection of one IGBT and four diodes; the anodes of two diodes are simultaneously connected to the emitters of the IGBT, and the cathodes of these two diodes are respectively connected to the capacitors of adjacent H-bridge modules; the cathodes of the other two diodes are simultaneously connected to the collectors of the IGBT, and the anodes of these two diodes are respectively connected to the capacitors of adjacent H-bridge modules.

[0011] Furthermore, the parallel branches are connected in a double-ended forward parallel configuration, meaning that N-1 positive parallel branches and N-1 negative parallel branches are simultaneously connected to the positive and negative terminals of N H-bridge module capacitors.

[0012] Alternatively, the parallel branch can be connected in a single-ended forward parallel configuration, i.e., N-1 positive parallel branches are connected to the positive terminals of N H-bridge module capacitors, or N-1 negative parallel branches are connected to the negative terminals of N H-bridge module capacitors.

[0013] Alternatively, the parallel branches can be connected in an alternating parallel configuration, where the positive and negative terminals of the capacitor are connected alternately by the positive and negative parallel branches.

[0014] A method for modulating the parallel branches of a cascaded H-bridge converter with hardware parallel voltage equalization capability is disclosed. When two adjacent H-bridge modules simultaneously exhibit the PZ state (i.e., when both upper switches are on, the negative parallel branch is activated); when two adjacent H-bridge modules simultaneously exhibit the NZ state (i.e., when both lower switches are on, the positive parallel branch is activated), the parallel branch is activated.

[0015] ;

[0016] Among them, S NPBi The modulation signal for the negative parallel branch; S i1 S i3 S （i+1）1 S （i+1）3 The modulation signals for the two upper switches of two adjacent H-bridge modules; S PPBi The modulation signal for the positive parallel branch; S i2 S i4 S （i+1）2 S （i+1）4 The modulation signals are for the two lower switches of two adjacent H-bridge modules.

[0017] A pre-charging method for a cascaded H-bridge converter includes the following steps:

[0018] S1: Construct a path for all capacitors to be connected in parallel simultaneously;

[0019] S2: Connect the positive and negative terminals of any capacitor to a DC voltage source;

[0020] S3: The DC voltage source output voltage slowly increases from 0 to the capacitor's rated voltage;

[0021] S4: Lock all switches and wait for the start command.

[0022] Furthermore, in step S1,

[0023] When constructing a parallel path for cascaded H-bridge converters connected in forward parallel at both ends: lock out the switches of all H-bridge modules and close all positive parallel branches and negative parallel branches.

[0024] When a cascaded H-bridge converter with single-ended forward parallel connection constructs a parallel path: all H-bridge modules output PZ state, that is, the two upper switches are turned on and all negative parallel branches are closed; or all H-bridge modules output NZ state, that is, the two lower switches are turned on and all positive parallel branches are closed.

[0025] When constructing a parallel path using cascaded H-bridge converters connected in an interleaved parallel configuration: close the switches S of two adjacent H-bridge modules. i4 S (i+1)2 Positive parallel branch PPB i and closing switch S (i+1)3 S (i+2)1 Negative parallel branch NPB (i+1) All other switches of the H-bridge module are locked.

[0026] The beneficial effects of this invention are as follows: This invention proposes a cascaded H-bridge converter with hardware parallel self-equalizing voltage capability. It utilizes parallel branches to connect the positive and negative terminals of the capacitors of each sub-module. By conducting the parallel branches in the zero state of a traditional cascaded H-bridge converter, sequential equalization of the capacitors among the H-bridge modules is achieved. This topology avoids sampling the DC voltage of each module, high-speed data transmission, and capacitor voltage equalization control algorithms that consume high computational resources. It has the advantages of simple circuit structure and control system, low cost, small size, good voltage equalization effect, and easy expansion. Attached Figure Description

[0027] Figure 1 It is a traditional cascaded H-bridge converter.

[0028] Figure 2 This invention relates to a cascaded H-bridge converter connected in forward parallel configuration.

[0029] Figure 3 This invention relates to a cascaded H-bridge converter with interleaved parallel connections.

[0030] Figure 4 The topologies for parallel branches are: (a) reverse series IGBT / D; (b) reverse parallel IGBT; (c) hybrid IGBT / D.

[0031] Figure 5 The equivalent circuit diagrams are shown when the parallel branches are conducting; (a) the negative parallel branch is in the PZ state; (b) the positive parallel branch is in the NZ state.

[0032] Figure 6 This is a schematic diagram of modulation.

[0033] Figure 7 A schematic diagram of the method for constructing a parallel path for pre-charging IP-CHBC. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The present invention proposes a cascaded H-bridge converter with hardware parallel self-equalizing voltage capability. It utilizes parallel branches to connect the positive and negative terminals of the capacitors in each sub-module. By conducting the parallel branches in a zero-state state, a sequential equalization of the capacitors among the H-bridge modules is achieved. Specifically:

[0035] 1. Topology Description

[0036] Traditional cascaded H-bridge converters consist of a series of H-bridge converters connected end-to-end, such as... Figure 1 As shown. Switching allows a single Half Bridge Module (HBM) to output ±1 and 0 voltage levels, while the entire CHBC outputs a high-frequency stepped waveform. Since all HBM capacitors exist only in bypass and series states, voltage equalization exists between them. To enable parallel voltage equalization in the CHBC, parallel branches can be used to connect the positive and negative terminals of capacitors from adjacent HBMs. For example... Figure 2 As shown, the positive parallel branch (PPB) is used to connect to the positive terminal of the capacitor, and the negative parallel branch (NPB) is used to connect to the negative terminal of the capacitor. The parallel branches can be constructed as follows: Figure 4 The three types of bidirectional switches shown constitute the circuit. The connection forms of parallel branches vary. This paper presents three typical connection forms: (1) Double Straight Forward Parallel (DSFP): N-1 PPBs and N-1 NPBs are simultaneously connected to the positive and negative terminals of all HBM capacitors, such as... Figure 2As shown; (2) Single Straight Forward Parallel (SSFP): N-1 PPBs are connected to the positive terminal of the capacitor, or N-1 NPBs are connected to the negative terminal of the capacitor; (3) Interleaving Parallel (IP): PPBs and NPBs are alternately connected to the positive and negative terminals of the capacitor, as shown. Figure 3 As shown.

[0037] 2. Operating Principle

[0038] Since the upper and lower switches of each HBM are complementary and conduction is complementary, there are a total of 4 switch states, namely (1) P state (Positive State): S1=1, S3=0; (2) N state (Negative State): S1=0, S3=1; (3) NZ state (Negative Zero State): S1=0, S3=0; (4) PZ state (Positive Zero State): S1=1, S3=1.

[0039] In P and N states, HBM outputs +V respectively. c -V c In the zero-state, the HBM outputs 0 voltage. For HBMs under phase-shifted carrier modulation, the phase difference between the modulated waves of each module is π / N, and there is one PZ state and one NZ state within one carrier cycle. To achieve parallel connection between module capacitors without affecting the normal output voltage of the modules, the NPB can be turned on when two adjacent modules are simultaneously in the PZ state, such as... Figure 5 (a) and / or PPB is activated when two adjacent modules simultaneously reach the NZ state, such as Figure 5 (b), that is:

[0040] (1)

[0041] The equivalent circuit when PB is turned on is as follows: Figure 5 As shown.

[0042] It can be observed that the zero-state switch of the HBM, in addition to providing a path for the normal operating current, also provides a path for the parallel voltage-equalizing current of the two capacitors. Since both HBMs are in the zero state, their output voltage is zero, and the conduction of the parallel branch will not affect the original output voltage. When PB is in the off state, based on the switching state combination of the two HBMs, the voltage across PB can be ±V. ci ±V c(i+1) ±(V) ci -V c(i+1) Therefore, the selection of the withstand voltage value of the switching transistor in the PB branch is consistent with that of HBM.

[0043] 3. Comparison of the three proposed topologies

[0044] Taking a 4-module CHBC as an example for analysis, when the reference modulation wave V mref When =0.4, the switching signals of each PB are as follows: Figure 6 As shown. It can be observed that: with V mref Approaching 0, S PPB1 ~S PPB3 or S NPB1 ~S NPB3 There will be overlap. Specifically, when V... mref When the voltage is 0, all three PPB branches and three NPB branches are simultaneously conducting, resulting in a total CHBC output voltage of 0. Since there is always a slight voltage difference between the HBM capacitors, when multiple capacitors are connected in parallel to equalize the voltage, an equalization current flows through each parallel branch, leading to increased switching losses during the equalization process.

[0045] Therefore, for DSFP-CHBC, the loss caused by the equalization inrush current is the greatest, and the number of parallel branches is the largest (2N-2), but the voltage equalization effect is the best because the equalization process occurs simultaneously in both PZ and NZ states. For SSFP-CHBC, the loss caused by the equalization inrush current is the second greatest, the number of parallel branches is smaller (N-1), and the voltage equalization effect is relatively good, with the equalization process occurring only in either the PZ or NZ state. Figure 4 It can be seen that adjacent S PPB With S NPB There is no overlap between them, meaning that IP-CHBC will not have multiple capacitors connected in parallel for voltage equalization at the same time. The parallel connection process alternates between two adjacent HBMs. Therefore, it has the least loss due to the equalization inrush current, fewer parallel branches (N-1), good voltage equalization effect, and the equalization process only alternates between PZ and NZ states.

[0046] 4. Pre-charge strategy

[0047] When a large voltage difference exists between the HBM capacitors, the conduction of PB will lead to a large equalization current surge. Theoretically, an inductor can be inserted in series in the parallel equalization branch to limit the current surge, but this will reduce the voltage equalization effect between the capacitors to some extent (with a fixed zero-state time, the smaller the current flowing through PB, the less energy is exchanged between the capacitors, and the worse the equalization effect), and it will also increase the cost and size of the system. It is worth noting that for a parallel CHBC operating in steady state, the voltage deviation between the capacitors is small, and due to the internal resistance and forward voltage drop of the IGBT and diodes, the actual equalization surge current is small. In addition, large voltage deviations between capacitors generally only occur at the initial operating moment of the system. If the initial capacitor voltages are basically equal, the use of a current-limiting inductor can be avoided.

[0048] For traditional CHBCs, the pre-charging strategy is relatively complex. With the addition of parallel branches, the pre-charging method of parallel CHBCs becomes particularly simple. The basic method is as follows: (1) Construct a path in which all capacitors are connected in parallel at the same time; (2) Select the positive and negative terminals of any capacitor to connect to a DC voltage source; (3) Slowly increase the output voltage of the DC voltage source from 0 to the rated voltage of the capacitor; (4) Lock all switches and wait for the start command.

[0049] The method for constructing a parallel path for DSFP-CHBC is as follows: Block all HBM switches and close all PPBs and NPBs; the method for constructing a parallel path for SSFP-CHBC is as follows: All HBMs output PZ state and close all NPBs, or all HBMs output NZ state and close all PPBs; the method for constructing a parallel path for IP-CHBC is as follows: Close S... i4 S (i+1)2 PPB i and closed S (i+1)3 S (i+2)1 NPB (i+1) All other switches of HBM are locked, such as Figure 7 As shown.

Claims

1. A method for modulating the parallel branches of a cascaded H-bridge converter, characterized in that, The cascaded H-bridge converter, based on the traditional cascaded H-bridge converter, connects the positive and / or negative terminals of the capacitors of adjacent H-bridge modules via parallel branches. The branch connected to the positive terminal of the capacitor is the positive parallel branch, and the branch connected to the negative terminal of the capacitor is the negative parallel branch. The parallel branches are constructed from bidirectional switches. The connection method of the parallel branches is a double-ended forward parallel connection, that is, N-1 positive parallel branches and N-1 negative parallel branches are simultaneously connected to the positive and negative terminals of the capacitors of N H-bridge modules. Alternatively, the parallel branch can be connected in a single-ended forward parallel configuration, i.e., N-1 positive parallel branches are connected to the positive terminals of N H-bridge module capacitors, or N-1 negative parallel branches are connected to the negative terminals of N H-bridge module capacitors. Alternatively, the parallel branches can be connected in an alternating parallel configuration, where the positive and negative terminals of the capacitor are connected alternately by the positive and negative parallel branches. When two adjacent H-bridge modules simultaneously enter the PZ state (i.e., both upper switches are on), the negative parallel branch is activated; when two adjacent H-bridge modules simultaneously enter the NZ state (i.e., both lower switches are on), the positive parallel branch is activated. ； Wherein, S NPBi is the modulation signal of the negative parallel branch; S i1 , S i3 , S （i+1）1 , S （i+1）3 is the modulation signal of the two upper switches of the adjacent two H-bridge modules; S PPBi is the modulation signal of the positive parallel branch; S i2 , S i4 , S （i+1）2 , S （i+1）4 is the modulation signal of the two lower switches of the adjacent two H-bridge modules.

2. A pre-charging method using the parallel branch modulation method of the cascaded H-bridge converter as described in claim 1, characterized in that, Includes the following steps: S1: Construct a path for all capacitors to be connected in parallel simultaneously; S2: Connect the positive and negative terminals of any capacitor to a DC voltage source; S3: The DC voltage source output voltage slowly increases from 0 to the capacitor's rated voltage; S4: Lock all switches and wait for the start command.

3. The pre-charging method according to claim 2, characterized in that, In step S1, When constructing a parallel path for cascaded H-bridge converters connected in forward parallel at both ends: lock out the switches of all H-bridge modules and close all positive parallel branches and negative parallel branches. When a cascaded H-bridge converter with single-ended forward parallel connection constructs a parallel path: all H-bridge modules output PZ state, that is, the two upper switches are turned on and all negative parallel branches are closed; or all H-bridge modules output NZ state, that is, the two lower switches are turned on and all positive parallel branches are closed. When constructing a parallel path using cascaded H-bridge converters connected in an interleaved parallel configuration: close the switches S of two adjacent H-bridge modules. i4 S (i+1)2 Positive parallel branch PPB i and closing switch S (i+1)3 S (i+2)1 Negative parallel branch NPB (i+1) All other switches of the H-bridge module are locked.

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