Data delay method, apparatus, circuit, electronic device, and readable storage medium
By performing store and read operations on only one register within a single clock cycle in the data delay circuit, the problem of high power consumption in the data delay circuit is solved, resulting in a significant reduction in power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- VIVO MOBILE COMM CO LTD
- Filing Date
- 2023-03-21
- Publication Date
- 2026-05-19
AI Technical Summary
In existing technologies, data delay circuits consume a lot of power when the data bit width is large or the number of register stages is large.
The data is stored in the target register in the Mth clock cycle, and if M is greater than N, the data stored in the target register in the MNth clock cycle is retrieved in the Mth clock cycle. The storage and read operations are performed on a register only in one clock cycle.
It reduces power consumption during data latency, especially when the data bit width is large or the number of register levels is high, with a power consumption reduction of up to 81.86%.
Smart Images
Figure CN116248088B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of digital circuits, and specifically relates to a data delay method, apparatus, circuit, electronic device, and readable storage medium. Background Technology
[0002] In the field of digital circuits, there is a common data delay circuit that uses multi-level registers to store valid input data level by level for each clock pulse, so that the data output of the last level register is delayed by several clock cycles compared to the input data.
[0003] For example, during a clock cycle when the input data is valid, the input data is stored in data register 0, the output data Q of register 0 is stored in data register 1, and so on. If the input data is invalid, each register retains the value from the previous clock cycle. After several clock cycles, the output value Q of data register N-1 is the final output data of the entire data delay circuit. Because each register stage is updated during a valid clock cycle, the power consumption of the data delay circuit will be high when the data bit width is large or the number of register stages is large. Therefore, the existing technology suffers from the problem of high power consumption during data delay. Summary of the Invention
[0004] The purpose of this application is to provide a data delay method, apparatus, circuit, electronic device, and readable storage medium that can solve the problem of high power consumption during data delay.
[0005] In a first aspect, embodiments of this application provide a data delay method applied to an electronic device, the electronic device including a data delay circuit, the data delay circuit including N independent first registers, characterized in that the method includes:
[0006] In the Mth clock cycle, the first data is stored in the target register, which is the Lth first register among the N first registers;
[0007] When M is greater than N, the second data output by the target register is obtained in the Mth clock cycle, and the second data is the data stored in the target register in the MNth clock cycle.
[0008] Secondly, embodiments of this application provide a data delay device applied to an electronic device, the electronic device including a data delay circuit, the data delay circuit including N independent first registers, and the data delay device including:
[0009] The storage control module is used to store the first data into the target register in the Mth clock cycle, wherein the target register is the Lth first register among the N first registers;
[0010] The acquisition module is used to acquire the second data output by the target register in the M-th clock cycle when M is greater than N. The second data is the data stored in the target register in the MN-th clock cycle.
[0011] Thirdly, embodiments of this application provide a data delay circuit, including: a first counter, a second counter, a delay sub-circuit, N first registers, a first selection element, and a second selection element, where N is an integer greater than 1.
[0012] The input terminal of the first counter is electrically connected to the input terminal of the second counter through the delay sub-circuit; the output terminal of the first counter is electrically connected to the control terminal of the first selection element; and the output terminal of the second counter is electrically connected to the control terminal of the second selection element.
[0013] The N output terminals of the first selection element are electrically connected one-to-one with the data input terminals of the N first registers, and the first selection element is used to control the data input terminal of the first selection element to connect with the first register associated with the value of the first counter through the data output terminal of the first selection element;
[0014] The N input terminals of the second selection element are electrically connected one-to-one with the data input terminals of the N first registers, and the second selection element is used to control the data output terminal of the second selection element to be connected to the first register associated with the value of the first counter through the data input terminal of the second selection element.
[0015] Fourthly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.
[0016] Fifthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.
[0017] In a sixth aspect, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.
[0018] In a seventh aspect, embodiments of this application provide a chip that includes the data delay circuit described in the third aspect.
[0019] In this embodiment, first data is stored in a target register during the Mth clock cycle. The target register is the Lth first register among the N independent first registers. If M is greater than N, second data output from the target register is obtained during the Mth clock cycle. This second data is the data stored in the target register during the MNth clock cycle. Thus, since data storage and / or reading operations are performed on only one first register within a single clock cycle, compared to the prior art which requires data storage and reading operations on every level of register, this embodiment reduces power consumption due to data latency. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a flowchart illustrating a data delay method provided in an embodiment of this application;
[0022] Figure 2 This is a structural diagram of a data delay circuit provided in an embodiment of this application;
[0023] Figure 3 This is a flowchart illustrating another data delay method provided in an embodiment of this application;
[0024] Figure 4 This is a structural diagram of another data delay circuit provided in an embodiment of this application;
[0025] Figure 5 This is a structural diagram of a data delay device provided in an embodiment of this application;
[0026] Figure 6 This is a structural diagram of another data delay device provided in an embodiment of this application;
[0027] Figure 7 This is a structural diagram of an electronic device provided in an embodiment of this application;
[0028] Figure 8 This is a structural diagram of another electronic device provided in an embodiment of this application. Detailed Implementation
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0031] The data delay method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.
[0032] See Figure 1 , Figure 1 This is a flowchart of a data delay method provided in an embodiment of this application. The data delay method is applied to an electronic device, which includes a data delay circuit (such as...). Figure 2 As shown), the data delay circuit includes N independent first registers, such as... Figure 1 As shown, this data delay method includes the following steps:
[0033] Step 101: In the Mth clock cycle, store the first data into the target register, where the target register is the Lth first register among the N first registers;
[0034] In this embodiment of the application, the above-mentioned N independent first registers can be understood as having no electrical connection between the data ports of the N first registers. The data output by one first register will not affect the data currently stored in other first registers, that is, the data output by one first register will not be written as input data to other first registers.
[0035] Optionally, in some embodiments, data can be sequentially and cyclically stored into N first registers. In other embodiments, the validity of the clock cycle can be further considered; for invalid clock cycles, no data will be stored. In this case, data can be stored by skipping one or more first registers to achieve skip-based storage. A valid clock cycle indicates that the data corresponding to that clock cycle is valid, and an invalid clock cycle indicates that the data in that clock cycle is invalid. The valid clock cycle can include a valid clock cycle for storage operations and a valid clock cycle for read operations. Storage operations can be performed during the valid clock cycle for storage operations, and read operations can be performed during the valid clock cycle for read operations.
[0036] Optionally, in some embodiments, the value of L can correspond to the value of M modulo N. In some embodiments, when M is an integer multiple of N, the value of L is the same as the value of N; when M is not an integer multiple of N, the value of L is the same as the value obtained by taking M modulo N. For example, the modulo results in 1, 2, ..., N-1, 0, which correspond to the first, second, ..., N-1th, and Nth registers, respectively. In other words, the data corresponding to the first clock cycle is stored in the first register (i.e., register 0), the data corresponding to the second clock cycle is stored in the second register (i.e., register 1), and after N clock cycles, storage continues starting from the first register. That is, the data corresponding to the N+1th clock cycle is stored in the first register (i.e., register 0), and the data corresponding to the N+2th clock cycle is stored in the second register (i.e., register 1). In this way, only one register needs to be stored in each clock cycle, thereby reducing power consumption.
[0037] Step 102: When M is greater than N, the second data output by the target register is obtained in the Mth clock cycle. The second data is the data stored in the target register in the MNth clock cycle.
[0038] It should be understood that the data stored in the Mth clock cycle will only take effect in the M+1th clock cycle. That is, the data stored in the Mth clock cycle cannot be read in the Mth clock cycle. What is read in the Mth clock cycle is the data stored in the MNth clock cycle, which is the data that was last stored in the target register.
[0039] In this embodiment, since the data output from the target register is obtained in the Mth clock cycle and stored in the target register in the MNth clock cycle, the data delay circuit described above delays the data by N clock cycles. For example, when M equals N+1, the data stored in the first register in the first clock cycle can be read from the first first register; when M equals N+2, the data stored in the second register in the second clock cycle can be read from the second first register.
[0040] It should be noted that when M is greater than N, the data stored in the MNth cycle can be retrieved from the corresponding first register in each clock cycle or each valid clock cycle.
[0041] In this embodiment, first data is stored in a target register during the Mth clock cycle. The target register is the Lth first register among the N independent first registers. If M is greater than N, second data output from the target register is obtained during the Mth clock cycle. This second data is the data stored in the target register during the MNth clock cycle. Thus, since data storage and / or reading operations are performed on only one first register within a single clock cycle, compared to the prior art which requires data storage and reading operations on every level of register, this embodiment reduces power consumption due to data latency.
[0042] Optionally, such as Figure 2 and Figure 3 As shown, in some embodiments, the data delay circuit further includes a delay sub-circuit formed by N second registers cascaded in sequence.
[0043] The step of storing the first data into the target register in the Mth clock cycle includes:
[0044] If the first signal is valid, the first data is stored in the target register in the Mth clock cycle;
[0045] The method further includes:
[0046] Step 103: Input the first signal into the delay sub-circuit;
[0047] Step 104: Obtain the second signal obtained after the first signal is delayed by the delay sub-circuit for N clock cycles;
[0048] Step 105: Based on the second signal, acquire the first data output by the target register in the M+Nth clock cycle.
[0049] In this embodiment, each second register is used to delay the first signal by one clock cycle. N second registers cascaded sequentially can delay the first signal by N clock cycles. It should be understood that the first and second signals are of the same type; that is, if the first signal corresponding to the Mth clock cycle is valid, the second signal corresponding to the M+Nth clock cycle is also valid; if the first signal corresponding to the Mth clock cycle is invalid, the second signal corresponding to the M+Nth clock cycle is also invalid.
[0050] Optionally, when the first signal is valid in the Mth clock cycle, the first data corresponding to the Mth clock cycle can be stored in the target register. Similarly, when the second signal is valid in the M+Nth clock cycle, the first data output by the target register can be obtained in the M+Nth clock cycle.
[0051] It should be understood that the aforementioned first and second signals can be interpreted as validity signals, used to indicate the validity of data in the corresponding clock cycle, or the validity of the corresponding clock cycle. For example, if the first signal corresponding to the Mth clock cycle is a valid signal, it can be understood that the Mth clock cycle is a valid clock cycle for storage operations; if the second signal corresponding to the M+Nth clock cycle is a valid signal, it can be understood that the M+Nth clock cycle is a valid clock cycle for read operations. In this embodiment, by increasing the validity of the signals, data storage and retrieval can be performed only for the clock cycle corresponding to the valid signal, thereby further reducing the power consumption of the electronic device.
[0052] Optionally, in some embodiments, the data delay circuit further includes a first counter and a second counter, wherein the value of the first counter cycles between 1 and N, and the value of the second counter cycles between 1 and N;
[0053] In the Mth clock cycle, the value of the first counter is L; when M is greater than N, the value of the second counter is L in the Mth clock cycle.
[0054] In this embodiment, the first counter and the second counter are used to count the number of clock cycles. Specifically, they can be used to record the total number of clock cycles or the number of valid clock cycles. The value of the first counter is used to determine the location of the first register storing data, and the value of the second counter is used to determine the location of the first register reading data.
[0055] For example, after each clock cycle or a valid clock cycle, the first counter and the second counter increment by 1. By using the first and second counters to record the number of clock cycles or valid clock cycles, and determining the location of the first register for storing data based on the value of the first counter, and determining the location of the first register for reading data based on the value of the second counter, the first register affected by the storage and / or read operations can be quickly located, reducing the latency of data storage and / or read operations.
[0056] Optionally, in some embodiments, the first counter performs a first counting operation when it receives a first signal and the first signal is a valid signal;
[0057] The second counter performs a second counting operation when it receives a second signal and the second signal is a valid signal.
[0058] In this embodiment of the application, when the first counter receives a first signal, and the first signal is a valid signal, the current clock cycle can be considered a valid clock cycle, thereby controlling the first counter to increment by 1. It should be understood that if the current value of the first counter is N, the value of the first counter will be 1 after the first counter performs the first counting operation.
[0059] Similarly, when the second counter receives the second signal, and the second signal is valid, the current clock cycle can be considered a valid clock cycle, thereby controlling the second counter to increment by 1. It should be understood that if the current value of the second counter is N, the value of the second counter will be 1 after performing the second counting operation.
[0060] Reference Figure 2 This application also provides a data delay circuit, such as... Figure 2 As shown, the data delay circuit provided in this embodiment includes: a first counter 11, a second counter 12, a delay sub-circuit 13, N first registers 14, a first selection element 15, and a second selection element 16, where N is an integer greater than 1.
[0061] The input terminal of the first counter 11 is electrically connected to the input terminal of the second counter 12 through the delay sub-circuit 13, the output terminal of the first counter 11 is electrically connected to the control terminal of the first selection element 15, and the output terminal of the second counter 12 is electrically connected to the control terminal of the second selection element.
[0062] The N output terminals of the first selection element 15 are electrically connected one-to-one with the data input terminals of the N first registers 14, and the first selection element is used to control the data input terminals of the first selection element 15 to connect with the first register 14 associated with the value of the first counter through the data output terminals of the first selection element 15;
[0063] The N input terminals of the second selection element are electrically connected one-to-one with the data input terminals of the N first registers 14, and the second selection element 16 is used to control the data output terminal of the second selection element 16 to be connected to the first register 14 associated with the value of the first counter through the data input terminal of the second selection element 16.
[0064] In this embodiment of the application, the increment of the first counter 11 and the second counter 12 for each count can be 1, and the range of the cyclic count can be from 1 to N, or from 0 to N-1.
[0065] Optionally, the first counter 11 and the second counter 12 are used to count the number of clock cycles. Specifically, they can be used to record the total number of clock cycles or the number of valid clock cycles. The value of the first counter 11 is used to determine the location of the first register 14 storing data, and the value of the second counter 12 is used to determine the location of the first register 14 for reading data.
[0066] For example, after each clock cycle or a valid clock cycle, the first counter 11 and the second counter 12 increment by 1. Since the first counter 11 and the second counter 12 record the number of clock cycles or valid clock cycles, and the location of the first register 14 for storing data is determined based on the value of the first counter 11, and the location of the first register 14 for reading data is determined based on the value of the second counter 12, the first register 14 affected by the storage and / or read operations can be quickly located, reducing the latency of data storage and / or read operations.
[0067] Optionally, in some embodiments, the first counter 11 can increment by 1 in each clock cycle, starting from 1, counting up to N, and then continuing to the next round of counting. The second counter 12 operates on the same principle as the first counter 11.
[0068] Optionally, in some embodiments, the counter can increment by 1 for each valid clock cycle. For example, when the first counter 11 receives the first signal in the Mth clock cycle and the first signal is valid, the first counter 11 increments by 1. After counting to N, the next round of counting continues. The counting principle of the second counter 12 is the same as that of the first counter 11, except that the second counter 12 targets the second signal. That is, when the second counter 12 receives the second signal in the Mth clock cycle and the second signal is valid, the second counter 12 increments by 1.
[0069] Optionally, the specific structures of the first selection element 15 and the second selection element 16 can be configured according to actual needs. For example, in some embodiments, a multiplexer can be used. That is, the first selection element 15 and / or the second selection element 16 can be an N-to-1 selector.
[0070] Optionally, in some embodiments, it can be assumed that the data output terminal of the first selection element 15 includes ports 0 to N-1. When the first count value is 1, port 0 of the first selection element 15 is connected to the data input port of the first selection element 15, so that the data input by the data input port can be stored in register 0 through port 0. Similarly, it is assumed that the data output port of the second selection element 16 includes data output ports 0 to N-1. When the second count value is 1, the data input port of the second selection element 16 is connected to the data output port 0 of the first selection element 15, so as to obtain the data output by register 0.
[0071] It should be understood that the output terminals of the first counter 11 and the second counter 12 mentioned above may include multiple ones. For example, when N is 16, the output terminals of the first counter 11 and the second counter 12 mentioned above can both be four, so that a 4-bit count value can be output.
[0072] Optionally, the structure of the aforementioned delay sub-circuit 13 can be configured according to actual needs, for example, as follows: Figure 4 As shown, in some embodiments, the aforementioned delay sub-circuit 13 can be formed by cascading N second registers. For example, the first signal can be input to the input terminal of the first-stage second register. During the transmission of the first signal through the N second registers, in each clock cycle, the output of the previous-stage second register can be used as the input of the next-stage second register, and the data output from the output terminal of the last-stage second register is the aforementioned second signal, that is, the signal after the first signal has been delayed by N clock cycles through the N second registers.
[0073] In this embodiment, a data delay circuit is formed by employing a first counter 11, a second counter 12, a delay sub-circuit 13, N first registers 14, a first selection element 15, and a second selection element 16, thereby realizing the aforementioned data delay method. Since data storage and / or reading operations are performed on only one first register within one clock cycle, compared to the prior art which requires data storage and reading operations on every level of register, this embodiment reduces the power consumption of data delay.
[0074] It should be noted that the first and second counters mentioned above can also be implemented using other control chips with data processing capabilities. They can also be implemented using other logic gate circuit structures, without further limitation here. Meanwhile, the selection element mentioned above can be implemented using a multi-pole single-throw switch in conjunction with a control chip, without further limitation here.
[0075] Optionally, taking a data width of 120 bits and a delay of 16 stages (i.e., N and M equal 16, delaying for 16 clock cycles) as an example, a power consumption evaluation tool was used to experimentally compare the power consumption of a traditional data delay circuit and the power consumption of the data delay circuit of this application. The following data was obtained: the power consumption of the traditional data delay circuit is 0.2806 milliwatts; the power consumption of the data delay circuit of this application is 0.0509 milliwatts, a reduction of 81.86%. Therefore, the data delay circuit provided by this application provides greater benefits in scenarios with larger bit widths and more delay stages.
[0076] It should be noted that the data delay method provided in this application embodiment can be executed by a data delay device or a control module within that data delay device for executing the data loading delay method. This application embodiment uses the execution of the data loading delay method by a data delay device as an example to illustrate the data delay device provided in this application embodiment.
[0077] Reference Figure 5 This application also provides a data delay device, such as... Figure 5 As shown, an electronic device is applied to the device, which includes a data delay circuit. The data delay circuit includes N independent first registers. The data delay device 500 includes:
[0078] Storage control module 501 is used to store the first data into a target register in the Mth clock cycle, wherein the target register is the Lth first register among the N first registers;
[0079] The acquisition module 502 is used to acquire the second data output by the target register in the M-th clock cycle when M is greater than N. The second data is the data stored in the target register in the MN-th clock cycle.
[0080] Optionally, the second data is delayed by N clock cycles relative to the first data.
[0081] Optionally, the data delay circuit further includes a delay sub-circuit formed by N second registers cascaded in sequence. The storage control module is specifically used to store the first data into the target register in the Mth clock cycle when the first signal is a valid signal.
[0082] Optionally, such as Figure 6 As shown, the data delay device 500 further includes:
[0083] Input module 503 is used to input the first signal into the delay sub-circuit;
[0084] The acquisition module 502 is further configured to acquire a second signal obtained after the first signal is delayed by the delay sub-circuit for N clock cycles; and acquire the first data output by the target register according to the second signal in the M+Nth clock cycle.
[0085] Optionally, the data delay circuit further includes a first counter and a second counter, wherein the value of the first counter cycles between 1 and N, and the value of the second counter cycles between 1 and N;
[0086] In the Mth clock cycle, the value of the first counter is L; when M is greater than N, the value of the second counter is L in the Mth clock cycle.
[0087] Optionally, the first counter performs a first counting operation when it receives a first signal and the first signal is a valid signal;
[0088] The second counter performs a second counting operation when it receives a second signal and the second signal is a valid signal.
[0089] Optionally, when M is an integer multiple of N, the value of L is the same as the value of N; when M is not an integer multiple of N, the value of L is the same as the value obtained by taking M modulo N.
[0090] The data delay device in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.
[0091] The data delay device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.
[0092] The data delay device provided in this application embodiment can achieve... Figure 1 and Figure 3 The various processes implemented by the data delay device in the method embodiment will not be described again here to avoid repetition.
[0093] Optional, refer to Figure 7 This application also provides an electronic device, including a processor 710, a memory 709, and a program or instructions stored in the memory 709 and executable on the processor 710. When the program or instructions are executed by the processor 710, they implement the various processes of the above-described data delay method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.
[0094] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.
[0095] Figure 8 A schematic diagram of the hardware structure of an electronic device for implementing the various embodiments of this application.
[0096] The electronic device 800 includes, but is not limited to, components such as: radio frequency unit 801, network module 802, audio output unit 803, input unit 804, sensor 805, display unit 806, user input unit 807, interface unit 808, memory 809, and processor 810.
[0097] Those skilled in the art will understand that the electronic device 800 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 810 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 8 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.
[0098] The electronic device includes a data delay circuit, which includes N independent first registers and a processor 810 for storing first data into a target register in the Mth clock cycle. The target register is the Lth first register among the N first registers. When M is greater than N, the processor obtains second data output from the target register in the Mth clock cycle. The second data is the data stored in the target register in the MNth clock cycle.
[0099] Optionally, the data delay circuit further includes a delay sub-circuit formed by N second registers cascaded in sequence, and the processor 810 is further configured to: input the first signal into the delay sub-circuit; obtain a second signal obtained after the first signal is delayed by the delay sub-circuit for N clock cycles; and obtain the first data output by the target register in the M+Nth clock cycle according to the second signal.
[0100] Optionally, the data delay circuit further includes a first counter and a second counter, wherein the value of the first counter cycles between 1 and N, and the value of the second counter cycles between 1 and N;
[0101] In the Mth clock cycle, the value of the first counter is L; when M is greater than N, the value of the second counter is L in the Mth clock cycle.
[0102] Optionally, the first counter performs a first counting operation when it receives a first signal and the first signal is a valid signal;
[0103] The second counter performs a second counting operation when it receives a second signal and the second signal is a valid signal.
[0104] Optionally, when M is an integer multiple of N, the value of L is the same as the value of N; when M is not an integer multiple of N, the value of L is the same as the value obtained by taking M modulo N.
[0105] It should be noted that, in the embodiments of this application, the processor can be any module containing processing functions, such as CPU, GPU, NPU, DSP, ISP and other processing chips.
[0106] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data delay method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.
[0107] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0108] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described data delay method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0109] This application embodiment also provides a chip, which includes the above-described data delay circuit.
[0110] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.
[0111] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0113] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A data delay method applied to an electronic device, the electronic device including a data delay circuit, the data delay circuit including N independent first registers, characterized in that, The method includes: In the Mth clock cycle, the first data is stored in the target register, which is the Lth first register among the N first registers; When M is greater than N, the second data output by the target register is obtained in the Mth clock cycle, and the second data is the data stored in the target register in the MNth clock cycle; The data delay circuit also includes a delay sub-circuit formed by N second registers cascaded in sequence. The second signal is obtained by delaying the first signal by N clock cycles by the N second registers cascaded in sequence. The first signal and the second signal are of the same type. The step of storing the first data into the target register in the Mth clock cycle includes: If the first signal is valid, the first data is stored in the target register in the Mth clock cycle; The method further includes: The first signal is input into the delay sub-circuit; Obtain the second signal obtained after the first signal is delayed by the delay sub-circuit for N clock cycles; Based on the second signal, the first data output by the target register is acquired in the M+Nth clock cycle, where the M+Nth clock cycle is the valid clock cycle for the read operation.
2. The method according to claim 1, characterized in that, The data delay circuit further includes a first counter and a second counter, wherein the value of the first counter cycles between 1 and N, and the value of the second counter cycles between 1 and N. In the Mth clock cycle, the value of the first counter is L; when M is greater than N, the value of the second counter is L in the Mth clock cycle.
3. The method according to claim 2, characterized in that, When the first counter receives the first signal and the first signal is a valid signal, it performs a first counting operation. The second counter performs a second counting operation when it receives a second signal and the second signal is a valid signal.
4. The method according to claim 1, characterized in that, When M is an integer multiple of N, the value of L is the same as the value of N; when M is not an integer multiple of N, the value of L is the same as the value obtained by taking M modulo N.
5. A data delay device applied to an electronic device, the electronic device including a data delay circuit, the data delay circuit including N independent first registers, characterized in that, The data delay device includes: The storage control module is used to store the first data into the target register in the Mth clock cycle, wherein the target register is the Lth first register among the N first registers; The acquisition module is configured to acquire the second data output by the target register in the M-th clock cycle when M is greater than N, wherein the second data is the data stored in the target register in the MN-th clock cycle; The data delay circuit also includes a delay sub-circuit formed by N second registers cascaded in sequence. The second signal is obtained by delaying the first signal by N clock cycles by the N second registers cascaded in sequence. The first signal and the second signal are of the same type. The storage control module is specifically used to store the first data into the target register in the Mth clock cycle when the first signal is a valid signal. The data delay device further includes: An input module is used to input the first signal into the delay sub-circuit; The acquisition module is further configured to acquire a second signal obtained after the first signal is delayed by the delay sub-circuit for N clock cycles; based on the second signal, acquire the first data output by the target register in the M+Nth clock cycle, where the M+Nth clock cycle is the valid clock cycle for the read operation.
6. The apparatus according to claim 5, characterized in that, The data delay circuit further includes a first counter and a second counter, wherein the value of the first counter cycles between 1 and N, and the value of the second counter cycles between 1 and N. In the Mth clock cycle, the value of the first counter is L; when M is greater than N, the value of the second counter is L in the Mth clock cycle.
7. The apparatus according to claim 6, characterized in that, When the first counter receives the first signal and the first signal is a valid signal, it performs a first counting operation. The second counter performs a second counting operation when it receives a second signal and the second signal is a valid signal.
8. The apparatus according to claim 5, characterized in that, When M is an integer multiple of N, the value of L is the same as the value of N; when M is not an integer multiple of N, the value of L is the same as the value obtained by taking M modulo N.
9. A data delay circuit for performing the method of claim 1, characterized in that, include: The circuit consists of a first counter, a second counter, a delay sub-circuit, N first registers, a first selection element, and a second selection element, where N is an integer greater than 1. The input terminal of the first counter is electrically connected to the input terminal of the second counter through the delay sub-circuit; the output terminal of the first counter is electrically connected to the control terminal of the first selection element; and the output terminal of the second counter is electrically connected to the control terminal of the second selection element. The N output terminals of the first selection element are electrically connected one-to-one with the data input terminals of the N first registers, and the first selection element is used to control the data input terminal of the first selection element to connect with the first register associated with the value of the first counter through the data output terminal of the first selection element; The N input terminals of the second selection element are electrically connected one-to-one with the data input terminals of the N first registers, and the second selection element is used to control the data output terminal of the second selection element to be connected to the first register associated with the value of the first counter through the data input terminal of the second selection element; The delay sub-circuit is formed by N second registers cascaded in sequence; The first selection element and / or the second selection element are N-to-1 selectors.
10. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the data delay method as described in any one of claims 1 to 4.
11. A readable storage medium having a program or instructions stored thereon, characterized in that, When the program or instructions are executed by the processor, they implement the steps of the data delay method according to any one of claims 1 to 4.
12. A chip, characterized in that, The chip includes a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run a program or instructions, the program or instructions being executed by the processor to implement the steps of the data delay method according to any one of claims 1 to 4.
13. A chip, characterized in that, The chip includes a data delay circuit as described in any one of claims 9 to 10.