Storage system and data writing method for storage system

Abstract

The present disclosure relates to the field of semiconductor technology and provides a storage system and a method for writing data to the storage system. The storage system includes: the storage system is configured to enter a write copy mode in response to a write copy enable signal. During the write copy mode, if at least two groups of data among multiple groups of data output from a data port are identical, the at least two groups of data are defined as the same group, an identification signal is generated to indicate data copying, and one group of data in the same group is transmitted to an interface of a storage array, while the transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array is disabled. The storage array, in response to the write copy enable signal and the identification signal, copies the one group of data in the same group to the interface of the storage array corresponding to the remaining groups of data in the same group. The present disclosure embodiment at least helps save power consumption when writing data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a storage system and a method for writing data into the storage system. Background Art

[0002] Memory is used in many electronic systems to write and read information, such as in mobile phones, tablets, computers, servers, and other electronic systems that include a processor or need to store information. Memory can be controlled using memory commands, such as write and read commands, which are received by the memory over a command bus. Information to be stored can be written to the memory using a write command and retrieved at a later time by reading the information from the memory using a read command.

[0003] Among them, multiple data transmission paths can be driven in parallel to write multiple data into the memory. However, when the written data contains the same data, driving multiple data transmission paths consumes more power than driving a single data. Summary of the Invention

[0004] The embodiments of the present disclosure provide a storage system and a method for writing data to the storage system, which are at least beneficial for saving power consumption during data writing.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a storage system, including: the storage system is configured to enter a write copy mode in response to a write copy enable signal, and during the write copy mode, if at least two groups of data among multiple groups of data output from a data port are the same, the at least two groups of data are defined as the same group, an identification signal for characterizing data copying is generated, and one group of data in the same group is transmitted to an interface of a storage array, and the transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array is disabled, and the storage array copies one group of data in the same group to the interface of the storage array corresponding to the remaining groups of data in the same group in response to the write copy enable signal and the identification signal.

[0006] In some embodiments, the storage system is further configured to output the identification signal if all groups of data in the plurality of groups of data are identical.

[0007] In some embodiments, the storage system is further configured to, if there is at least one group of data in the plurality of groups of data that is different from the same group of data, further transmit the at least one group of data to a corresponding interface of the storage array.

[0008] In some embodiments, the storage system includes: a processing module, which responds to the write copy enable signal and the multiple groups of data to output a first drive signal, a second drive signal and the identification signal, and sends the identification signal to the storage array; multiple data paths, each of the data paths serving as a transmission path for a group of the data between the interface of the storage array and the data port, the data paths corresponding to one group of data in the same group being turned on in response to the first drive signal, and the data paths corresponding to the remaining groups of data in the same group being disabled in response to the second drive signal.

[0009] In some embodiments, the data path includes: multiple stages of data transmission circuits connected in series, and each stage of the data transmission circuit transmits data based on the first driving signal, or each stage of the data transmission circuit is disabled based on the second driving signal.

[0010] In some embodiments, the processing module includes: multiple stages of identification signal transmission circuits connected in series, the input end of each stage of the identification signal transmission circuit is used to receive the identification signal, and the output end is used to output the identification signal, and the identification signal transmission circuit at the last stage transmits the identification signal to the storage array.

[0011] In some embodiments, each stage of the identification signal transmission circuit includes an even number of inverters connected in series.

[0012] In some embodiments, the processing module further includes: a plurality of signal generating units, each of the signal generating units corresponding to the first-level identification signal transmission circuit and the first-level data transmission circuit, and the signal generating unit is configured to provide the first drive signal and the second drive signal to the corresponding data transmission circuit in response to the write copy enable signal and the identification signal received at the input end of the identification signal transmission circuit.

[0013] In some embodiments, the storage system further includes: a plurality of input buffer circuits, each of the input buffer circuits being connected between the data path and the data port, the input buffer circuits being configured such that the processing module outputs a disable enable signal to the input buffer circuit, and the input buffer circuits corresponding to the remaining groups of data in the same group are disabled in response to the disable enable signal.

[0014] In some embodiments, the processing module includes: an instruction decoding unit, which is connected to each of the input buffer circuits, and the instruction decoding unit is configured to output the disable enable signal to the input buffer circuits corresponding to the remaining groups of data of the same group based on the instruction signal and the disable enable signal, wherein the instruction signal is generated based on the existence of the same group in the multiple groups of data.

[0015] In some embodiments, the storage system further includes: an instruction generating unit, which receives the multiple groups of data and outputs the instruction signal if the same group exists in the multiple groups of data.

[0016] In some embodiments, the processing module is further configured to output a third drive signal if there is at least one set of data with different data among the multiple sets of data; the data path corresponding to the at least one set of data with different data is turned on in response to the third drive signal.

[0017] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a data writing method for a storage system, comprising: responding to a write copy enable signal to enter a write copy mode, during the write copy mode, if at least two groups of data among multiple groups of data output from a data port are the same, the at least two groups of data are defined as the same group, an identification signal for characterizing data copying is generated, and one group of data in the same group is transmitted to an interface of a storage array, and a transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array is disabled, and the storage array copies one group of data in the same group to the corresponding interface of the storage array corresponding to the remaining groups of data in the same group in response to the write copy enable signal and the identification signal.

[0018] In some embodiments, outputting an identification signal for indicating data replication includes: determining whether all groups of data in the multiple groups of data are identical; and outputting the identification signal if all groups of data in the multiple groups of data are identical.

[0019] In some embodiments, transmitting one set of data in the same group to the interface of the storage array and disabling the transmission path between the data ports corresponding to the remaining sets of data in the same group and the interface of the storage array includes: generating a first drive signal and a second drive signal in response to the write copy enable signal and the multiple sets of data; the data path corresponding to the one set of data in the same group transmits data in response to the first drive signal to transmit the data to the corresponding interface of the storage array, and the data paths corresponding to the remaining sets of data in the same group are disabled in response to the second drive signal.

[0020] In some embodiments, the step of transmitting one set of data in the same group to an interface of a storage array and disabling a transmission path between data ports corresponding to remaining sets of data in the same group and the interface of the storage array further includes: disabling an input buffer circuit connected between the data ports corresponding to remaining sets of data in the same group and the data path.

[0021] In some embodiments, the identification signal is transmitted to the storage array via multiple stages of identification transmission circuits connected in series, the data path includes multiple stages of data transmission circuits connected in series, and each stage of the data transmission circuit corresponds to the identification transmission circuit of one stage; the transmission of one group of data in the same group to the interface of the storage array and disabling the transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array also includes: responding to the write copy enable signal and the identification signal received at the input end of the identification transmission circuit of the current stage to generate the first drive signal for driving at least the data transmission circuit of the current stage, and generating the second drive signal for disabling the data transmission circuit of the current stage.

[0022] The technical solution provided by the embodiments of the present disclosure has the following advantages:

[0023] During the copy-on-write mode, if it is discovered that the data in multiple groups of data to be written to the storage array is identical, the transmission path for writing one group of data in the same data group to the storage system is enabled, and the transmission paths for writing the data in other groups of data in the same data group to the storage array are disabled. The transmission paths for the data in the other groups of data in the same data group will then retain the data from the last write operation without flipping. That is, during this data transmission, the transmission paths for the data in the other groups of data in the same data group will not generate new power consumption, thereby helping to reduce the power consumption of writing data to the storage array. In addition, if the data in the multiple groups of data to be written to the storage array is identical, the storage system will also output an identification signal to indicate that duplication has occurred among the multiple groups of data in this data write operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] Figure 1 A functional structural diagram of a storage system provided in accordance with an embodiment of the present disclosure;

[0026] Figure 2 Another functional structural diagram of a storage system provided in accordance with an embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure;

[0028] Figure 4 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure;

[0030] Figure 6 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] As known from the background art, the power consumption of writing data into a storage system needs to be reduced.

[0032] Analysis revealed that the memory interface specification includes a write data copy mode. In this mode, if multiple sets of data to be written to the memory are identical, only one set of data will be transmitted to the memory array interface. However, the transmission path from the other sets of data to the storage array interface remains open, and a special instruction is sent to the storage array to indicate that a copy of the write data has occurred. Upon receiving this special instruction, the storage array will copy the previously transmitted set of data to the storage array interfaces corresponding to the other sets of data, thereby writing the complete data into the storage array.

[0033] However, the transmission paths of the other groups of data to the interfaces of the storage array are still connected, and power consumption is still generated during the data writing process.

[0034] The present disclosure provides a storage system and a method for writing data to the storage system. In the storage system, during a write-copy mode, if it is found that the same data exists in multiple groups of data that need to be written to a storage array, a transmission path for writing one group of data in the same group to the storage system is enabled, and a transmission path for writing other groups of data in the same group to the storage system is disabled. During this data writing process, the transmission paths for the other groups of data in the same group will not generate new power consumption, thereby helping to reduce power consumption for writing data to the storage system.

[0035] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0036] An embodiment of the present disclosure provides a storage system, which will be described in detail below with reference to the accompanying drawings. Figure 1 A functional structural diagram of a storage system provided in accordance with an embodiment of the present disclosure; Figure 2 Another functional structural diagram of a storage system provided in accordance with an embodiment of the present disclosure; Figure 3 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of another functional structure of a storage system provided in an embodiment of the present disclosure.

[0038] In the embodiments of the present disclosure, reference Figure 1 The storage system 100 is configured to enter a copy-on-write mode in response to a copy-on-write enable signal 101a. During the copy-on-write mode, if at least two groups of data among the multiple groups of data output from the data port 102 are identical, the at least two groups of data are defined as the same group, an identification signal 101b for indicating data copying is generated, and one group of data in the same group is transmitted to the interface of the storage array 103, and the transmission path between the data port 102 corresponding to the remaining groups of data in the same group and the interface of the storage array 103 is disabled. The storage array 103 copies the one group of data in the same group to the interface of the storage array 103 corresponding to the remaining groups of data in the same group in response to the copy-on-write enable signal 101a and the identification signal 101b.

[0039] In some embodiments, continue to refer to Figure 1 , the multiple groups of data output from the data port 102 can be 8 groups of data, for example, D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, D5<7:0>, D6<7:0> and D7<7:0>, each group of data contains an 8-bit unsigned number, and any two groups of data are the same means that the arrangement order of the 8-bit unsigned numbers in any two groups of data is the same. It should be noted that Figure 1 In the example, the multiple groups of data output from the data port 102 are 8 groups of data, and each group of data contains an 8-bit unsigned number. In actual applications, there is no limit on the number of groups of data output from the data port 102 at the same time, and the number of bits of the unsigned number contained in each group of data.

[0040] If at least two of the eight groups of data, for example, the data of D0<7:0> and D1<7:0>, are identical, then D0<7:0> and D1<7:0> can be defined as the same group, an identification signal 101b for indicating data replication is output, and D0<7:0> is transmitted to the corresponding interface of the storage array 103, while the transmission path between D1<7:0> and the corresponding interface of the storage array 103 is disabled. In this way, the transmission path between D1<7:0> and the corresponding interface of the storage array 103 does not generate new power consumption, thereby helping to reduce the power consumption of writing data to the storage array 103.

[0041] How to write data into the storage array 103 is described in detail below using two embodiments.

[0042] In some embodiments, the storage system 100 may be further configured to output an identification signal 101 b if all groups of data in the plurality of groups of data are identical. For example, the data in D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0> are all the same. Therefore, one of the eight groups of data, such as D0<7:0>, can be selected. The transmission path for transmitting D0<7:0> to the interface of the corresponding storage array 103 is enabled, and the transmission paths for transmitting the remaining groups of data in the same group to the interface of the corresponding storage array 103 are disabled, such as the seven transmission paths between D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0> to the interface of the corresponding storage array 103. In this way, when transmitting the eight groups of identical data, unnecessary power consumption can be avoided in the transmission paths corresponding to the seven groups of data, thereby reducing the power consumption generated by writing data to the storage array 103.

[0043] It should be noted that, in actual applications, the data output from the data port 102 may be N groups of data, and the data in all groups of the N groups of data are identical. Therefore, when transmitting the N groups of data, unnecessary power consumption generated by the N-1 transmission paths corresponding to the N-1 group of data can be avoided, thereby reducing the power consumption generated by writing data to the memory array 103. Wherein, N is a positive integer greater than or equal to 2.

[0044] In other embodiments, the storage system 100 may be further configured to transmit at least one set of data to a corresponding interface of the storage array 103 if at least one set of data in the multiple sets of data is different from the same set of data.

[0045] For example, among D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0>, the data in D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, and D5<7:0> are the same, but the data in D6<7:0> is different from the data in D0<7:0>, and the data in D7<7:0> is the same as the data in D0<7:0>. If the data in D0<7:0> and the data in D6<7:0> are different, meaning three of the eight data sets are different, the storage system 100 transmits the data in D0<7:0> to the interface of the storage array 103 corresponding to D0<7:0>. Furthermore, the storage system 100 transmits the data in D6<7:0> to the interface of the storage array 103 corresponding to D6<7:0>, and the data in D7<7:0> to the interface of the storage array 103 corresponding to D7<7:0>. In this way, the three transmission paths are enabled to enable data transmission between D0<7:0>, D6<7:0>, and D7<7:0>, thereby writing D0<7:0>, D6<7:0>, and D7<7:0> to the storage array 103. Meanwhile, the remaining five transmission paths are disabled to avoid unnecessary power loss when writing data to the storage array 103.

[0046] Furthermore, since the data in D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, and D5<7:0> are identical, in practical applications, it suffices to select any one set of data to establish a transmission path between the interface of the corresponding storage array 103. For ease of description, the transmission path between D0<7:0> and the interface of the storage array 103 corresponding to D0<7:0> is selected to be established.

[0047] It should be noted that the above is only a specific example given for the convenience of description. In actual applications, data transmission can be achieved through the above solution as long as there is at least one group of data in multiple groups of data that is different from the data in the same group. For example, among D0<7:0>, D1<7:0>, D2<7:0>, D3<7:0>, D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0>, the data in D0<7:0>, D1<7:0>, D2<7:0>, and D3<7:0> are the same, the data in D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0> are the same, and the data in D0<7:0> is different from the data in D4<7:0>. That is, among the eight groups of data, there are two identical groups with different data. In this case, the storage system 100 will transmit the data in D0<7:0> to the interface of the storage array 103 corresponding to D0<7:0> and simultaneously transmit the data in D4<7:0> to the interface of the storage array 103 corresponding to D4<7:0> according to the identification signal 101b. In this way, the remaining six transmission paths can be disconnected according to the identification signal 101 b to avoid unnecessary power loss when writing data into the storage array 103 .

[0048] Furthermore, since the data in D0<7:0>, D1<7:0>, D2<7:0>, and D3<7:0> are identical, in actual applications, any one set of data may be selected to have a transmission path between the interface of the corresponding storage array 103 connected. For ease of description, the transmission path between D0<7:0> and the interface of the storage array 103 corresponding to D0<7:0> is selected to be connected. Since the data in D4<7:0>, D5<7:0>, D6<7:0>, and D7<7:0> are identical, in actual applications, any one set of data may be selected to have a transmission path between the interface of the corresponding storage array 103 connected. For ease of description, the transmission path between D4<7:0> and the interface of the storage array 103 corresponding to D4<7:0> is selected to be connected.

[0049] It should be noted that the above examples are merely for ease of description. When the number of identical groups is two, the data in D0<7:0>, D1<7:0>, D2<7:0>, and D3<7:0> are identical. In actual applications, the groups with identical data can also be other groups, including multiple consecutive data groups or multiple data groups with gaps between them. This is not limited in the present embodiment. Furthermore, the number of identical groups can also be greater than two.

[0050] In the present disclosure, continue to refer to Figure 1The storage system 100 includes: a processing module 101, which responds to a write copy enable signal 101a and multiple groups of data to output a first drive signal 101c, a second drive signal 101d, and an identification signal 101b, and sends the identification signal 101b to the storage array 103; multiple data paths 104, each data path 104 serving as a transmission path for a group of data between an interface of the storage array 103 and a data port 102, wherein the data path 104 corresponding to a group of data in the same group is turned on in response to the first drive signal 101c, and the data paths 104 corresponding to the remaining groups of data in the same group are disabled in response to the second drive signal 101d.

[0051] Since one data path 104 is randomly selected from multiple groups of data with the same data and is turned on upon receiving the first drive signal 101c, and the data paths 104 of the remaining groups of the same group are all disabled upon receiving the second drive signal 101d, when transmitting the multiple groups of data with the same data, only one data path 104 can be controlled to be turned on by the first drive signal 101c, and the data paths 104 corresponding to the remaining groups of the multiple groups of data can be controlled to be disabled by the second drive signal 101d, thereby avoiding unnecessary power consumption generated by the transmission paths corresponding to the remaining groups of the multiple groups of data, thereby further reducing the power consumption generated by writing data to the storage array 103.

[0052] In some embodiments, reference Figure 2 The data path 104 may include: multiple stages of data transmission circuits 114 connected in series, and each stage of the data transmission circuit 114 transmits data based on the first driving signal 101c, or each stage of the data transmission circuit 114 is disabled based on the second driving signal 101d.

[0053] During data transmission from data port 102 to the interface of storage array 103, data is easily distorted due to the length of data path 104. That is, by the time data is transmitted to the interface of storage array 103, it is already different from the data output from data port 102, resulting in errors in the data written to storage array 103. Therefore, data path 104 includes multiple stages of data transmission circuits 114 connected in series, which helps ensure that the data to be transmitted by data path 104 is not distorted after being processed by each stage of data transmission circuit 114.

[0054] Among them, reference Figure 3 The processing module 101 may further include: a plurality of stages of identification signal transmission circuits 105 connected in series, wherein the input end of each stage of the identification signal transmission circuit 105 is used to receive the identification signal 101b, and the output end is used to output the identification signal 101b, and the identification signal transmission circuit 105 at the last stage transmits the identification signal 101b to the storage array 103.

[0055] Since the identification signal 101b is easily distorted during transmission from the processing module 101 to the storage array 103 due to the long transmission path, that is, when the identification signal 101b is transmitted to the storage array 103, it is already different from the identification signal 101b output by the processing module 101, causing the storage array 103 to misread the identification signal 101b, which is not conducive to the storage array 103 determining whether multiple groups of data written to the storage array 103 are duplicated and which groups of data are identical based on the identification signal 101b. Therefore, adding multiple stages of identification signal transmission circuits 105 in series to the processing module 101 helps ensure that the identification signal 101b output by the processing module 101 is processed by each stage of the identification signal transmission circuit 105 and is transmitted to the storage array 103 without distortion.

[0056] In some embodiments, reference Figure 4 Each stage of the identification signal transmission circuit 105 may include an even number of inverters 115 connected in series. Inverters 115 have advantages such as a large noise margin, extremely high input resistance, extremely low static power consumption, and insensitivity to noise and interference. Furthermore, an even number of inverters 115 connected in series will not cause inversion of the identification signal 101b ultimately transmitted to the storage array 103. This helps reduce interference experienced by the identification signal 101b during transmission from the processing module 101 to the storage array 103, thereby further ensuring that the identification signal 101b transmitted to the storage array 103 is not distorted.

[0057] In some embodiments, continue to refer to Figure 4 The data transmission circuit 114 may include a driver 124 and a latch 134. The driver 124 responds to the first drive signal 101c to turn on the data transmission circuit 114, or responds to the second drive signal 101d to disable the data transmission circuit 114. Thus, after the driver 124 is turned on, the data transmitted by the data transmission circuit 114 is divided into two paths: one path is transmitted to the latch 134 for latching, and the other path is transmitted to the data transmission circuit 114 of the next stage.

[0058] It should be noted that Figures 2 to 4 In the example, the data path 104 includes two data transmission circuits 114 connected in series. In practical applications, there is no limit on the number of data transmission circuits 114 included in the data path 104. Figures 3 and 4 In the figure, two identification signal transmission circuits 105 connected in series are taken as an example. In practical applications, there is no limitation on the number of identification signal transmission circuits 105 .

[0059] In some embodiments, reference Figure 5The processing module 101 may further include: a plurality of signal generating units 106, each signal generating unit 106 corresponding to a first-level identification signal transmission circuit 105 and a first-level data transmission circuit 114, the signal generating unit 106 being configured to provide a first drive signal 101c and a second drive signal 101d to the corresponding data transmission circuit 114 in response to the write copy enable signal 101a and the identification signal 101b received at the input end of the identification signal transmission circuit 105.

[0060] Because the identification signal 101b can indicate data duplication, that is, which groups have the same data, the signal generating unit 106 can generate a new first drive signal 101c for the next-stage data transmission circuit 114 that needs to perform data transmission, and a new second drive signal 101d for the next-stage data transmission circuit 114 of the data path 104 that has disabled the previous-stage data transmission circuit 114, based on the identification signal 101b received at the input end of the identification signal transmission circuit 105. In this way, while ensuring that the data to be transmitted by the data path 104 is not distorted after being processed by each stage of the data transmission circuit 114, it is also beneficial to ensure that each stage of the data transmission circuit 114 of the data path 104 corresponding to other groups in the same group is disabled, thereby preventing interference with data transmission and reducing power consumption when writing data to the memory array 103.

[0061] In some embodiments, reference Figure 6 The storage system 100 may further include: a plurality of input buffer circuits 107, each of which is connected between the data path 104 and the data port 102. The input buffer circuits 107 are configured such that, when the processing module 101 outputs a disable enable signal 101e to the input buffer circuit 107, the input buffer circuits 107 corresponding to the remaining data groups in the same group are disabled in response to the disable enable signal 101e. Thus, when the input buffer circuit 107 receives the disable enable signal 101e and is disabled, the input buffer circuits 107 corresponding to the remaining data groups in the same group are not driven, i.e., the data output from the data port 102 is not transmitted to the data path 104. The data path 104 corresponding to the disabled input buffer circuit 107 is also disabled based on the second drive signal 101d. As a result, the transmission path between the remaining data groups in the same group from the input buffer circuit 107 to the corresponding interface of the storage array 103 does not generate additional power consumption, thereby facilitating reduced power consumption in writing data to the storage array 103.

[0062] Among them, continue to refer to Figure 6The processing module 101 may further include: an instruction decoding unit 108, the instruction decoding unit 108 is connected to each input buffer circuit 107, and the instruction decoding unit 108 is configured to output a disable enable signal 101e to the input buffer circuits 107 corresponding to the remaining group data of the same group based on the instruction signal 101f and the disable enable signal 101e. In this way, the instruction decoding unit 108 can transmit the disable enable signal 101e to the input buffer circuits 107 corresponding to the remaining group data in the same group based on the instruction signal 101f, so that the input buffer circuits 107 corresponding to the remaining group data in the same group are disabled based on the disable enable signal 101e.

[0063] In some embodiments, continue to refer to Figure 6 The storage system 100 may further include: an instruction generating unit 109, which receives multiple groups of data and outputs an instruction signal 101f if there is an identical group among the multiple groups of data.

[0064] It should be noted that the instruction generation unit 109 can be used to analyze multiple groups of data that need to be transmitted by the data port 102. In some examples, the instruction signal 101f generated based on the multiple groups of data can indicate the existence of the same group in the multiple groups of data, indicate which group of data in the same group is transmitted normally, and indicate the position of the input buffer circuit 107 corresponding to each data. Subsequently, the instruction decoding unit 108 can transmit the disable enable signal 101e to the input buffer circuits 107 corresponding to the remaining groups of data in the same group based on the instruction signal 101f, and disable the input buffer circuits 107 corresponding to the remaining groups of data in the same group based on the disable enable signal 101e. And disable the transmission path between the input buffer circuit 107 and the interface of the corresponding storage array 103; in other examples, if the number of identical groups is greater than or equal to 2, the instruction signal 101f generated based on multiple groups of data can indicate which data ports 102 output data belonging to the same identical group, and indicate the position of the input buffer circuit 107 corresponding to each data, so that the subsequent instruction decoding unit 108 can transmit the disable enable signal 101e to the input buffer circuit 107 corresponding to any data in the same group that does not need to be transmitted based on the instruction signal 101f, thereby avoiding the input buffer circuits 107 between different identical groups from erroneously reading the disable enable signal 101e.

[0065] In this way, the instruction generation unit 109 can be used to analyze multiple groups of data that need to be transmitted by the data port 102 to obtain an instruction signal 101f that represents which data in the multiple groups of data are the same and the position of the input buffer circuit 107 corresponding to each data. This is beneficial for disabling the input buffer circuits 107 corresponding to the remaining groups of data in the same group while avoiding the input buffer circuits 107 corresponding to different data from erroneously reading the disable enable signal 101e.

[0066] It should be noted that, in actual applications, the instruction generating unit 109 may be a subunit of the processing module 101 , a module parallel to the processing module 101 , or a peripheral unit outside the storage system 100 .

[0067] In some embodiments, the processing module 101 can also be configured to output a third drive signal (not shown in the figure) if there is at least one group of data with different data among the multiple groups of data; the data path 104 corresponding to the at least one group of data with different data is turned on in response to the third drive signal.

[0068] Because some of the multiple groups of data have the same data while the data of other groups are different from the data of the same group, the first drive signal 101c and the second drive signal 101d are generated based on the data of the same group while a third drive signal of the other group that is different from the data of the same group is also generated. This is beneficial in ensuring that only one of the multiple data paths 104 corresponding to the data of the same group is turned on to save power consumed by data transmission. At the same time, based on the third drive signal, the data paths 104 corresponding to the other groups that are different from the data of the same group are turned on, which is beneficial in ensuring the integrity of the data ultimately written into the storage array 103.

[0069] It should be noted that, in actual applications, the data path 104 corresponding to at least one group of data with different data may also be turned on in response to the first driving signal 101 c.

[0070] In summary, during the copy-on-write mode, if it is found that the same data exists among multiple groups of data to be written to the storage array 103, the transmission path for writing one group of data in the same group to the storage array 103 is enabled, and the transmission paths for writing other groups of data in the same group to the storage array 103 are disabled. During this data writing process, the transmission paths for the other groups of data in the same group will not generate new power consumption, thereby helping to reduce the power consumption required for writing data to the storage array 103.

[0071] Another embodiment of the present disclosure further provides a method for writing data into a storage system, which is applied to the storage system provided in the above embodiment. The method for writing data into a storage system provided in another embodiment of the present disclosure will be described in detail below.

[0072] In an embodiment of the present disclosure, a method for writing data to a storage system includes: responding to a copy-on-write enable signal to enter a copy-on-write mode; during the copy-on-write mode, if at least two groups of data among multiple groups of data output from a data port are identical, defining the at least two groups of data as the same group; generating an identification signal for indicating data copying; transmitting one group of data in the same group to an interface of a storage array; and disabling a transmission path between the data ports corresponding to the remaining groups of data in the same group and the interface of the storage array; the storage array, in response to the copy-on-write enable signal and the identification signal, copies the one group of data in the same group to the corresponding interfaces of the storage array corresponding to the remaining groups of data in the same group. In this way, the transmission path between the remaining groups of data in the same group and the corresponding interfaces of the storage array does not generate new power consumption, thereby facilitating reduced power consumption when writing data to the storage array.

[0073] In some embodiments, the step of outputting an identification signal for indicating data replication may include: determining whether all groups of data in the plurality of groups of data are identical; and outputting an identification signal if all groups of data in the plurality of groups of data are identical. Thus, if all groups of data in N groups of data are identical, the identification signal may be used to disable the transmission path corresponding to the N-1 group of data during transmission of the N groups of data, thereby avoiding unnecessary power consumption by the N-1 transmission paths corresponding to the N-1 group of data, thereby reducing power consumption associated with writing data to the storage array. Where N is a positive integer greater than or equal to 2.

[0074] In some embodiments, the steps of transmitting one set of data in the same group to the interface of the storage array and disabling the transmission path between the data port corresponding to the remaining sets of data in the same group and the interface of the storage array may include: generating a first drive signal and a second drive signal in response to a write copy enable signal and multiple sets of data; the data path corresponding to the one set of data in the same group transmitting data in response to the first drive signal to transmit the data to the corresponding interface of the storage array, and disabling the data paths corresponding to the remaining sets of data in the same group in response to the second drive signal.

[0075] In this way, when transmitting multiple sets of identical data, a first drive signal can be used to control only one of the data paths corresponding to the multiple sets of data to be conductive, while a second drive signal can be used to control the data paths corresponding to the remaining sets of data to be disabled. This can avoid unnecessary power consumption in the transmission paths corresponding to the remaining sets of data, thereby further reducing the power consumption associated with writing data to the storage array. Subsequently, based on the identification signal, data received by the interface of the storage array corresponding to the remaining sets of data can be copied to the data transmitted by the conductive data paths.

[0076] In some embodiments, the step of transmitting one set of data in the same group to the interface of the storage array and disabling the transmission path between the data ports corresponding to the remaining sets of data in the same group and the interface of the storage array may further include disabling input buffer circuits connected between the data ports corresponding to the remaining sets of data in the same group and the data path. Disabling the input buffer circuits means that the input buffer circuits corresponding to the remaining sets of data in the same group will not be driven and will not transmit data output from the data ports to the corresponding data paths, thereby reducing power consumption when writing data to the storage array.

[0077] In some embodiments, multiple groups of data to be transmitted by the data port 102 can be analyzed to generate a command signal and a disable enable signal; based on the command signal and the disable enable signal, a disable enable signal is output to the input buffer circuits corresponding to the remaining groups of data in the same group. In some examples, the command signal can indicate the existence of the same group among the multiple groups of data and indicate which group of data in the same group is normally transmitted, so that the disable enable signal can be subsequently transmitted to the input buffer circuits corresponding to the remaining groups of data in the same group based on the command signal, and the input buffer circuits corresponding to the remaining groups of data in the same group are disabled based on the disable enable signal, and the transmission path between the input buffer circuit and the interface of the corresponding memory array is disabled; in other examples, if the number of the same groups is greater than or equal to 2, the command signal generated based on the multiple groups of data can indicate which data ports output the same group of data and the location of the input buffer circuit corresponding to each data, so that the subsequent command decoding unit can transmit the disable enable signal to the input buffer circuit corresponding to any data in the same group that does not need to be transmitted based on the command signal, thereby preventing the input buffer circuits of different groups from erroneously reading the disable enable signal.

[0078] In some embodiments, the identification signal is transmitted to the memory array via multiple stages of identification transmission circuits connected in series, the data path including multiple stages of data transmission circuits connected in series, and each stage of data transmission circuit corresponds to a stage of identification transmission circuit. The step of transmitting a group of data in the same group to the interface of the memory array and disabling the transmission path between the data ports corresponding to the remaining groups of data in the same group and the interface of the memory array may further include: further responding to the write copy enable signal and the identification signal received at the input end of the identification transmission circuit of the current stage to generate a first drive signal for driving at least the data transmission circuit of the current stage, and generating a second drive signal for disabling the data transmission circuit of the current stage. In this way, while ensuring that the data to be transmitted is not distorted after each stage of data transmission circuit 114 in the data path 104 is turned on based on the first drive signal, it is also beneficial to ensure that each stage of data transmission circuit 114 in the data path 104 corresponding to the other groups in the same group is disabled, thereby preventing interference with data transmission and reducing power consumption when writing data to the memory array 103.

[0079] To summarize, when the storage system enters the copy-write mode in response to the copy-write enable signal, if it is found that the data in multiple groups of data to be written to the storage array are identical, the transmission path for writing one group of data in the same group to the storage array is enabled, and the transmission paths for writing other groups of data in the same group to the storage array are disabled. In this case, during the data writing process, the transmission paths for the other groups of data in the same group will not generate new power consumption, thereby helping to reduce the power consumption required for writing data to the storage array.

[0080] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage system, characterized in that: include: The storage system is configured to enter a copy-on-write mode in response to a copy-on-write enable signal, and during the copy-on-write mode, if at least two groups of data among a plurality of groups of data output from a data port are identical, define the at least two groups of data as the same group, generate an identification signal for indicating data copying, transmit one group of data in the same group to an interface of a storage array, and disable a transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array, wherein the storage array copies the one group of data in the same group to the interface of the storage array corresponding to the remaining groups of data in the same group in response to the copy-on-write enable signal and the identification signal; The storage system includes: a processing module, the processing module outputting a first driving signal, a second driving signal, and the identification signal in response to the write copy enable signal and the multiple sets of data, and sending the identification signal to the storage array; A plurality of data paths are provided, each of the data paths serving as a transmission path for a group of the data between the interface of the storage array and the data port, the data paths corresponding to a group of the data in the same group being turned on in response to the first drive signal, and the data paths corresponding to the remaining groups of the data in the same group being disabled in response to the second drive signal.

2. The storage system according to claim 1, wherein: The storage system is further configured to output the identification signal if all the groups of data in the plurality of groups of data are identical.

3. The storage system according to claim 1, wherein: The storage system is further configured to, if there is at least one group of data in the plurality of groups of data that is different from the same group of data, further transmit the at least one group of data to a corresponding interface of the storage array.

4. The storage system according to claim 1, wherein: The data path includes: A plurality of stages of data transmission circuits are connected in series, and each stage of the data transmission circuit transmits data based on the first driving signal, or each stage of the data transmission circuit is disabled based on the second driving signal.

5. The storage system according to claim 4, wherein: The processing module includes: A multi-stage identification signal transmission circuit is connected in series, wherein the input end of each stage of the identification signal transmission circuit is used to receive the identification signal, and the output end is used to output the identification signal, and the identification signal transmission circuit at the last stage transmits the identification signal to the storage array.

6. The storage system according to claim 5, wherein: Each level of the identification signal transmission circuit includes an even number of inverters connected in series.

7. The storage system according to claim 5, wherein: The processing module further includes: Multiple signal generating units, each of the signal generating units corresponds to the first-level identification signal transmission circuit and the first-level data transmission circuit, and the signal generating unit is configured to provide the first drive signal and the second drive signal to the corresponding data transmission circuit in response to the write copy enable signal and the identification signal received at the input end of the identification signal transmission circuit.

8. The storage system according to claim 1, wherein: The storage system further includes: Multiple input buffer circuits, each of which is connected between the data path and the data port, and the input buffer circuits are configured so that the processing module outputs a disable enable signal to the input buffer circuit, and the input buffer circuits corresponding to the remaining groups of data in the same group are disabled in response to the disable enable signal.

9. The storage system according to claim 8, wherein: The processing module includes: An instruction decoding unit, the instruction decoding unit being connected to each of the input buffer circuits, the instruction decoding unit being configured to output the disable enable signal to the input buffer circuits corresponding to the remaining groups of data of the same group based on an instruction signal and the disable enable signal, wherein the instruction signal is generated based on the existence of the same group in the multiple groups of data.

10. The storage system according to claim 9, wherein: The storage system further includes: The instruction generating unit receives the multiple sets of data and outputs the instruction signal if the same set exists in the multiple sets of data.

11. The storage system according to claim 4, wherein: The processing module is further configured to output a third driving signal if there is at least one set of data with different data among the multiple sets of data; The data paths corresponding to at least one group of data having different data are turned on in response to the third driving signal.

12. A method for writing data into a storage system, characterized in that: include: Entering a copy-on-write mode in response to a copy-on-write enable signal. During the copy-on-write mode, if at least two groups of data among the multiple groups of data output from the data port are identical, defining the at least two groups of data as the same group, generating an identification signal for indicating data copying, transmitting one group of data in the same group to an interface of a storage array, and disabling a transmission path between the data port corresponding to the remaining groups of data in the same group and the interface of the storage array. The storage array, in response to the copy-on-write enable signal and the identification signal, copies the one group of data in the same group to the corresponding interfaces of the storage array corresponding to the remaining groups of data in the same group. The step of transmitting one set of data in the same group to an interface of a storage array and disabling a transmission path between data ports corresponding to other sets of data in the same group and the interface of the storage array includes: generating a first driving signal and a second driving signal in response to the write copy enable signal and the plurality of sets of data; The data paths corresponding to one group of data in the same group transmit data in response to the first driving signal to transfer the data to the corresponding interface of the storage array, and the data paths corresponding to the remaining groups of data in the same group are disabled in response to the second driving signal.

13. The data writing method according to claim 12, wherein: The output is used to indicate an identification signal of data replication, including: Determining whether all of the multiple sets of data are the same; If all the groups of data in the plurality of groups of data are identical, the identification signal is output.

14. The data writing method according to claim 12, wherein: The method of transmitting one set of data in the same group to an interface of a storage array and disabling a transmission path between data ports corresponding to other sets of data in the same group and the interface of the storage array further includes: Input buffer circuits connected between data ports corresponding to the remaining groups of data in the same group and the data path are disabled.

15. The data writing method according to claim 12, wherein: The identification signal is transmitted to the storage array via multiple stages of identification transmission circuits connected in series, the data path includes multiple stages of data transmission circuits connected in series, and each stage of the data transmission circuit corresponds to one stage of the identification transmission circuit; the method of transmitting one set of data in the same group to the interface of the storage array and disabling the transmission path between the data ports corresponding to the remaining sets of data in the same group and the interface of the storage array further includes: It also responds to the write copy enable signal and the identification signal received at the input end of the identification transmission circuit of the current stage to generate the first driving signal for driving at least the data transmission circuit of the current stage, and generates the second driving signal for disabling the data transmission circuit of the current stage.

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