Epitaxial structure and method of manufacturing the same, semiconductor device

Abstract

The embodiment of the present application discloses an epitaxial structure, a preparation method thereof and a semiconductor device. The epitaxial structure comprises a substrate, an epitaxial layer and a passivation layer. The epitaxial layer is located on one side of the substrate, and the epitaxial layer comprises a III-V compound-based semiconductor material. The passivation layer is located on the side of the epitaxial layer away from the substrate. The thickness of the passivation layer is positively correlated with the warping degree of the substrate. Compared with the prior art, the embodiment of the present application makes the passivation layer more stable in inhibiting the effect of traps on electrons, makes the epitaxial surface state on substrates with different warping degrees consistent as much as possible, and improves the reliability of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of microelectronics technology, and in particular to an epitaxial structure and its preparation method, and a semiconductor device. Background Technology

[0002] Group III nitride materials possess unique advantages in realizing optoelectronic devices and high electron mobility transistors (HEMTs), and their research has undergone a long development process. Due to the lattice mismatch between gallium nitride (GaN) and aluminum gallium nitride (AlGaN), the AlGaN barrier layer exhibits significant tensile stress. Furthermore, AlGaN is a strong piezoelectric material, resulting in a very strong piezoelectric polarization field within the AlGaN barrier layer. Under the influence of this piezoelectric polarization field, a high carrier density can be achieved at the AlGaN / GaN heterojunction interface without any doping, which is one of the key advantages of GaN HEMT devices compared to devices made from other materials. In fact, AlGaN / GaN HEMTs have broad application prospects in communications, radar, sensing, and automation.

[0003] However, the presence of numerous dangling bonds on the AlGaN barrier layer surface introduces a large number of surface state traps. When the gate voltage is off, electrons tunneling from under the gate fill these traps. These electrons filling the surface traps create a "virtual gate effect," depleting the two-dimensional electron gas in the channel layer. When the gate voltage is on, a two-dimensional electron gas is generated in the channel directly below the gate, while the two-dimensional electron gas under the "virtual gate" remains depleted. As the electrons trapped by the surface traps are slowly released, the concentration of the two-dimensional electron gas under the "virtual gate" gradually increases and approaches a steady state. Therefore, there is a delay in the turn-on of the semiconductor device channel relative to the turn-on of the gate voltage, known as the "gate delay effect." The existence of gate delay significantly affects various performance characteristics of semiconductor devices. To suppress gate delay, a common practice is to apply a passivation layer to the barrier layer surface. The passivation layer's role is to suppress the influence of these traps on electrons. However, in existing technologies, the passivation layer's effect on suppressing the influence of traps on electrons is unstable, resulting in poor reliability of the semiconductor device. Summary of the Invention

[0004] This invention provides an epitaxial structure and its fabrication method, as well as a semiconductor device, to stabilize the effect of the passivation layer on the suppression of traps on electrons and improve the reliability of the semiconductor device.

[0005] In a first aspect, embodiments of the present invention provide an epitaxial structure, comprising:

[0006] Substrate;

[0007] An epitaxial layer located on one side of the substrate, the epitaxial layer comprising a semiconductor material based on a III-V compound;

[0008] A passivation layer is located on the side of the epitaxial layer away from the substrate; wherein the thickness of the passivation layer is positively correlated with the warpage of the substrate.

[0009] Optionally, the degree of warpage of the substrate is positively correlated with the size of the substrate; correspondingly, the thickness of the passivation layer is positively correlated with the size of the substrate.

[0010] Optionally, the substrate has a size of X inch, the passivation layer has a thickness of Y nm, and X and Y satisfy a linear inequality relationship.

[0011] Optionally, the substrate has a size of X inch, the passivation layer has a thickness of Y nm, and X / 5 <Y<50X。

[0012] Optionally, X / 2 <Y<20X。

[0013] Optionally, if the size of the substrate is greater than or equal to a size threshold, the growth rate of the passivation layer thickness decreases as the size of the substrate increases.

[0014] Optionally, the substrate may be 2 inches, 3 inches, 4 inches, 6 inches, or 8 inches in size.

[0015] Optionally, the epitaxial layer includes at least one of the following: a nucleation layer, a buffer layer, a superlattice buffer layer, a channel layer, and a barrier layer.

[0016] Optionally, the material of the epitaxial layer includes at least one of aluminum nitride, gallium nitride, aluminum gallium nitride, and indium gallium nitride.

[0017] Optionally, the substrate material includes at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon.

[0018] Secondly, embodiments of the present invention also provide a semiconductor device, including: a gate and an epitaxial structure as described in any embodiment of the present invention, wherein the gate is located on the side of the passivation layer away from the substrate.

[0019] Thirdly, embodiments of the present invention also provide a method for preparing an epitaxial structure, used to prepare an epitaxial structure as described in any embodiment of the present invention; the preparation method includes:

[0020] Provide substrate;

[0021] An epitaxial layer is formed on the substrate; the epitaxial layer comprises a semiconductor material based on a III-V compound.

[0022] A passivation layer is formed on the epitaxial layer; wherein the thickness of the passivation layer is positively correlated with the degree of warpage of the substrate.

[0023] Optionally, the process for forming the passivation layer includes at least one of in-situ growth and non-in-situ growth.

[0024] Optionally, the process for forming the passivation layer includes at least one of continuous growth and pulsed growth.

[0025] By increasing the thickness of the passivation layer on substrates with greater warpage, this invention can suppress the "slow-state" traps that arise due to increased substrate warpage, thereby making the passivation layer's suppression of traps' influence on electrons more stable. Therefore, the passivation layer provided by this invention can, by adjusting the relationship between its thickness and the substrate warpage, make the epitaxial surface states on substrates with different warpages as consistent as possible, thus improving the reliability of semiconductor devices. Attached Figure Description

[0026] Figure 1 A schematic diagram of the film layer in an epitaxial structure, showing how the thickness of the passivation layer varies with the warpage of the substrate, as provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of another epitaxial structure film provided in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0029] Figure 4 This is a schematic flowchart illustrating a method for preparing an epitaxial structure according to an embodiment of the present invention. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0031] As described in the background section, in existing technologies, the effect of passivation layer suppression traps on electrons is unstable, resulting in poor reliability of semiconductor devices. The inventors conducted in-depth research on this technical problem and creatively discovered that the cause of this problem is related to the degree of substrate warpage. The specific analysis is as follows:

[0032] The degree of warpage can be characterized by the surface curvature of the substrate when warpage occurs. A greater degree of warpage results in a larger height difference between the substrate edge and the center, leading to more severe substrate deformation. Consequently, the AlGaN barrier layer experiences greater stress, resulting in a deterioration in its quality. Furthermore, this deterioration in the AlGaN barrier layer quality leads to an increase in deep-level traps within the AlGaN, many of which are "slow-state" traps. Specifically, when the energy levels of surface traps are shallow, trapped electrons are released quickly, resulting in a short gate delay time. Conversely, when the energy levels of surface traps are deep, the trapped electrons are released more slowly, resulting in a longer gate delay time; these are called "slow-state" traps. These "slow-state" traps require a longer time to release the trapped electrons.

[0033] The above analysis explains why semiconductor devices fabricated using the same epitaxial process on substrates with different degrees of warpage have very different performance. Specifically, on substrates with greater warpage, the surface of the AlGaN barrier layer has more "slow-state" traps, which makes the silicon nitride used on substrates with less warpage insufficient to suppress these additional "slow-state" traps.

[0034] In view of this, the inventors of this invention further discovered that by increasing the thickness of the silicon nitride passivation layer on a substrate with a large degree of warpage, the gate delay suppression effect can remain comparable to that of a 2-inch substrate. In other words, by increasing the thickness of the passivation layer, these additional "slow-state" traps can be effectively suppressed, and even if the degree of substrate warpage is different, the performance of the semiconductor device can remain basically consistent, thereby improving the reliability of the semiconductor device.

[0035] The above describes the technical concept of the present invention. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram illustrating the variation of the passivation layer thickness with substrate warpage in an epitaxial structure, as provided in an embodiment of the present invention. See also... Figure 1 The epitaxial structure includes a substrate 10, an epitaxial layer 20, and a passivation layer 30. The epitaxial layer 20 is located on one side of the substrate 10 and comprises a semiconductor material based on a III-V compound. The passivation layer 30 is located on the side of the epitaxial layer 20 away from the substrate 10; wherein, the thickness of the passivation layer 30 is positively correlated with the warpage of the substrate 10, that is, the greater the warpage of the substrate 10, the thicker the passivation layer 30; conversely, the smaller the warpage of the substrate 10, the thinner the passivation layer 30.

[0037] As the warpage of the substrate 10 increases, the quality of the epitaxial layer 20 deteriorates, leading to more deep-level traps and surface "slow-state" traps, thus exacerbating the gate delay problem. This embodiment of the invention increases the thickness of the passivation layer 30 on the substrate 10 with greater warpage, thereby suppressing the additional "slow-state" traps caused by increased warpage. This makes the passivation layer 30's suppression of traps' influence on electrons more stable. Therefore, the passivation layer 30 provided in this embodiment of the invention can adjust the relationship between its thickness and the warpage of the substrate 10 to make the epitaxial surface states on substrates 10 with different warpage degrees as consistent as possible, improving the reliability of semiconductor devices.

[0038] It is understandable that different substrate sizes result in different degrees of warpage for the same curvature. Specifically, as the size increases, the degree of warpage for the same curvature increases. This is because, for the same curvature, the larger the size, the greater the height difference between the substrate edge and the center. This embodiment of the invention does not specifically limit the relationship between the degree of warpage and the thickness of the passivation layer 30. In practical applications, the thickness of the passivation layer 30 can be adjusted according to changes in the degree of warpage.

[0039] Further research by the inventors revealed that the thickness of the passivation layer 30 is also related to the size of the substrate. For example, when using a silicon nitride passivation layer on a larger substrate, the suppression effect on gate delay is far less than that on a 2-inch substrate. This is because a larger substrate can introduce greater warpage.

[0040] See also Figure 1 Based on the above embodiments, optionally, the warpage of the substrate 10 is positively correlated with the size of the substrate 10; correspondingly, the thickness of the passivation layer 30 is positively correlated with the size of the substrate 10, that is, the larger the size of the substrate 10, the thicker the passivation layer 30; conversely, the smaller the size of the substrate 10, the thinner the passivation layer 30. Specifically, as the size of the substrate 10 increases, the warpage of the substrate 10 becomes greater, the quality of the epitaxial layer 20 deteriorates, the number of deep-level traps in the epitaxial layer 20 increases, the number of surface "slow-state" traps increases, and the gate delay problem becomes more serious. By increasing the thickness of the passivation layer 30 on a large-size substrate 10, the embodiments of the present invention can suppress the "slow-state" traps that increase due to the increase in the size of the substrate 10, thereby making the effect of the passivation layer 30 in suppressing the influence of traps on electrons more stable. Therefore, the passivation layer 30 provided by the embodiments of the present invention can adjust the relationship between its thickness and the size of the substrate 10 to make the epitaxial surface states on substrates 10 of different sizes as consistent as possible, thereby improving the reliability of semiconductor devices.

[0041] Based on the above embodiments, the embodiments of the present invention further define the relationship between the size of the substrate 10 and the thickness of the passivation layer 30. Optionally, the size of the substrate 10 is X inch, the thickness of the passivation layer 30 is Y nm, and X and Y satisfy a binary linear inequality relationship. Optionally, X / 5 < Y < 50X. Through research by the inventor, it is found that such a relationship limitation makes the performance of the semiconductor device have a better consistency effect. Preferably, X / 2 < Y < 20X.

[0042] Based on the above embodiments, optionally, if the size of the substrate 10 is greater than or equal to the size threshold, the growth rate of the thickness of the passivation layer 30 decreases as the size of the substrate increases. Through research by the inventor, when the size of the substrate 10 increases to a certain extent, the thickness of the passivation layer 30 that needs to be matched tends to level off. The embodiments of the present invention are set in this way, so that the matching degree of the passivation layer 30 to the size of the substrate 10 is better, further improving the reliability of the semiconductor device.

[0043] The embodiments of the present invention do not limit the shape of the substrate. Exemplarily, the substrate 10 is a substrate with a circular main body. Among them, wafers are mostly used for the substrate 10, so circular substrates have the widest range of applications. The size of the substrate can be a physical quantity such as the area, perimeter, side length, diameter, radius, etc. of the substrate that can characterize the size of the substrate. Exemplarily, if the shape of the substrate is a circular wafer, the size of the substrate 10 is set as the diameter of the substrate. The size X of the substrate 10 is generally a positive integer greater than 0. Exemplarily, the size of the substrate 10 includes: 2 inch, 3 inch, 4 inch, 6 inch, or 8 inch, etc.

[0044] It should be noted that the selection of the size of the substrate 10 can be determined according to process conditions or by special requirements. The present invention does not limit it. Any technical solution that satisfies the positive correlation between the thickness of the passivation layer 30 and the size of the substrate 10 is within the protection scope of the present invention.

[0045] Based on the above embodiments, the following describes the specific structures and materials of the substrate 10, the epitaxial layer 20, and the passivation layer 30, but it is not a limitation to the present invention.

[0046] Continue to refer to Figure 1 , in an embodiment of the present invention, optionally, the material of the passivation layer 30 is an insulating material, generally including one or more of silicon nitride (SiN), silicon oxide, silicon dioxide, etc. Compared with other materials, the insulating material has a good suppression effect on the "slow state" traps in the epitaxial layer 20. Using SiN as the passivation layer 30 is beneficial to suppressing the gate delay problem of the device. And, under the same gate delay suppression effect, compared with other materials, the epitaxial layer 20 using SiN can be set with a thinner film thickness, which is beneficial to realizing the miniaturization of the device.

[0047] In one embodiment of the present invention, the epitaxial layer 20 optionally includes at least one of a nucleation layer, a buffer layer, a superlattice buffer layer, a channel layer, and a barrier layer. Figure 2 This is a schematic diagram of another epitaxial structure provided in an embodiment of the present invention. In one embodiment of the present invention, the epitaxial layer 20 may optionally be a multilayer structure. Specifically, the epitaxial layer 20 includes: a nucleation layer 21, a buffer layer 22, a channel layer 23, and a barrier layer 24. The nucleation layer 21 and the buffer layer 22 are used for lattice matching between the substrate 10 and the channel layer 23. The channel layer 23 and the barrier layer 24 form a heterojunction structure, and a two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 23 and the barrier layer 24. Specifically, the material of the nucleation layer 21 may be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the buffer layer 22 may be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the channel layer 23 may be, for example, GaN or other semiconductor materials; and the material of the barrier layer 24 may be, for example, aluminum gallium nitride (AlGaN) or indium gallium nitride (InGaN). Therefore, the epitaxial layer 20 can be one or more of the common epitaxial layers 20 such as AlN, GaN, AlGaN, InGaN, etc.

[0048] Based on the above embodiments, optionally, the material of the substrate 10 includes at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. That is, the material of the substrate 10 includes one, two, or a combination of the above materials. In other embodiments, the material of the substrate 10 may also be any other material capable of growing group III nitrides.

[0049] This invention also provides a semiconductor device. Figure 3 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention. See also... Figure 3 The semiconductor device includes a gate 40 and an epitaxial structure as provided in any embodiment of the present invention, wherein the gate 40 is located on the side of the passivation layer 30 away from the substrate 10. Optionally, the semiconductor device further includes a source 50 and a drain 60, wherein the source 50 and the drain 60 are located on the side of the passivation layer 30 away from the substrate 10.

[0050] Semiconductor devices may include, for example, high electron mobility transistors (HEMTs), silicon-on-insulator (SOI) transistors, gallium arsenide (GaAs)-based transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors; the present invention is not limited thereto.

[0051] Since the semiconductor device includes the epitaxial structure provided in any embodiment of the present invention, its technical principle and the resulting effect are similar, and will not be described in detail here.

[0052] This invention also provides a method for preparing an epitaxial structure, used to prepare the epitaxial structure as provided in any embodiment of this invention, with similar technical principles and effects. Specifically, Figure 4 This is a schematic flowchart illustrating a method for preparing an epitaxial structure according to an embodiment of the present invention. See also... Figure 4 The preparation method includes the following steps:

[0053] S110 provides a substrate.

[0054] The substrate material can be any material capable of growing group III nitrides, such as at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. The substrate size X is generally a positive integer greater than 0; for example, the substrate size is 2 inches, 3 inches, 4 inches, 6 inches, or 8 inches.

[0055] S120. Form an epitaxial layer on the substrate; the epitaxial layer includes a semiconductor material based on III-V group compounds.

[0056] Exemplarily, the epitaxial layer is a multi-layer structure. Specifically, the epitaxial layer includes: a nucleation layer, a buffer layer, a channel layer, and a barrier layer. Among them, the nucleation layer and the buffer layer are used for lattice matching between the substrate and the channel layer, and the channel layer and the barrier layer form a heterojunction structure, and a two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer. Specifically, the material of the nucleation layer can be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the buffer layer can be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the channel layer can be, for example, GaN or other semiconductor materials; the material of the barrier layer can be, for example, aluminum gallium nitride (AlGaN) or indium gallium nitride (InGaN). Thus, the epitaxial layer can be a combination of one or more of common epitaxial layers such as AlN, GaN, AlGaN, InGaN, etc.

[0057] S130. Form a passivation layer on the epitaxial layer; wherein, the thickness of the passivation layer is positively correlated with the warping degree of the substrate.

[0058] Optionally, the warping degree of the substrate 10 is positively correlated with the size of the substrate 10; correspondingly, the thickness of the passivation layer 30 is positively correlated with the size of the substrate 10. Exemplarily, the size of the substrate is X inch, the thickness of the passivation layer is Y nm, and X / 5 < Y < 50X. Through research by the inventor, it is found that such a relationship limitation makes the device performance have a better consistency effect. Preferably, X / 2 < Y < 20X.

[0059] Among them, there are various processes for forming the passivation layer, which are not limited in this invention. Exemplarily, the process for forming the passivation layer includes at least one of in-situ growth and non-in-situ growth. In-situ passivation growth can be, for example, Metal-organic Chemical Vapor Deposition (MOCVD). Specifically, a SiN passivation layer is grown in a MOCVD device. Non-in-situ growth can be, for example, Molecular Beam Epitaxy (MBE). Specifically, a SiN passivation layer is grown in a MBE device. The combination of in-situ growth and non-in-situ growth can be, for example, first growing a certain thickness of SiN passivation layer in MOCVD; then taking out the epitaxial structure from the MOCVD device and placing it into other devices such as a MBE device to grow a certain thickness of SiN passivation layer.

[0060] Exemplarily, the process for forming the passivation layer further includes at least one of continuous growth and pulsed growth.

[0061] In summary, by increasing the thickness of the passivation layer on substrates with greater warpage, the embodiments of the present invention can suppress the additional "slow-state" traps caused by the increased warpage of the substrate, thereby making the effect of the passivation layer in suppressing traps on electrons more stable. Therefore, the passivation layer provided by the embodiments of the present invention can, by adjusting the relationship between its thickness and the warpage of the substrate, make the epitaxial surface states on substrates with different warpages as consistent as possible, thus improving the reliability of semiconductor devices.

[0062] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An epitaxial structure, characterized in that, include: Substrate; An epitaxial layer located on one side of the substrate, the epitaxial layer comprising a semiconductor material based on a III-V compound; A passivation layer is located on the side of the epitaxial layer away from the substrate; wherein the thickness of the passivation layer is positively correlated with the warpage of the substrate. The degree of warpage of the substrate is positively correlated with the size of the substrate; correspondingly, the thickness of the passivation layer is positively correlated with the size of the substrate. If the size of the substrate is greater than or equal to a size threshold, the growth rate of the passivation layer thickness decreases as the size of the substrate increases; The substrate has a size of X inch, the passivation layer has a thickness of Y nm, and X and Y satisfy a linear inequality relationship. The substrate size and passivation layer thickness meet X / 5 <Y<50X; The passivation layer is made of an insulating material.

2. The epitaxial structure according to claim 1, characterized in that, The substrate size and passivation layer thickness satisfy X / 2 <Y<20X。 3. The epitaxial structure according to claim 1, characterized in that, The substrate has the following dimensions: 2 inch, 3 inch, 4 inch, 6 inch, or 8 inch.

4. The epitaxial structure according to claim 1, characterized in that, The epitaxial layer includes at least one of the following: a nucleation layer, a buffer layer, a superlattice buffer layer, a channel layer, and a barrier layer.

5. A semiconductor device, characterized in that, include: The epitaxial structure as described in any one of claims 1-4.

6. A method for preparing an epitaxial structure, characterized in that, A method for preparing the epitaxial structure as described in any one of claims 1-4; the preparation method includes: Provide substrate; An epitaxial layer is formed on the substrate; the epitaxial layer comprises a semiconductor material based on a III-V compound. A passivation layer is formed on the epitaxial layer; wherein the thickness of the passivation layer is positively correlated with the degree of warpage of the substrate.

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