A filtering device suitable for a single photon detector

Abstract

The application discloses a filtering device suitable for a single photon detector, comprising a single photon detector, a histogram statistical algorithm unit based on convolution, a histogram statistical algorithm unit based on a detection algorithm and a super-resolution processing algorithm unit connected in sequence, the single photon detector is used for converting an optical signal into an electrical pulse signal, the histogram statistical algorithm unit based on convolution is used for filtering, storing first filtering data in an odd frame and outputting second filtering data in an even frame; the histogram statistical algorithm unit based on the detection algorithm is used for performing product operation on storage values of the same address in an odd frame accumulation result and an even frame accumulation result, the super-resolution processing algorithm unit is used for obtaining a more accurate peak value address based on a product result, and a distance between the single photon detector and a target object is obtained according to a time of flight calculation formula. The application can reduce resource consumption of the filtering device, improve a signal-to-noise ratio of a statistical histogram and improve distance resolution.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing, and specifically relates to a filtering device suitable for single-photon detectors. Background Technology

[0002] Single-photon detectors are a crucial component of solid-state lidar systems. Their core function is to convert the optical signals received by the single-photon detector into electrical pulse signals. By measuring the time interval between the emitted and received laser pulse signals, information such as the distance between the single-photon detector and the target object, the angular difference, and the surface reflectivity of the target object can be obtained. Therefore, solid-state lidar systems based on single-photon detectors are characterized by high stability, high accuracy, and a large dynamic range, and are currently widely used in fields such as autonomous driving and target recognition.

[0003] In existing technologies, because the core component of a single-photon detector, the single-photon avalanche breakdown diode, has the characteristics of high gain and high sensitivity, the system needs to filter out background noise from the histogram statistical results through a correlation filter circuit in actual operation. However, due to the large amount of data, the filter circuit usually has a large circuit area and high power consumption. In addition, the traditional histogram statistical algorithm sums the effective outputs obtained at any sampling time in the time and spatial domains by linear superposition, resulting in a low signal-to-noise ratio in the histogram statistical results. At the same time, since single-photon detectors have a minimum resolution, and the traditional single-photon detector distance extraction algorithm uses the position of the peak in the histogram statistical results as the basis for distance conversion, the obtained distance resolution is limited. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a filtering device suitable for single-photon detectors. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A filtering device suitable for single-photon detectors includes: a single-photon detector, a convolution-based histogram statistical algorithm unit, a detection algorithm-based histogram statistical algorithm unit, and a super-resolution processing algorithm unit, which are connected in sequence.

[0006] The single-photon detector is used to convert the received optical signal into an electrical pulse signal;

[0007] The convolution-based histogram statistical algorithm unit is used to filter the electrical pulse signal, accumulate all first filtered data within the same odd-numbered frames according to the time difference to obtain the odd-numbered frame accumulation result corresponding to the time difference, store the odd-numbered frame accumulation result corresponding to the first address as the first address, and output the second filtered data within the even-numbered frames to the histogram statistical algorithm unit based on the detection algorithm. The first filtered data is used to characterize the equivalent total number of times the single-photon detector is triggered at a single sampling time within the odd-numbered frames, and the second filtered data is used to characterize the equivalent total number of times the single-photon detector is triggered at a single sampling time within the even-numbered frames. The time difference is the time difference between the external transmitting device transmitting the optical signal and the single-photon detector receiving the optical signal.

[0008] The histogram statistics algorithm unit based on the detection algorithm is used to accumulate all the second filtered data in the same even frame according to the time difference as the even frame accumulation result corresponding to the time difference, store the even frame accumulation result corresponding to the second address as the second address, multiply the storage value of the third address in the odd frame accumulation result and the even frame accumulation result by performing a product operation, and rewrite the product result as the storage unit value corresponding to the third address, wherein the third address is the address value of any address in the second address;

[0009] The super-resolution processing algorithm unit is used to obtain the distance between the single-photon detector and the target object based on the third address, the product result corresponding to the third address, and the time-of-flight calculation formula.

[0010] In one embodiment of the present invention, the convolution-based histogram statistical algorithm unit includes a filtering circuit, a first adder, a first RAM read / write control circuit, a first RAM unit, and a first RAM address generation circuit, wherein,

[0011] The input terminal of the filtering circuit is electrically connected to the output terminal of the single-photon detector, and the output terminal of the filtering circuit is connected to the input terminal of the first adder and the input terminal of the histogram statistical algorithm unit based on the detection algorithm. The filtering circuit is used to filter the background noise of the electrical pulse signal, and outputs the first filtered data in odd frames to the first adder, and outputs the second filtered data in even frames to the histogram statistical algorithm unit based on the detection algorithm.

[0012] The input terminal of the first adder is connected to the output terminal of the first RAM unit, and the output terminal of the first adder is connected to the input terminal of the first RAM unit. The first adder is used to obtain the first accumulation result output by the first RAM unit, sum the first filtered data and the first accumulation result, and return the summation result to the first RAM unit.

[0013] The input terminal of the first RAM address generation circuit is connected to an external control circuit to control the address increment of the first RAM cell to be synchronized with the laser pulse emission signal at all times. The first RAM address generation circuit is also used to transmit the first address to the first RAM cell.

[0014] The input terminal of the first RAM read / write control circuit receives a first level signal from an external circuit, and the output terminal of the first RAM read / write control circuit is electrically connected to the read enable port and write enable port of the first RAM cell. The first RAM read / write control circuit is used to control the read enable and write enable ports of the first RAM cell according to the first level signal.

[0015] The first RAM unit is used to read the first accumulation result corresponding to the first address according to the first address. The first RAM unit receives the summation result returned by the first adder and updates the summation result to the storage unit corresponding to the first address.

[0016] In one embodiment of the present invention, the first RAM unit is used to read the first accumulated result corresponding to the first address according to the first address, including: when the first accumulated result is not empty, outputting the first accumulated result to the first adder; when the first accumulated result is empty, marking the first accumulated result as NULL and outputting the first accumulated result to the first adder.

[0017] In one embodiment of the present invention, summing the first filtered data and the first accumulated result and returning the summation result to the first RAM unit includes: when the first accumulated result is NULL, directly returning the first filtered data as the summation result to the first RAM unit; when the first accumulated result is not NULL, summing the first filtered data and the first accumulated result and returning the summation result to the first RAM unit.

[0018] In one embodiment of the present invention, the histogram statistics algorithm unit based on the detection algorithm includes a second adder, a second RAM address generation circuit, a second RAM unit, a second RAM read / write control circuit, and a multiplier, wherein,

[0019] The input terminals of the second adder are respectively connected to the output terminal of the filter circuit and the output terminal of the second RAM unit. The output terminal of the second adder is electrically connected to the input terminal of the second RAM unit. The second adder is used to obtain the second filtered data and the second accumulation result output by the second RAM unit, sum the second filtered data and the second accumulation result, and return the summation result to the second RAM unit.

[0020] The input terminal of the second RAM address generation circuit is connected to an external control circuit to control the address increment of the second RAM cell to be synchronized with the laser pulse emission signal. The output terminal of the second RAM address generation circuit is electrically connected to the input terminal of the second RAM cell. The second RAM address generation circuit is used to transmit the second address to the second RAM cell.

[0021] The input terminal of the second RAM read / write control circuit receives a second level signal from an external circuit, and the output terminal of the second RAM read / write control circuit is electrically connected to the read enable port and write enable port of the second RAM cell. The second RAM read / write control circuit is used to control the read enable and write enable ports of the second RAM cell according to the second level signal.

[0022] The input terminal of the second RAM unit is connected to the output terminal of the multiplier, and the output terminal of the second RAM unit is connected to the input terminal of the multiplier. Under the control of the second RAM read / write control circuit, the second RAM unit reads the second accumulation result according to the second address and outputs the second accumulation result to the second adder, receives the summation result returned by the second adder, updates the summation result to the storage unit corresponding to the second address, outputs the summation result corresponding to the third address to the multiplier, receives the product result output by the multiplier, and rewrites the product result to the storage unit corresponding to the third address.

[0023] The input of the multiplier is also connected to the output of the first RAM unit. It is used to obtain the storage value corresponding to the third address in the first RAM unit and the second RAM unit in the adjacent odd and even frames after the data writing is completed, and to perform a product operation. The product result is then rewritten into the storage unit corresponding to the third address in the second RAM unit.

[0024] In one embodiment of the present invention, the second RAM unit reads the second accumulated result according to the second address and outputs the second accumulated result to the second adder, including: when the second accumulated result is not empty, outputting the second accumulated result to the second adder; when the second accumulated result is empty, marking the second accumulated result as NULL and outputting the second accumulated result to the second adder.

[0025] In one embodiment of the present invention, the second filtered data and the second accumulated result are summed, and the summation result is returned to the second RAM unit. This includes: when the second accumulated result is NULL, the second adder directly returns the second filtered data as the summation result to the second RAM unit; when the second accumulated result is not NULL, the second filtered data and the second accumulated result are summed, and the summation result is returned to the second RAM unit.

[0026] In one embodiment of the present invention, the super-resolution processing algorithm unit includes a peak detection algorithm unit, an echo detection algorithm unit, a full width at half maximum (FWHM) calculation unit, a divider, and a third adder, wherein,

[0027] The input terminal of the peak detection algorithm unit is electrically connected to the output terminal of the second RAM unit, and the output terminal of the peak detection algorithm unit is electrically connected to the input terminal of the full width at half maximum (FWHM) calculation unit. The peak detection algorithm unit is used to extract the peak value of the data stored in the second RAM unit and the address corresponding to the peak value.

[0028] The input terminal of the echo detection algorithm unit is electrically connected to the output terminal of the second RAM unit, and the output terminal of the echo detection algorithm unit is electrically connected to the input terminal of the full width at half maximum (FWHM) calculation unit. The echo detection algorithm unit is used to extract the start position value, stop position value, address of the start position value, and address of the stop position value of the valid echo signal in the second RAM unit. The valid echo signal refers to the value stored in the second RAM unit compared with a preset standard value, and the value less than the preset standard value is the valid echo signal.

[0029] The output of the full width at half maximum (FWHM) calculation unit is electrically connected to the input of the divider. The FWHM calculation unit is used to calculate the left half-height value of the peak point and the start position of the effective echo data, and the right half-height value of the peak point and the stop position of the effective echo signal.

[0030] The output of the divider is electrically connected to the input of the third adder. The divider is used to obtain the address offset according to the super-resolution algorithm formula, which is:

[0031]

[0032] Where A represents the address offset obtained according to the super-resolution algorithm formula, S1 represents the starting position value, S2 represents the left half-height value, S3 represents the peak value, S4 represents the right half-height value, and S5 represents the stopping position value.

[0033] The third adder is used to add the address offset to the peak address to obtain an accurate peak address that is equivalent to exceeding the inherent resolution of the single-photon detector, and to calculate the distance between the single-photon detector and the target object based on the accurate peak address and the time-of-flight calculation formula.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] The filtering device for single-photon detectors provided by this invention reduces resource consumption and computation time of the filtering circuit by implementing a front-end filtering circuit architecture, thereby reducing circuit area and power consumption, while increasing the system's operating frequency. By multiplying the data corresponding to the BIN of the histogram statistical results of two adjacent frames, the response of the effective echo signal in the histogram statistical results is enhanced, improving the measurement signal-to-noise ratio of the single-photon detector. By employing a super-resolution processing algorithm, it achieves an effect equivalent to exceeding the minimum resolution of the single-photon detector, obtaining higher distance resolution and improving the distance measurement accuracy between the single-photon detector and the target object.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a filtering device suitable for a single-photon detector provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of the histogram statistics algorithm unit based on convolution provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of the histogram statistics algorithm unit based on the detection algorithm provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of the super-resolution processing algorithm unit provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0042] Please see Figure 1 , Figure 1This is a schematic diagram of a filtering device suitable for a single-photon detector provided in an embodiment of the present invention. The filtering device provided in this embodiment includes a single-photon detector 100, a histogram statistical algorithm unit based on convolution 200, a histogram statistical algorithm unit based on detection algorithm 300, and a super-resolution processing algorithm unit 400 connected in sequence.

[0043] Specifically, the single-photon detector 100 is used to convert the received optical signal into an electrical pulse signal.

[0044] The convolution-based histogram statistical algorithm unit 200 has its input terminal electrically connected to the output terminal of the single-photon detector 100. The convolution-based histogram statistical algorithm unit 200 filters the electrical pulse signal, accumulates all first-filtered data within the same odd-numbered frame according to the time difference, and stores the accumulated result of the odd-numbered frame corresponding to the time difference as the first address. It then outputs second-filtered data within even-numbered frames to the detection algorithm-based histogram statistical algorithm unit 300. The first-filtered data characterizes the equivalent total number of times the single-photon detector 100 is triggered at a single sampling time within an odd-numbered frame, and the second-filtered data characterizes the equivalent total number of times the single-photon detector 100 is triggered at a single sampling time within an even-numbered frame. The time difference is the time difference between the optical signal emitted by the external transmitting device and the optical signal received by the single-photon detector 100.

[0045] The histogram statistical algorithm unit 300 based on the detection algorithm has its input terminal electrically connected to the output terminal of the histogram statistical algorithm unit 200 based on convolution. The histogram statistical algorithm unit 300 based on the detection algorithm is used to accumulate all the second filtered data in the same even-numbered frame according to the time difference to obtain the even-numbered frame accumulation result corresponding to the time difference. The time difference corresponding to the second filtered data is used as the second address to store the even-numbered frame accumulation result corresponding to the second address. The histogram statistical algorithm unit 300 based on the detection algorithm is used to perform a product operation on the accumulated result of the odd-numbered frame and the stored value of the third address in the accumulated result of the even-numbered frame, and the product result is used as the storage unit value corresponding to the third address to rewrite the histogram statistical algorithm unit 300 based on the detection algorithm. The third address is the address value of any address in the second address.

[0046] The super-resolution processing algorithm unit 400 has its input terminal electrically connected to the output terminal of the histogram statistical algorithm unit 300 based on the detection algorithm. The super-resolution processing algorithm unit 400 is used to obtain the distance between the single-photon detector and the target object based on the third address, the product result corresponding to the third address, and the time-of-flight calculation formula.

[0047] The filtering device provided in this embodiment uses a convolution-based histogram statistical algorithm unit 200 to implement a front-end architecture for the filtering circuit 210, reducing the resource consumption and computation time of the filtering circuit 210, decreasing the circuit area and power consumption, while simultaneously increasing the operating frequency of the single-photon detector 100. A detection-based histogram statistical algorithm unit 300 multiplies the data corresponding to the BIN of the histogram statistical results of two adjacent frames, strengthening the response of the effective echo signal in the histogram statistical results and improving the measurement signal-to-noise ratio of the single-photon detector 100. A super-resolution processing algorithm unit 400 implements a multi-point centroid calculation super-resolution algorithm, achieving an effect equivalent to exceeding the minimum resolution of the single-photon detector 100, obtaining higher distance resolution. This allows for the precise distance between the single-photon detector 100 and the target object to be obtained based on accurate peak address and time-of-flight calculation formulas, improving the accuracy of distance measurement.

[0048] In this embodiment, the single-photon detector 100 converts the received optical signal into an electrical pulse signal; the convolution-based histogram statistical algorithm unit 200 drives the filtering circuit 210 with the electrical pulse signal output by the single-photon detector 100 and stores the filtering result in the first RAM unit 240. The architecture of the filtering circuit 210 being placed in front reduces the system's resource consumption and circuit area; the detection algorithm-based histogram statistical algorithm unit 300 suppresses common-mode noise in the working state of the single-photon detector 100 by multiplying the data corresponding to the BIN of the histogram statistical results of adjacent frames, thereby improving the signal-to-noise ratio of the histogram statistical results; the super-resolution processing algorithm unit 400 achieves an effect equivalent to exceeding the minimum resolution of the single-photon detector 100 by using a super-resolution algorithm with multi-point centroid calculation to effectively improve the distance resolution of the single-photon detector 100.

[0049] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the histogram statistical algorithm unit based on convolution provided in an embodiment of the present invention. The histogram statistical algorithm unit 200 based on convolution includes a filter circuit 210, a first adder 220, a first RAM read / write control circuit 230, a first RAM unit 240, and a first RAM address generation circuit 250.

[0050] The input terminal of the filter circuit 210 is electrically connected to the output terminal of the single-photon detector 100. The output terminal of the filter circuit 210 is connected to the input terminal of the first adder 220 and the input terminal of the histogram statistical algorithm unit 300 based on the detection algorithm. The filter circuit 210 is used to filter the background noise of the electrical pulse signal output by the single-photon detector 100 by using a convolution algorithm, and outputs the first filtered data in odd frames to the first adder 220, and outputs the second filtered data in even frames to the histogram statistical algorithm unit 300 based on the detection algorithm.

[0051] The input of the first adder 220 is connected to the output of the first RAM unit 240, and the output of the first adder 220 is connected to the input of the first RAM unit 240. The first adder 220 is used to obtain the first accumulation result output by the first RAM unit 240, sum the first filtered data and the first accumulation result, and return the summation result to the first RAM unit 240. Specifically, when the first accumulation result is NULL, the first filtered data is directly returned to the first RAM unit 240 as the summation result; when the first accumulation result is not NULL, the first filtered data and the first accumulation result are summed, and the summation result is returned to the first RAM unit 240.

[0052] The input terminal of the first RAM address generation circuit 250 is connected to an external control circuit, so that the address increment of the first RAM cell 240 is synchronized with the laser pulse emission signal. The address of the first RAM cell 240 corresponds one-to-one with the flight time. The first RAM address generation circuit 250 is used to transmit a first address to the first RAM cell 240. The first address represents the time difference between the optical signal emitted by the external transmitting device and the optical signal received by the single-photon detector 100 within the same odd-numbered frame.

[0053] The input terminal of the first RAM read / write control circuit 230 receives a first level signal from an external circuit. The output terminal of the first RAM read / write control circuit 230 is electrically connected to the read enable port and write enable port of the first RAM cell 240. The first RAM read / write control circuit 230 is used to control the read enable and write enable ports of the first RAM cell 240 according to the first level signal to facilitate storage and retrieval.

[0054] The first RAM unit 240 is used to read the first accumulated result corresponding to the first address transmitted by the first RAM address generation circuit 250. When the first accumulated result is not empty, the first accumulated result is output to the first adder 220. When the first accumulated result is empty, the first accumulated result is marked as NULL and the first accumulated result is output to the first adder 220. In addition, the first RAM unit 240 receives the summation result returned by the first adder 220 and updates the summation result to the storage unit corresponding to the first address output by the first RAM address generation circuit 250.

[0055] In this embodiment, the filtering circuit 210 filters the electrical pulse signal output by the single-photon detector 100 before storing it in the statistical histogram, and outputs first filtered data and second filtered data respectively. The first adder 220 receives the first filtered data. At the same time, under the control of the first RAM read-write control circuit 230, the first RAM unit 240 reads the first accumulation result corresponding to the address of the current sampling time output by the first RAM address generation circuit 250, and outputs the first accumulation result to the first adder 220. Then, the first adder 220 sums the first filtered data and the first accumulation result, and returns the summation result to the first RAM unit 240. Under the control of the first RAM read-write control circuit 230, the first RAM unit 240 rewrites the summation result into the storage unit corresponding to the address of the current sampling time to prepare data for subsequent product operations.

[0056] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the histogram statistical algorithm unit based on the detection algorithm provided in the embodiment of the present invention. The histogram statistical algorithm unit 300 based on the detection algorithm includes a second adder 310, a second RAM address generation circuit 320, a second RAM unit 330, a second RAM read / write control circuit 340, and a multiplier 350.

[0057] Specifically, the input terminal of the second adder 310 is connected to the output terminal of the filter circuit 210 and the output terminal of the second RAM unit 330, respectively. The output terminal of the second adder 310 is electrically connected to the input terminal of the second RAM unit 330. The second adder 310 is used to obtain the second filtered data output by the filter circuit 210 and the second accumulated result output by the second RAM unit 330, sum the second filtered data and the second accumulated result, and return the summation result to the second RAM unit (330).

[0058] Furthermore, when the second accumulation result is NULL, the second filtered data is directly returned to the second RAM unit 330 as the summation result; when the second accumulation result is not NULL, the second filtered data and the second accumulation result are summed, and the summation result is returned to the second RAM unit 330.

[0059] The input terminal of the second RAM address generation circuit 320 is connected to an external control circuit to control the address increment of the second RAM unit 330 to be synchronized with the laser pulse emission signal. The output terminal of the second RAM address generation circuit 320 is electrically connected to the input terminal of the second RAM unit 330. The second RAM address generation circuit 320 is used to transmit the second address to the second RAM unit 330.

[0060] The input terminal of the second RAM read / write control circuit 340 receives a second level signal from an external circuit. The output terminal of the second RAM read / write control circuit 340 is electrically connected to the read enable port and write enable port of the second RAM cell 330. The second RAM read / write control circuit 340 is used to control the read enable and write enable ports of the second RAM cell 330 according to the second level signal.

[0061] The input terminal of the second RAM unit 330 is connected to the output terminal of the multiplier 350, and the output terminal of the second RAM unit 330 is connected to the input terminal of the multiplier 350. Under the control of the second RAM read / write control circuit 340, the second RAM unit 330 reads the second accumulated result corresponding to the second address according to the second address, and outputs the second accumulated result to the second adder 310. Specifically, when the second accumulated result is not empty, the second accumulated result is output to the second adder 310; when the second accumulated result is empty, the second accumulated result is marked as NULL and the second accumulated result is output to the second adder 310.

[0062] In addition, the second RAM unit 330 receives the summation result returned by the second adder 310 and updates the summation result to the storage unit corresponding to the second address. The second RAM unit 330 is also used to output the summation result corresponding to the third address to the multiplier 350, and receive the product result output by the multiplier 350, and rewrite the product result into the storage unit corresponding to the third address in the second RAM unit 330.

[0063] The input of multiplier 350 is also connected to the output of the first RAM unit 240. It is used to obtain the storage value corresponding to the third address in the first RAM unit 240 and the second RAM unit 330 in the adjacent odd and even frames after the data writing is completed. That is, the BIN corresponding to the histogram statistical result of the two adjacent frames at the same address, multiply the BIN corresponding to the histogram statistical result of the two adjacent frames at the third address, and rewrite the product result into the storage unit corresponding to the third address in the second RAM unit 330.

[0064] In this embodiment, the second adder 310 receives the second filtered data and, under the control of the second RAM read / write control circuit 340, reads the second accumulated result corresponding to the address at the current sampling time output by the second RAM address generation circuit 320, and outputs the second accumulated result to the second adder 310. Subsequently, the second adder 310 sums the second filtered data and the second accumulated result, and returns the summation result to the second RAM unit 330. Under the control of the second RAM read / write control circuit 340, the second RAM unit 330 rewrites the summation result into the storage unit corresponding to the address at the current sampling time to prepare data for subsequent operations. After both adjacent odd and even frames have completed intra-frame storage, the multiplier 350 obtains the stored values ​​in the third address of the first RAM unit 240 and the second RAM unit 330 in the adjacent odd and even frames, performs a product operation, and rewrites the product result into the third address of the second RAM unit 330 until the product operation of the stored values ​​corresponding to all addresses in the first RAM unit 240 and the second RAM unit 330 is completed. At this time, the stored value in any address in the second RAM unit 330 is the product of the BIN values ​​corresponding to the histogram statistics results in the adjacent odd and even frames. The filtering device provided in this embodiment can improve the ratio of effective signal to background noise in the histogram data and suppress common-mode noise by performing a product operation on the stored values ​​in the same address in adjacent odd and even frames and using the product result as the equivalent total number of times the detector 100 corresponding to the current sampling time represented by the address value.

[0065] The filtering device provided in this embodiment enhances the distribution characteristics of the measurement results, increases the amplitude of the effective echo signal, strengthens the response of the effective echo signal in the histogram statistical results, and thus improves the signal-to-noise ratio of the measurement results by multiplying the BIN values ​​corresponding to the histogram statistical results at the address in adjacent odd and even frames using multiplier 350 and storing them in the second RAM unit 330.

[0066] Please see Figure 4 As shown, Figure 4This is a schematic diagram of the structure of the super-resolution processing algorithm unit provided in the embodiment of the present invention. The super-resolution processing algorithm unit 400 includes a peak detection algorithm unit 410, an echo detection algorithm unit 420, a full width at half maximum (FWHM) calculation unit 430, a divider 440, and a third adder 450.

[0067] The input terminal of the peak detection algorithm unit 410 is electrically connected to the output terminal of the second RAM unit 330, and the output terminal of the peak detection algorithm unit 410 is electrically connected to the input terminal of the half-width at half-height calculation unit 430. The peak detection algorithm unit 410 is used to extract the peak value of the data stored in the second RAM unit 330 and the address corresponding to the peak value according to the bubble sort method.

[0068] The input terminal of the echo detection algorithm unit 420 is electrically connected to the output terminal of the second RAM unit 330, and the output terminal of the echo detection algorithm unit 420 is electrically connected to the input terminal of the full width at half maximum (FWHM) calculation unit 430. The echo detection algorithm unit 420 is used to extract the start position value, stop position value, address of the start position value, and address of the stop position value of the valid echo signal from the data stored in the second RAM unit 330. Specifically, the valid echo signal refers to the value stored in the second RAM unit 330 compared with a preset standard value, and the value less than the preset standard value is a valid echo signal.

[0069] The output of the full width at half maximum (WHM) calculation unit 430 is electrically connected to the input of the divider 440. The full width at half maximum (WHM) calculation unit 430 is used to calculate the WHM value (left WHM value) between the peak point and the start position of the valid echo data, and the WHM value (right WHM value) between the peak point and the stop position of the valid echo signal. The result is obtained by establishing a linear expression, which provides data support for the divider 440.

[0070] The output of divider 440 is electrically connected to the input of third adder 450. Divider 440 is used to obtain the address offset according to the super-resolution algorithm formula, which is:

[0071]

[0072] Where A represents the address offset obtained according to the super-resolution algorithm formula, S1 represents the starting position value, S2 represents the left half-height value, S3 represents the peak value, S4 represents the right half-height value, and S5 represents the stopping position value.

[0073] Adder 450 is used to add the address offset to the peak address to obtain an accurate peak address that is equivalent to exceeding the inherent resolution of the single-photon detector 100, and to calculate the distance between the single-photon detector 100 and the target object based on the accurate peak address and the time-of-flight calculation formula.

[0074] The filtering device provided in this embodiment uses a super-resolution processing algorithm unit 400 to implement a super-resolution algorithm for multi-point centroid calculation, thereby obtaining a more accurate peak position. Then, based on the peak address and time-of-flight calculation formula, the distance between the single-photon detector and the target object is obtained, thus realizing the function of lidar. The filtering device provided in this embodiment can achieve an effect that is equivalent to exceeding the minimum resolution of the single-photon detector 100, improving the distance resolution and the accurate distance of the target object.

[0075] It should be noted that BIN in the convolution-based histogram statistical algorithm unit 200, the detection algorithm-based histogram statistical algorithm unit 300, and the super-resolution processing algorithm unit 400 is the interval width value corresponding to the minimum time resolution, and the preset standard value in the super-resolution processing algorithm unit 400 is the mean of the statistical histogram results minus the standard deviation in this invention.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0077] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A filtering device suitable for single-photon detectors, characterized in that, include: A single-photon detector (100), a convolution-based histogram statistical algorithm unit (200), a detection algorithm-based histogram statistical algorithm unit (300), and a super-resolution processing algorithm unit (400) are sequentially electrically connected, wherein... The single-photon detector (100) is used to convert the received optical signal into an electrical pulse signal; The convolution-based histogram statistical algorithm unit (200) is used to filter the electrical pulse signal, accumulate all the first filtered data in the same odd frame according to the time difference as the odd frame accumulation result corresponding to the time difference, store the odd frame accumulation result corresponding to the first address as the first address, and output the second filtered data in the even frame to the histogram statistical algorithm unit (300) based on the detection algorithm. The first filtered data is used to characterize the equivalent total number of times the single photon detector (100) is triggered at a sampling time in the odd frame, and the second filtered data is used to characterize the equivalent total number of times the single photon detector (100) is triggered at a sampling time in the even frame. The time difference is the time difference between the external transmitting device transmitting the optical signal and the single photon detector (100) receiving the optical signal. The histogram statistics algorithm unit (300) based on the detection algorithm is used to accumulate all the second filtered data in the same even frame according to the time difference as the even frame accumulation result corresponding to the time difference, store the even frame accumulation result corresponding to the second address as the second address, perform a product operation on the storage value of the third address in the odd frame accumulation result and the even frame accumulation result, and rewrite the product result as the storage unit value corresponding to the third address, wherein the third address is the address value of any address in the second address; The super-resolution processing algorithm unit (400) is used to obtain the distance between the single-photon detector (100) and the target object based on the third address, the product result corresponding to the third address, and the time-of-flight calculation formula.

2. The filtering device for single-photon detectors according to claim 1, characterized in that, The convolution-based histogram statistics algorithm unit (200) includes a filter circuit (210), a first adder (220), a first RAM read / write control circuit (230), a first RAM unit (240), and a first RAM address generation circuit (250), wherein, The input terminal of the filter circuit (210) is electrically connected to the output terminal of the single-photon detector (100). The output terminal of the filter circuit (210) is connected to the input terminal of the first adder (220) and the input terminal of the histogram statistical algorithm unit (300) based on the detection algorithm. The filter circuit (210) is used to filter the background noise of the electrical pulse signal, and outputs the first filtered data in odd frames to the first adder (220), and outputs the second filtered data in even frames to the histogram statistical algorithm unit (300) based on the detection algorithm. The input terminal of the first adder (220) is connected to the output terminal of the first RAM unit (240), and the output terminal of the first adder (220) is connected to the input terminal of the first RAM unit (240). The first adder (220) is used to obtain the first accumulation result output by the first RAM unit (240), sum the first filtered data and the first accumulation result, and return the summation result to the first RAM unit (240). The input terminal of the first RAM address generation circuit (250) is connected to an external control circuit to control the address increment of the first RAM unit (240) to be synchronized with the laser pulse emission signal. The first RAM address generation circuit (250) is also used to transmit the first address to the first RAM unit (240). The input terminal of the first RAM read / write control circuit (230) receives a first level signal from an external circuit, and the output terminal of the first RAM read / write control circuit (230) is electrically connected to the read enable port and write enable port of the first RAM unit (240). The first RAM read / write control circuit (230) is used to control the read enable and write enable ports of the first RAM unit (240) according to the first level signal. The first RAM unit (240) is used to read the first accumulation result corresponding to the first address according to the first address. The first RAM unit (240) receives the summation result returned by the first adder (220) and updates the summation result to the storage unit corresponding to the first address.

3. The filtering device for single-photon detectors according to claim 2, characterized in that, The first RAM unit (240) is used to read the first accumulation result corresponding to the first address according to the first address, including: when the first accumulation result is not empty, outputting the first accumulation result to the first adder (220); when the first accumulation result is empty, marking the first accumulation result as NULL and outputting the first accumulation result to the first adder (220).

4. The filtering device for single-photon detectors according to claim 3, characterized in that, The first filtered data and the first accumulated result are summed, and the summation result is returned to the first RAM unit (240). This includes, when the first accumulated result is NULL, directly returning the first filtered data as the summation result to the first RAM unit (240); When the first accumulated result is not NULL, the first filtered data and the first accumulated result are summed, and the summation result is returned to the first RAM unit (240).

5. The filtering device for single-photon detectors according to claim 4, characterized in that, The histogram statistics algorithm unit (300) based on the detection algorithm includes a second adder (310), a second RAM address generation circuit (320), a second RAM unit (330), a second RAM read / write control circuit (340), and a multiplier (350), wherein, The input terminals of the second adder (310) are respectively connected to the output terminals of the filter circuit (210) and the output terminal of the second RAM unit (330). The output terminal of the second adder (310) is electrically connected to the input terminal of the second RAM unit (330). The second adder (310) is used to obtain the second filtered data and the second accumulation result output by the second RAM unit (330), sum the second filtered data and the second accumulation result, and return the summation result to the second RAM unit (330). The input terminal of the second RAM address generation circuit (320) is connected to an external control circuit to control the address increment of the second RAM unit (330) to keep synchronized with the laser pulse emission signal. The output terminal of the second RAM address generation circuit (320) is electrically connected to the input terminal of the second RAM unit (330). The second RAM address generation circuit (320) is used to transmit the second address to the second RAM unit (330). The input terminal of the second RAM read / write control circuit (340) receives a second level signal from an external circuit. The output terminal of the second RAM read / write control circuit (340) is electrically connected to the read enable port and write enable port of the second RAM cell (330). The second RAM read / write control circuit (340) is used to control the read enable and write enable ports of the second RAM cell (330) according to the second level signal. The input terminal of the second RAM unit (330) is connected to the output terminal of the multiplier (350), and the output terminal of the second RAM unit (330) is connected to the input terminal of the multiplier (350). Under the control of the second RAM read / write control circuit (340), the second RAM unit (330) reads the second accumulation result according to the second address and outputs the second accumulation result to the second adder (310), receives the summation result returned by the second adder (310), updates the summation result to the storage unit corresponding to the second address, outputs the summation result corresponding to the third address to the multiplier (350), receives the product result output by the multiplier (350), and rewrites the product result into the storage unit corresponding to the third address. The input of the multiplier (350) is also connected to the output of the first RAM unit (240). It is used to obtain the storage value corresponding to the third address in the first RAM unit (240) and the second RAM unit (330) in the adjacent odd and even frames after the data writing is completed, and to perform a product operation. The product result is then rewritten into the storage unit corresponding to the third address in the second RAM unit (330).

6. The filtering device for single-photon detectors according to claim 5, characterized in that, The second RAM unit (330) reads the second accumulated result according to the second address and outputs the second accumulated result to the second adder (310). This includes outputting the second accumulated result to the second adder (310) when the second accumulated result is not empty, and marking the second accumulated result as NULL and outputting the second accumulated result to the second adder (310) when the second accumulated result is empty.

7. The filtering device for single-photon detectors according to claim 6, characterized in that, The second filtered data and the second accumulated result are summed, and the summation result is returned to the second RAM unit (330). This includes the following: when the second accumulated result is NULL, the second adder (310) directly returns the second filtered data as the summation result to the second RAM unit (330); when the second accumulated result is not NULL, the second filtered data and the second accumulated result are summed, and the summation result is returned to the second RAM unit (330).

8. The filtering device for single-photon detectors according to claim 7, characterized in that, The super-resolution processing algorithm unit (400) includes a peak detection algorithm unit (410), an echo detection algorithm unit (420), a full width at half maximum (FWHM) calculation unit (430), a divider (440), and a third adder (450), wherein, The input terminal of the peak detection algorithm unit (410) is electrically connected to the output terminal of the second RAM unit (330), and the output terminal of the peak detection algorithm unit (410) is electrically connected to the input terminal of the half-height full width calculation unit (430). The peak detection algorithm unit (410) is used to extract the peak value of the data stored in the second RAM unit (330) and the address corresponding to the peak value. The input terminal of the echo detection algorithm unit (420) is electrically connected to the output terminal of the second RAM unit (330), and the output terminal of the echo detection algorithm unit (420) is electrically connected to the input terminal of the full width at half maximum (FWHM) calculation unit (430). The echo detection algorithm unit (420) is used to extract the start position value, stop position value, address of the start position value, and address of the stop position value of the valid echo signal in the second RAM unit (330). The valid echo signal refers to the value stored in the second RAM unit (330) compared with a preset standard value, and the value less than the preset standard value is the valid echo signal. The output of the full width at half maximum (WHM) calculation unit (430) is electrically connected to the input of the divider (440). The full width at half maximum (WHM) calculation unit (430) is used to calculate the left half-height value of the peak point and the start position of the effective echo data and the right half-height value of the peak point and the stop position of the effective echo signal. The output of the divider (440) is electrically connected to the input of the third adder (450). The divider (440) is used to obtain the address offset according to the super-resolution algorithm formula, which is: Where A represents the address offset obtained according to the super-resolution algorithm formula, S1 represents the starting position value, S2 represents the left half-height value, S3 represents the peak value, S4 represents the right half-height value, and S5 represents the stopping position value. The third adder (450) is used to add the address offset to the peak address to obtain an accurate peak address that is equivalent to exceeding the inherent resolution of the single-photon detector (100), and to calculate the distance between the single-photon detector (100) and the target object according to the accurate peak address and the time-of-flight calculation formula.

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