A multifunctional dynamic loading signal detection method based on FPGA

Abstract

The present invention relates to a multifunctional, dynamically loaded signal detection method based on an FPGA, pertaining to the field of signal detection in phased array detection equipment. First, a signal detection scheme for both full-array and sub-array detection modes is designed. Furthermore, a method combining these full-array and sub-array detection modes with dynamic loading enables real-time dynamic switching of the instantaneous detection bandwidth of phased array detection equipment. This method overcomes the drawback of hardware resource limitations in the expansion of the instantaneous detection bandwidth of phased array detection equipment, thereby improving the resource utilization of the hardware platform.

Description

Technical Field

[0001] The invention belongs to the field of signal detection in phased array detection system equipment. Background Art

[0002] With the advancement of science and technology and the rapid development of electronic reconnaissance techniques, phased array systems, with their advantages of wide bandwidth, long range, and high accuracy, have broad application prospects in the field of technical reconnaissance in today's complex electromagnetic environment. The continuous development of broadband array technology and the increasing complexity and diversity of combat environments have placed higher demands on FPGA processing resources. Existing single-chip FPGA hardware resources are increasingly unable to meet the requirements of multi-function, high-bandwidth, and high-data-capacity signal detection. Therefore, the efficient utilization of hardware resources within a single hardware platform has become increasingly urgent.

[0003] Dynamic loading technology has developed rapidly with the improvement of hardware level. The commonly used dynamic loading methods are as follows, and each of them has certain shortcomings. For example: 1. Using the FPGA+CPLD+DSP hardware architecture and the high-speed serial RapidIO interface to realize dynamic loading of function items through command control words, and realizing high-speed dynamic loading and function item updates through the high-speed serial port data channel. Its disadvantages are that dynamic loading is realized through the main control module, FPGA module, CPLD module, and DSP module connected in sequence, which requires a large number of chips, is costly, and does not involve signal detection. 2. Using network interface circuits and configuration FPGAs to realize dynamic loading of multiple working FPGAs. The disadvantages of this method are that it requires additional network interface circuits, and the hardware program needs to be updated every time loading is performed. Uncontrollable factors are prone to cause loading failure during the program burning process, and signal detection is not involved. 3. Using the User Datagram Protocol (UDP) message format, the packets are transmitted to the ARM chip, which then writes them to the SPIFlash via the Serial Peripheral Interface (SPI), and then controls the FPGA chip to load the program. The disadvantage of this method is that it uses the ARM to achieve dynamic loading control, which is slow and has no connection with the DBF signal detection of this patent. 4. Using the dynamic structure interface provided by the FPGA, the CPU and CPLD cooperate to generate the timing that meets the FPGA structure interface, thereby realizing the FPGA program update. This method requires additional configuration of the CPU and CPLD, which increases the hardware design and manufacturing costs, and the process is complicated and not convenient for fast operation.

[0004] The above method only addresses dynamic loading and does not address the signal detection requirements of phased array systems. Due to the limited hardware logic resources of a single FPGA, it is generally unable to meet the detection requirements of large bandwidths. To expand the detection bandwidth of signal detection programs, improve hardware resource utilization, reduce hardware costs, and meet diverse functional requirements, a multifunctional dynamic loading signal detection method for FPGAs is needed. Summary of the Invention

[0005] To meet the requirements of phased array detection equipment for both high detection accuracy and large bandwidth, the present invention provides a multifunctional dynamic loading signal detection method based on FPGA. While ensuring signal measurement accuracy, it also enables real-time switching between different detection bandwidths.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] Step 1: Select a hardware board with parallel connection between FPGA chip and FLASH chip for design;

[0008] Step 2: Design a signal detection solution for real-time switching between full array and sub-array detection modes of the phased array detection equipment;

[0009] Step 3: Call the dynamic loading module ICAPE2 inside the FPGA chip in the signal detection program;

[0010] Step 4: Build a state machine in the signal detection program to configure the logical ports of ICAPE2 in step 2;

[0011] Step 5: Determine the configuration file addresses of the signal detection programs for the full array and sub-array detection modes in the FLASH chip;

[0012] Step 6: After the program is solidified, the bandwidth of the two detection modes is dynamically switched in real time through the trigger signal.

[0013] Furthermore, the parallel connection method in step 1 is:

[0014] Step 101: Select a FLASH chip that supports parallel transmission as the configuration chip of the FPGA;

[0015] Furthermore, the full array and sub-array detection scheme in step 2 is:

[0016] Step 201: The number of arrays in the full array detection mode is 32, the instantaneous bandwidth is B, and the detection bandwidth of the two-subarray detection mode is twice the instantaneous detection bandwidth of the full array, that is, 2*B;

[0017] Step 202: After beamforming the received full array detection mode channelized data, a total of 32 sets of I and Q data are obtained, corresponding to 32 beams;

[0018] Step 203: Call the cordic core inside the FPGA chip to generate pulse amplitude and phase. After the cordic core calculates the I and Q data corresponding to each beam, an amplitude value and a phase value can be obtained. There are 32 sets of amplitude values ​​and phase values ​​in total.

[0019] Step 204: pre-processing the amplitude value obtained in step 203 using a 64-point summation method;

[0020] Step 205: Count the channel noise value, set the noise value obtained by counting as the threshold N1, and set 1 / 2 of the amplitude value obtained by preprocessing in step 204 as the threshold N2;

[0021] Step 206: The amplitude value obtained in step 203 is subjected to a threshold check with N1 in step 205. The amplitude value obtained by pre-processing in step 204 is subjected to a threshold check with N2 in step 205. The amplitude values ​​that meet the judgment conditions and the corresponding phase values ​​are statistically analyzed and processed to obtain the pulse width, frequency and amplitude of the pulse.

[0022] Step 207: Combining the pulse information obtained in steps 203 and 206 to generate a PDW;

[0023] Step 208: In the subarray detection mode, there are two subarrays, each with 16 array elements. The instantaneous detection bandwidth is 2*B. After beamforming the channelized data in the subarray detection mode, each subarray obtains 16 sets of I and Q data, corresponding to 16 beam signals. The signal detection scheme is the same as described in steps 203 to 207 in step 2.

[0024] Furthermore, the method for calling the dynamic loading module ICAPE2 inside the FPGA chip in step 3 is:

[0025] Step 301: Find ICAPE2 by searching for FPGA primitives, and directly call ICAPE2 in the top-level module of the signal detection program without generating an IP core.

[0026] Furthermore, the method for configuring the logical port of ICAPE2 using the state machine in step 4 is:

[0027] Step 401: The length of the command input port configuration instruction of ICAPE2 is 4 bytes;

[0028] Step 402: Perform bit flipping on each byte of the 4-byte configuration instruction, with the middle line of the 8-bit bit as the axis of symmetry, and the bit values ​​on both sides of the axis of symmetry swapping positions according to the axis of symmetry;

[0029] Step 403: Use the state machine to control the configuration instruction timing and perform instruction configuration on the internal registers of ICAPE2.

[0030] Furthermore, in step 5, the method for determining the configuration file addresses of the signal detection programs for the full array and sub-array detection modes in the FLASH chip is as follows:

[0031] Step 501: Determine the addresses of the signal detection programs for the full array detection mode and the sub-array detection mode fixed in the FLASH chip respectively. The storage capacity between the two addresses is larger than the size of the fixed configuration file.

[0032] Furthermore, the method for dynamically switching the bandwidths of the two detection modes in real time by triggering the signal in step 6 is:

[0033] Step 601: After the FPGA is powered on, the full array detection mode signal detection program is run by default. When a dynamic loading trigger signal is received, the dynamic loading module within the signal detection program is started, and the full array detection mode signal detection program is dynamically switched to the sub-array detection mode signal detection program. If there is no trigger signal, the full array detection mode signal detection program continues to run.

[0034] Step 602: When the FPGA is running the sub-array detection mode signal detection program, it receives a dynamic loading trigger signal, starts the dynamic loading module inside the signal detection program, and dynamically switches the sub-array detection mode signal detection program to the full array detection mode signal detection program. If there is no trigger signal, the sub-array detection mode signal detection program continues to run.

[0035] Compared with existing technologies, the present invention offers the following advantages: It provides a multifunctional, dynamically loaded signal detection method based on an FPGA. This method combines full-array and sub-array detection modes with dynamic loading, enabling real-time dynamic switching of the instantaneous detection bandwidth of phased array detection equipment while ensuring signal measurement accuracy. This overcomes the limitation of instantaneous detection bandwidth expansion during signal detection in phased array detection equipment and improves hardware platform resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Implementation flow chart of the present invention.

[0037] Figure 2 Schematic diagram of parallel connection between FPGA and FLASH chip.

[0038] Figure 3 Schematic diagram of signal detection in full array detection mode.

[0039] Figure 4 Schematic diagram of signal detection in subarray detection mode.

[0040] Figure 5 Schematic diagram of calling the dynamic loading primitive ICAPE2.

[0041] Figure 6 Schematic diagram of byte bit flipping.

[0042] Figure 7 Dynamically load the logic port timing configuration diagram. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the implementation methods and drawings.

[0044] The preferred embodiments of the present invention are described as follows:

[0045] After the FPGA is powered on, it will first read and load the MCS file stored at address 0 of the Flash (the default read address is 0). At this time, the full array signal detection program will be run by default. After the program is loaded successfully, it will continuously detect the instruction status in the program configuration register. Figure 1 shown.

[0046] Step 1: Select a hardware board with parallel connection between FPGA chip and FLASH chip for design.

[0047] The FPGA hardware program involved in the present invention needs to run on a hardware board in which the FPGA chip and the FLASH chip adopt a parallel connection mode (Bpi connection) for data exchange.

[0048] Figure 2 The figure shows a schematic diagram of the parallel connection between the FPGA chip and the FLASH chip (Bpi connection).

[0049] Step 2: Design a signal detection solution for real-time switching between full-array and sub-array detection modes of the phased array detection equipment.

[0050] Figure 3 、 Figure 4 The following diagrams illustrate the signal detection schemes for full-array and sub-array detection modes, respectively. Taking the full-array signal detection program as an example, in full-array detection mode, there are 32 antenna columns, each corresponding to a beam, and the full-array detection bandwidth is B. The FPGA first receives channelized data from the array front end and then uses digital beamforming to synthesize I and Q data, with each beam corresponding to a set of I and Q data. The Cordic core is invoked within the FPGA. After the I and Q data are processed by the Cordic core, a single amplitude and phase value is obtained, resulting in a total of 32 sets of amplitude and phase values. The amplitude value corresponding to each beam is tested against a noise threshold. Amplitude values ​​that meet the criteria are then processed using the 64-point summation method and tested against a 1 / 2 amplitude threshold.

[0051] The 3 / 5 discrimination method is used to remove false signals from points that meet the threshold detection criteria. Then, the amplitude value, pulse width, and frequency that meet the discrimination conditions are calculated, and finally the PDW corresponding to each beam is obtained. Finally, the PDW of the corresponding channel is output through the PDW screening module, and signal detection with a detection bandwidth of B can be achieved. Figure 1 and Figure 4 shown.

[0052] If the full array can be divided into two subarrays with the same number of arrays, each subarray has 16 arrays, each with a total of 16 beams. After beamforming, each subarray has a total of 16 channels of I and Q data. The I and Q data corresponding to each beam undergoes a cordic kernel operation to obtain an amplitude and phase value, giving each subarray a total of 16 sets of amplitude and phase values. Each beam's amplitude is then tested for crossing a threshold to remove spurious signals. Points that meet the threshold crossing criteria are then tested using the 3 / 5 discrimination method to remove spurious signals. The amplitude, pulse width, and frequency that meet the discrimination criteria are then calculated to determine the PDW corresponding to each beam. Finally, the PDW filtering module outputs the PDW for the corresponding channel, enabling signal detection with a detection bandwidth of 2B.

[0053] Step 3: Call the dynamic loading module ICAPE2 inside the FPGA chip in the signal detection program.

[0054] Figure 5 The following diagram shows a schematic diagram of calling the ICAPE2 primitive, a dynamic reloading primitive within the FPGA chip. To perform dynamic reloading, call the ICAPE2 primitive shown in the figure above and configure it as needed. The "clk" configuration interface is the system clock input, and the "I" configuration interface is the register configuration port. Timing configuration for the ICAPE2 module primarily involves configuring the "I" port. The remaining configuration ports should be configured strictly according to the official Xilinx manual and the program primitive requirements.

[0055] Step 4: Build a state machine in the signal detection program to configure the logical ports of ICAPE2 in step 2.

[0056] Figure 6The following diagram shows a single-byte bit flip. The address register's configuration address is byte-flipped to point to the fixed address of the target program. The remaining logical port configuration commands are similarly bit-flipped. For example, the binary representation of the hexadecimal code 0x'ABCD is B'1010101111001101. Each byte has 8 bits, for a total of two bytes. A single byte bit flip is then performed. This single byte becomes B'1101010110110011 in binary, which translates to 0x'D5B3 in hexadecimal. Therefore, if the program address to be switched starts at 0x'ABCD in the FLASH chip, the configuration port of ICAPE2 in the program must be configured with 0x'D5B3.

[0057] Figure 7 The figure shows the state machine timing diagram when configuring the logic port of ICAPE2. Using the state machine to configure the logic port can strictly control the timing and improve the configuration accuracy.

[0058] Step 5: Determine the configuration file addresses of the signal detection programs for the full array and sub-array detection modes in the FLASH chip.

[0059] Determine the addresses of the configuration files for the full array detection mode and sub-array detection mode signal detection programs fixed in the FLASH chip. Pre-calculate the storage capacity between the two addresses to ensure that the storage capacity between the two addresses is larger than the size of the fixed configuration files. Avoid overlapping of the two configuration files.

[0060] Step 6: After the program is solidified, the bandwidth of the two detection modes is dynamically switched in real time through the trigger signal.

[0061] When the FPGA receives the trigger signal for switching to the sub-array mode signal detection program, the full array signal detection program will enter the logic port configuration timing state machine of the dynamic reload module inside the program. This state machine is used to send the IPROG instruction to ICAPE2, and dynamically load the required register data in accordance with the state machine timing configuration. Figure 7 shown.

[0062] When the logic configuration port instruction is correct, the FPGA reads the FLASH and loads the sub-array signal detection program configuration file stored at the address. After successful loading, it starts running the sub-array mode signal detection program.

[0063] After the subarray signal detection program is loaded successfully, if no external program switching trigger signal is received, the FPGA continues to run the current program; if an external program switching trigger signal is received, the program enters the dynamic loading module logic port configuration timing state machine and repeats the above steps to read and load the program at the corresponding address. Figure 1 shown.

[0064] The present invention provides a multifunctional FPGA-based dynamic loading signal detection method. Its advantages lie in combining full-array and sub-array detection modes with dynamic loading, enabling real-time dynamic switching of the instantaneous detection bandwidth of phased array detection equipment while ensuring signal measurement accuracy. This method overcomes the limitation of instantaneous detection bandwidth expansion during signal detection in phased array detection equipment and improves hardware platform resource utilization.

Claims

1. A multifunctional dynamic loading signal detection method based on FPGA, characterized by: Step 1: Select a hardware board with parallel connection between FPGA chip and FLASH chip for design; Step 2: Design a signal detection scheme for real-time switching between the full array and sub-array detection modes of the phased array detection equipment. Its characteristics are that there are 32 antenna columns in the full array detection mode, the full array detection bandwidth is B, and each antenna column corresponds to a beam. The FPGA first receives the channelized data sent by the front end of the array, and uses the digital beam synthesis method to synthesize I and Q data. Each beam corresponds to a set of I and Q data. The cordic core is called inside the FPGA. After the I and Q data are calculated by the cordic core, an amplitude value and a phase value can be obtained. There are a total of 32 sets of amplitude values ​​and phase values. The amplitude value corresponding to each beam is tested by the noise threshold, and the amplitude value that meets the judgment criteria is then subjected to the 64-point summation method. Processing, and at the same time perform 1 / 2 amplitude value threshold detection, use the 3 / 5 discrimination method to remove false signals at the points that meet the threshold detection conditions, then calculate the amplitude value, pulse width, and frequency that meet the discrimination conditions, and finally obtain the PDW corresponding to each beam, and finally output the PDW data, which can realize signal detection with a detection bandwidth of B. The full array can be divided into two sub-arrays with the same number of arrays. In the sub-array detection mode, each sub-array has 16 columns of antennas, and the sub-array detection bandwidth is 2*B. Each column of antennas corresponds to a beam, and each sub-array has 16 beams. The beam data processing process of each column of antennas in the sub-array refers to the beam data processing process in the full-array mode until the PDW data is output. The sub-array mode can realize signal detection with a bandwidth of 2*B; Step 3: Call the dynamic loading module ICAPE2 inside the FPGA chip in the signal detection program; Step 4: Build a state machine in the signal detection program to configure the logical ports of ICAPE2 in step 2; Step 5: Determine the configuration file addresses of the signal detection programs for the full array and sub-array detection modes in the FLASH chip; Step 6: After the program is solidified, the bandwidth of the two detection modes is dynamically switched in real time through the trigger signal.

2. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The parallel connection method in step 1 includes: Step 101: Select a FLASH chip that supports parallel transmission as the configuration chip of the FPGA.

3. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The full array and sub-array detection scheme in step 2 includes: Step 201: The number of arrays in the full array detection mode is 32, the instantaneous bandwidth is B, and the detection bandwidth of the two-subarray detection mode is twice the instantaneous detection bandwidth of the full array, that is, 2×B; Step 202: After beamforming the received full array detection mode channelized data, a total of 32 sets of I and Q data are obtained, corresponding to 32 beams; Step 203: Call the cordic core inside the FPGA chip to generate pulse amplitude and phase. After the cordic core calculates the I and Q data corresponding to each beam, an amplitude value and a phase value can be obtained. There are 32 sets of amplitude values ​​and phase values ​​in total. Step 204: pre-processing the amplitude value obtained in step 203 using a 64-point summation method; Step 205: Count the channel noise value, set the noise value obtained by counting as the threshold N1, and set 1 / 2 of the amplitude value obtained by preprocessing in step 204 as the threshold N2; Step 206: The amplitude value obtained in step 203 is subjected to a threshold check with N1 in step 205. The amplitude value obtained by pre-processing in step 204 is subjected to a threshold check with N2 in step 205. The amplitude values ​​that meet the judgment conditions and the corresponding phase values ​​are statistically analyzed and processed to obtain the pulse width, frequency and amplitude of the pulse. Step 207: Combining the pulse information obtained in steps 203 and 206 to generate a PDW; Step 208: In the subarray detection mode, there are two subarrays, each with 16 array elements. The instantaneous detection bandwidth is 2 × B. After beamforming the channelized data in the subarray detection mode, each subarray obtains 16 sets of I and Q data, corresponding to 16 beam signals. The signal detection scheme is the same as described in steps 203 to 207 in step 2.

4. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The method of calling the dynamic loading module ICAPE2 inside the FPGA chip in step 3 includes: Step 301: Find ICAPE2 by searching for FPGA primitives, and directly call ICAPE2 in the top-level module of the signal detection program without generating an IP core.

5. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The method for constructing the state machine to configure the logical port of ICAPE2 in step 4 includes: Step 401: The length of the command input port configuration instruction of ICAPE2 is 4 bytes; Step 402: Perform bit flipping on each byte of the 4-byte configuration instruction, with the middle line of the 8-bit bit as the axis of symmetry, and the bit values ​​on both sides of the axis of symmetry swapping positions according to the axis of symmetry; Step 403: Use the state machine to control the configuration instruction timing and perform instruction configuration on the internal registers of ICAPE2.

6. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The method for determining the configuration file addresses of the signal detection programs for the full array and sub-array detection modes in step 5, respectively, in the internal FLASH chip includes: Step 501: Determine the addresses of the configuration files of the signal detection programs of the full array detection mode and the sub-array detection mode in the FLASH chip respectively. The storage capacity between the two addresses must be larger than the size of the configuration files.

7. The multifunctional dynamic loading signal detection method based on FPGA according to claim 1, characterized in that: The method for dynamically switching the bandwidths of the two detection modes in real time by using a trigger signal in step 6 includes: Step 601: After the FPGA is powered on, the full array detection mode signal detection program is run by default. When a dynamic loading trigger signal is received, the dynamic loading module within the signal detection program is started, and the full array detection mode signal detection program is dynamically switched to the sub-array detection mode signal detection program. If there is no trigger signal, the full array detection mode signal detection program continues to run. Step 602: When the FPGA is running the sub-array detection mode signal detection program, it receives a dynamic loading trigger signal, starts the dynamic loading module inside the signal detection program, and dynamically switches the sub-array detection mode signal detection program to the full array detection mode signal detection program. If there is no trigger signal, the sub-array detection mode signal detection program continues to run.

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