Clock control circuit module, memory storage device and clock control method

Abstract

The application provides a clock control circuit module, a memory storage device and a clock control method. The clock control circuit module is used to generate a clock signal, receive a first signal and the clock signal, sample the first signal according to the clock signal to generate a first sampling signal and a second sampling signal, obtain first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal respectively, and evaluate a frequency offset state between the first signal and the clock signal according to the first position information and the second position information. Thus, the signal receiving quality of a signal receiving end can be improved.

Description

Technical Field

[0001] This invention relates to a clock control technology, and more particularly to a clock control circuit module, a memory storage device, and a clock control method. Background Technology

[0002] Most signal receivers are equipped with a phase detector, which aligns the phase of the received data signal with the phase of the internal clock signal used to sample the data signal, thereby improving the sampling accuracy. However, as data transmission speeds increase, aligning the data signal phase with the internal clock signal becomes increasingly difficult. Furthermore, if the frequency difference between the data signal and the internal clock signal is too large, a typical phase detector will not function properly. To address these issues, some types of signal receivers incorporate a frequency detector to help reduce the frequency difference between the data signal and the internal clock signal.

[0003] Common frequency detectors include reference clock signal-based frequency detectors (also known as Clock FDs) and data signal-based frequency detectors (also known as Data FDs). Reference clock signal-based frequency detectors track the frequency of a reference clock signal to correct the frequency of the internal clock signal, and then use a phase detector to align the phase of the received data signal with the phase of this internal clock signal. However, this type of frequency detector still cannot solve the problem of the phase detector failing to function properly when the frequency of the data signal differs too much from the frequency of the reference clock signal. On the other hand, data signal-based frequency detectors can use multiple internal clock signals with different phases to sequentially sample the data signal and evaluate whether the frequency of the data signal is higher or lower than the frequency of the internal clock signal based on the sampling results. However, this type of frequency detector requires internal clock signals with multiple phases to operate, so it is not suitable for all types of signal receivers. These drawbacks all lead to a decrease in the sampling accuracy of the data signal at the signal receiver. Summary of the Invention

[0004] This invention provides a clock control circuit module, a memory storage device, and a clock control method, which can improve the signal reception quality of the signal receiver.

[0005] An exemplary embodiment of the present invention provides a clock control circuit module, which includes a clock generation circuit, a sampling circuit, and a control circuit. The clock generation circuit generates a clock signal. The sampling circuit samples a first signal based on the clock signal and generates a sampled signal, wherein the sampled signal includes a first sampled signal and a second sampled signal. The first sampled signal reflects a first sampling result of the clock signal on a first target signal within the first signal, and the second sampled signal reflects a second sampling result of the clock signal on a second target signal within the first signal. The control circuit is connected to the clock generation circuit and the sampling circuit. The control circuit is used to: obtain first position information corresponding to a first transition point of the first target signal and second position information corresponding to a second transition point of the second target signal based on the first sampled signal and the second sampled signal, respectively; and evaluate the frequency offset state between the first signal and the clock signal based on the first position information and the second position information.

[0006] In an exemplary embodiment of the present invention, the first position information reflects the first position of the first transition point in the first sampling window of the clock signal, and the second position information reflects the second position of the second transition point in the second sampling window of the clock signal.

[0007] In one exemplary embodiment of the present invention, the duration of the first sampling window is the same as the duration of the second sampling window.

[0008] In an exemplary embodiment of the present invention, the first position information includes a first count value, the second position information includes a second count value, and the operation of the control circuit to evaluate the frequency offset state between the first signal and the clock signal based on the first position information and the second position information includes: evaluating the frequency offset state between the first signal and the clock signal based on the difference between the first count value and the second count value.

[0009] In one exemplary embodiment of the present invention, the difference is positively correlated with the frequency difference between the first signal and the clock signal.

[0010] In an exemplary embodiment of the present invention, the operation of the control circuit to obtain the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: continuously analyzing the sampling signal; determining that the first target signal in the first signal is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point based on the first sampling result in response to the detection of the first target signal; determining that the second target signal in the first signal is detected in response to the sampling signal meeting the preset condition again; and obtaining the second position information corresponding to the second transition point based on the second sampling result in response to the detection of the second target signal.

[0011] In an exemplary embodiment of the present invention, the control circuit is further configured to: control the clock generating circuit to adjust the frequency of the clock signal according to the frequency offset state.

[0012] In an exemplary embodiment of the present invention, the clock control circuit module is disposed in a memory storage device, and the first target signal and the second target signal are received from the host system during the handover phase between the memory storage device and the host system.

[0013] In an exemplary embodiment of the present invention, the control circuit includes a phase detector, a frequency detector, and a low-pass filter. The low-pass filter is connected to the phase detector, the frequency detector, and the clock generation circuit. The phase detector is used to detect the phase offset state between the first signal and the clock signal. The frequency detector is used to detect the frequency offset state between the first signal and the clock signal. The low-pass filter is used to control the clock generation circuit to adjust the frequency of the clock signal based on the detection results of at least one of the phase detector and the frequency detector.

[0014] In an exemplary embodiment of the present invention, the frequency detector includes a delay line circuit, a target signal detector, a window mapper, an event memory, and a decision circuit. The target signal detector is connected to the delay line circuit. The window mapper is connected to both the delay line circuit and the target signal detector. The event memory is connected to the window mapper. The decision circuit is connected to the event memory. The delay line circuit is used to receive the sampled signal. The target signal detector is used to detect a first target signal and a second target signal in the first signal based on the sampled signal. The window mapper is used to obtain first position information in response to the first target signal and second position information in response to the second target signal. The event memory is used to store the first position information and the second position information. The decision circuit is used to generate a control signal based on the first position information and the second position information to control the low-pass filter to adjust the frequency of the clock signal.

[0015] An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, a memory control circuit unit, and a clock control circuit module. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The clock control circuit module is disposed in the connection interface unit. The clock control circuit module is used to: generate a clock signal; receive a first signal and the clock signal, and sample the first signal according to the clock signal to generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, the first sampling signal reflecting a first sampling result of the clock signal on a first target signal in the first signal, and the second sampling signal reflecting a second sampling result of the clock signal on a second target signal in the first signal; obtain, according to the first sampling signal and the second sampling signal, first position information corresponding to a first transition point of the first target signal and second position information corresponding to a second transition point of the second target signal, respectively; and evaluate the frequency offset state between the first signal and the clock signal according to the first position information and the second position information.

[0016] In an exemplary embodiment of the present invention, the first position information includes a first count value, the second position information includes a second count value, and the operation of the clock control circuit module to evaluate the frequency offset state between the first signal and the clock signal based on the first position information and the second position information includes: evaluating the frequency offset state between the first signal and the clock signal based on the difference between the first count value and the second count value.

[0017] In an exemplary embodiment of the present invention, the operation of the clock control circuit module to obtain the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: continuously analyzing the sampling signal; determining that the first target signal in the first signal is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point based on the first sampling result in response to the detection of the first target signal; determining that the second target signal in the first signal is detected in response to the sampling signal meeting the preset condition again; and obtaining the second position information corresponding to the second transition point based on the second sampling result in response to the detection of the second target signal.

[0018] In an exemplary embodiment of the present invention, the clock control circuit module is further configured to: adjust the frequency of the clock signal according to the frequency offset state.

[0019] An exemplary embodiment of the present invention further provides a clock control method, comprising: generating a clock signal; receiving a first signal and the clock signal and sampling the first signal according to the clock signal to generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, the first sampling signal reflecting a first sampling result of the clock signal on a first target signal in the first signal, and the second sampling signal reflecting a second sampling result of the clock signal on a second target signal in the first signal; obtaining first position information corresponding to a first transition point of the first target signal and second position information corresponding to a second transition point of the second target signal according to the first sampling signal and the second sampling signal, respectively; and evaluating the frequency offset state between the first signal and the clock signal according to the first position information and the second position information.

[0020] In an exemplary embodiment of the present invention, the first position information includes a first count value, the second position information includes a second count value, and the step of evaluating the frequency offset state between the first signal and the clock signal based on the first position information and the second position information includes: evaluating the frequency offset state between the first signal and the clock signal based on the difference between the first count value and the second count value.

[0021] In an exemplary embodiment of the present invention, the step of obtaining the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: continuously analyzing the sampling signal; determining that the first target signal in the first signal is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point based on the first sampling result in response to the detection of the first target signal; determining that the second target signal in the first signal is detected in response to the sampling signal meeting the preset condition again; and obtaining the second position information corresponding to the second transition point based on the second sampling result in response to the detection of the second target signal.

[0022] In one exemplary embodiment of the present invention, the clock control method further includes: adjusting the frequency of the clock signal according to the frequency offset state.

[0023] In an exemplary embodiment of the present invention, the clock control method further includes: detecting a phase offset state between the first signal and the clock signal by a phase detector; detecting a frequency offset state between the first signal and the clock signal by a frequency detector; and adjusting the frequency of the clock signal based on the detection results of at least one of the phase detector and the frequency detector.

[0024] In an exemplary embodiment of the present invention, the step of detecting the frequency offset state between the first signal and the clock signal by the frequency detector includes: receiving the sampled signal; detecting the first target signal and the second target signal in the first signal based on the sampled signal; obtaining the first position information in response to the first target signal and obtaining the second position information in response to the second target signal; storing the first position information and the second position information; and generating a control signal based on the first position information and the second position information to adjust the frequency of the clock signal.

[0025] Based on the above, after receiving the first signal, the clock signal can be used to sample the first signal to generate a first sampled signal and a second sampled signal. Specifically, the first sampled signal reflects the first sampling result of the clock signal on a first target signal within the first signal, and the second sampled signal reflects the second sampling result of the clock signal on a second target signal within the first signal. Then, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal can be obtained respectively based on the first sampled signal and the second sampled signal. Furthermore, the frequency offset state between the first signal and the clock signal can be evaluated based on the first position information and the second position information. This improves the signal reception quality at the signal receiver. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, sampling a first signal using multiple sampling windows based on a clock signal to generate a first sampled signal and a second sampled signal.

[0028] Figure 3 This is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a frequency detector according to an exemplary embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0031] Figure 6 This is a flowchart illustrating a clock control method according to an exemplary embodiment of the present invention. Detailed Implementation

[0032] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0033] The present invention is illustrated below with several exemplary embodiments; however, the invention is not limited to these exemplary embodiments. Suitable combinations are also permitted between the exemplary embodiments. The term "connection" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device connected to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

[0034] Figure 1 This is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention.

[0035] Please refer to Figure 1 The clock control circuit module 10 includes a clock generation circuit 11, a sampling circuit 12, and a control circuit 13. The clock generation circuit 11 generates a signal (also called a clock signal) CLK. For example, the signal CLK can be generated by a voltage-controlled oscillator (VCO) or other type of oscillation circuit in the clock generation circuit 11. The signal CLK can have a specific frequency.

[0036] Clock generation circuit 11 is connected to sampling circuit 12. Sampling circuit 12 can be used to receive signal (also referred to as first signal) S(1) and signal CLK. For example, signal S(1) is provided by an external device, while signal CLK is provided by clock generation circuit 11. In addition, signal S(1) also has a specific frequency. The frequency of signal S(1) may be different from the frequency of signal CLK. For example, the frequency of signal CLK may be higher than the frequency of signal S(1).

[0037] The sampling circuit 12 can also be used to sample the signal S(1) according to the signal CLK and generate a sampling signal. For example, the sampling circuit 12 can use the rising edge and / or falling edge of the signal CLK to sample the signal S(1) sequentially to generate a sampling signal.

[0038] It should be noted that this sampling signal includes signal SP(1) (also known as the first sampling signal) and signal SP(2) (also known as the second sampling signal). Signal SP(1) reflects the sampling result of signal CLK on a specific signal (also known as the first target signal) in signal S(1) (also known as the first sampling result). Signal SP(2) reflects the sampling result of signal CLK on another signal (also known as the second target signal) in signal S(1) (also known as the second sampling result). For example, sampling circuit 12 can use the rising edge and / or falling edge of signal CLK to sample the first target signal and the second target signal in signal S(1) sequentially to generate signals SP(1) and SP(2).

[0039] Control circuit 13 is connected to clock generation circuit 11 and sampling circuit 12. Control circuit 13 can be used to receive the sampled signals (including signals SP(1) and SP(2)). Control circuit 13 can obtain the position information (also called first position information) corresponding to the transition point (also called the first transition point) of the first target signal and the position information (also called the second position information) corresponding to the transition point (also called the second transition point) of the second target signal based on the sampled signals (including signals SP(1) and SP(2)). Then, control circuit 13 can evaluate the frequency offset state between signal S(1) and signal CLK based on the first position information and the second position information. For example, this frequency offset state is related to the frequency difference between signal S(1) and signal CLK. Or, from another perspective, this frequency offset state can reflect or correspond to the frequency difference between signal S(1) and signal CLK.

[0040] In one exemplary embodiment, the sampling circuit 12 can sample the signal S(1) (containing the first target signal and the second target signal) based on multiple sampling windows of the signal CLK and sequentially generate signals SP(1) and SP(2). Therefore, the first position information can reflect that a transition point of the first target signal (i.e., the first transition point) is located at a specific position (also called the first position) in a certain sampling window (also called the first sampling window) of the signal CLK. In addition, the second position information can reflect that a transition point of the second target signal (i.e., the second transition point) is located at a specific position (also called the second position) in another sampling window (also called the second sampling window) of the signal CLK. The time length of the first sampling window is the same as the time length of the second sampling window.

[0041] In one exemplary embodiment, the first position information includes a count value (also referred to as the first count value), and the second position information includes another count value (also referred to as the second count value). The first count value corresponds to a first position. The second count value corresponds to a second position. The control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK based on the difference between the first count value and the second count value. For example, the control circuit 13 can subtract the second count value from the first count value or subtract the first count value from the second count value to obtain the difference between the first count value and the second count value. Then, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK based on this difference. For example, this difference can be positively correlated with the frequency difference between the signal S(1) and the signal CLK. For example, the larger this difference is, the larger the frequency difference between the signal S(1) and the signal CLK is.

[0042] In one exemplary embodiment, the control circuit 13 continuously analyzes the sampled signal generated by the sampling circuit 12. For example, the control circuit 13 can determine whether the sampled signal meets a preset condition. In response to the sampled signal meeting the preset condition, the control circuit 13 can determine that a first target signal in the signal S(1) has been detected. In response to the detection of the first target signal, the control circuit 13 can obtain first position information (e.g., a first count value) corresponding to the transition point (i.e., the first transition point) of the first target signal based on the first sampling result. Then, the control circuit 13 continuously analyzes the sampled signal generated by the sampling circuit 12. In response to the sampled signal meeting the preset condition again, the control circuit 13 can determine that a second target signal in the signal S(1) has been detected. In response to the detection of the second target signal, the control circuit 13 can obtain second position information (e.g., a second count value) corresponding to the transition point (i.e., the second transition point) of the second target signal based on the second sampling result. Then, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK based on the first count value and the second count value.

[0043] In one exemplary embodiment, the control circuit 13 can determine whether there are consecutive bits "1" (or "0") in the sampling result corresponding to the sampling signal. In response to the presence of consecutive bits "1" (or "0") in the sampling result, the control circuit 13 can determine that the sampling signal meets a preset condition. However, if there are no consecutive bits "1" (or "0") in the sampling result, the control circuit 13 can determine that the sampling signal does not meet the preset condition.

[0044] In one exemplary embodiment, the consecutive plurality of bits "1" (or "0") can refer to a set number or more of consecutive bits "1" (or "0"). For example, the set number can be 16, 32, or other numbers, and the present invention is not limited thereto. Furthermore, the consecutive plurality of bits "1" (or "0") can be located in a single sampling window of the signal CLK or span multiple sampling windows of the signal CLK.

[0045] In one exemplary embodiment, the control circuit 13 can control the clock generation circuit 11 to adjust the frequency of the signal CLK based on the frequency offset state between the signal S(1) and the signal CLK. For example, based on the frequency offset state, the control circuit 13 can generate a signal (also called an adjustment signal) ADJ. The control circuit 13 can use the signal ADJ to control the clock generation circuit 11 to adjust (e.g., increase or decrease) the frequency of the signal CLK. For example, assuming that the frequency offset state reflects that the frequency of the signal S(1) is higher than the frequency of the signal CLK, the control circuit 13 can use the signal ADJ to increase the frequency of the signal CLK to reduce the frequency difference between the signal CLK and the signal S(1). Alternatively, assuming that the frequency offset state reflects that the frequency of the signal S(1) is lower than the frequency of the signal CLK, the control circuit 13 can use the signal ADJ to decrease the frequency of the signal CLK to reduce the frequency difference between the signal CLK and the signal S(1). Thus, the frequency of the adjusted signal CLK can be closer to the frequency of the signal S(1), or even exactly the same as the frequency of the signal S(1). Compared to the unadjusted signal CLK, using the adjusted signal CLK to sample the data signal in signal S(1) can effectively improve the sampling quality (e.g., sampling accuracy) of this data signal.

[0046] Figure 2 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, the sampling of a first signal by multiple sampling windows based on a clock signal to generate a first sampled signal and a second sampled signal.

[0047] Please refer to Figure 1 and Figure 2 Assume the first target signal includes signal ST(1) and the second target signal includes signal ST(2). Signal ST(1) and signal ST(2) may be included in signal S(1) within different time ranges. Signal ST(1) and signal ST(2) have the same frequency and / or waveform. For example, in signal S(1), the frequencies of signals ST(1) and ST(2) may be lower than the frequencies of the other signals, such as... Figure 2As shown. In addition, the frequencies of signals ST(1) and ST(2) can be lower than the frequency of signal CLK. In another exemplary embodiment, signals ST(1) and ST(2) can be a set of fixed-pattern signals, for example, signals ST(1) and ST(2) can be used to transmit 16 or other numbers of consecutive 0 / 1 sequences respectively.

[0048] The sampling circuit 12 can sample the signal S(1) based on multiple consecutive sampling windows TW corresponding to the signal CLK. For example, in a certain sampling window TW, the signal CLK can be used to continuously sample the signal S(1) k times to obtain k sample values. k can be any integer greater than 1. These k sample values ​​can reflect the sampling results of continuously sampling the signal S(1) k times using the signal CLK in the sampling window TW.

[0049] In one exemplary embodiment, signal SP(1) may reflect or present the sampling result of signal CLK on signal ST(1) in sampling window TW(1) (i.e., the first sampling window) (i.e., the first sampling result). For example, signal SP(1) may reflect or present the sampling result of signal CLK on signal ST(1) in sampling window TW(1) containing n(1) consecutive bits "1" and m(1) consecutive bits "0". In response to n(1) and / or m(1) being greater than a preset value (i.e., the sampled signal meets the preset condition), control circuit 13 may determine that the first target signal has been detected. In response to the detection of the first target signal, control circuit 13 may determine a count value (i.e., the first count value) based on n(1) and / or m(1). For example, the first count value may be equal to n(1) or m(1). In particular, in the sampling window TW(1), the boundary position of these n(1) consecutive bits "1" and m(1) consecutive bits "0" reflects the position of the transition point TP(1) (i.e., the first transition point) of the signal ST(1) (i.e., the first position). Alternatively, from another perspective, the first count value can reflect the position of the transition point TP(1) of the signal ST(1) in the sampling window TW(1).

[0050] In one exemplary embodiment, signal SP(2) may reflect or present the sampling result of signal CLK on signal ST(2) in sampling window TW(2) (i.e., the second sampling window) (i.e., the second sampling result). For example, signal SP(2) may reflect or present the sampling result of signal CLK on signal ST(2) in sampling window TW(2) containing n(2) consecutive bits "1" and m(2) consecutive bits "0". In response to n(2) and / or m(2) being greater than a preset value (i.e., the sampled signal again meets the preset condition), control circuit 13 may determine that a second target signal has been detected. In response to the detection of the second target signal, control circuit 13 may determine a count value (i.e., the second count value) based on n(2) and / or m(2). For example, the second count value may be equal to n(2) or m(2). In particular, the boundary position of these n(2) consecutive bits "1" and m(2) consecutive bits "0" in the sampling window TW(2) reflects the position of the transition point TP(2) (i.e., the second transition point) of the signal ST(2) (i.e., the second position). Alternatively, from another perspective, the second count value can reflect the position of the transition point TP(2) of the signal ST(2) in the sampling window TW(2).

[0051] In one exemplary embodiment, the difference between n(1) and n(2) (i.e., the difference between the first count value and the second count value) is positively correlated with the frequency difference between signal S(1) and signal CLK. For example, the larger the difference between n(1) and n(2), the larger the frequency difference between signal S(1) and signal CLK. Therefore, control circuit 13 can evaluate the frequency offset state between signal S(1) and signal CLK based on the difference between n(1) and n(2). Then, control circuit 13 can adjust the frequency of signal CLK based on this frequency offset state. For example, assuming n(1) is 4 and n(2) is 8, it means that the frequency of signal CLK is higher than the frequency of signal S(1). Therefore, control circuit 13 can instruct clock generation circuit 11 to slightly reduce the frequency of signal CLK. Alternatively, assuming n(1) is 28 and n(2) is 6, it means that the frequency of signal CLK is lower than the frequency of signal S(1). Therefore, control circuit 13 can instruct clock generation circuit 11 to slightly increase the frequency of signal CLK. Furthermore, the adjustment range of the frequency of signal CLK can also be positively correlated with the difference between n(1) and n(2) (i.e. the difference between the first count value and the second count value).

[0052] In one exemplary embodiment, the difference between m(1) and m(2) (i.e., the difference between the first count value and the second count value) is also positively correlated with the frequency difference between signal S(1) and signal CLK. For example, the larger the difference between m(1) and m(2), the larger the frequency difference between signal S(1) and signal CLK. Therefore, the control circuit 13 can also evaluate the frequency offset state between signal S(1) and signal CLK based on the difference between m(1) and m(2). Subsequently, the control circuit 13 can adjust the frequency of signal CLK based on this frequency offset state.

[0053] Figure 3 This is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 3 The clock control circuit module 30 includes a clock generation circuit 31, an analog-to-digital converter (ADC) 32, a control circuit 33, and an equalizer 34. The clock generation circuit 31 may include... Figure 1 Clock generation circuit 11. For example, clock generation circuit 31 can be used to generate signal CLK.

[0055] The analog-to-digital converter 32 is connected to the clock generation circuit 31. The analog-to-digital converter 32 may include... Figure 1 The sampling circuit 12. For example, the analog-to-digital converter 32 can sample the signal S(1) according to the signal CLK and generate the signal S(2). The signal S(2) can reflect the sampling result of the signal CLK on the signal S(1). For example, the signal S(2) can include Figure 1 and / or Figure 2 Signal SP(1) (i.e., the first target signal) and signal SP(2) (i.e., the second target signal).

[0056] The control circuit 33 is connected to the analog-to-digital converter 32 and the clock generation circuit 31. The control circuit 33 may include... Figure 1 The control circuit 13. The control circuit 33 can obtain the position information (i.e., first position information) corresponding to the transition point (i.e., the first transition point) of the first target signal and the position information (i.e., second position information) corresponding to the transition point (i.e., the second transition point) of the second target signal according to the signal S(2). Then, the control circuit 33 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the first position information and the second position information. Then, the control circuit 33 can send the signal ADJ according to this frequency offset state to instruct the clock generation circuit 31 to adjust the frequency of the signal CLK.

[0057] In one exemplary embodiment, the control circuit 33 includes a frequency detector 331, a low-pass filter 332, and a phase detector 333. The frequency detector 331 is connected to the analog-to-digital converter 32. The frequency detector 331 can receive a signal S(2) and detect the frequency offset state between the signal S(1) and the signal CLK based on the signal S(2). For example, the frequency detector 331 may refer to... Figure 1 and Figure 2 The example implementation described above is used to detect the frequency offset state between signal S(1) and signal CLK, and will not be repeated here.

[0058] A low-pass filter 332 is connected to a frequency detector 331 and a phase detector 333. The low-pass filter 332 can generate a signal ADJ based on the detection result of the frequency detector 331 to adjust the frequency of the signal CLK.

[0059] Phase detector 333 is connected to analog-to-digital converter 32 and low-pass filter 332. Phase detector 333 can receive signal S(2) and detect the phase offset state between signal S(1) and signal CLK based on signal S(2). This phase offset state can reflect or correspond to the phase difference between signal S(1) and signal CLK. For example, phase detector 333 can evaluate whether the phase of signal S(1) leads or lags the phase of signal CLK based on the continuous sampling results of signal S(1) by signal CLK reflected by signal S(2). Phase detector 333 can include any conventional phase detector, which will not be described in detail here. Then, low-pass filter 332 can generate signal ADJ based on the detection result of phase detector 333 to adjust the phase or frequency of signal CLK.

[0060] In one exemplary embodiment, when initially correcting the frequency and / or phase of signal CLK, control circuit 33 may first activate frequency detector 331 to adjust the frequency of signal CLK. For example, activating frequency detector 331 may include turning on the signal path from frequency detector 331 to low-pass filter 332 and / or cutting off the signal path from phase detector 333 to low-pass filter 332. After activating frequency detector 331, control circuit 33 can detect the frequency offset state between signal S(1) and signal CLK through frequency detector 331 and control clock generation circuit 31 to adjust the frequency of signal CLK based on this frequency offset state. Thus, when initially correcting the frequency and / or phase of signal CLK, control circuit 33 may preferentially reduce the frequency difference between signal S(1) and signal CLK.

[0061] After completing the frequency adjustment of signal CLK (e.g., the frequency difference between signal S(1) and signal CLK is less than a preset value), control circuit 33 can activate phase detector 333 to adjust the phase of signal CLK. For example, activating phase detector 333 may include turning on the signal path from phase detector 333 to low-pass filter 332 and / or cutting off the signal path from frequency detector 331 to low-pass filter 332. After activating phase detector 333, control circuit 33 can detect the phase offset state between signal S(1) and signal CLK through phase detector 333 and control clock generation circuit 31 to adjust the phase of signal CLK according to this phase offset state. Thus, after the initial frequency correction of signal CLK has been completed, control circuit 33 can further reduce the phase difference between signal S(1) and signal CLK.

[0062] Equalizer 34 is connected to analog-to-digital converter 32. Equalizer 34 can be used to compensate the output of analog-to-digital converter 32 (i.e., signal S(2)). For example, equalizer 34 may include a feed-forward equalization (FFE) equalizer and / or other types of equalizers.

[0063] In one exemplary embodiment, by sequentially adjusting the frequency and phase of the signal CLK, the problem that the phase detector 333 might not operate properly due to excessive phase or frequency difference between the signal S(1) and the signal CLK can be effectively improved. Furthermore, during the operation of the frequency detector 331, it is not necessary to introduce an additional reference clock signal or use a multi-phase signal CLK to sample the signal S(1), thereby effectively improving the versatility of the frequency detector 331.

[0064] Figure 4 This is a schematic diagram of a frequency detector according to an exemplary embodiment of the present invention.

[0065] Please refer to Figure 3 and Figure 4 In one exemplary embodiment, the frequency detector 331 includes a delay line circuit 41, a target signal detector 42, a window mapper 43, an event memory 44, and a decision circuit 45. The delay line circuit 41 can receive a signal S(2) and provide the delayed signal S(2) to the target signal detector 42. The target signal detector 42 can analyze the delayed signal S(2) to detect the presence of a first target signal and / or a second target signal in the signal S(1). Figure 2 For example, the target signal detector 42 can detect signals ST(1) and ST(2) respectively based on signals SP(1) and SP(2) that meet preset conditions.

[0066] In one exemplary embodiment, in response to the presence of a first target signal in signal S(1), target signal detector 42 may notify window mapper 43 to obtain the position information (i.e., first position information) corresponding to the transition point (i.e., the first transition point) of the first target signal. For example, in response to the first notification from target signal detector 42, window mapper 43 may store a first count value (i.e., first position information) in event memory 44. Later, in response to target signal detector 42 determining that a second target signal exists in signal S(1), target signal detector 42 may again notify window mapper 43 to obtain the position information (i.e., second position information) corresponding to the transition point (i.e., the second transition point) of the second target signal. For example, in response to the second notification from target signal detector 42, window mapper 43 may store a second count value (i.e., second position information) in event memory 44.

[0067] In one exemplary embodiment, after storing a first count value (i.e., first position information) and a second count value (i.e., second position information) in the event memory 44, the decision circuit 45 can generate a signal (also called a control signal) CT based on the difference between the first count value (i.e., first position information) and the second count value (i.e., second position information) in the event memory 44. The signal CT can be used to control... Figure 3 The low-pass filter 332 generates a corresponding signal ADJ to adjust the frequency of the signal CLK. Furthermore, all other related operational details have been described in the foregoing exemplary embodiments and will not be repeated here.

[0068] It should be noted that, Figure 1 , Figure 3 and Figure 4 The internal structures of the clock control circuit module and frequency detector shown in the exemplary embodiments are merely examples and not intended to limit the invention. That is, the connections between the various electronic circuits in the aforementioned clock control circuit module and frequency detector can be adjusted according to practical needs. Furthermore, the aforementioned clock control circuit module and frequency detector may also include other types of electronic circuits to provide additional functionality, and this invention is not limited thereto.

[0069] In one exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may be disposed in a memory storage device. Alternatively, in one exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may also be disposed in any type of electronic device, and the present invention is not limited thereto.

[0070] Figure 5 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0071] Please refer to Figure 5The memory storage device 50 includes a connection interface unit 501, a memory control circuit unit 502, and a rewritable non-volatile memory module 503. The aforementioned clock control circuit module 10 or 30 may be disposed in the memory storage device 50.

[0072] The connection interface unit 501 is used to connect the memory storage device 50 to the host system 51. The memory storage device 50 can communicate with the host system 51 through the connection interface unit 501. In an exemplary embodiment, the connection interface unit 501 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 501 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 501 may be packaged in a chip with the memory control circuit unit 502, or the connection interface unit 501 may be disposed outside a chip containing the memory control circuit unit 502.

[0073] The memory control circuit unit 502 is connected to the connection interface unit 501 and the rewritable non-volatile memory module 503. The memory control circuit unit 502 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 503 according to the instructions of the host system.

[0074] The rewritable non-volatile memory module 503 is used to store data written by the host system 51. The rewritable non-volatile memory module 503 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0075] Each memory cell in the rewritable non-volatile memory module 503 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 503 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0076] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 503 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0077] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0078] In one exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may be disposed in the connection interface unit 501. Therefore, the first signal (i.e. Figure 1 or Figure 3 The signal S(1)) may include a signal from the host system 51. Alternatively, in an exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may also be disposed in the memory control circuit unit 502 and / or the rewritable non-volatile memory module 503.

[0079] In one exemplary embodiment, the first signal (i.e. Figure 1 or Figure 3The first target signal and the second target signal in signal S(1)) are received from the host system 51 during the handshake phase between the memory storage device 50 and the host system 51. For example, when the connection between the memory storage device 50 and the host system 51 has just been established or when the connection between the memory storage device 50 and the host system 51 is unstable, the memory storage device 50 may enter the handshake phase with the host system 51. During this handshake phase, the memory storage device 50 may perform handshake operations with the host system 51 to perform interactive behaviors such as clock correction and / or voltage correction with the host system 51.

[0080] In one exemplary embodiment, the first target signal and the second target signal are used to transmit identification information regarding the communication standard between the memory storage device 50 and the host system 51 during this handshake phase, such as EIEOSQ information in the PCI Express standard. Furthermore, the first target signal and the second target signal may also include other signals with similar properties (i.e., having the same signal pattern and being repeatedly transmitted in the first signal according to specific rules), which is not a limitation of the present invention.

[0081] In one exemplary embodiment, after leaving the handshake phase, the first signal (i.e. Figure 1 or Figure 3 The signal S(1) may carry a data signal from the host system 51. For example, this data signal may carry data bits that the host system 51 intends to store in the memory storage device 50. In an exemplary embodiment, by... Figure 1 or Figure 3 Adjusting the CLK signal can improve the sampling quality of this data signal in subsequent iterations.

[0082] Figure 6 This is a flowchart illustrating a clock control method according to an exemplary embodiment of the present invention.

[0083] Please refer to Figure 6 In step S601, a clock signal is generated. In step S602, the first signal is sampled according to the clock signal to generate a first sampled signal and a second sampled signal. In step S603, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal are obtained according to the first sampled signal and the second sampled signal, respectively. In step S604, the frequency offset state between the first signal and the clock signal is evaluated according to the first position information and the second position information.

[0084] However, Figure 6 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 6 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 6 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0085] In summary, the clock control circuit module, memory storage device, and clock control method provided in this embodiment of the invention can effectively evaluate (and reduce) the frequency difference between the first signal and the clock signal without introducing an additional reference clock signal or using a multi-phase clock signal to sample the first signal. Therefore, the signal reception quality at the signal receiver can be effectively improved.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock control circuit module, characterized in that, include: Clock generation circuit, used to generate clock signals; A sampling circuit is configured to sample a first signal according to the clock signal and generate a sampled signal, wherein the sampled signal includes a first sampled signal and a second sampled signal, the first sampled signal reflecting a first sampling result of the clock signal on a first target signal in the first signal, and the second sampled signal reflecting a second sampling result of the clock signal on a second target signal in the first signal; and The control circuit is connected to the clock generation circuit and the sampling circuit. The control circuit mentioned above is used to: Based on the first sampling signal and the second sampling signal, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal are obtained respectively. as well as The frequency offset between the first signal and the clock signal is evaluated based on the first location information and the second location information.

2. The clock control circuit module according to claim 1, wherein the first position information reflects the first transition point being located at a first position in the first sampling window of the clock signal, and the second position information reflects the second transition point being located at a second position in the second sampling window of the clock signal.

3. The clock control circuit module according to claim 2, wherein the time length of the first sampling window is the same as the time length of the second sampling window.

4. The clock control circuit module according to claim 1, wherein the first position information includes a first count value, the second position information includes a second count value, and the operation of the control circuit to evaluate the frequency offset state between the first signal and the clock signal based on the first position information and the second position information includes: The frequency offset state between the first signal and the clock signal is evaluated based on the difference between the first count value and the second count value.

5. The clock control circuit module according to claim 4, wherein the difference is positively correlated with the frequency difference between the first signal and the clock signal.

6. The clock control circuit module according to claim 1, wherein the operation of the control circuit to obtain the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: Continuously analyze the sampled signal; In response to the sampling signal meeting a preset condition, it is determined that the first target signal in the first signal has been detected; In response to detecting the first target signal, the first position information corresponding to the first transition point is obtained based on the first sampling result; In response to the sampling signal meeting the preset condition again, it is determined that the second target signal in the first signal has been detected; as well as In response to the detection of the second target signal, the second position information corresponding to the second transition point is obtained based on the second sampling result.

7. The clock control circuit module according to claim 1, wherein the control circuit is further configured to: The clock generation circuit is controlled to adjust the frequency of the clock signal according to the frequency offset state.

8. The clock control circuit module according to claim 1, wherein the clock control circuit module is disposed in a memory storage device, and the first target signal and the second target signal are received from the host system during the handover phase between the memory storage device and the host system.

9. The clock control circuit module according to claim 1, wherein the control circuit comprises: Phase detector; Frequency detector; as well as A low-pass filter is connected to the phase detector, the frequency detector, and the clock generation circuit. The phase detector is used to detect the phase offset between the first signal and the clock signal. The frequency detector is used to detect the frequency offset state between the first signal and the clock signal, and The low-pass filter is used to control the clock generation circuit to adjust the frequency of the clock signal based on the detection result of at least one of the phase detector and the frequency detector.

10. The clock control circuit module according to claim 9, wherein the frequency detector comprises: Delay line circuit; The target signal detector is connected to the delay line circuit; A window mapper is connected to the delay line circuit and the target signal detector; An event storage device is connected to the window mapper; as well as The decision circuit is connected to the event memory. The delay line circuit is used to receive the sampled signal. The target signal detector is used to detect the first target signal and the second target signal in the first signal based on the sampled signal. The window mapper is used to obtain the first location information in response to the first target signal and to obtain the second location information in response to the second target signal. The event memory is used to store the first location information and the second location information, and The decision circuit is used to generate a control signal based on the first position information and the second position information to control the low-pass filter to adjust the frequency of the clock signal.

11. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; Rewritable non-volatile memory module; A memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module; as well as The clock control circuit module is located in the connection interface unit. The clock control circuit module is used to: Generate clock signal; The system receives a first signal and a clock signal, and samples the first signal according to the clock signal to generate a sampled signal, wherein the sampled signal includes a first sampled signal and a second sampled signal, the first sampled signal reflecting a first sampling result of the clock signal on a first target signal in the first signal, and the second sampled signal reflecting a second sampling result of the clock signal on a second target signal in the first signal; Based on the first sampling signal and the second sampling signal, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal are obtained respectively. as well as The frequency offset between the first signal and the clock signal is evaluated based on the first location information and the second location information.

12. The memory storage device of claim 11, wherein the first location information reflects the first transition point being located at a first position in a first sampling window of the clock signal, and the second location information reflects the second transition point being located at a second position in a second sampling window of the clock signal.

13. The memory storage device of claim 12, wherein the time length of the first sampling window is the same as the time length of the second sampling window.

14. The memory storage device of claim 11, wherein the first location information includes a first count value, the second location information includes a second count value, and the operation of the clock control circuit module to evaluate the frequency offset state between the first signal and the clock signal based on the first location information and the second location information includes: The frequency offset state between the first signal and the clock signal is evaluated based on the difference between the first count value and the second count value.

15. The memory storage device of claim 14, wherein the difference is positively correlated with the frequency difference between the first signal and the clock signal.

16. The memory storage device according to claim 11, wherein the operation of the clock control circuit module to obtain the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: Continuously analyze the sampled signal; In response to the sampling signal meeting a preset condition, it is determined that the first target signal in the first signal has been detected; In response to detecting the first target signal, the first position information corresponding to the first transition point is obtained based on the first sampling result; In response to the sampling signal meeting the preset condition again, it is determined that the second target signal in the first signal has been detected; as well as In response to the detection of the second target signal, the second position information corresponding to the second transition point is obtained based on the second sampling result.

17. The memory storage device according to claim 11, wherein the clock control circuit module is further configured to: The frequency of the clock signal is adjusted according to the frequency offset state.

18. The memory storage device of claim 11, wherein the first target signal and the second target signal are received from the host system during the handover phase between the memory storage device and the host system.

19. The memory storage device of claim 11, wherein the clock control circuit module comprises: Phase detector; Frequency detector; as well as A low-pass filter is connected to the phase detector and the frequency detector. The phase detector is used to detect the phase offset between the first signal and the clock signal. The frequency detector is used to detect the frequency offset state between the first signal and the clock signal, and The low-pass filter is used to adjust the frequency of the clock signal based on the detection result of at least one of the phase detector and the frequency detector.

20. The memory storage device of claim 19, wherein the frequency detector comprises: Delay line circuit; The target signal detector is connected to the delay line circuit; A window mapper is connected to the delay line circuit and the target signal detector; An event storage device is connected to the window mapper; as well as The decision circuit is connected to the event memory. The delay line circuit is used to receive the first sampled signal and the second sampled signal. The target signal detector is used to detect the first target signal and the second target signal in the first signal based on the sampled signal. The window mapper is used to obtain the first location information in response to the first target signal and to obtain the second location information in response to the second target signal. The event memory is used to store the first location information and the second location information, and The decision circuit is used to generate a control signal based on the first position information and the second position information to control the low-pass filter to adjust the frequency of the clock signal.

21. A clock control method, characterized in that, include: Generate clock signal; The system receives a first signal and a clock signal, and samples the first signal according to the clock signal to generate a sampled signal, wherein the sampled signal includes a first sampled signal and a second sampled signal, the first sampled signal reflecting a first sampling result of the clock signal on a first target signal in the first signal, and the second sampled signal reflecting a second sampling result of the clock signal on a second target signal in the first signal; Based on the first sampling signal and the second sampling signal, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal are obtained respectively. as well as The frequency offset between the first signal and the clock signal is evaluated based on the first location information and the second location information.

22. The clock control method according to claim 21, wherein the first position information reflects the first transition point being located at a first position in a first sampling window of the clock signal, and the second position information reflects the second transition point being located at a second position in a second sampling window of the clock signal.

23. The clock control method according to claim 22, wherein the time length of the first sampling window is the same as the time length of the second sampling window.

24. The clock control method of claim 21, wherein the first position information includes a first count value, the second position information includes a second count value, and the step of evaluating the frequency offset state between the first signal and the clock signal based on the first position information and the second position information includes: The frequency offset state between the first signal and the clock signal is evaluated based on the difference between the first count value and the second count value.

25. The clock control method of claim 24, wherein the difference is positively correlated with the frequency difference between the first signal and the clock signal.

26. The clock control method according to claim 21, wherein the step of obtaining the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal based on the first sampling signal and the second sampling signal respectively includes: Continuously analyze the sampled signal; In response to the sampling signal meeting a preset condition, it is determined that the first target signal in the first signal has been detected; In response to detecting the first target signal, the first position information corresponding to the first transition point is obtained based on the first sampling result; In response to the sampling signal meeting the preset condition again, it is determined that the second target signal in the first signal has been detected; as well as In response to the detection of the second target signal, the second position information corresponding to the second transition point is obtained based on the second sampling result.

27. The clock control method according to claim 21, further comprising: The frequency of the clock signal is adjusted according to the frequency offset state.

28. The clock control method according to claim 21, wherein the first target signal and the second target signal are received from the host system during the handover phase between the memory storage device and the host system.

29. The clock control method according to claim 21, further comprising: The phase offset state between the first signal and the clock signal is detected by a phase detector; The frequency offset state between the first signal and the clock signal is detected by a frequency detector; as well as The frequency of the clock signal is adjusted based on the detection result of at least one of the phase detector and the frequency detector.

30. The clock control method of claim 29, wherein the step of detecting the frequency offset state between the first signal and the clock signal by the frequency detector includes: Receive the sampling signal; The first target signal and the second target signal in the first signal are detected based on the sampling signal; The first location information is obtained in response to the first target signal, and the second location information is obtained in response to the second target signal; Store the first location information and the second location information; as well as A control signal is generated based on the first position information and the second position information to adjust the frequency of the clock signal.

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