Memory device and operating method thereof, memory system and operating method thereof

Abstract

This disclosure provides a memory device and its operation method, as well as a memory system and its operation method. The memory device includes at least one column, each column includes at least one memory chip, and each memory chip includes peripheral circuitry. The peripheral circuitry is configured to: receive a first command, which instructs the setting of an identification number for a memory chip in a selected column of the memory device; receive a second command, which instructs the selection of a memory chip in the selected column; the second command includes a first number, which corresponds to the identification number of at least a portion of the memory chips in the selected column; and determine the selected memory chip based on the identification number of the at least a portion of the memory chips in the selected column corresponding to the first number.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory device and its operation method, and a memory system and its operation method. Background Technology

[0002] Memory, also known as main memory, is the storage space that the Central Processing Unit (CPU) can directly address, and it is made of semiconductor devices. Memory is a major component of a computer. Commonly used programs, such as the Windows operating system, word processing software, and games, are generally installed on external storage such as hard drives. However, they cannot function on their own; they must be loaded into memory to run and truly utilize their functions.

[0003] However, as the requirements for memory modules continue to increase, there are still many problems with the addressing and configuration of the storage chips in memory modules.

[0004] Public content

[0005] In view of the above, embodiments of the present disclosure provide a memory device and its operation method, and a memory system and its operation method.

[0006] According to a first aspect of this disclosure, a memory device is provided, the memory device comprising at least one column, each column comprising at least one memory chip, and each memory chip comprising peripheral circuitry;

[0007] The peripheral circuit is configured as follows:

[0008] Receive a first command, which instructs the setting of an identity document (ID) for the memory chip in the selected column of the memory device;

[0009] Receive a second command, which instructs to select memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0010] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0011] In the above scheme, the first number corresponds to the identification number of all memory chips in the selected column;

[0012] The peripheral circuit is configured as follows:

[0013] Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

[0014] In the above scheme, each of the memory chips has an enable input port and an enable output port. The enable output port of each memory chip is connected to the enable input port of the adjacent memory chip. The peripheral circuit is configured as follows:

[0015] Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that has an identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that has an identification number set; the first voltage is greater than the second voltage.

[0016] In the above scheme, each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is the first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

[0017] In the above scheme, the peripheral circuit is configured as follows:

[0018] After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

[0019] In the above scheme, the peripheral circuit is configured as follows:

[0020] After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

[0021] In the above scheme, at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the peripheral circuit is configured as follows:

[0022] Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

[0023] In the above scheme, the memory device includes a memory module.

[0024] According to a second aspect of this disclosure, a memory system is provided, the memory system including a memory device and a memory controller coupled to the memory device; the memory device includes at least one column, each column including at least one memory chip;

[0025] The memory controller is configured to:

[0026] Send a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device;

[0027] Send a second command, which instructs to select the memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0028] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0029] According to a third aspect of this disclosure, a method of operating a memory device is provided, the method comprising:

[0030] Receive a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device;

[0031] Receive a second command, which instructs to select memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0032] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0033] In the above scheme, the first number corresponds to the identification number of all memory chips in the selected column;

[0034] The step of determining the selected memory chip based on the identification numbers of at least a portion of the memory chips in the selected column corresponding to the first number includes:

[0035] Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

[0036] In the above scheme, each of the memory chips has an enable input port and an enable output port, and the enable output port of each memory chip is connected to the enable input port of the adjacent memory chip. The method further includes:

[0037] Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that has an identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that has an identification number set; the first voltage is greater than the second voltage.

[0038] In the above scheme, each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is the first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

[0039] The method in the above scheme further includes:

[0040] After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

[0041] The method in the above scheme further includes:

[0042] After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

[0043] In the above scheme, the at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the method further includes:

[0044] Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

[0045] According to a fourth aspect of this disclosure, a method of operating a memory system is provided, the method comprising:

[0046] Send a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device;

[0047] Send a second command, which instructs to select the memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0048] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0049] This disclosure provides a memory device and its operation method, a memory system and its operation method. The operation method of the memory device includes: receiving a first command, the first command instructing the setting of identification numbers for memory chips in a selected column of the memory device; receiving a second command, the second command instructing the selection of memory chips in the selected column; the second command includes a first number, the first number corresponding to the identification numbers of at least some of the memory chips in the selected column; and determining the selected memory chips based on the identification numbers of the at least some of the memory chips in the selected column corresponding to the first number. In this disclosure, by first setting the identification numbers for the memory chips in the selected column of the memory device, each memory chip in the selected column has a corresponding identification number. Then, by using the first number included in the second command corresponding to the identification numbers of at least some of the memory chips in the selected column, some or all of the memory chips in the selected column are selected, thereby enabling different configurations to be performed on some or all of the memory chips in the selected column simultaneously. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the framework structure of a memory system provided in an embodiment of this disclosure;

[0051] Figure 2 This is a schematic diagram of the structure of a memory device provided in an embodiment of this disclosure;

[0052] Figure 3 A timing diagram of a memory device in monolithic addressable mode provided for embodiments of this disclosure;

[0053] Figure 4 A schematic flowchart illustrating an operation method of a memory device provided in an embodiment of this disclosure;

[0054] Figure 5a This is a schematic diagram of the connection relationship of a memory chip provided in an embodiment of the present disclosure;

[0055] Figure 5b A timing diagram illustrating the receipt of a first command provided in an embodiment of this disclosure;

[0056] Figure 6 This is a schematic diagram of the state machine change process provided in an embodiment of the present disclosure;

[0057] Figure 7 This is a flowchart illustrating an operation method of a memory device provided in an embodiment of the present disclosure. Detailed Implementation

[0058] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0059] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0060] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0061] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0062] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0063] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0064] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0065] Figure 1 A schematic diagram of the framework structure of an exemplary memory system having a memory device according to some aspects of this disclosure is shown. Figure 1 As shown, a memory system may include one or more memory devices and a memory controller, the memory controller being coupled to and controlling the memory devices. The memory controller can output commands (CMD), addresses (ADD), and clock signals (CLK) to the memory devices via predetermined transmission lines. Here, the memory device includes, but is not limited to, memory modules; the following embodiments use a memory module as an example for illustrative purposes.

[0066] A memory device may include at least one rank. The memory device may be a dual in-line memory module (DIMM) that includes one or two ranks, or it may be a chip packaged with multiple ranks. A rank can be understood as including all memory chips (die) connected to the same chip select line (CS).

[0067] Dual in-line memory (DIM) modules are a new type of memory module. A DIM module is composed of Dynamic Random Access Memory (DRAM) chips used for storing data. A single DIM module can include multiple columns, each column consisting of several memory chips. For a multi-column memory module with a 64-bit data width, if each memory chip has an 8-bit data width, one column can consist of 8 memory chips. Figure 2An exemplary embodiment is shown of a memory device comprising two columns (Rank0-Rank1), each column comprising eight memory chips (Die0-Die7), all memory chips in Rank0 being connected to the same chip select line CS0, and all memory chips in Rank1 being connected to another chip select line CS1.

[0068] It should be noted that, Figure 2 The number of memory chips and columns in the memory device shown are merely exemplary examples, and the number of columns in a memory device is not limited to... Figure 2 The two shown, the number of memory chips in one column is not limited to Figure 2 The eight shown.

[0069] In some specific examples, when selecting memory chips in a memory device, a single memory chip can be selected using the Per DRAM Addressability (PDA) mode, thereby enabling individual configuration of the single memory chip, such as MRS configuration, Write leveling, VrefDQ training, and setting different ODT values ​​to improve signal integrity.

[0070] The PDA mode process includes the following steps: 1. Configure PDA and enable MRS; 2. Configure MRS, Writeleveling, VrefDQ training, and ODT; 3. Determine whether to enter PDA mode through DQ0. If DQ0 is low, execute the current MRS command; 4. Configure MRS and exit PDA.

[0071] Figure 3 This is a timing diagram of a memory device in PDA mode provided for an embodiment of this disclosure. The following is in conjunction with... Figure 3 The process of PDA mode is explained in detail. In some specific examples, PDA mode can be enabled using the MR[x] address bit "A[y] = 1b" (e.g., MR3 bit "A4 = 1b"), which is the allowed MRS command in PDA mode. In PDA mode, all MRS commands are qualified via DQ0. Figure 3 The DQ0 signal can be sampled using the differential signal pair DQS_c / DQS_t. If the value of DQ0 is 0, the current MRS command is executed; if the value of DQ0 is 1, the current MRS command is ignored. In some specific examples, the PDA mode can be exited by setting the MR[x] address bit "A[y] = 0b" (e.g., MR3 bit "A4 = 0b"). Figure 3In the example shown, the mode register set command cycle time in PDA mode is shown as including the additional wait time AL (i.e., internal delay), the column address strobe write wait time CWL, and the mode register set command cycle time tMRD_PDA for PDA, where CWL indicates the number of clock cycles between the registration of the write command and the availability of the first bit of data.

[0072] Although PDA mode allows for single-chip addressing, it still has several drawbacks. Firstly, enabling PDA mode is limited by DQ0, but the DQ setting method differs across different package types. When the DQ0 of memory chips in a Rank is shared, the memory device cannot enter PDA mode via DQ0. Secondly, only MRS commands are allowed in PDA mode; other commands, such as read and write commands, are not permitted. Thirdly, only one memory chip can be selected at a time in PDA mode, preventing the simultaneous configuration of multiple memory chips.

[0073] Therefore, to solve the above problems, embodiments of this disclosure provide an operation method for a memory device, such as... Figure 4 As shown, the operation method of the memory device provided in this embodiment includes the following steps:

[0074] S100: Receive a first command, the first command instructing the setting of an identification number for the memory chip in the selected column of the memory device;

[0075] S200: Receive a second command, the second command instructing to select memory chips in the selected column; the second command includes a first number, the first number corresponding to the identification number of at least some of the memory chips in the selected column;

[0076] S300: Determine the selected memory chip based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0077] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs.

[0078] Here, the first command includes, but is not limited to, the SET ID command, and the second command includes, but is not limited to, the SELECT ID command.

[0079] After receiving the first command, the identification number of the memory chips in the selected column will be set sequentially. The following will explain in detail how to set the identification number of the memory chips in the selected column after receiving the first command.

[0080] In some embodiments, each of the memory chips has an enable input port and an enable output port, and the enable output port of each memory chip is connected to the enable input port of an adjacent memory chip. The method further includes:

[0081] Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that has an identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that has an identification number set; the first voltage is greater than the second voltage.

[0082] Figure 5a This is a schematic diagram of the connection relationship of a memory chip provided in an embodiment of this disclosure; Figure 5b This is a timing diagram illustrating the receipt of a first command, provided as an embodiment of this disclosure. Figure 5a as well as Figure 5b The diagram illustrates, by way of example, the interconnection and timing of three memory chips in a memory device. Figure 5a as well as Figure 5b As shown, memory chips Die0-Die2 are arranged sequentially. Each memory chip has an enable input port ENI and an enable output port ENO. The enable output port of each memory chip is connected to the enable input port of the adjacent memory chip. Since the current memory chip can only be assigned an identification number when the enable input port is high and the enable output port is low, in the initial state, the enable output ports of all memory chips except Die2 can be controlled by the control module LG_ENO_DIE, so that the enable output ports of all memory chips except Die2 receive the second voltage; while the enable input port of Die0 is provided with the first voltage through an external analog circuit. Since the first voltage is greater than the second voltage, upon receiving the first command, the Die0 state machine jumps to SETTED_ID. The signal of the enable output port of Die0, which is also the enable input port of Die1, is pulled high, making the enable input port of Die1 high. At this time, the enable output port of Die1 is low, thus enabling the setting of the identification number of Die1. The Die1 state machine jumps to SETTED_ID, and the signal of the enable output port of Die1, which is also the enable input port of Die2, is pulled high, thereby realizing the sequential setting of the identification number from Die0 to Die2.

[0083] In some embodiments, the at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the method further includes:

[0084] Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

[0085] Here, the first chip select line can be any chip select line in the memory device, and the first chip select line corresponds to the column that needs to be selected.

[0086] It is understandable that multiple memory chips in each column are connected to the same chip select line, and the chip select lines connected to each column are different. For example... Figure 2 As shown, Die0-Die7 in Rank0 all correspond to chip select line CS0, and Die0-Die7 in Rank1 all correspond to chip select line CS1. By selecting one of the chip select lines, a Rank connected to that chip select line can be selected. After selecting a Rank, the memory chips in the selected Rank can be selected.

[0087] Here, the first number corresponds to the identification number of at least some of the memory chips in the selected column, and can include several cases: 1. The first number can correspond to the identification number of one memory chip in the selected column; 2. The first number can correspond to the identification numbers of multiple, but not all, memory chips in the selected column; 3. The first number can correspond to the identification numbers of all memory chips in the selected column. In the first case, it can be determined that a single memory chip in the selected column is selected; in the second case, it can be determined that multiple, but not all, memory chips in the selected column are selected; and in the third case, it can be determined that all memory chips in the selected column are selected.

[0088] It is understood that the solution provided in this disclosure, after setting the identification number of the storage chip, supports selecting one storage chip in the selected column or selecting multiple storage chips in the selected column simultaneously according to specific needs, that is, it can meet different requirements. In addition, since only one storage chip can be selected at a time in PDA mode, if multiple storage chips need to be configured differently, multiple operations of entering and exiting PDA mode are required, making the operation steps more complicated and time-consuming. However, this disclosure supports selecting multiple storage chips at the same time, which can save operation steps and time when configuring multiple storage chips differently.

[0089] In some specific examples, different corresponding contents can be customized for different first numbers, so that different first numbers correspond to different identification numbers, thereby allowing different first numbers to correspond to different storage chips, and thus enabling the selection of the required storage chip according to specific needs.

[0090] The following example uses the identification number of all memory chips in the selected column corresponding to the first number as an example for illustrative purposes.

[0091] In some embodiments, the first number corresponds to the identification number of all memory chips in the selected column;

[0092] The step of determining the selected memory chip based on the identification numbers of at least a portion of the memory chips in the selected column corresponding to the first number includes:

[0093] Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

[0094] When the second command (SELECT ID command) is received, the identification number corresponding to the first number is compared with the identification number of the memory chip itself. When the first number corresponds to the identification number of all memory chips in the selected column, the state machine of all memory chips in the selected column jumps from SETTED_ID to SELECTED_ID, so that all memory chips in the selected column are selected. Since each memory chip has a different identification number, different settings can be adjusted for all memory chips in the selected column simultaneously and separately.

[0095] Figure 6 This is a schematic diagram illustrating the change process of a state machine provided in an embodiment of this disclosure. Figure 6 As shown, for a memory chip whose state machine is in the NOT_SET_ID state, after receiving the first command SET_ID_CMD, an identification number is set for the memory chip whose state machine is in the NOT_SET_ID state. Then, the state machine of the memory chip with the set identification number transitions to SETTED_ID. Next, after receiving the second command SELECTED_ID_CMD, the identification number of the memory chip corresponding to the first number is compared with the memory chip's own identification number. For memory chips whose identification numbers match, their state machine transitions to SELECTED_ID; for memory chips whose identification numbers do not match, their state machine transitions to NOT_SELECTED_ID.

[0096] In some embodiments, each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is a first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

[0097] Taking a memory device with a data width of 64 bits, each Rank consisting of 8 memory chips, and each memory chip having a data width of 8 bits as an example, each memory chip has 8 data port lines (DQ0-DQ7). Here, the data port line corresponding to the least significant bit can be DQ0, and the corresponding DQ7 is the data port line corresponding to the most significant bit.

[0098] It is understandable that the DQ0 settings of multiple memory chips in a Rank differ depending on the packaging method. In some specific examples, the DQ0 of multiple memory chips in a Rank is shared, meaning that the DQ0s of multiple memory chips in a Rank are all connected together; in other specific examples, the DQ0s of multiple memory chips in a Rank are not shared, meaning that the DQ0s of multiple memory chips in a Rank are separate from each other. Because of the limitations imposed by DQ0 in PDA mode, PDA mode can only be enabled if the first data port lines of multiple memory chips in each column are not shared, and cannot be used if the first data port lines of multiple memory chips in each column are shared. However, in this embodiment, the SET ID command and SELECT ID command are used, which eliminates the need to start via DQ0, thus broadening the application scope.

[0099] In some embodiments, the method further includes:

[0100] After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

[0101] Here, the third command includes, but is not limited to, the MRS command and training.

[0102] In some embodiments, the method further includes:

[0103] After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

[0104] In some specific examples, after the selected memory chip is determined, the third and fourth commands can be accepted simultaneously, that is, the MRS command and read / write commands can be accepted at the same time.

[0105] It is understandable that, since only MRS commands are allowed during PDA mode, read and write commands are only allowed after exiting PDA mode. However, the method provided in this disclosure embodiment can accept both MRS commands and read / write commands simultaneously after the memory chip is selected, thus saving operation time.

[0106] It is understood that the solution provided in this disclosure has the following advantages: 1. It supports selecting a single memory chip, thereby enabling individual training or MRS configuration for that single memory chip; 2. It supports selecting all memory chips in the selected column, thereby enabling simultaneous training or MRS configuration for all memory chips; 3. When PDA mode is not supported due to DQ limitations in multi-die packaging, it supports bit width expansion through the SET ID command and SELECT ID command; 4. The SET ID command and SELECT ID command are themselves command types supported by memory modules, requiring no additional pins and thus having low implementation cost.

[0107] This disclosure provides an operation method for a memory device, comprising: receiving a first command, the first command instructing the setting of identification numbers for memory chips in a selected column of the memory device; receiving a second command, the second command instructing the selection of memory chips in the selected column; the second command including a first number, the first number corresponding to the identification numbers of at least some memory chips in the selected column; and determining the selected memory chips based on the identification numbers of the at least some memory chips in the selected column corresponding to the first number. In this disclosure, by first setting identification numbers for the memory chips in the selected column, each memory chip in the selected column possesses a corresponding identification number; and then by using the first number included in the second command corresponding to the identification numbers of at least some memory chips in the selected column, some or all of the memory chips in the selected column are selected, thereby enabling different configurations to be applied to some or all of the memory chips in the selected column simultaneously.

[0108] Based on the above-described method of operating a memory device, this disclosure also provides a method of operating a memory system, such as... Figure 7 As shown, the operation method of the memory system provided in this embodiment includes the following steps:

[0109] S100: Send a first command, the first command instructing the setting of an identification number for the memory chip in the selected column of the memory device;

[0110] S200: Send a second command, the second command instructing to select the memory chips in the selected column; the second command includes a first number, the first number corresponding to the identification number of at least some of the memory chips in the selected column;

[0111] S300: Determine the selected memory chip based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0112] In some embodiments, the first number corresponds to the identification number of all memory chips in the selected column;

[0113] The step of determining the selected memory chip based on the identification numbers of at least a portion of the memory chips in the selected column corresponding to the first number includes:

[0114] Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

[0115] In some embodiments, the method further includes:

[0116] After the selected memory chip is determined, a third command is sent, which instructs the selected memory chip to perform a mode register configuration operation.

[0117] In some embodiments, the method further includes:

[0118] After the selected memory chip is determined, a fourth command is sent, which instructs the selected memory chip to perform a write operation or a read operation.

[0119] In some embodiments, the at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the method further includes:

[0120] Before sending the first command, a fifth command is sent, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

[0121] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory device comprising at least one column, each column comprising at least one memory chip, and each memory chip comprising peripheral circuitry.

[0122] The peripheral circuit is configured as follows:

[0123] Receive a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device;

[0124] Receive a second command, which instructs to select memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0125] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0126] In some embodiments, the first number corresponds to the identification number of all memory chips in the selected column;

[0127] The peripheral circuit is configured as follows:

[0128] Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

[0129] In some embodiments, each of the memory chips has an enable input port and an enable output port, and the enable output port of each memory chip is connected to the enable input port of an adjacent memory chip. The peripheral circuitry is configured as follows:

[0130] Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that has an identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that has an identification number set; the first voltage is greater than the second voltage.

[0131] In some embodiments, each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is a first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

[0132] In some embodiments, the peripheral circuit is configured as follows:

[0133] After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

[0134] In some embodiments, the peripheral circuit is configured as follows:

[0135] After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

[0136] In some embodiments, the at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the peripheral circuit is configured as follows:

[0137] Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

[0138] In some embodiments, the memory device includes a memory module.

[0139] The memory device provided in the above embodiments has been described in detail in the method section, and will not be repeated here.

[0140] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory device includes at least one column, each column including at least one memory chip;

[0141] The memory controller is configured to:

[0142] Send a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device;

[0143] Send a second command, which instructs to select the memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column.

[0144] The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

[0145] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0146] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0147] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, characterized in that, The memory device includes at least one column, each column includes at least one memory chip, each memory chip includes peripheral circuitry; each memory chip has an enable input port and an enable output port, and the enable output port of each memory chip is connected to the enable input port of an adjacent memory chip. The peripheral circuit is configured as follows: Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that needs to have its identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that needs to have its identification number set, so that the identification number of the memory chips in the selected column in the memory device is set after receiving the first command; the first voltage is greater than the second voltage. Receive the first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device; Receive a second command, which instructs to select memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column. The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

2. The memory device according to claim 1, characterized in that, The first number corresponds to the identification number of all memory chips in the selected column; The peripheral circuit is configured as follows: Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

3. The memory device according to claim 1, characterized in that, Each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is the first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

4. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

5. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

6. The memory device according to claim 1, characterized in that, The at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the peripheral circuit is configured as follows: Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

7. The memory device according to claim 1, characterized in that, The memory device includes a memory module.

8. A memory system, characterized in that, The memory system includes a memory device as described in any one of claims 1 to 7 and a memory controller coupled to the memory device; the memory device includes at least one column, each column including at least one memory chip; The memory controller is configured to: Send a first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device; Send a second command, which instructs to select the memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column. The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

9. A method of operating a memory device, characterized in that, The memory device includes at least one column, each column including at least one memory chip; each memory chip has an enable input port and an enable output port, the enable output port of each memory chip being connected to the enable input port of an adjacent memory chip; the method includes: Before receiving the first command, a first voltage is applied to the enable input port of the first memory chip in the selected column that needs to have its identification number set, and a second voltage is applied to the enable output ports of all memory chips in the selected column except the last memory chip that needs to have its identification number set, so that the identification number of the memory chips in the selected column in the memory device is set after receiving the first command; the first voltage is greater than the second voltage. Receive the first command, which instructs the setting of an identification number for the memory chip in the selected column of the memory device; Receive a second command, which instructs to select memory chips in the selected column; the second command includes a first number, which corresponds to the identification number of at least some of the memory chips in the selected column. The selected memory chip is determined based on the identification number of at least some of the memory chips in the selected column corresponding to the first number.

10. The operating method according to claim 9, characterized in that, The first number corresponds to the identification number of all memory chips in the selected column; The step of determining the selected memory chip based on the identification numbers of at least a portion of the memory chips in the selected column corresponding to the first number includes: Based on the identification numbers of all memory chips in the selected column corresponding to the first number, it is determined that all memory chips in the selected column are selected.

11. The operating method according to claim 9, characterized in that, Each of the memory chips includes multiple data port lines, and the data port line corresponding to the least significant bit in each memory chip is the first data port line. The first data port lines of multiple memory chips in each column may be shared or not shared.

12. The operating method according to claim 9, characterized in that, The method further includes: After the selected memory chip is determined, a third command is received, which instructs the selected memory chip to perform a mode register configuration operation.

13. The operating method according to claim 9, characterized in that, The method further includes: After the selected memory chip is determined, a fourth command is received, which instructs the selected memory chip to perform a write operation or a read operation.

14. The operating method according to claim 9, characterized in that, The at least one memory chip in each column corresponds to the same chip select line, and the chip select lines corresponding to each column are different; the method further includes: Before receiving the first command, a fifth command is received, which instructs the selection of the first selection line; the first selection line corresponds to the selected column.

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