Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes multiple pixel circuits and multiple light-emitting elements; the pixel circuits include a driving module, the driving module includes a dual-gate driving transistor, the dual-gate driving transistor includes a first gate and a second gate, the dual-gate driving transistor generates a driving current in response to the voltage of the first gate, and the dual-gate driving transistor adjusts its threshold voltage in response to the voltage of the second gate, wherein the second gate of at least some different positions of the dual-gate driving transistor is subjected to different voltages, so that the difference in luminous brightness of the light-emitting elements driven by the dual-gate driving transistors at different positions at the same grayscale is within a preset range. According to the embodiments of this application, it is beneficial to improve display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] As society progresses, people's lives become increasingly busy and colorful, leading to higher demands for display panel performance. For example, users are constantly seeking better image quality, faster response times, lower power consumption, and narrower bezels.

[0003] However, in related technologies, the display panel still suffers from uneven display. Summary of the Invention

[0004] This application provides a display panel and display device, which helps to improve display uniformity and thus improve display quality.

[0005] In a first aspect, embodiments of this application provide a display panel including multiple pixel circuits and multiple light-emitting elements; the pixel circuits include a driving module, the driving module includes a dual-gate driving transistor, the dual-gate driving transistor includes a first gate and a second gate, the dual-gate driving transistor generates a driving current in response to the voltage of the first gate, the dual-gate driving transistor adjusts its threshold voltage in response to the voltage of the second gate, and the second gate of at least some dual-gate driving transistors at different locations is subjected to different voltages, so that the difference in luminous brightness of the light-emitting elements driven by the dual-gate driving transistors at different locations at the same gray level is within a preset range.

[0006] In one possible implementation of the first aspect, the pixel circuit is connected to the first electrode of the light-emitting element via an electrode connection line, and the second gate of the dual-gate driving transistor corresponding to electrode connection lines of different lengths is subjected to different voltages.

[0007] Preferably, the longer the electrode connection line, the smaller or larger the voltage applied to the second gate of the corresponding dual-gate drive transistor.

[0008] In one possible implementation of the first aspect, the dual-gate driving transistor is a PMOS type transistor, and the longer the electrode connection line is, the smaller the voltage applied to the second gate of the corresponding first driving transistor.

[0009] Alternatively, if the dual-gate drive transistor is an NMOS transistor, the longer the electrode connection line, the greater the voltage applied to the second gate of the corresponding dual-gate drive transistor.

[0010] In one possible implementation of the first aspect, the display panel includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0011] The pixel circuit includes a first pixel circuit and a second pixel circuit, and the light-emitting element includes a first light-emitting element and a second light-emitting element;

[0012] The first light-emitting element is located in the first display area, and the first pixel circuit is used to drive the first light-emitting element and is located outside the first display area;

[0013] The second pixel circuit is used to drive the second light-emitting element, and the second pixel circuit and the second light-emitting element are located in the second display area;

[0014] The driving module of the first pixel circuit includes a dual-gate driving transistor, and the driving module of the second pixel circuit includes a single-gate driving transistor.

[0015] Preferably, in the row direction and in the direction close to the center point of the first display area, the length of the multiple electrode connection lines connecting the multiple first light-emitting elements in the same row gradually increases.

[0016] In one possible implementation of the first aspect, the display panel includes a display area and a bonding area. In the column direction, the bonding area is located on one side of the display area, and a plurality of pixel circuits and a plurality of light-emitting elements are located in the display area, with the plurality of pixel circuits arranged in rows and columns.

[0017] In the column direction, the second gates of the dual-gate drive transistors in at least some of the pixel circuits in different rows of the same column pixel circuit are subjected to different voltages.

[0018] In one possible implementation of the first aspect, the dual-gate driving transistor is a PMOS type transistor, and the voltage applied to the second gate of the dual-gate driving transistor in the same column pixel circuit gradually decreases in the column direction and in the direction away from the bonding region.

[0019] Alternatively, the dual-gate driving transistor is an NMOS type transistor, and in the column direction and in the direction away from the bonding region, the voltage applied to the second gate of the dual-gate driving transistor in the same column pixel circuit gradually increases.

[0020] In one possible implementation of the first aspect, the second gates of the dual-gate drive transistors of multiple pixel circuits in the same row are subjected to the same voltage.

[0021] In one possible implementation of the first aspect, the display panel includes a voltage divider trace, one end of which is connected to a first voltage terminal and the other end of which is connected to a second voltage terminal. The second gates of dual-gate drive transistors, which are subjected to different voltages, are connected to different locations on the voltage divider trace, wherein the voltage at the first voltage terminal is greater than the voltage at the second voltage terminal.

[0022] Preferably, the pixel circuit is connected to the first electrode of the light-emitting element through an electrode connection line. The dual-gate driving transistor is a PMOS type transistor. The longer the electrode connection line, the closer the connection position of the second gate of the corresponding dual-gate driving transistor to the voltage divider line is to the second voltage terminal. Alternatively, the dual-gate driving transistor is an NMOS type transistor. The longer the electrode connection line, the closer the connection position of the second gate of the corresponding dual-gate driving transistor to the voltage divider line is to the first voltage terminal.

[0023] In one possible implementation of the first aspect, the display panel includes:

[0024] Substrate;

[0025] The first metal layer is located on one side of the substrate;

[0026] A semiconductor layer is located on the side of the first metal layer away from the substrate;

[0027] The second metal layer is located on the side of the semiconductor layer away from the substrate;

[0028] The anode layer is located on the side of the second metal layer away from the substrate and is insulated from the metal layer;

[0029] The voltage divider trace is located in any one of the semiconductor layer, the first metal layer, the second metal layer, and the anode layer.

[0030] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device including a display panel as described in the first aspect embodiment.

[0031] According to the display panel and display device provided in the embodiments of this application, when different voltages are applied to the second gate, the degree of adjustment of the threshold voltage of the dual-gate driving transistor is different. The threshold voltage of the dual-gate driving transistor affects the magnitude of its driving current. Since the voltage applied to the second gate of the dual-gate driving transistor at different positions is different, and the length of the traces connected to the pixel circuit at different positions is different, the driving current received by the different light-emitting elements driven by the dual-gate driving transistor at different positions can be made to tend to be the same by controlling the voltage applied to the second gate. That is, the difference in luminous brightness of the light-emitting elements driven by the dual-gate driving transistor at different positions under the same gray level can be made to be within a preset range, thereby improving display uniformity and thus improving display quality. Attached Figure Description

[0032] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0033] Figure 1 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0034] Figure 2 A schematic diagram of the IDVG characteristic curve of a dual-gate transistor provided in an embodiment of this application;

[0035] Figure 3 Show Figure 1 A timing diagram of a mid-pixel circuit;

[0036] Figure 4 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0037] Figure 5 This diagram illustrates the brightness of a display panel.

[0038] Figure 6 This illustration shows another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application;

[0039] Figure 7 This illustration shows another structural diagram of the display panel provided in an embodiment of this application;

[0040] Figure 8 This illustration shows a schematic diagram of a voltage divider trace in a display panel provided in an embodiment of this application;

[0041] Figure 9 This illustration shows another structural diagram of the voltage divider wiring in the display panel provided in this application embodiment;

[0042] Figure 10 This illustration shows a connection diagram of pixel circuits and voltage divider traces in a display panel provided in an embodiment of this application;

[0043] Figure 11 This illustration shows a connection diagram of pixel circuits and voltage divider traces in a display panel provided in an embodiment of this application;

[0044] Figure 12 This illustration shows a schematic diagram of a film structure of a display panel provided in an embodiment of this application;

[0045] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0046] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0048] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0049] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0050] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0051] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0052] As mentioned earlier, in related technologies, the display panel still suffers from uneven display.

[0053] In order to solve the above-mentioned technical problems, the inventors of this application first studied and analyzed the root causes of the above-mentioned technical problems. The specific research and analysis process is as follows:

[0054] The display panel may be equipped with a pixel circuit to drive the light-emitting element to emit light. Specifically, the pixel circuit can receive data signals through data lines and power signals (such as power signal ELVDD) through power lines, and generate a driving current according to the received signals. The driving current can be transmitted to the light-emitting element through the electrode connection line, thereby driving the light-emitting element to emit light.

[0055] However, due to the varying lengths of data lines and power lines corresponding to pixel circuits at different locations, or the varying lengths of electrode connection lines, the impedance of these differently long lines differs. Consequently, the voltage drop and parasitic capacitance values ​​also differ, leading to varying driving currents received by the different light-emitting elements driven by the pixel circuits at different locations. This results in uneven display performance. This is especially pronounced in low grayscale or low brightness displays, where the driving transistors of the pixel circuits may operate in the linear region, making the uneven display performance particularly severe in these areas.

[0056] In view of the inventors' above-mentioned research findings, the embodiments of this application provide a display panel and a display device, which are beneficial to improving display uniformity and thus improving display image quality. The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0057] Figure 1 This diagram illustrates the structure of a pixel circuit in a display panel according to an embodiment of this application. Figure 1 As shown, the display panel may include multiple pixel circuits 10 and multiple light-emitting elements 20. Among them, the light-emitting elements 20 include, but are not limited to, organic light-emitting diodes (OLEDs).

[0058] Multiple pixel circuits 10 are distributed at different positions on the display panel, and multiple light-emitting elements 20 can also be distributed at different positions on the display panel. Pixel circuits 10 at different positions can receive signals through signal traces of different lengths and generate driving currents according to the signals they receive. Alternatively, pixel circuits 10 at different positions can be connected to the light-emitting elements they drive through electrode connection lines of different lengths, thereby transmitting the driving current they generate to the light-emitting elements through the electrode connection lines.

[0059] The pixel circuit 10 may include a driving module 11, which includes a driving transistor M1. The driving transistor M1 may be a dual-gate driving transistor M1. The dual-gate driving transistor M1 is a four-terminal device. Specifically, the dual-gate driving transistor M1 may include a first gate TG, a second gate BG, a first terminal, and a second terminal. Depending on the signal and type of the first gate of the dual-gate driving transistor M1, its first terminal may be used as the source (S) and its second terminal as the drain (D), or its first terminal may be used as the drain (D) and its second terminal as the source (S), which is not distinguished here.

[0060] The dual-gate driving transistor M1 can generate a driving current in response to the voltage of the first gate TG, and the dual-gate driving transistor M1 can adjust its threshold voltage Vth in response to the voltage of the second gate BG. The second gate BG of the dual-gate driving transistor M1 at at least some different locations is subjected to different voltages.

[0061] See Figure 2 The horizontal axis represents the voltage Vg of the first gate TG of the dual-gate driving transistor M1, and the vertical axis represents the driving current Ids generated by the dual-gate driving transistor M1. Figure 2 The characteristic curves in the diagram shift with the voltage difference Vbs between the second gate BG and the source S of the dual-gate drive transistor M1. Taking an N-type transistor as an example, Figure 2 The diagram shows the variation of the voltage difference Vbs from -4V to +4V. As the voltage difference Vbs increases, the characteristic curve shifts to the left, indicating that a smaller first gate voltage Vg is sufficient to turn on the dual-gate drive transistor M1, meaning the threshold voltage Vth of the dual-gate drive transistor M1 decreases. Therefore, it can be seen that the threshold voltage Vth can be controlled by adjusting the voltage difference Vbs, and the larger the voltage difference Vbs, the more negative (smaller) the threshold voltage Vth, and the larger the drive current Ids.

[0062] In addition, the inventors tested two sets of characteristic curves: the change of voltage difference Vbs from -4V to +4V when Vds equals 0.1V, and the change of voltage difference Vbs from -4V to +4V when Vds equals 5.1V. For N-type transistors, regardless of whether Vds equals 0.1V or 5.1V, the results show that the larger the voltage difference Vbs, the more negative (smaller) the threshold voltage Vth, and the larger the drive current Ids.

[0063] In this embodiment, the degree of adjustment of the threshold voltage Vth of the dual-gate driving transistor M1 is different when the second gate BG is applied with different voltages. The threshold voltage Vth of the dual-gate driving transistor M1 affects the magnitude of its driving current. Since the voltage applied to the second gate BG of the dual-gate driving transistor M1 at different positions is different, and the length of the traces connected to the pixel circuit at different positions is different, the driving current received by the different light-emitting elements 20 driven by the dual-gate driving transistor M1 at different positions can be made to be similar by controlling the voltage applied to the second gate BG. This makes the luminous brightness of the different light-emitting elements 20 driven by the dual-gate driving transistor M1 at different positions tend to be similar under the same gray level. In other words, the difference in luminous brightness of the different light-emitting elements 20 driven by the dual-gate driving transistor M1 at different positions under the same gray level can be kept within a preset range, which is beneficial to improving display uniformity and thus improving display quality.

[0064] For example, the first gate TG and the second gate BG are the top gate and bottom gate, respectively. Specifically, if the first gate TG is the top gate, then the second gate BG is the bottom gate; if the first gate TG is the bottom gate, then the second gate BG is the top gate.

[0065] As an example, please continue to refer to Figure 1 The pixel circuit 10 may further include a data writing module 12, a threshold compensation module 13, a first initialization module 14, a first light emission control module 15, a second light emission control module 16, a second initialization module 17, and a storage capacitor Cst. The data writing module 12 may include a second transistor M2, the threshold compensation module 13 may include a third transistor M3, the first initialization module 14 may include a fourth transistor M4, the first light emission control module 15 may include a fifth transistor M5, the second light emission control module 16 may include a sixth transistor M6, and the second initialization module 17 may include a seventh transistor M7. It should be noted that... Figure 1 The pixel circuit modules and their connections shown are merely an example and are not intended to limit this application.

[0066] Please refer to the reference. Figure 1 and Figure 3 The operation of the pixel circuit 10 may include an initialization phase t1, a data writing phase t2, and a light emission phase t3.

[0067] During the initialization phase t1, the first scan signal S1 controls the first initialization module 14 to turn on, and the first initialization signal Verf1 is transmitted to the first gate TG of the dual-gate driving transistor M1 to initialize the first gate TG of the dual-gate driving transistor M1.

[0068] During the data writing stage t2, the second scan signal S2 controls the data writing module 12 and the threshold compensation module 13 to be turned on, and the data signal Vdata is transmitted to the first gate TG of the dual-gate driving transistor M1, and the threshold compensation module 13 compensates the threshold voltage of the dual-gate driving transistor M1.

[0069] Additionally, during the data writing phase t2, the second scan signal S2 can also control the second initialization module 17 to turn on, and the second initialization signal Verf2 is transmitted to the first electrode of the light-emitting element 20 to initialize the first electrode of the light-emitting element 20. The voltage values ​​of the first initialization signal Verf1 and the second initialization signal Verf2 can be the same or different.

[0070] During the light-emitting stage t3, the light-emitting control signal EM controls the first light-emitting control module 15 and the second light-emitting control module 16 to be turned on, and the power signal ELVDD is transmitted to the first terminal of the dual-gate driving transistor M1. The dual-gate driving transistor M1 generates a driving current, which is transmitted to the light-emitting element 20, and the light-emitting element 20 emits light.

[0071] During the initialization phase t1, data writing phase t2, and light emission phase t3, the second gate BG of the dual-gate driving transistor M1 can be continuously subjected to voltage. This helps maintain the stability of the dual-gate driving transistor M1 and is easy to implement and mass-produce.

[0072] For the same dual-gate driving transistor M1, the voltage applied to its second gate BG can remain constant. Of course, depending on the actual needs, the voltage applied to the second gate BG of the same dual-gate driving transistor M1 can also be different in different application scenarios.

[0073] In some embodiments, such as Figure 4 As shown, the pixel circuit 10 can be connected to the first electrode of the light-emitting element 20 via the electrode connection line 30. The driving current generated by the pixel circuit 10 can be transmitted to the light-emitting element 20 via the electrode connection line 30. The voltage applied to the second gate of the dual-gate driving transistor corresponding to different lengths of the electrode connection line 30 is different. For example, the longer the length of the electrode connection line 30, the more gradually the voltage applied to the second gate of the corresponding dual-gate driving transistor can be increased or decreased.

[0074] In some embodiments, the first electrode of the light-emitting element 20 can be the anode, and the electrode connection line 30 is connected to the anode of the light-emitting element 20.

[0075] For example, the line width and material of different electrode connection lines 30 can be the same, that is, the impedance of different electrode connection lines 30 per unit length can be the same.

[0076] Specifically, such as Figure 4As shown, the pixel circuits 10 can be distributed in the row direction X and the column direction Y. Figure 4 The diagram illustrates the first to nth pixel circuits 10 in a row and their connected light-emitting elements 20. The first pixel circuit 10 is connected to the light-emitting element 20 via electrode connection line 30(1), the second pixel circuit 10 via electrode connection line 30(2), the third pixel circuit 10 via electrode connection line 30(3), the fourth pixel circuit 10 via electrode connection line 30(4), and so on, with the nth pixel circuit 10 connected to the light-emitting element 20 via electrode connection line 30(n). The trace lengths of electrode connection lines 30(1) to 30(n) can be different, resulting in different voltage drops across them. Even with the same current generated by the pixel circuits, the driving current received by the light-emitting elements 20 connected to electrode connection lines 30(1) to 30(n) will differ due to the different voltage drops across the electrode connection lines. In this embodiment, the voltages applied to the second gates BG of the dual-gate driving transistors M1 in the first pixel circuit 10 to the nth pixel circuit 10 can all be different. For example, the voltages applied to the second gates BG of the dual-gate driving transistors M1 in the first pixel circuit 10 to the nth pixel circuit 10 can be gradually increased or gradually decreased. This can adjust the threshold voltages of the dual-gate driving transistors M1 in the first pixel circuit 10 to the nth pixel circuit 10, so that they generate different driving currents. This is beneficial to achieve a consistent driving current received by the light-emitting elements 20 connected to the electrode connection lines 30(1) to 30(n). This can make the brightness of the light-emitting elements 20 connected to the electrode connection lines 30(1) to 30(n) tend to be consistent under the same gray level, thereby improving the display uniformity.

[0077] In some examples, the dual-gate driving transistor M1 can be a PMOS transistor. The threshold voltage of a PMOS transistor is less than 0. The inventors discovered that when the dual-gate driving transistor M1 is a PMOS transistor, the larger its threshold voltage, the larger the corresponding drive current. Furthermore, the smaller the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the greater the positive drift of its threshold voltage; that is, the smaller the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the larger its threshold voltage.

[0078] Because a longer electrode connection line 30 results in a larger voltage drop, the light-emitting element connected to it receives a smaller driving current, leading to lower brightness. To address this, when the dual-gate driving transistor M1 is a PMOS transistor, a longer electrode connection line 30 allows for a smaller voltage VB applied to the second gate BG of the corresponding dual-gate driving transistor M1. This results in a larger positive drift of the threshold voltage of the dual-gate driving transistor M1, leading to a larger driving current. This, in turn, increases the driving current received by the light-emitting element connected to the longer electrode connection line 30, thereby improving the brightness of the light-emitting element.

[0079] For example, still using Figure 4 For example, the second gate BG of the dual-gate driving transistor M1 of the first pixel circuit 10 is applied with voltage VB1, the second gate BG of the dual-gate driving transistor M1 of the second pixel circuit 10 is applied with voltage VB2, the second gate BG of the dual-gate driving transistor M1 of the third pixel circuit 10 is applied with voltage VB3, and so on, the second gate BG of the dual-gate driving transistor M1 of the nth pixel circuit 10 is applied with voltage VBn.

[0080] As an example, within the same row of light-emitting elements 20, the length of the electrode connection lines 30 connected to the light-emitting elements 20 can gradually increase in the direction closer to the center of the row. Still using... Figure 4 For example, 2n light-emitting elements 20 can be located in the same row. The pixel circuits 10 connected to the n light-emitting elements 20 on the left are located to the left of the light-emitting elements 20 in that row, and the pixel circuits 10 connected to the n light-emitting elements 20 on the right are located to the right of the light-emitting elements 20 in that row. Taking the n light-emitting elements 20 on the left as an example, the trace length of the electrode connection line 30(1) to the electrode connection line 30(n) gradually increases, and the voltage drop of the electrode connection line 30(1) to the electrode connection line 30(n) gradually increases. When the driving current of the first pixel circuit 10 to the nth pixel circuit 10 is the same, the driving current received by the light-emitting elements 20 connected to the electrode connection line 30(1) to the electrode connection line 30(n) gradually decreases. Therefore, the brightness of the light-emitting elements 20 connected to the electrode connection line 30(1) to the electrode connection line 30(n) gradually decreases. Figure 5 As shown, the inventors collected the brightness of two rows of light-emitting elements, where L01 represents the brightness of the center point of one row and L02 represents the brightness of the center point of the other row. It can be seen that, in the direction closer to the center of the row, as the length of the electrode connection line 30 connected to the light-emitting element 20 gradually increases, the brightness of the light-emitting element 20 gradually decreases.

[0081] In response to this, when the dual-gate driving transistor M1 is a PMOS type transistor, as the length of the electrode connection line 30 gradually increases, the voltage VB1 to VBn applied to the second gate BG of the dual-gate driving transistor M1 in the first pixel circuit 10 to the nth pixel circuit 10 can gradually decrease. This results in a gradual increase in the degree to which the threshold voltage of the first pixel circuit 10 to the nth pixel circuit 10 drifts in the positive direction, and a gradual increase in the driving current of the first pixel circuit 10 to the nth pixel circuit 10, in order to compensate for the decrease in brightness caused by the increase in voltage drop from the electrode connection line 30(1) to the electrode connection line 30(n).

[0082] In other examples, the dual-gate driving transistor M1 can be an NMOS transistor. The threshold voltage of an NMOS transistor is greater than 0. The inventors discovered that when the dual-gate driving transistor M1 is an NMOS transistor, the smaller its threshold voltage, the larger the corresponding drive current. Furthermore, the larger the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the greater the negative drift of its threshold voltage; that is, the larger the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the smaller its threshold voltage.

[0083] Because a longer electrode connection line 30 results in a larger voltage drop, the light-emitting element connected to it receives a smaller driving current, leading to lower brightness. To address this, when the dual-gate driving transistor M1 is an NMOS transistor, a longer electrode connection line 30 allows for a larger voltage VB applied to the second gate BG of the corresponding dual-gate driving transistor M1. This results in a larger negative threshold voltage drift of the dual-gate driving transistor M1, leading to a larger driving current. This, in turn, increases the driving current received by the light-emitting element connected to the longer electrode connection line 30, thereby improving the brightness of the light-emitting element.

[0084] For example, still using Figure 4 For example, the second gate BG of the dual-gate driving transistor M1 of the first pixel circuit 10 is applied with voltage VB1, the second gate BG of the dual-gate driving transistor M1 of the second pixel circuit 10 is applied with voltage VB2, the second gate BG of the dual-gate driving transistor M1 of the third pixel circuit 10 is applied with voltage VB3, and so on, the second gate BG of the dual-gate driving transistor M1 of the nth pixel circuit 10 is applied with voltage VBn.

[0085] The trace lengths of electrode connection lines 30(1) to 30(n) gradually increase, and the voltage drop of electrode connection lines 30(1) to 30(n) gradually increases. When the driving currents of the first pixel circuit 10 to the nth pixel circuit 10 are the same, the driving current received by the light-emitting element 20 connected to electrode connection lines 30(1) to 30(n) gradually decreases. Therefore, the brightness of the light-emitting element 20 connected to electrode connection lines 30(1) to 30(n) gradually decreases.

[0086] In response to this, when the dual-gate driving transistor M1 is an NMOS transistor, as the length of the electrode connection line 30 gradually increases, the voltage VB1 to VBn applied to the second gate BG of the dual-gate driving transistor M1 in the first pixel circuit 10 to the nth pixel circuit 10 can gradually increase, thereby gradually increasing the degree to which the threshold voltage of the first pixel circuit 10 to the nth pixel circuit 10 drifts in the negative direction, and gradually increasing the driving current of the first pixel circuit 10 to the nth pixel circuit 10 to compensate for the decrease in brightness caused by the increase in voltage drop from the electrode connection line 30(1) to the electrode connection line 30(n).

[0087] In some embodiments, such as Figure 4 As shown, the display panel 100 may include a first display area AA1 and a second display area AA2, with the first display area AA1 having a higher light transmittance than the second display area AA2. This allows for the placement of light-sensing components such as cameras at the positions corresponding to the first display area AA1, thereby achieving full-screen technology.

[0088] To improve the light transmittance of the first display area AA1, the pixel circuits corresponding to the light-emitting elements in the first display area AA1 can be externalized.

[0089] Specifically, the pixel circuit 10 may include a first pixel circuit 101 and a second pixel circuit 102. The light-emitting element 20 may include a first light-emitting element 21 and a second light-emitting element 22.

[0090] The first light-emitting element 21 is located in the first display area AA1, and the first pixel circuit 101 is used to drive the first light-emitting element 21. The first pixel circuit 101 is located outside the first display area AA1. For example, the first pixel circuit 101 may be located in the second display area AA2 or in the non-display area of ​​the display panel. For example, the first pixel circuit 101 and the first light-emitting element 21 it drives are referred to as a first pixel. It is understood that in the same first pixel, the orthographic projection of the first pixel circuit 101 on the light-emitting surface of the display panel and the orthographic projection of the first light-emitting element 21 on the light-emitting surface of the display panel do not overlap, and a relatively long electrode connection line 30 is required to connect them. In addition, the lengths of the electrode connection lines corresponding to at least some different first pixels are different.

[0091] The second light-emitting element 22 and the second pixel circuit 102 are both located in the second display area AA2, and the second pixel circuit 102 is used to drive the second light-emitting element 12.

[0092] As an example, the second pixel circuit 102 and the second light-emitting element 22 it drives are referred to as a second pixel. In the same second pixel, the orthographic projection of the second pixel circuit 102 on the light-emitting surface of the display panel can overlap with the orthographic projection of the second light-emitting element 22 on the light-emitting surface of the display panel. The length of the electrode connection line between the second pixel circuit 102 and the second light-emitting element 22 is relatively short, and the length of the electrode connection line corresponding to different second pixels is basically the same.

[0093] The driving module 11 in the first pixel circuit 101 may include a dual-gate driving transistor M1. For example... Figure 6 As shown, the driving module 11 in the second pixel circuit 102 may include a single-gate driving transistor M1'.

[0094] For example, in the first pixel circuit 101 and the second pixel circuit 102, apart from the difference in the driving transistor, the structure and connection relationship of the other modules can be the same.

[0095] In the X-direction of the row and near the center of the first display area AA1, the lengths of the multiple electrode connection lines 30 connecting the multiple first light-emitting elements 21 in the same row can gradually increase. Correspondingly, the voltage applied to the second gate of the dual-gate driving transistor M1 of the first pixel circuit 101 can be smaller or larger. For example, if the dual-gate driving transistor M1 of the first pixel circuit 101 is a PMOS transistor, the voltage applied to the second gate of the dual-gate driving transistor M1 connecting the multiple first light-emitting elements 21 in the same row can be smaller in the X-direction of the row and near the center of the first display area AA1. Alternatively, if the dual-gate driving transistor M1 of the first pixel circuit 101 is an NMOS transistor, the voltage applied to the second gate of the dual-gate driving transistor M1 connecting the multiple first light-emitting elements 21 in the same row can be larger in the X-direction of the row and near the center of the first display area AA1.

[0096] In other examples, such as Figure 7 As shown, the display panel 100 includes a display area AA and a bonding area BA. In the column direction Y, the bonding area BA is located on one side of the display area AA. Multiple pixel circuits 10 are arranged in rows and columns in the display area AA. Multiple light-emitting elements 20 may also be arranged in rows and columns in the display area AA.

[0097] The display panel 100 may also include a data line 41 extending along the column direction Y, with pixel circuits 10 in the same column connected to the same data line 41. A data signal Vdata can be transmitted to the pixel circuit 10 via the data line 41.

[0098] Additionally, the display panel 100 may include a power line 42 extending along the column direction Y, with pixel circuits 10 in the same column connected to the same power line 42. The power signal ELVDD can be transmitted to the pixel circuits 10 via the power line 42.

[0099] The inventors discovered that the greater the voltage drop of the data line 41 and / or the power line 42 in the column direction Y and in the direction away from the bonding area BA, the brightness of the light-emitting element 20 will gradually decrease.

[0100] To address this, the voltage VB applied to the second gate BG of the dual-gate driving transistor M1 in at least some different rows of pixel circuits within the same column of pixel circuits can be different. In other words, in the column direction Y, the voltage VB applied to the second gate BG of the dual-gate driving transistor M1 in pixel circuits with different distances from the bonding region BA can be different.

[0101] Specifically, such as Figure 7 As shown, pixel circuits 10 can be distributed in the row direction X and column direction Y. Pixel circuits in the same column are connected to the same data line 41 and the same power line 42. The first pixel circuit 10(1) is connected to the light-emitting element 20(1), the second pixel circuit 10(2) is connected to the light-emitting element 20(2), and so on, with the nth pixel circuit 10(n) connected to the light-emitting element 20(n). Taking the data line 41 as an example, the pixel circuits 10(1) to 10(n) are connected to different positions on the data line 41. Therefore, the voltage drop caused by the data line 41 to the pixel circuits 10(1) to 10(n) is different. When the data signals sent from the data signal terminal are the same, the data signals received by the pixel circuits 10(1) to 10(n) will be different due to the different voltage drops of the data line, resulting in a gradual decrease in the brightness of the light-emitting elements 20(1) to 20(n). In this embodiment, the voltage applied to the second gate BG of the dual-gate driving transistor M1 in the first pixel circuit 10(1) to the nth pixel circuit 10(n) can be different. This can adjust the threshold voltage of the dual-gate driving transistor M1 in the first pixel circuit 10 to the nth pixel circuit 10, so that it generates different driving currents. This is beneficial to achieve the consistency of the driving current received by the light-emitting elements 20(1) to the light-emitting elements 20(n), thereby improving the uniformity of the display.

[0102] As described above, the dual-gate driving transistor M1 can be a PMOS type transistor. In the column direction and in the direction away from the bonding region BA, the voltage applied to the second gate BG of the dual-gate driving transistor M1 in the same column pixel circuit can gradually decrease. Figure 7 As shown, the voltage applied to the second gate BG of the dual-gate driving transistor M1 in pixel circuits 10(1) to 10(n) can be gradually reduced. As a result, the degree to which the threshold voltage of pixel circuits 10(1) to 10(n) drifts in the positive direction gradually increases, so that the driving current of pixel circuits 10(1) to 10(n) can be gradually increased to compensate for the decrease in brightness caused by the increase in voltage drop of data line 41 and / or power line 42.

[0103] As described above, the dual-gate driving transistor M1 can be an NMOS transistor. In the column direction and in the direction away from the bonding region BA, the voltage applied to the second gate BG of the dual-gate driving transistor M1 in the same column pixel circuit can gradually increase. Figure 7 As shown, the voltage applied to the second gate BG of the dual-gate driving transistor M1 in pixel circuits 10(1) to 10(n) can be gradually increased. In this way, the degree of negative drift of the threshold voltage of pixel circuits 10(1) to 10(n) is gradually increased, so that the driving current of pixel circuits 10(1) to 10(n) can be gradually increased to compensate for the decrease in brightness caused by the increase in voltage drop of data line 41 and / or power line 42.

[0104] Please continue to refer to this. Figure 7 The second gate BG of the dual-gate driving transistor M1 in the same row of pixel circuit 10 can be subjected to the same voltage. In this way, the second gate BG of multiple dual-gate driving transistors M1 in the same row can be connected to the same signal terminal through the same trace, which is beneficial to improving the resolution of the display panel.

[0105] In some embodiments, such as Figure 8 As shown, the display panel may also include a voltage divider trace 50, with one end connected to a first voltage terminal VH and the other end connected to a second voltage terminal VL. The second gates of dual-gate driving transistors M1, which are subjected to different voltages, are connected to different locations on the voltage divider trace 50. The first voltage terminal VH and the second voltage terminal VL can provide different voltages; in this paper, we take an example where the voltage of the first voltage terminal VH is greater than the voltage of the second voltage terminal VL. The voltage divider trace 50 can be understood as a resistor string. The voltages at different locations on the voltage divider trace 50 are different. In this way, only the voltage divider trace 50 needs to be set to achieve different voltages applied to the second gates of dual-gate driving transistors M1 at different locations, resulting in a simple structure and low cost.

[0106] Taking the voltage of the first voltage terminal VH as an example that is greater than the voltage of the second voltage terminal VL, the pixel circuit is connected to the first electrode of the light-emitting element 21 through the electrode connection line. When the dual-gate driving transistor M1 is a PMOS type transistor, the longer the length of the electrode connection line 30, the closer the connection position of the second gate of the corresponding dual-gate driving transistor M1 and the voltage divider line 50 can be to the second voltage terminal VL. Alternatively, when the dual-gate driving transistor M1 is an NMOS type transistor, the longer the length of the electrode connection line 30, the closer the connection position of the second gate of the corresponding dual-gate driving transistor M1 and the voltage divider line 50 is to the first voltage terminal VH.

[0107] like Figure 8 As shown, the voltage divider trace 50 may include sequentially arranged location points 1 BG up to n BG Location point 1 BG Near the first voltage terminal VH, n BG Location point 1 is close to the second voltage terminal VL. BG up to n BG The partial pressure gradually decreases.

[0108] Reference Figure 4 and Figure 8 Taking the dual-gate driving transistor M1 as a PMOS type transistor as an example, the first pixel circuit 10 can be connected to position point 1. BG The second pixel circuit 10 can be connected to position point 2. BG And so on, the nth pixel circuit 10 can connect to position point n. BG .

[0109] Or, such as Figure 9 As shown, the voltage divider trace 50 may include sequentially arranged location points 1 BG up to n BG Location point 1 BG Near the second voltage terminal VL, n BG Location point 1 is close to the first voltage terminal VH. BG up to n BG The partial pressure gradually increases.

[0110] Reference Figure 4 and Figure 9 Taking the dual-gate driving transistor M1 as an NMOS type transistor as an example, the first pixel circuit 10 can be connected to position point 1. BG The second pixel circuit 10 can be connected to position point 2. BG And so on, the nth pixel circuit 10 can connect to position point n. BG .

[0111] To more intuitively illustrate the connection positions of pixel circuits and voltage divider traces at different locations, such as Figure 10 and Figure 11 As shown, Figure 10 Taking the dual-gate driving transistor M1 as a PMOS type transistor as an example, the first pixel circuit 10 can be connected to position point 1BG, the second pixel circuit 10 can be connected to position point 2BG, and so on, the nth pixel circuit 10 can be connected to position point nBG.

[0112] Figure 11 Taking the dual-gate driving transistor M1 as an NMOS transistor as an example, the first pixel circuit 10 can be connected to position point 1BG, the second pixel circuit 10 can be connected to position point 2BG, and so on, the nth pixel circuit 10 can be connected to position point nBG.

[0113] It should be noted that, in order to better distinguish it from electrode connection line 30, Figure 10 and Figure 12 The dashed lines in the diagram illustrate that the first to nth pixel circuits 10 are connected to positions 1BG to nBG. Furthermore, the positions of the dashed lines are not used to define the specific locations of the connection lines between the pixel circuits and the voltage divider traces 50.

[0114] As an example, the voltage difference between adjacent points on voltage divider trace 50 can be equal. For example, point 1. BG With location point 2 BG Voltage difference, location point 2 BG With position point 3 BG Voltage difference, location point 3 BG With position point 4 BG Voltage difference, location point 4 BG With position point 5 BG Voltage difference, location point (n-1) BG With position point n BG The voltage difference is equal.

[0115] Of course, the voltage difference between adjacent points on the voltage divider line 50 can also be set differently according to actual needs, and this application does not limit this.

[0116] For example, the voltage of the first voltage terminal VH can be less than or equal to the maximum operating voltage of the display panel. For instance, if the maximum operating voltage of the display panel is 7V, the voltage of the first voltage terminal VH can be less than or equal to 7V.

[0117] The voltage of the second voltage terminal VL can be less than or equal to the minimum operating voltage of the display panel. For example, if the minimum operating voltage of the display panel is -7V, the voltage of the second voltage terminal VL can be less than or equal to -7V.

[0118] It is understood that the specific voltage values ​​of the first voltage terminal VH and the second voltage terminal VL can be determined through debugging, and this application does not impose specific limitations on this.

[0119] like Figure 4 As shown, each row of first pixel circuits 11 can correspond to a voltage divider trace 50, or all rows of first pixel circuits 11 can correspond to the same voltage divider trace.

[0120] In some embodiments, such as Figure 12 As shown, the display panel may include a substrate 01, a first metal layer M1, a semiconductor layer B, a second metal layer M2, and an anode layer RE. The first metal layer M1 is located on one side of the substrate 01, the semiconductor layer B is located on the side of the first metal layer M1 away from the substrate 01, the second metal layer M2 is located on the side of the semiconductor layer B away from the substrate 01, and the anode layer RE is located on the side of the second metal layer M2 away from the substrate 01. The second metal layer M2 may include multiple stacked and insulated metal sublayers; for example, the second metal layer M2 may include metal sublayer M21 and metal sublayer M22. The first metal layer M1, the semiconductor layer B, the second metal layer M2, and the anode layer RE are all insulated from each other.

[0121] The voltage divider trace 50 can be located in any one of the first metal layer M1, the semiconductor layer B, the second metal layer M2, and the anode layer RE.

[0122] It should be noted that the transistors in the embodiments of this application can be either NMOS or PMOS transistors. For NMOS transistors, the on-state level is high and the off-state level is low. That is, when the gate of an NMOS transistor is high, its first and second terminals are connected; when the gate of an NMOS transistor is low, its first and second terminals are off. For PMOS transistors, the on-state level is low and the off-state level is high. That is, when the gate of a PMOS transistor is low, its first and second terminals are connected; when the gate of a PMOS transistor is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of this application are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0123] NMOS transistors can be fabricated using metal-oxide-semiconductor processes, specifically indium gallium zinc oxide (IGZO). PMOS transistors can be fabricated using polycrystalline silicon semiconductor processes, specifically low-temperature polycrystalline silicon (LTPS).

[0124] Based on the same inventive concept, this application also provides a display device, which includes the display panel provided in this application embodiment. Therefore, this display device possesses the technical features of the display panel provided in this application embodiment and can achieve the beneficial effects of the display panel provided in this application embodiment. Similarities can be found in the above description of the display panel provided in this application embodiment, and will not be repeated here.

[0125] For example, Figure 13 This diagram illustrates a structural schematic of a display device provided according to an embodiment of this application. For example... Figure 13 As shown, the display device 200 provided in this application embodiment includes the display panel provided in any of the above embodiments of this application. Figure 13 The embodiments use only a mobile phone as an example to illustrate the display device 200. It is understood that the display device 200 provided in the embodiments of this application can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of this invention do not make any special limitations in this regard.

[0126] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits and multiple light-emitting elements; The pixel circuit includes a driving module, which includes a dual-gate driving transistor. The dual-gate driving transistor includes a first gate and a second gate. The dual-gate driving transistor generates a driving current in response to the voltage of the first gate and adjusts its threshold voltage in response to the voltage of the second gate. The voltage applied to the second gate of the dual-gate driving transistor at at least some different locations is different. The driving current received by the light-emitting elements driven by the dual-gate driving transistors at different locations tends to be the same, so that the difference in luminous brightness of the light-emitting elements driven by the dual-gate driving transistors at different locations at the same gray level is within a preset range. The display panel includes a voltage divider trace, one end of which is connected to a first voltage terminal and the other end of which is connected to a second voltage terminal. The second gate of the dual-gate driving transistor, which is subjected to different voltages, is connected to different positions on the voltage divider trace, wherein the voltage at the first voltage terminal is greater than the voltage at the second voltage terminal.

2. The display panel according to claim 1, characterized in that, The pixel circuit is connected to the first electrode of the light-emitting element via an electrode connection line. The second gate of the dual-gate driving transistor corresponding to the electrode connection lines of different lengths is subjected to different voltages.

3. The display panel according to claim 2, characterized in that, The longer the electrode connection line, the smaller or larger the voltage applied to the second gate of the corresponding dual-gate driving transistor.

4. The display panel according to claim 3, characterized in that, The dual-gate driving transistor is a PMOS type transistor. The longer the electrode connection line, the smaller the voltage applied to the second gate of the dual-gate driving transistor. Alternatively, the dual-gate driving transistor is an NMOS transistor, and the longer the electrode connection line, the greater the voltage applied to the second gate of the corresponding dual-gate driving transistor.

5. The display panel according to any one of claims 2 to 4, characterized in that, The display panel includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area; The pixel circuit includes a first pixel circuit and a second pixel circuit, and the light-emitting element includes a first light-emitting element and a second light-emitting element; The first light-emitting element is located in the first display area, and the first pixel circuit is used to drive the first light-emitting element and is located outside the first display area; The second pixel circuit is used to drive the second light-emitting element, and the second pixel circuit and the second light-emitting element are located in the second display area; The driving module of the first pixel circuit includes the dual-gate driving transistor, and the driving module of the second pixel circuit includes a single-gate driving transistor.

6. The display panel according to claim 5, characterized in that, In the row direction and in the direction close to the center point of the first display area, the length of the multiple electrode connection lines connected to the multiple first light-emitting elements in the same row gradually increases.

7. The display panel according to claim 1, characterized in that, The display panel includes a display area and a bonding area. In the column direction, the bonding area is located on one side of the display area, and the plurality of pixel circuits and the plurality of light-emitting elements are located in the display area, with the plurality of pixel circuits arranged in rows and columns. In the column direction, the second gate of the dual-gate driving transistor in at least some of the pixel circuits in different rows of the same column of the pixel circuit is subjected to different voltages.

8. The display panel according to claim 7, characterized in that, The dual-gate driving transistor is a PMOS type transistor, and in the column direction and in the direction away from the bonding region, the voltage applied to the second gate of the dual-gate driving transistor in the same column of the pixel circuit gradually decreases; Alternatively, the dual-gate driving transistor is an NMOS transistor, and in the column direction and in the direction away from the bonding region, the voltage applied to the second gate of the dual-gate driving transistor in the same column of the pixel circuit gradually increases.

9. The display panel according to claim 7, characterized in that, The second gate of the dual-gate driving transistors of multiple pixel circuits in the same row is subjected to the same voltage.

10. The display panel according to claim 1, characterized in that, The pixel circuit is connected to the first electrode of the light-emitting element through an electrode connection line. The dual-gate driving transistor is a PMOS transistor. The longer the electrode connection line, the closer the connection position of the second gate of the dual-gate driving transistor to the voltage divider line is to the second voltage terminal. Alternatively, the dual-gate driving transistor is an NMOS transistor. The longer the electrode connection line, the closer the connection position of the second gate of the dual-gate driving transistor to the voltage divider line is to the first voltage terminal.

11. The display panel according to claim 1, characterized in that, The display panel includes: Substrate; A first metal layer is located on one side of the substrate; A semiconductor layer is located on the side of the first metal layer away from the substrate; The second metal layer is located on the side of the semiconductor layer away from the substrate; An anode layer is located on the side of the second metal layer away from the substrate; The voltage divider trace is located in any one of the semiconductor layer, the first metal layer, the second metal layer, and the anode layer.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

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