High aperture ratio array substrate with reduced feedthrough voltage and manufacturing method thereof

Abstract

The application relates to the technical field of display, and provides a high-aperture-ratio array substrate capable of reducing Feedthrough voltage, which comprises a glass substrate, a first metal layer plated on the upper surface of the glass substrate to form a gate electrode, a first gate insulating layer plated on the upper surface of the glass substrate and the first metal layer, a second metal layer to form first CK signal traces, third CK signal traces and TP traces which are distributed at intervals, an active layer plated on the upper surface of the second gate insulating layer, a third metal layer to form source electrodes, drain electrodes and first signal connecting lines which are distributed at intervals, a conductive layer plated on the upper surface of a passivation layer, a common electrode plated on the upper surface of the passivation layer, and a pixel electrode plated on an outer insulating layer. The application has the advantage that the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, and the Feedthrough voltage is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of displays, and in particular to a high-aperture ratio array substrate capable of reducing feedthrough voltage and a manufacturing method thereof. Background Art

[0002] For TFT-LCD displays, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is called the parasitic capacitance C. gd The gate of the TFT device is connected to the horizontally distributed gate line to control the on and off of the TFT device; the source of the TFT device is connected to the vertically distributed data line to write the data voltage to be displayed into the TFT device; when the TFT is turned on, the source and drain are connected, the data voltage enters the drain and then reaches the liquid crystal capacitor Cst through the pixel electrode to adjust the transmittance of the liquid crystal; when the TFT is turned off, the source and drain are cut off and disconnected, and the data voltage of the source cannot enter the drain. The data voltage of the source changes periodically between positive and negative polarity, and is the deflection voltage that causes the liquid crystal to produce positive and negative polarity.

[0003] Combine Figure 1 and Figure 2 At the moment when TFT is turned off, the gate voltage V g From the high level V high The V low , due to the parasitic capacitance C gd The existence of V g The instantaneous change is coupled to the drain, causing the drain voltage to drop. Since the TFT device is turned off at this time, the voltage difference between the pixel electrode and the drain will cause the pixel electrode voltage to jump. This jump value ΔV is called the feedthrough voltage. Figure 2 In the waveform diagram, V g is the gate voltage, V d is the ideal drain voltage, It is the actual common electrode voltage provided, that is, the center point of the actual positive and negative polarity deflection voltage provided, V p (t) is the actual pixel electrode voltage, V com It is the common electrode voltage that keeps the voltage at both ends of the liquid crystal the same in the positive and negative polarity states. offset is the deviation between the ideal common electrode voltage and the actual common electrode voltage, T f is the switching period of the TFT device, V lc >V com It is the area where the pixel electrode voltage is greater than the common electrode voltage in the current ideal state, V lc <V comis a region where the pixel electrode voltage is less than the common electrode voltage in the ideal state.

[0004] As shown in Figure 2 Due to the existence of the Feedthrough voltage, the ideal state of the common electrode V com deviates from the center position of the actual provided positive and negative polarity deflection voltage, that is, the ideal state of the common electrode voltage changes, but the actual provided positive and negative polarity deflection voltage remains unchanged, which results in that the liquid crystal has different deflection angles in the positive and negative polarity states, and thus the light transmittance of the array substrate is different, causing flicker of the picture of the liquid crystal display. Therefore, reducing the Feedthrough voltage is a problem to be solved at present. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a high aperture ratio array substrate with reduced Feedthrough voltage and a manufacturing method thereof. By arranging a conductive layer above the drain electrode, the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are mutually offset, thereby reducing the Feedthrough voltage.

[0006] The present application is implemented as follows:

[0007] A high aperture ratio array substrate with reduced Feedthrough voltage comprises:

[0008] a glass substrate;

[0009] a first metal layer plated on the upper surface of the glass substrate to form a gate electrode;

[0010] a first gate insulating layer plated on the upper surfaces of the glass substrate and the first metal layer;

[0011] a second metal layer plated on the upper surface of the first gate insulating layer to form a first CK signal trace, a third CK signal trace and a TP trace which are distributed at intervals, the first CK signal trace and the third CK signal trace are located on the left side of the gate electrode, and the TP trace is located on the right side of the gate electrode, the potential of the first CK signal trace is opposite to the potential of the third CK signal trace;

[0012] a second gate insulating layer plated on the upper surfaces of the second metal layer and the first gate insulating layer, the second gate insulating layer is provided with a first hole and a second hole, the first hole penetrates the first gate insulating layer, and the gate electrode is exposed to the first hole, and the first CK signal trace is exposed to the second hole;

[0013] an active layer, plated on the upper surface of the second gate insulating layer and located directly above the gate;

[0014] a third metal layer, plated on the upper surface of the second gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, the right end of the first signal connection line passing through the first hole to be connected to the gate electrode, and the left end of the first signal connection line passing through the second hole to be connected to the first CK signal line;

[0015] a passivation layer, plated on the upper surfaces of the second gate insulating layer, the active layer, and the third metal layer, the passivation layer being provided with a third hole and a fourth hole, both of which penetrate the second gate insulating layer, the third CK signal line being exposed through the third hole, and the TP line being exposed through the fourth hole;

[0016] a conductive layer, plated on the upper surface of the passivation layer and directly above the drain electrode; a second signal connection line is further plated on the upper surface of the passivation layer; the conductive layer is connected to the right end of the second signal connection line; and the left end of the second signal connection line passes through the third hole and is connected to the third CK signal line;

[0017] a common electrode, plated on the upper surface of the passivation layer and spaced apart from the conductive layer, wherein a lead of the common electrode passes through the fourth hole and is connected to the TP trace;

[0018] an outer insulating layer, plated on the upper surfaces of the passivation layer, the conductive layer, and the common electrode, wherein the outer insulating layer is provided with a fifth hole, the fifth hole penetrating the passivation layer, and the drain electrode is exposed in the fifth hole;

[0019] A pixel electrode is plated on the outer insulating layer, and a lead of the pixel electrode passes through the fifth hole and is connected to the drain electrode.

[0020] Furthermore, an upper surface of the TP line and an upper surface of the third CK signal line are at the same height, and an upper surface of the TP line is lower than an upper surface of the drain.

[0021] Furthermore, the first metal layer, the second metal layer, and the third metal layer are all MO / AL / MO three-layer structures or Ti / AL / Ti three-layer structures.

[0022] Furthermore, the gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is made of SiO2, and the outer insulating layer is made of SiOx, SiNO or SiNx.

[0023] Furthermore, the active layer is made of IGZO material, and the conductive layer, pixel electrode and common electrode are all made of ITO material.

[0024] Furthermore, the second metal layer further forms a second CK signal line and a fourth CK signal line that are spaced apart, and the potential of the second CK signal line is opposite to that of the fourth CK signal line;

[0025] The first CK signal line is connected to the gate of the array substrate in the first row, the second CK signal line is connected to the gate of the array substrate in the second row, the third CK signal line is connected to the conductive layer of the array substrate in the first row, and the fourth CK signal line is connected to the conductive layer of the array substrate in the second row.

[0026] Furthermore, the signal timing phase of the first CK signal line is one quarter cycle earlier than the signal timing phase of the second CK signal line, and the signal timing phase of the third CK signal line is one quarter cycle earlier than the signal timing phase of the fourth CK signal line.

[0027] A method for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage comprises the following steps:

[0028] S1, plating a first metal layer on the upper surface of the glass substrate to form a gate;

[0029] S2, coating a first gate insulating layer on the upper surface of the glass substrate and the first metal layer;

[0030] S3. Plate a second metal layer on the upper surface of the first gate insulating layer to form a first CK signal line, a third CK signal line, and a TP line that are spaced apart from each other, wherein the first CK signal line and the third CK signal line are located to the left of the gate, and the TP line is located to the right of the gate;

[0031] S4, plating a second gate insulating layer on the upper surface of the second metal layer and the first gate insulating layer;

[0032] S5, coating an active layer on the upper surface of the second gate insulating layer, wherein the active layer is located directly above the gate;

[0033] S6. Opening a first hole and a second hole in the second gate insulating layer, wherein the first hole penetrates the first gate insulating layer, the gate is exposed through the first hole, and the first CK signal trace is exposed through the second hole;

[0034] S7. Plate a third metal layer on the upper surface of the second gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart. The source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, the right end of the first signal connection line passes through the first hole and is connected to the gate electrode, and the left end of the first signal connection line passes through the second hole and is connected to the first CK signal line.

[0035] S8, coating a passivation layer on the upper surfaces of the second gate insulating layer, the active layer, and the third metal layer, wherein the passivation layer is provided with a third hole and a fourth hole, both of which penetrate the second gate insulating layer, and the third CK signal line is exposed through the third hole, and the TP line is exposed through the fourth hole;

[0036] S9. Plate a conductive layer, a second signal connection line, and a common electrode on the upper surface of the passivation layer, wherein the conductive layer is also located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, the left end of the second signal connection line passes through the third hole and is connected to the third CK signal line, the common electrode is also spaced apart from the conductive layer and the second signal connection line, and the lead of the common electrode passes through the fourth hole and is connected to the TP line;

[0037] S10, plating an outer insulating layer on the upper surfaces of the passivation layer, the conductive layer, and the common electrode;

[0038] A fifth hole is formed in the outer insulating layer, the fifth hole penetrates the passivation layer, and the drain electrode is exposed in the fifth hole;

[0039] S11 , plating a pixel electrode on the outer insulating layer, and connecting a lead of the pixel electrode through the fifth hole to the drain electrode.

[0040] Furthermore, an upper surface of the TP line and an upper surface of the third CK signal line are at the same height, and an upper surface of the TP line is lower than an upper surface of the drain.

[0041] Furthermore, the first metal layer, the second metal layer, and the third metal layer are all MO / AL / MO three-layer structures or Ti / AL / Ti three-layer structures.

[0042] The advantages of the present invention are: 1. A conductive layer is provided above the drain electrode, forming a supplementary capacitor between the conductive layer and the drain electrode. The gate signal is provided by the first CK signal line, and the conductive layer signal is provided by the third CK signal line. The potential of the conductive layer is opposite to that of the gate. The coupling effect of the gate on the drain electrode and the coupling effect of the conductive layer on the drain electrode offset each other, reducing the voltage difference between the pixel electrode and the drain electrode, thereby reducing the feedthrough voltage and reducing the screen flicker of the liquid crystal display; when the supplementary capacitor is equal to the parasitic capacitance, the feedthrough voltage is eliminated, improving the display stability of the liquid crystal display. 2. The conductive layer is provided near the position where the drain electrode contacts the active layer. The field strength at this position will be greater, thereby reducing the Schottky barrier formed by the contact between the active layer semiconductor and the metal wire of the drain electrode, reducing the contact resistance, and thus increasing the on-state current. 3. ITO has good conductivity and light transmittance. The conductive layer and common electrode of the array substrate of the present invention are both made of ITO, so the conductive layer and common electrode can be formed in the same process, which can simplify the substrate structure and improve production capacity. 4. The TP lines and source-drain metal lines are formed in different processes, so that the TP lines can be made below the source-drain metal lines, which can improve the aperture ratio of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] Figure 1 This is a schematic diagram of the parasitic capacitance between the gate and drain of a TFT device in the background art.

[0045] Figure 2 The ideal common electrode V is caused by the existence of the Feedthrough voltage in the background technology. com Schematic diagram of point deviation.

[0046] Figure 3 This is a simplified design diagram of the array substrate for maintaining pixel electrode potential levels according to the present invention.

[0047] Figure 4 yes Figure 3 FIG. 1 is a circuit diagram of the first row of TFT devices on the array substrate.

[0048] Figure 5 yes Figure 3 FIG. 1 is a circuit diagram of the second row of TFT devices on the array substrate.

[0049] Figure 6 This is a timing diagram of the first CK signal routing, the second CK signal routing, the third CK signal routing, and the fourth CK signal routing in the present invention.

[0050] Figure 7 It is a top view schematic diagram of the array substrate for maintaining the pixel electrode potential level of the present invention.

[0051] Figure 8 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 1 .

[0052] Figure 9 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 2 .

[0053] Figure 10 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 3 .

[0054] Figure 11 The present invention is a process for manufacturing a high aperture ratio array substrate that avoids reducing the feedthrough voltage. Figure 4 .

[0055] Figure 12 The present invention is a process for manufacturing a high aperture ratio array substrate that avoids reducing the feedthrough voltage. Figure 5 .

[0056] Figure 13 The present invention is a process for manufacturing a high aperture ratio array substrate that avoids reducing the feedthrough voltage. Figure 6 .

[0057] Figure 14 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 7 .

[0058] Figure 15 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 8 .

[0059] Figure 16 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 9 .

[0060] Figure 17 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 10 .

[0061] Figure 18 The present invention is a process for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage. Figure 10one.

[0062] Reference numerals:

[0063] Glass substrate 1; pixel display area 11;

[0064] Gate 2;

[0065] First gate insulating layer 3; first CK signal line 31; second CK signal line 32; third CK signal line 33; fourth CK signal line 34; TP line 35;

[0066] Second gate insulating layer 4; first hole 41; second hole 42;

[0067] active layer 5;

[0068] Source 6;

[0069] Drain 7;

[0070] First signal connection line 81; right end 811 of the first signal connection line; left end 812 of the first signal connection line; second signal connection line 82;

[0071] Passivation layer 9; third hole 91; fourth hole 92;

[0072] Conductive layer 10;

[0073] Common electrode 20;

[0074] Outer insulating layer 30; fifth hole 301;

[0075] Pixel electrode 40. DETAILED DESCRIPTION

[0076] The embodiments of the present invention provide a high aperture ratio array substrate and a manufacturing method thereof that reduce the feedthrough voltage, thereby solving the disadvantage of flickering of the LCD screen due to the existence of the feedthrough voltage in the background art, and achieving the technical effect of reducing the feedthrough voltage and stabilizing the LCD screen.

[0077] The technical solution in the embodiment of the present invention is to solve the above shortcomings, and the overall idea is as follows:

[0078] The main improvement of the present invention is that after the passivation layer is plated, a conductive layer is plated above the drain electrode, and the conductive layer and the drain electrode form a supplementary capacitor C 补充 , then the potential of the conductive layer is exactly opposite to the potential of the gate of the TFT array substrate at any time. There is a parasitic capacitance C between the drain and the gate. gdIn this way, the coupling effect of the gate on the drain and the coupling effect of the conductive layer on the drain will cancel each other out, thereby reducing the voltage difference between the pixel electrode and the drain, reducing the voltage jump caused by the pixel electrode, and achieving the purpose of reducing the feedthrough voltage. The gate signal is provided by the first CK signal line, and the conductive layer signal is provided by the third CK signal line. When the supplementary capacitor C 补充 and parasitic capacitance C gd When the size of the gate is consistent, the feedthrough voltage caused by the signal change of the gate can be eliminated. The supplementary capacitance C can be achieved by adjusting the facing area and film distance between the conductive layer and the drain. 补充 and parasitic capacitance C gd The same size.

[0079] The TP traces and source-drain metal lines are formed in different processes. The TP traces and the first and third CK signal traces are completed first, and then the source and drain are made. In this way, the TP traces can be made below the source-drain metal lines, which can improve the aperture ratio of the array substrate.

[0080] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0081] See Figures 1 to 18 , a preferred embodiment of the present invention.

[0082] A high aperture ratio array substrate for reducing feedthrough voltage, comprising:

[0083] Glass substrate 1;

[0084] A first metal layer is plated on the upper surface of the glass substrate 1 to form a gate 2;

[0085] a first gate insulating layer 3, plated on the upper surfaces of the glass substrate 1 and the first metal layer;

[0086] A second metal layer is plated on the upper surface of the first gate insulating layer 3 to form a first CK signal line 31, a third CK signal line 33, and a TP line 35 that are spaced apart. The first CK signal line 31 and the third CK signal line 33 are located to the left of the gate 2, and the TP line 35 is located to the right of the gate 2. The potential of the first CK signal line 31 is opposite to that of the third CK signal line.

[0087] A second gate insulating layer 4 is plated on the upper surface of the second metal layer and the first gate insulating layer 3. The second gate insulating layer 4 is provided with a first hole 41 and a second hole 42. The first hole penetrates the first gate insulating layer, the gate 2 is exposed in the first hole 41, and the first CK signal trace 31 is exposed in the second hole 42.

[0088] An active layer 5 is plated on the upper surface of the second gate insulating layer 4 and is also located directly above the gate 2;

[0089] A third metal layer is plated on the upper surface of the second gate insulating layer 4, forming a source electrode 6, a drain electrode 7 and a first signal connection line 81 that are spaced apart. The source electrode 6 is connected to the left end of the active layer 5, and the drain electrode 7 is connected to the right end of the active layer 5. The right end 811 of the first signal connection line passes through the first hole to connect to the gate, and the left end 812 of the first signal connection line passes through the second hole to connect to the first CK signal line 31;

[0090] A passivation layer 9 is plated on the upper surfaces of the second gate insulating layer 4, the active layer 5, and the third metal layer. The passivation layer 9 is provided with a third hole 91 and a fourth hole 92. The third hole 91 and the fourth hole 92 both penetrate the second gate insulating layer 4. The third CK signal trace 33 is exposed in the third hole 91, and the TP trace 35 is exposed in the fourth hole 92.

[0091] A conductive layer 10 is plated on the upper surface of the passivation layer 9 and is also located directly above the drain electrode 7. A second signal connection line 82 is also plated on the upper surface of the passivation layer 9. The conductive layer 10 is connected to the right end of the second signal connection line 82. The left end of the second signal connection line 82 passes through the third hole 91 and is connected to the third CK signal line 33.

[0092] The common electrode 20 is plated on the upper surface of the passivation layer 9 and is spaced apart from the conductive layer 10 . The lead of the common electrode 20 passes through the fourth hole 92 and is connected to the TP trace 35 .

[0093] An outer insulating layer 30 is plated on the upper surfaces of the passivation layer 9, the conductive layer 10, and the common electrode 20. The outer insulating layer 30 is provided with a fifth hole 301. The fifth hole 301 penetrates the passivation layer 9 and the drain electrode 7 is exposed in the fifth hole 301.

[0094] The pixel electrode 40 is plated on the outer insulating layer 30 , and the lead of the pixel electrode 40 passes through the fifth hole 301 and is connected to the drain electrode 7 .

[0095] In the present invention, a conductive layer 10 is provided above the drain electrode 7, and a supplementary capacitor is formed between the conductive layer 10 and the drain electrode 7. The signal of the gate 2 is provided by the first CK signal line 31, and the signal of the conductive layer 10 is provided by the third CK signal line 33. The potential of the conductive layer 10 is opposite to the potential of the gate 2. The coupling effect of the gate 2 on the drain electrode 7 and the coupling effect of the conductive layer 10 on the drain electrode 7 offset each other, reducing the voltage difference between the pixel electrode 40 and the drain electrode 7, thereby reducing the feedthrough voltage and reducing the screen flicker of the liquid crystal display; when the supplementary capacitor is equal to the parasitic capacitor, the feedthrough voltage is eliminated, improving the screen display stability of the liquid crystal display; effectively preventing the V of the common electrode 20 under ideal conditions com The dot position will deviate from the center position of the actual positive and negative polarity deflection voltage provided; so that the voltage values ​​at both ends of the liquid crystal remain the same in the positive and negative polarity states, and the deflection angles of the liquid crystal under the positive and negative polarity are the same, so that the light transmittance of the array substrate is the same and the LCD display screen is stable.

[0096] The conductive layer 10 is arranged at a position close to the contact between the drain 7 and the active layer 5. The field strength at this position will be greater, which can reduce the Schottky barrier formed by the metal wire contact between the active layer 5 semiconductor and the drain 7, reduce the contact resistance, and thus increase the on-state current.

[0097] The TP trace 35 and the source-drain metal wire 7 are formed in different processes. The TP trace 35 and the first CK signal trace 31 and the third CK signal trace 33 are completed first, and then the source-drain 7 is manufactured. In this way, the TP trace 35 can be made below the source-drain metal wire 7, which can improve the aperture ratio of the array substrate.

[0098] The upper surface of the TP trace 35 is at the same height as the upper surface of the third CK signal trace 33 , so that the third hole 91 and the fourth hole 92 are etched simultaneously in the passivation layer 9 . The etching depth of the third hole 91 and the fourth hole 92 is the same, and the etching depth is the thickness of two layers of the passivation layer 9 and the second gate insulation layer 4 .

[0099] The upper surface of the TP line 35 is lower than the upper surface of the drain 7 , which helps to arrange the TP line 35 below the metal line of the source and drain 7 , and helps to improve the aperture ratio of the array substrate.

[0100] The first metal layer, the second metal layer, and the third metal layer are all MO / AL / MO three-layer structures or Ti / AL / Ti three-layer structures.

[0101] The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer 9 is made of SiO2, and the outer insulating layer 30 is made of SiOx, SiNO or SiNx.

[0102] The active layer 5 is made of IGZO, while the conductive layer 10, pixel electrode 40, and common electrode 20 are all made of ITO. ITO has excellent conductivity and light transmittance. Since both the conductive layer and the common electrode of the array substrate of the present invention are made of ITO, they can be formed in the same process, simplifying the substrate structure and improving production capacity.

[0103] The second metal layer further forms a second CK signal line 32 and a fourth CK signal line 34 that are spaced apart. The potential of the second CK signal line 32 is opposite to that of the fourth CK signal line 34.

[0104] The first CK signal line (CK1) is connected to the gate of the array substrate in the first row, the second CK signal line (CK2) is connected to the gate of the array substrate in the second row, the third CK signal line (CK3) is connected to the conductive layer of the array substrate in the third row, and the fourth CK signal line (CK4) is connected to the conductive layer of the array substrate in the fourth row.

[0105] For the first row of the array substrate, a first hole 41 is opened at the position of the first row gate 2, a second hole 42 is opened at the position of the first CK signal line 31, and a third hole 91 is opened at the position of the third CK signal line 33. The first row of the array substrate has a first signal connection line 81 and a second signal connection line 82; for the second row of the array substrate, a first hole 41 is opened at the position of the second row gate 2, a second hole 42 is opened at the position of the second CK signal line 32, and a third hole 91 is opened at the position of the fourth CK signal line 34. The second row of the array substrate also has a first signal connection line 81 and a second signal connection line 82.

[0106] The signal timing phase of the first CK signal line 31 is one-quarter cycle ahead of the signal timing phase of the second CK signal line 32. The signal timing phase of the third CK signal line 33 is one-quarter cycle ahead of the signal timing phase of the fourth CK signal line 34. When the first CK signal line 31 drives the gate 2 of the TFT device in the first row to a high potential, the source 6 and drain 7 of the TFT device in the first row are conductive, and the data voltage signal is written to the pixel electrode 5. After one-quarter cycle, the second CK signal line 32 drives the gate 2 of the TFT device in the second row to a high potential, conductively connecting the source 6 and drain 7 of the TFT device in the second row, and the data voltage signal is written to the pixel electrode 5. When the first CK signal line 31 is high, the third CK signal line 33 is low. When the first CK signal line 31 is low, the third CK signal line 33 is high. Similarly, the potential of the second CK signal line 32 is opposite to that of the fourth CK signal line 34. Under the control of the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34, the array substrate illuminates the display screen in an orderly manner, row by row, from top to bottom or from bottom to top. For example, when the first CK signal line is 10V, the third CK signal line is -15V; when the first CK signal line is -15V, the third CK signal line is 10V.

[0107] The system further includes a driver IC connected to the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34. The driver IC is configured to provide different timing signals to the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34.

[0108] The working principle of the high aperture ratio array substrate for reducing feedthrough voltage of the present invention is as follows:

[0109] Here, this embodiment is described by taking the design of single-side transmission 4CK as an example (note that the circuit design of this invention is not limited to single-side transmission 4CK, it can also be double-side transmission), the timing diagram is as follows Figure 5 As shown, Figure 4 yes Figure 3Circuit diagram of all pixels in the first row. Simply put, the image is displayed by lighting up the pixels row by row, either from top to bottom or from bottom to top. Pixel lighting requires that the gate 2 corresponding to the TFT device in that row be at a high potential. This allows the TFT device to turn on, allowing data signals to be written to the pixel electrode 40, thereby controlling the liquid crystal twist and illuminating the pixel. Taking the first row of pixel display as an example, when the first CK signal line 31 is at a high potential, the third CK signal line 33 is at a low potential. The high potential of the first CK signal line 31 is transmitted to the first row gate 2, the first row TFT device is turned on, the pixel electrode 40 signal is written, and the low potential of the third CK signal line 33 is transmitted to the first row conductive layer 10; when the first CK signal line 31 switches to a low potential, the third CK signal line 33 switches to a high potential, the gate 2 switches from a high potential to a low potential, and the parasitic capacitance formed by the gate 2 and the drain 7 will have a coupling effect, thereby pulling down the drain 7 voltage. However, since the third CK signal line 33 is switched from a low potential to a high potential at this time, that is, the conductive layer 10 of the first row switches from a low potential to a high potential, the supplementary capacitance formed by the conductive layer 10 and the drain 7 will also have a coupling effect, thereby pulling up the drain 7 voltage. Therefore, the drain 7 voltage will not change due to the jump of the gate 2, that is, the voltage of the pixel electrode 40 will not change. Note that the design requires C 补充 with C gd The purpose of this design is to ensure that there are two feedthrough voltages, one increasing and one decreasing, of equal magnitude at the drain 7. Similarly, each row of TFT devices can avoid the feedthrough voltage caused by the gate 2 production jump.

[0110] From a microscopic perspective, it is actually the migration of charges between the drain 7 and the pixel electrode 40 that causes the amount of charge stored on the pixel electrode 40 to change, thereby causing the voltage to change. After the pixel electrode 40 is charged, the potential between the drain 7 and the pixel electrode 40 is equal, and no electron migration occurs between them. However, since the gate 2 voltage switches from a high potential to a low potential at this moment, this change will be coupled to the drain 7 through the parasitic capacitance formed by the gate 2 and the drain 7. At this time, a voltage difference will be generated between the drain 7 and the pixel electrode 40, causing charge migration between the drain 7 and the pixel electrode 40, thereby causing the pixel electrode 40 to change. The starting point for the present invention to solve this problem is to add a conductive layer 10, which forms a supplementary capacitor C with the drain 7. 补充 Then, opposite potential signals are given to the gate 2 and the conductive layer 10 through the first CK signal line 31 and the third CK signal line 33, respectively, which offsets the coupling effect of the parasitic capacitance and the supplementary capacitance and improves the working performance of the device.

[0111] A method for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage comprises the following steps:

[0112] S1. See Figure 8 , a first metal layer is plated on the upper surface of the glass substrate 1 to form a gate 2; the gate 2 is used to turn on and off the TFT device.

[0113] The first metal layer can be made of a three-layer structure of MO / AL / MO, a three-layer structure of Ti / AL / Ti, a two-layer structure of AL / MO (MO as the top layer), or a two-layer structure of AL / Ti (Ti as the top layer), all formed using PVD. AL's low resistance makes it conductive (Cu can be used as a substitute), reducing impedance and power consumption. Furthermore, the low coefficient of expansion of MO or Ti can suppress deformation of AL during high-temperature processes and prevent oxidation.

[0114] S2. See Figure 9 , coating a first gate insulating layer 3 on the upper surface of the glass substrate 1 and the first metal layer;

[0115] The first gate insulating layer 3 serves as an insulating dielectric and also as a capacitor dielectric between the gate 2 and the active layer 5. It is made of a single SiOx layer or a double SiNx / SiOx layer, formed by CVD and dry etching. Considering the current requirements for TFT devices, which are fast response and low power consumption, and these are achieved by shrinking the TFT device, a suitable high-K material (such as HfO2) needs to be selected for the gate insulating layer to achieve device miniaturization. However, considering that HfO2 has many defects at the interface, direct contact with the active layer 5 or the gate 2 metal may affect the stability of the device. Therefore, SiOx or SiNx with a relatively good interface can be considered (SiNx can only serve as a contact film layer with the gate metal layer. If it serves as a contact surface with IGZO, hydrogen residue in the SiNx film during the film formation process will degrade the IGZO properties) as the contact surface. For example, a SiOx / HfO2 / SiOx three-layer structure can be used as the GI insulating layer. In order to ensure the advantages of the high-K material, the thickness of the HfO2 in the three-layer structure needs to be greater than that of the SiOx.

[0116] S3, see Figure 10A second metal layer is plated on the upper surface of the first gate insulating layer 3 to form a first CK signal line 31, a second CK signal line 32, a third CK signal line 33, a fourth CK signal line 34, and a TP line 35. The first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34 are located to the left of the gate 2, and the TP line 35 is located to the right of the gate 2. The first CK signal line 31 is used to transmit the first row gate 2 signal, the second CK signal line 32 is used to transmit the second row gate signal, the third CK signal line 33 is used to transmit the first row conductive layer 20 signal, and the fourth CK signal line 34 is used to transmit the second row conductive layer signal. The full name of the TP line is Touch Panel Senser Line; the TP line provides a voltage signal to the common electrode.

[0117] The material of the second metal layer can be selected from MO / AL / MO three-layer structure pair, Ti / AL / Ti three-layer structure, AL / MO double-layer structure (MO as the top layer), AL / Ti double-layer structure (Ti as the top layer), etc., and PVD film formation is performed.

[0118] S4. See Figure 11 , plating a second gate insulating layer 4 on the upper surface of the second metal layer and the first gate insulating layer 3;

[0119] The second gate insulating layer 4 is made of a SiOx single layer or a SiNx / SiOx double layer, formed by CVD and dry etching.

[0120] S5. See Figure 12 , coating an active layer 5 on the upper surface of the second gate insulating layer 4 , wherein the active layer 5 is located directly above the gate 2 ;

[0121] The material of the active layer 5 is a metal oxide semiconductor such as IGZO, formed by PVD, and etched by wet etching.

[0122] S6. See Figure 13 The second gate insulating layer 4 is provided with a first hole 41 and a second hole 42 . The first hole 41 penetrates the first gate insulating layer 3 , the gate 2 is exposed in the first hole 41 , and the first CK signal trace 31 is exposed in the second hole 42 .

[0123] For the first row of the array substrate, a first hole 41 is formed at the location of the first row gate 2, and a second hole 42 is formed at the location of the first CK signal trace 31. For the second row of the array substrate, a first hole 41 is formed at the location of the second row gate 2, and a second hole 42 is formed at the location of the second CK signal trace 32. Both the first hole 41 and the second hole 42 are located outside the pixel display area 11.

[0124] The first hole 41 and the second hole 42 are dug out by dry etching. The function of the first hole 41 and the second hole 42 is to provide a connection between the first CK signal line 31 (or the second CK signal line 32) and the gate 2. It should be noted that the depths of the first hole 41 and the second hole 42 are different. If the first hole 41 and the second hole 42 are etched at the same time, the top metal of the gate 2 at the position of the first hole 41 may be over-etched during etching. Therefore, this solution improves the aperture ratio of the panel at the expense of impedance while reducing the feedthrough voltage.

[0125] S7, see Figure 14 , a third metal layer is plated on the upper surface of the second gate insulating layer 4 to form a source electrode 6, a drain electrode 7 and a first signal connection line 81 that are distributed at intervals. The source electrode 6 is connected to the left end of the active layer 5, and the drain electrode 7 is connected to the right end of the active layer 5. The right end 811 of the first signal connection line passes through the first hole 41 to be connected to the gate 2, and the left end 812 of the first signal connection line passes through the second hole 42 to be connected to the first CK signal line 31; the source electrode 6 and the drain electrode 7 are both within the pixel display area 11.

[0126] The third metal layer can be constructed using a three-layer structure of MO / AL / MO or Ti / AL / Ti, using PVD deposition and acid wet etching. AL has low electrical resistance and is used for conductivity (Cu can be used instead), reducing impedance and power consumption. Furthermore, the low coefficient of expansion of the outer metal layers, MO or Ti, can suppress deformation of the AL during high-temperature processes and prevent oxidation.

[0127] S8, see Figure 15 A passivation layer 9 is plated on the upper surface of the second gate insulating layer 4, the active layer 5, and the third metal layer. A third hole 91 and a fourth hole 92 are etched in the passivation layer 9. Both the third hole 91 and the fourth hole 92 penetrate the second gate insulating layer 4. The third CK signal line 33 is exposed in the third hole 91, and the TP line 35 is exposed in the fourth hole 92. The third hole 101 is outside the pixel display area 11, and the fourth hole 102 is inside the pixel display area 11.

[0128] For the first row of the array substrate, the third hole 91 is opened at the location of the third CK signal line 33 ; for the second row of the array substrate, the third hole 91 is opened at the location of the fourth CK signal line 34 .

[0129] The passivation layer 9 is made of SiO2, formed using CVD, and dry-etched to create a third hole 91 and a fourth hole 92. The third hole 91 provides a connection between the third CK signal trace 33 and the conductive layer 10, while the fourth hole 92 provides a connection between the common electrode 20 and the TP trace 35. The top surface of the TP trace 35 is at the same height as the top surface of the third CK signal trace 33. The etching depth of the third hole 91 and the fourth hole 92 is equal to the thickness of both the passivation layer 9 and the second gate insulation layer 4, and the etching depth is the same.

[0130] The upper surface of the TP line 35 is lower than the upper surface of the drain 7. This helps to arrange the TP line 35 below the metal line of the source and drain 7, and helps to improve the aperture ratio of the array substrate.

[0131] S9, see Figure 16 , a conductive layer 10, a second signal connection line 82, and a common electrode 20 are plated on the upper surface of the passivation layer 9. The conductive layer 10 is also located directly above the drain electrode 7. The conductive layer 10 is connected to the right end of the second signal connection line 82. The left end of the second signal connection line 82 passes through the third hole 91 and is connected to the third CK signal line 33. The common electrode 20 is also spaced apart from the conductive layer 10 and the second signal connection line 82. The lead of the common electrode 20 passes through the fourth hole 92 and is connected to the TP line 34.

[0132] One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 40, and the other end is connected to the common electrode 20. The TP line provides a voltage signal to the common electrode.

[0133] ITO is the material of choice for both the conductive layer 10 and the common electrode 20, primarily due to its excellent conductivity and light transmittance, and is suitable for PVD film formation and acid wet etching. The conductive layer 10 is designed to be directly above the drain electrode 7 to form a capacitive structure with the source electrode 6, known as a supplementary capacitor. The supplementary capacitor's capacitance must be consistent with the parasitic capacitance formed by the gate 2 and drain electrode 7. This can be achieved by adjusting the area directly above the conductive layer 10 and the distance between the film layers.

[0134] S10, see Figure 17 , plating an outer insulating layer 30 on the upper surfaces of the passivation layer 9, the conductive layer 10, and the common electrode 20;

[0135] A fifth hole 301 is formed in the outer insulating layer 30 . The fifth hole penetrates the passivation layer, and the drain electrode 7 is exposed in the fifth hole 301 . The fifth hole 301 is located within the pixel display area 11 .

[0136] The outer insulating layer 30 can be made of SiOx, SiNO, SiNx, etc., and formed by CVD. The outer insulating layer 30 and the passivation layer 9 are dry-etched to expose the drain electrode 7, thereby providing a connection between the pixel electrode 40 and the drain electrode 7.

[0137] S11. See Figure 18 , a pixel electrode 40 is plated on the outer insulating layer 30 , and a lead of the pixel electrode 40 passes through the fifth hole 301 and is connected to the drain electrode 7 .

[0138] The material of the pixel electrode 40 is ITO, mainly because ITO has good electrical conductivity and light transmittance, and is suitable for PVD film formation and acid wet etching.

[0139] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high aperture ratio array substrate for reducing feedthrough voltage, characterized in that: include: glass substrate; A first metal layer is plated on the upper surface of the glass substrate to form a gate; a first gate insulating layer, plated on the upper surfaces of the glass substrate and the first metal layer; a second metal layer, plated on the upper surface of the first gate insulating layer, forming a first CK signal line, a third CK signal line, and a TP line that are spaced apart from each other, wherein the first CK signal line and the third CK signal line are located to the left of the gate, and the TP line is located to the right of the gate, and the potential of the first CK signal line is opposite to that of the third CK signal line; a second gate insulating layer, plated on the upper surfaces of the second metal layer and the first gate insulating layer, the second gate insulating layer being provided with a first hole and a second hole, the first hole penetrating the first gate insulating layer, the gate being exposed through the first hole, and the first CK signal trace being exposed through the second hole; an active layer, plated on the upper surface of the second gate insulating layer and located directly above the gate; a third metal layer, plated on the upper surface of the second gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, the right end of the first signal connection line passing through the first hole to connect to the gate electrode, and the left end of the first signal connection line passing through the second hole to connect to the first CK signal line; a passivation layer, plated on the upper surfaces of the second gate insulating layer, the active layer, and the third metal layer, the passivation layer being provided with a third hole and a fourth hole, both of which penetrate the second gate insulating layer, the third CK signal line being exposed through the third hole, and the TP line being exposed through the fourth hole; a conductive layer, plated on the upper surface of the passivation layer and directly above the drain electrode; a second signal connection line is further plated on the upper surface of the passivation layer; the conductive layer is connected to the right end of the second signal connection line; and the left end of the second signal connection line passes through the third hole and is connected to the third CK signal line; a common electrode, plated on the upper surface of the passivation layer and spaced apart from the conductive layer, wherein a lead of the common electrode passes through the fourth hole and is connected to the TP trace; an outer insulating layer, plated on the upper surfaces of the passivation layer, the conductive layer, and the common electrode, wherein the outer insulating layer is provided with a fifth hole, the fifth hole penetrating the passivation layer, and the drain electrode is exposed in the fifth hole; A pixel electrode is plated on the outer insulating layer, and a lead of the pixel electrode passes through the fifth hole and is connected to the drain electrode.

2. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 1, wherein: The upper surface of the TP line is at the same height as the upper surface of the third CK signal line, and the upper surface of the TP line is lower than the upper surface of the drain.

3. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 2, wherein: The first metal layer, the second metal layer, and the third metal layer are all MO / AL / MO three-layer structures or Ti / AL / Ti three-layer structures.

4. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 2, wherein: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is made of SiO2, and the outer insulating layer is made of SiOx, SiNO or SiNx.

5. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 2, wherein: The active layer is made of IGZO material, and the conductive layer, pixel electrode and common electrode are all made of ITO material.

6. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 1, wherein: The second metal layer further forms a second CK signal line and a fourth CK signal line that are spaced apart from each other, and the potential of the second CK signal line is opposite to that of the fourth CK signal line; The first CK signal line is connected to the gate of the array substrate in the first row, the second CK signal line is connected to the gate of the array substrate in the second row, the third CK signal line is connected to the conductive layer of the array substrate in the first row, and the fourth CK signal line is connected to the conductive layer of the array substrate in the second row.

7. The high aperture ratio array substrate for reducing feedthrough voltage according to claim 6, wherein: The signal timing phase of the first CK signal line is one quarter cycle earlier than the signal timing phase of the second CK signal line, and the signal timing phase of the third CK signal line is one quarter cycle earlier than the signal timing phase of the fourth CK signal line.

8. A method for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage, characterized in that: The following steps are involved: S1, plating a first metal layer on the upper surface of the glass substrate to form a gate; S2, coating a first gate insulating layer on the upper surface of the glass substrate and the first metal layer; S3. Plate a second metal layer on the upper surface of the first gate insulating layer to form a first CK signal line, a third CK signal line, and a TP line that are spaced apart from each other, wherein the first CK signal line and the third CK signal line are located to the left of the gate, and the TP line is located to the right of the gate; S4, plating a second gate insulating layer on the upper surface of the second metal layer and the first gate insulating layer; S5, coating an active layer on the upper surface of the second gate insulating layer, wherein the active layer is located directly above the gate; S6. Opening a first hole and a second hole in the second gate insulating layer, wherein the first hole penetrates the first gate insulating layer, the gate is exposed through the first hole, and the first CK signal trace is exposed through the second hole; S7. Plate a third metal layer on the upper surface of the second gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart. The source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, the right end of the first signal connection line passes through the first hole and is connected to the gate electrode, and the left end of the first signal connection line passes through the second hole and is connected to the first CK signal line. S8, coating a passivation layer on the upper surfaces of the second gate insulating layer, the active layer, and the third metal layer, wherein the passivation layer is provided with a third hole and a fourth hole, both of which penetrate the second gate insulating layer, and the third CK signal line is exposed through the third hole, and the TP line is exposed through the fourth hole; S9. Plate a conductive layer, a second signal connection line, and a common electrode on the upper surface of the passivation layer, wherein the conductive layer is also located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, the left end of the second signal connection line passes through the third hole and is connected to the third CK signal line, the common electrode is also spaced apart from the conductive layer and the second signal connection line, and the lead of the common electrode passes through the fourth hole and is connected to the TP line; S10, plating an outer insulating layer on the upper surfaces of the passivation layer, the conductive layer, and the common electrode; A fifth hole is formed in the outer insulating layer, the fifth hole penetrates the passivation layer, and the drain electrode is exposed in the fifth hole; S11 , plating a pixel electrode on the outer insulating layer, and connecting a lead of the pixel electrode through the fifth hole to the drain electrode.

9. The method for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage according to claim 8, wherein: The upper surface of the TP line is at the same height as the upper surface of the third CK signal line, and the upper surface of the TP line is lower than the upper surface of the drain.

10. The method for manufacturing a high aperture ratio array substrate with reduced feedthrough voltage according to claim 8, wherein: The first metal layer, the second metal layer, and the third metal layer are all MO / AL / MO three-layer structures or Ti / AL / Ti three-layer structures.

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