Low power consumption ring oscillator

Abstract

The application provides a low-power consumption ring oscillator, which generates waveforms with phase differences through the ring oscillator, controls waveforms with corresponding phase differences generated on branches in a buffer through the waveforms generated by the buffer, and controls switches with parallel resistors on adjacent branches in the buffer through the three waveforms generated by the buffer, so that the switches on the same branch in the buffer do not exist at the same time, thereby reducing power consumption and current noise and improving the reliability of the circuit in actual application. The original circuit is not subjected to excessive noise reduction.

Description

Technical Field

[0001] This invention belongs to the field of circuit component technology, specifically relating to a low-power ring oscillator. Background Technology

[0002] With the development of science and technology, semiconductor devices are increasingly widely used due to their inherent advantages. Among them, in analog integrated circuits, the power consumption and current noise of the OSC oscillator that generates the frequency are important indicators of the circuit. In practical applications, the OSC generates a fixed frequency, and noise will also be generated in order to generate this frequency. The power consumption and current noise of the oscillation circuit will affect the performance of the circuit in practical circuit applications.

[0003] A common type of OSC circuit today uses a ring oscillator formed by three inverters. The desired oscillator frequency is achieved by adding capacitors between the connected inverters and limiting the overcurrent from the inverters to Vdd and ground. The charging and discharging of the capacitors forms a triangular wave, which can then be amplified and shaped by a buffer to obtain a square wave.

[0004] Capacitor charging is a linear process: U = It / c, such as... Figure 2 As shown, the three invs form a ring oscillator. The waveforms output from points m1, m2, and m3 are similar to triangular waves. Traditional buffers use inverters to convert triangular waves into square waves. When the triangular wave passes through the first inverter, a potential at the middle of the formed triangular wave will cause both switches on the inverter to open. This creates a low-resistance path from VDD to ground, generating a large current and increasing unnecessary power consumption and noise. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power ring oscillator and a circuit that reduces power consumption and current noise. By using a waveform with a minimum phase difference of 120 degrees between three points generated in the ring oscillator to control two inverters on the same branch in the buffer, the simultaneous operation of the inverters on the same branch in the buffer is prevented, thereby reducing power consumption and current noise and improving the reliability of the circuit in practical applications.

[0006] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0007] This invention provides a low-power ring oscillator, comprising:

[0008] A ring oscillator, comprising at least three inverters inv1, inv2, and inv3 connected in series;

[0009] The buffer, connected to the ring oscillator, includes at least three branches, each connected to one of the three points of the ring oscillator with a minimum phase difference of 120 degrees.

[0010] The waveform generated by the ring oscillator with a minimum phase difference of 120 degrees at three points controls the switch pairs connected in series with the resistors at the VDD and VSS terminals on the three branches of the buffer. The waveform output from the middle of this switch pair controls the switch pairs connected in parallel with the resistors at the VDD and VSS terminals on adjacent branches of the buffer, ensuring that there is no situation where the same branch in the buffer is open at the same time.

[0011] Furthermore, the oscillator contains three interconnected capacitors as capacitors required for delay.

[0012] Furthermore, the inverter is equipped with a current limiting device to control the magnitude of the current used to charge and discharge the capacitor.

[0013] Furthermore, each branch of the buffer has a resistor connected to the VDD and VSS terminals, with a pair of switching transistors connected in series in the middle of the resistors, controlled by the corresponding output point of the oscillator. The resistors at the VDD and VSS terminals are also connected in parallel with a pair of switching transistors. The three repeating units are connected in this way to form a buffer.

[0014] The buffer includes: switches K1, K2, K5, K6, K9, K10, K3, K4, K7, K8, K11, and K12. Switches K1, K2, K5, K6, K9, and K10 are defined as being on when low level and off when high level, while switches K3, K4, K7, K8, K11, and K12 are the opposite. Each switch connected to VDD and ground is connected in parallel with a resistor.

[0015] Furthermore, K2 and K3 are controlled by the same voltage circuit line node m1, while K1 and K4 are controlled by another voltage vout, and the phase of the control voltage vout is ahead of the phase of the control voltage circuit line node m1.

[0016] When vout changes from low to high, K1 is off and K4 is on. However, the change in the level of circuit node m1 is later than the change in vout. During the process of circuit node m1 rising from low to high, since only one of K1 and K4 is on, there will not be a situation where all switches are on in this branch. The level of circuit node m1 can make K3 conduct. At this time, the output level of the branch can be switched at circuit node m5. The role of the resistor is to maintain the level of circuit node m5 normally.

[0017] Because the phase of vout is ahead of the circuit node m1, when the level of vout switches from high to ground, because the potential of the circuit node m1 is at a high level at this time, K3 is turned on and K2 is not turned on. Therefore, when the circuit node m1 switches, the four switches on the same branch will not be turned on at the same time.

[0018] A resistor R1 is connected between K1 and K2 to Vdd, and a resistor R2 is connected between K3 and K4 to ground to ensure that the potential of circuit node m5 does not float when switching circuit node m1, thus ensuring the stability of the potential of circuit node m5.

[0019] The phase difference between circuit nodes m5, m6, and vout is determined by circuit nodes m1, m2, and m3. Since circuit nodes m1, m2, and m3 are generated by three ring oscillators, the minimum phase difference between them is 120 degrees. The minimum phase difference between the square wave generated by circuit nodes m1, m2, and m3 through the buffer is also 120 degrees. Therefore, by using this phase difference to stagger the switching on the same branch in the buffer, the generation of large current can be avoided, thereby reducing power consumption and noise.

[0020] Furthermore, there are more than three ring inverters.

[0021] Furthermore, current is limited on VDD and VSS of the three inverters in the ring oscillator. A current source is connected between VDD of inv1, inv2, and inv3 and ground to control the charging and discharging time of capacitors C1, C2, and C3. The size of the current source and the capacitors controls the oscillation frequency.

[0022] Furthermore, switching transistors K1, K2, K5, K6, K9, and K10 are replaced with PMOS transistors, while switching transistors K3, K4, K7, K8, K11, and K12 are replaced with NMOS transistors.

[0023] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0024] This invention provides a circuit for reducing power consumption and current noise. It uses a ring oscillator to generate waveforms with phase differences to control the generation of corresponding waveforms in the branches of the buffer. The three waveforms generated by the buffer then control the switches with parallel resistors in adjacent branches of the buffer, so that there is no situation where the same branch in the buffer is turned on at the same time. This reduces power consumption and current noise and improves the reliability of the circuit in practical applications. The original circuit did not perform much noise reduction processing.

[0025] To increase the driving capability of the buffer, the number of branches is increased on the buffer, which can reduce the rise and fall times of the generated square wave, and the magnitude of the frequency generated by the three capacitors is related to the charging speed of the capacitor.

[0026] The selection of resistors R1 to R6 should effectively isolate the large current during branch switching in the buffer and ensure the stability of the output level after switching. Attached Figure Description

[0027] Figure 1 This is the circuit structure of this application;

[0028] Figure 2 The circuit structure is based on existing technology;

[0029] Figure 3 The power supply current curve of the circuit structure in this application is shown.

[0030] Figure 4 This is the output of the buffer in this application.

[0031] In the diagram: buffer is a buffer, inv1, inv2, and inv3 form a ring oscillator, C1, C2, and C3 are capacitors, the area inside the dashed box is the buffer, K1 to K12 are switching transistors, and R1 to R6 are resistors. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0033] In the description of this embodiment, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this embodiment and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this embodiment.

[0034] Example 1:

[0035] This invention designs Figure 1 Circuit structure.

[0036] like Figure 1 The circuit structure shown is a frequency generation circuit for a loop oscillator composed of three inverters, inv1, inv2, and inv3. The connected capacitors C1, C2, and C3 serve as capacitors for delay (the frequency generated depends on the charging speed of these capacitors). Generally, to make the oscillation frequency more stable, each inverter has an internal current limiting device to control the current supplying the capacitors. The buffer circuit consisting of K1-K12 and R1-R6 within the dashed box is a key feature of this design. Each branch of the buffer has resistors connected to the VDD and VSS terminals. A pair of switches are connected in series in the middle of the resistors, controlled by the corresponding output point of the oscillator. Another pair of switches is connected in parallel to the resistors at the VDD and VSS terminals. Three repeating units are then connected in this manner to form the buffer. Switches K1, K2, K5, K6, K9, and K10 are defined as being on when low and off when high, while switches K3, K4, K7, K8, K11, and K12 are the opposite. Each switch connected to VDD and ground has a resistor connected in parallel. These three repeating units are then connected in this manner to form the buffer.

[0037] Capacitor charging is a linear process: U = It / c. The ring oscillator formed by three invs will produce waveforms at points m1, m2, and m3 that resemble triangular waves. Traditional buffers use inverters to convert triangular waves into square waves. When the triangular wave passes through the first inverter, a potential at the midpoint of the formed triangular wave will cause both switches on the inverter to open. This creates a low-resistance path from VDD to ground, generating a large current and increasing unnecessary power consumption and noise. The buffer circuit designed in this paper greatly optimizes this problem.

[0038] The working mode of this product is as follows: Figure 1The main oscillator formed by the three inverters in the circuit determines the frequency. The buffer module converts the triangular wave formed by the three loop inverters into a square wave, featuring low power consumption and low noise. Its operating mode ensures that the four switches on the same Vdd-to-ground branch in the buffer will not be on simultaneously. Taking the branch formed by K1, K2, K3, and K4 as an example, K2 and K3 are controlled by the same voltage at circuit node m1, while K1 and K4 are controlled by another voltage at circuit node vout. The phase of the control voltage vout is ahead of that at circuit node m1. Thus, when vout changes from low to high, K1 is off and K4 is on. The change in the level of circuit node m1 is later than the change in vout. Therefore, during the process of circuit node m1 rising from low to high, since only one of K1 and K4 is on, this branch will not have all switches on simultaneously. Only the level of circuit node m1 is needed to allow K3 to conduct. When the circuit is open, the output level of the branch can be switched at circuit node m5. The resistor is used to maintain the level of circuit node m5 normally. Because the phase of the vout level is ahead of that of circuit node m1, when the vout level switches from high to ground, because the potential of circuit node m1 is high at this time, K3 is on and K2 is off. Therefore, when circuit node m1 switches, the four switches on the same branch will not be on at the same time. However, in this state, circuit node m1 is low and vout is high, which will cause the potential of circuit node m5 to be disconnected from vdd and ground at the same time, which will pose a risk of floating potential. Therefore, a resistor R1 is connected between K1 and K2 to vdd, and a resistor R2 is connected between K3 and K4 to ground. This will ensure that the potential of circuit node m5 will not float when circuit node m1 switches, thus ensuring the stability of the potential of circuit node m5. The phase difference between circuit nodes m5, m6, and vout is determined by circuit nodes m1, m2, and m3. Since circuit nodes m1, m2, and m3 are generated by an oscillator composed of three inverters, the minimum phase difference between circuit nodes m1, m2, and m3 is 120 degrees. The minimum phase difference between the square wave circuit nodes m5, m6, and vout generated by circuit nodes m1, m2, and m3 through the buffer is also 120 degrees. Therefore, by using this phase difference to stagger the switching of the switches on the same branch in the buffer, the generation of large current can be avoided, thereby achieving the purpose of reducing power consumption and noise.

[0039] Figure 1 The diagram shows a relatively simple structure, which can be modified as needed. For example, more than three ring inverters can be used, and to increase the driving capability of the buffer, more can be added. Figure 1 The buffer's base has fewer branches, which reduces the rise and fall times of the generated square wave. In the diagram, m5, m6, and vout can all be used as outputs.

[0040] according to Figure 1 Taking the circuit diagram as an example, the ring oscillation module can be composed of three current-limiting inverters. That is, a current source is connected between Vdd of inv1, inv2, and inv3 and ground to control the charging and discharging time of capacitors C1, C2, and C3. The size of the current source and capacitors controls the oscillation frequency. K1, K2, K5, K6, K9, and K10 can be replaced by PMOS transistors, and K3, K4, K7, K8, K11, and K12 can be replaced by NMOS transistors to work normally. The selection of resistors R1 to R6 can effectively isolate the large current when the branch in the buffer switches, and also ensure the stability of the output level after switching.

[0041] Implementation principle: because Figure 1 and Figure 2 Since the inverter oscillation structure is the same, we only collect the total current of the buffers in the two circuits for comparison, with an oscillation period of 3µs.

[0042] Figure 3 The dashed line Figure 1 The power supply current curve, the solid line is... Figure 2 The voltage and current curves can be seen from the figure. Figure 2 The current is significantly greater than Figure 1 As for why Figure 1 The number of curve ripples is more than necessary. Figure 2 Because Figure 1 The buffer requires at least 3 branches, and Figure 2 Currently, the buffer only uses one inverter, so Figure 1 The buffer generates more ripple than Figure 2 .

[0043] Figure 4 The dashed line Figure 1 The output of the buffer, the solid line is Figure 2 The output of the buffer, because the two circuits being compared only have one stage of buffer, shows that the edges of the square wave have a certain time zone, which also proves... Figure 1 The structure can output normally.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0045] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0047] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A low-power ring oscillator, characterized in that, include: A ring oscillator, comprising at least three inverters inv1, inv2, and inv3 connected in series; The buffer, connected to the ring oscillator, includes three branches, each connected to one of the three points where the phase difference between the ring oscillator is 120 degrees. The waveform generated by the three points with a minimum phase difference of 120 degrees in the ring oscillator first controls the switch pairs connected in series with the resistors of VDD and VSS on the three branches of the buffer. The waveform output by the middle of this switch pair controls the switch pairs connected in parallel with the resistors of VDD and VSS on the adjacent branches of the buffer, so that there is no situation where the same branch in the buffer is open at the same time. The buffer has resistors connected to the VDD and VSS terminals on each branch, with a pair of switching transistors connected in series in the middle of the resistors, controlled by the corresponding output point of the oscillator. The resistors at the VDD and VSS terminals are also connected in parallel with a pair of switching transistors. The three repeating units are connected in this way to form the buffer. The buffer includes: resistors R1, R2, R3, R4, R5, R6, and switches K1, K2, K5, K6, K9, K10, K3, K4, K7, K8, K11, and K12. Switches K1, K2, K5, K6, K9, and K10 are defined as being on when low level and off when high level, while switches K3, K4, K7, K8, K11, and K12 are the opposite. Each switch connected to VDD and ground is connected in parallel with a resistor. The switching transistor has three ports: input, output, and control. The input terminal of K1 is connected to VDD, and its output terminal is connected to the input terminal of K2. The output terminal of K2 is connected to the input terminal of K3 at node m5. The output terminal of K3 is connected to the input terminal of K4, and the output terminal of K4 is connected to ground. The control terminals of K1 and K4 are connected to node vout, and the control terminals of K2 and K3 are connected to node m1. The input terminal of K5 is connected to VDD, and its output terminal is connected to the input terminal of K6. The output terminal of K6 is connected to the input terminal of K7 at node m6. The output terminal of K7 is connected to the input terminal of K8, and the output terminal of K8 is connected to ground. The control terminals of K5 and K8 are connected to node m5, and the control terminals of K6 and K7 are connected to node m2. The input terminal of K9 is connected to VDD, and its output terminal is connected to the input terminal of K10. The output terminal of K10 is connected to the input terminal of K11 at node vout. The output terminal of K11 is connected to the input terminal of K12, and the output terminal of K12 is connected to ground. The control terminals of K9 and K12 are connected to node m6, and the control terminals of K10 and K11 are connected to node m3. The two ends of resistor R1 are connected to the input and output terminals of K1, respectively. The two ends of resistor R2 are connected to the input and output terminals of K4, respectively. The two ends of resistor R3 are connected to the input and output terminals of K5, respectively. The two ends of resistor R4 are connected to the input and output terminals of K8, respectively. The two ends of resistor R5 are connected to the input and output terminals of K9, respectively. The two ends of resistor R6 are connected to the input and output terminals of K12, respectively.

2. The low-power ring oscillator according to claim 1, characterized in that, The oscillator contains three interconnected capacitors as the capacitors required for the delay.

3. The low-power ring oscillator according to claim 2, characterized in that, The inverter is equipped with a current limiting device to control the magnitude of the current used to charge and discharge the capacitor.

4. The low-power ring oscillator according to claim 1, characterized in that, The inverters exceed three.

5. The low-power ring oscillator according to claim 1, characterized in that, The VDD and VSS of the three inverters in the ring oscillator are current-limited. A current source is connected between the VDD terminal of the three inverters and the ground terminal to control the charging and discharging time of capacitors C1, C2 and C3. The size of the current source and the capacitors controls the oscillation frequency.

6. The low-power ring oscillator according to claim 1, characterized in that, Switching transistors K1, K2, K5, K6, K9, and K10 are replaced with PMOS transistors, while switching transistors K3, K4, K7, K8, K11, and K12 are replaced with NMOS transistors.

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