Decoding circuit and display device

Abstract

A decoding circuit and display device are provided, belonging to the field of electronic technology. In each logic circuit group of the decoding circuit, each N-type transistor and each P-type transistor are arranged along a second direction, and the N-type and P-type transistors are arranged along a first direction intersecting the second direction. The substrate isolation region of each transistor is located on both sides of the transistor in the first direction, and a transition hole arranged along the second direction is formed on the substrate isolation region. In this way, the P-type transistor and the N-type transistor can be isolated by the substrate isolation region with the transition hole, making the spacing between adjacent P-type and N-type transistors greater than the spacing between two adjacent transistors of the same type (e.g., N-type or P-type transistors), ensuring that the N-type and P-type transistors maintain a sufficiently large spacing. Furthermore, mutual interference between different types of transistors can be avoided, resulting in better circuit stability and preventing latch-up effects.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and in particular to a decoding circuit and a display device. Background Technology

[0002] Decoding circuits (such as 3-to-8 decoders) are one of the essential circuits in display devices, used to convert binary data into decimal data to adapt to the display device.

[0003] The decoding circuit typically includes multiple interconnected logic gates (e.g., NOT gates, NAND gates, and NOR gates). Each logic gate includes at least one N-type metal-oxide-semiconductor (MOS) transistor and one PMOS transistor. That is, each logic gate includes at least one complementary metal-oxide-semiconductor (CMOS) transistor.

[0004] However, due to the current arrangement, when one transistor in a CMOS transistor is affected by interference, it will feed back to the other transistor. This causes the PMOS and NMOS transistors in the CMOS transistor to be triggered and turned on in sequence, resulting in a latch-up effect. Summary of the Invention

[0005] A decoding circuit and display device are provided, which can solve the problem of latch-up effect in decoding circuits in related technologies. The technical solution is as follows:

[0006] On the one hand, a decoding circuit is provided, the decoding circuit comprising:

[0007] Multiple logic circuit groups arranged sequentially and interconnected along the first direction;

[0008] Each of the logic circuit groups includes: a plurality of logic circuits arranged sequentially and interconnected along a second direction, the second direction intersecting the first direction;

[0009] Each of the logic circuits includes at least one N-type transistor and at least one P-type transistor interconnected with each other. The N-type transistor and the P-type transistor each have a channel region and a substrate isolation region. The substrate isolation region is located on both sides of the channel region in the first direction, and a plurality of transition holes are formed on the substrate isolation region in sequence along the second direction for connecting the required parts.

[0010] In each of the logic circuit groups, the N-type transistors and P-type transistors of the multiple logic circuits are arranged sequentially along the second direction. The P-type transistors and the N-type transistors are arranged sequentially along the first direction, and the spacing between the channel regions of adjacent P-type transistors and N-type transistors in the first direction is greater than the spacing between the channel regions of two adjacent transistors of the same type in the second direction. The transistors of the same type include P-type transistors and N-type transistors.

[0011] Optionally, each pair of adjacent logic circuit groups is arranged in a mirror-symmetric manner along an axis extending in the second direction.

[0012] Optionally, in each of two adjacent logic circuit groups, the transistors located on both sides of the axis share the same substrate isolation region.

[0013] Optionally, in the two adjacent substrate isolation regions of the P-type transistor and N-type transistor adjacent in the first direction, the distance between the side of one substrate isolation region away from the other substrate isolation region and the side of the other substrate isolation region away from the first substrate isolation region is greater than the distance between the channel regions of two adjacent transistors of the same type in the second direction.

[0014] Optionally, for each of the P-type and N-type transistors adjacent in the first direction, the spacing between the substrate isolation region of the transistor closer to the adjacent transistor and the channel region of the transistor is greater than the spacing between the substrate isolation region of the transistor farther from the adjacent transistor and the channel region of the transistor.

[0015] Optionally, the spacing between the channel regions of adjacent P-type transistors and N-type transistors in the first direction is greater than the difference between the width of the channel region of the P-type transistor and the width of the N-type transistor, and the width of the channel region of the P-type transistor is greater than the width of the N-type transistor, wherein the direction of the width is parallel to the first direction.

[0016] Optionally, the area of ​​the substrate isolation region of the P-type transistor is larger than the area of ​​the substrate isolation region of the N-type transistor.

[0017] Optionally, in each of the logic circuits, the substrate isolation regions of each P-type transistor are adjacent on the same side and flush in the second direction, and the channel regions of each P-type transistor are spaced apart from each other and at least one side is flush in the second direction.

[0018] Furthermore, the substrate isolation regions of each N-type transistor are adjacent on the same side and flush in the second direction, and the channel regions of each N-type transistor are spaced apart from each other and at least one side is flush in the second direction.

[0019] Optionally, both the N-type transistor and the P-type transistor have a gate layer and a source / drain metal layer that are rectangular in top view;

[0020] Furthermore, the gate layer and the source / drain metal layer overlap each other, and the length direction of the gate layer extends along the first direction, while the length direction of the source / drain metal layer extends along the second direction;

[0021] The overlapping region of the gate layer and the source / drain metal layer is the channel region.

[0022] Optionally, each of the logic circuits is also connected to a first DC power line and a second DC power line respectively, and is used to perform logic processing based on the signals provided by the first DC power line and the signals provided by the second DC power line.

[0023] Among them, at least one of the first DC power lines and the second DC power lines has a width in the second direction that is greater than or equal to a width threshold.

[0024] Optionally, the first DC power line and the second DC power line are respectively located on both sides of the plurality of logic circuit groups in the second direction, and both extend along the first direction, and the width of the first DC power line in the second direction and the width of the second DC power line in the second direction are equal.

[0025] Optionally, the decoding circuit is located on one side of the substrate, and in the decoding circuit, the interconnected parts are connected by multiple layers of metal traces stacked sequentially in a direction away from the substrate, and each pair of adjacent metal traces overlaps with each other through vias, and the overlapping area is less than the area threshold.

[0026] Optionally, in the decoding circuit, the interconnected parts are connected by three layers of metal traces: a first metal trace, a second metal trace, and a third metal trace, which are stacked sequentially in a direction away from the substrate.

[0027] Wherein, the first metal trace includes multiple line segments extending along the first direction and multiple line segments extending along the second direction, the second metal trace includes multiple line segments extending along the second direction, and the third metal trace includes multiple line segments extending along the first direction.

[0028] Furthermore, the first DC power line and the second DC power line connected to each of the logic circuits are located on the same layer as the third metal trace.

[0029] Optionally, the decoding circuit is a 3-8 decoding circuit; the plurality of logic circuit groups are divided into a first logic circuit group and eight second logic circuit groups arranged sequentially along the first direction;

[0030] The first logic circuit group includes three first NOT gates and one two-input NAND gate arranged sequentially along the second direction;

[0031] Each of the multiple logic circuits in the second logic circuit group includes: a three-input NAND gate, a NOR gate and a second NOT gate arranged sequentially along the second direction;

[0032] Wherein, the first NOT gate and the second NOT gate each include one N-type transistor and one P-type transistor, the two-input NAND gate and the NOR gate each include two N-type transistors and two P-type transistors, and the three-input NAND gate includes three N-type transistors and three P-type transistors;

[0033] The input and output terminals of the three first NOT gates are respectively connected to the input terminals of each of the three-input NAND gates in the eight second logic circuit groups. The output terminal of the two-input NAND gate is connected to one input terminal of the NOR gate in each of the second logic circuit groups. In each of the second logic circuit groups, the output terminal of the three-input NAND gate is connected to the other input terminal of the NOR gate, and the output terminal of the NOR gate is connected to the input terminal of the second NOT gate.

[0034] On the other hand, a display device is provided, the display device comprising: a panel driving circuit and a display panel, the panel driving circuit being connected to the display panel and used to drive the display panel to display; wherein, the panel driving circuit includes the decoding circuit as described above.

[0035] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0036] A decoding circuit and a display device are provided. The decoding circuit includes multiple logic circuit groups arranged along a first direction. Each logic circuit group includes multiple logic circuits arranged along a second direction intersecting the first direction. Each logic circuit includes N-type transistors and P-type transistors. Furthermore, in each logic circuit group, each N-type transistor and each P-type transistor is arranged along the second direction, while the N-type and P-type transistors are arranged along the first direction. The substrate isolation region of each transistor is located on both sides of the transistor in the first direction, and a transition hole arranged along the second direction is formed on the substrate isolation region. In this way, the P-type transistors and N-type transistors can be isolated by the substrate isolation region with the transition hole, making the spacing between adjacent P-type transistors and N-type transistors greater than the spacing between two adjacent transistors of the same type (e.g., N-type transistors or P-type transistors), ensuring that the N-type transistors and P-type transistors maintain a sufficiently large spacing. This avoids mutual interference between different types of transistors, resulting in better circuit stability and preventing latch-up effects. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a decoding circuit provided in an embodiment of this disclosure;

[0039] Figure 2 This is a schematic diagram of the structure of multiple logic circuit groups in a decoding circuit provided in an embodiment of this disclosure;

[0040] Figure 3 This is a schematic diagram of the structure of multiple logic circuits in a logic circuit group provided in an embodiment of this disclosure;

[0041] Figure 4 This is a schematic diagram of another decoding circuit provided in an embodiment of the present disclosure;

[0042] Figure 5 This is a schematic diagram of the circuit structure of a 3-8 decoding circuit provided in an embodiment of this disclosure;

[0043] Figure 6 This is a schematic diagram of the NOT gate circuit structure in a 3-8 decoding circuit provided by an embodiment of the present disclosure;

[0044] Figure 7 This is a schematic diagram of the circuit structure of a two-input NAND gate in a 3-8 decoding circuit provided in this embodiment of the present disclosure;

[0045] Figure 8 This is a schematic diagram of the NOR gate in a 3-8 decoding circuit provided in this embodiment of the present disclosure;

[0046] Figure 9 This is a schematic diagram of the circuit structure of a three-input NAND gate in a 3-8 decoding circuit provided in this embodiment of the present disclosure;

[0047] Figure 10 This is a schematic diagram of the circuit structure of a logic circuit group in a 3-8 decoding circuit provided in an embodiment of the present disclosure;

[0048] Figure 11 This is a structural layout of a logic circuit group in a 3-8 decoding circuit provided in an embodiment of the present disclosure;

[0049] Figure 12 This is a structural layout of a logic circuit group in another 3-8 decoding circuit provided in this disclosure embodiment;

[0050] Figure 13 This is a structural layout of two adjacent logic circuit groups in a 3-8 decoding circuit provided in an embodiment of this disclosure;

[0051] Figure 14 This is a structural layout of two adjacent logic circuit groups in another 3-8 decoding circuit provided in this embodiment of the disclosure;

[0052] Figure 15 This is a structural layout of two adjacent logic circuit groups in another 3-8 decoding circuit provided in this embodiment of the disclosure;

[0053] Figure 16 This is a structural layout of a logic circuit group in another 3-8 decoding circuit provided in the embodiments of this disclosure;

[0054] Figure 17 Is Figure 16 A cross-sectional schematic diagram of a circuit based on the structure shown;

[0055] Figure 18 Is Figure 5 The diagram shows a layout of a 3-to-8 decoding circuit based on the structure shown.

[0056] Figure 19 Is Figure 18 The diagram illustrates a routing layout for a 3-to-8 decoder circuit based on the structure shown.

[0057] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0059] Figure 1 This is a schematic diagram of a decoding circuit provided in an embodiment of this disclosure. Figure 1 As shown, the decoding circuit includes multiple logic circuit groups 01 arranged sequentially and interconnected along the first direction X1.

[0060] exist Figure 1 Based on this, continue to refer to Figure 2 It can be seen that each logic circuit group 01 includes multiple logic circuits 011 arranged sequentially and interconnected along the second direction X2. The second direction X2 intersects with the first direction X1. For example, the second direction X2 and the first direction X1 can be perpendicular to each other, that is, the included angle is 90 degrees.

[0061] exist Figure 2 Based on this, continue to refer to Figure 3 It can be seen that each logic circuit 011 includes at least one N-type transistor 011-N and at least one P-type transistor 011-P that are interconnected. For example, Figure 3 Let's take an example where each logic circuit 011 includes one N-type transistor 011-N and one P-type transistor 011-P. Furthermore, Figure 3 The diagram only schematically illustrates the multiple logic circuits 011 included in a logic circuit group 01.

[0062] Both the N-type transistor 011-N and the P-type transistor 011-P can have a channel region A1 and a substrate isolation region S1. The substrate isolation region S1 can be located on both sides of the channel region A1 in the first direction X1, and multiple transition holes K1 are opened on the substrate isolation region S1 arranged sequentially along the second direction X2 for the purpose of connecting the required parts.

[0063] Furthermore, in each logic circuit group 01, the N-type transistors included in the multiple logic circuits 011 can be arranged sequentially along the second direction X2, the P-type transistors can be arranged sequentially along the second direction X2, and the P-type and N-type transistors can be arranged sequentially along the first direction X1. Moreover, combined with... Figure 3 It can also be seen that the spacing 'a' between the channel regions of adjacent P-type transistors and N-type transistors in the first direction X1 can be greater than the spacing 'b' between the channel regions of two adjacent transistors of the same type in the second direction X2, where the same type of transistors includes both P-type and N-type transistors (i.e., a>b).

[0064] In this way, the P-type transistor and the N-type transistor can be effectively isolated through the substrate isolation region S1 with the transition hole K1, ensuring that a sufficiently large gap can be maintained between the P-type transistor and the N-type transistor, and reducing the resistance of the transition and contact in the substrate isolation region S1, thus giving the decoding circuit better stability and avoiding latch-up effects. Furthermore, combined with... Figure 3 It can also be seen that this layout makes good use of space.

[0065] Optionally, the P-type transistors described in the embodiments of this disclosure can all be PMOS transistors. The N-type transistors described in the embodiments of this disclosure can all be NMOS transistors.

[0066] In summary, this disclosure provides a decoding circuit. The decoding circuit includes multiple logic circuit groups arranged along a first direction. Each logic circuit group includes multiple logic circuits arranged along a second direction intersecting the first direction. Each logic circuit includes N-type transistors and P-type transistors. Furthermore, in each logic circuit group, each N-type transistor and each P-type transistor are arranged along the second direction, while the N-type and P-type transistors are arranged along the first direction. The substrate isolation region of each transistor is located on both sides of the transistor in the first direction, and a transition hole arranged along the second direction is formed on the substrate isolation region. Thus, the P-type transistors and N-type transistors can be isolated by the substrate isolation region with the transition hole, making the spacing between adjacent P-type and N-type transistors greater than the spacing between two adjacent transistors of the same type (e.g., N-type or P-type transistors), ensuring that the N-type and P-type transistors maintain a sufficiently large spacing. This avoids mutual interference between different types of transistors, resulting in better circuit stability and preventing latch-up effects.

[0067] Optionally, the decoding circuit provided in this embodiment can be a 3-to-8 decoding circuit, also known as a 3-to-8 decoder. A 3-to-8 decoder is a circuit that decodes a 3-bit binary input into an 8-bit decimal output. Correspondingly, such as Figure 4 As can be seen from the decoding circuit shown, the plurality of logic circuit groups 01 described in this embodiment can be divided into a first logic circuit group 01-1 and eight second logic circuit groups 01-2 arranged sequentially along the first direction X1.

[0068] exist Figure 4 Based on the structure shown, Figure 5 A circuit diagram of a 3-to-8 decoder is shown. (Reference) Figure 5It can be seen that the multiple logic circuits 011 in the first logic circuit group 01-1 may include: three first NOT gates (NTG) NTG-1 and one two-input NAND gate (NAG) NAG-2 arranged sequentially along the second direction X2. That is, the first logic circuit group 01-1 may include 4 logic circuits 011. The multiple logic circuits 011 in each second logic circuit group 01-2 may include: one three-input NAND gate NAG-3, one NOR gate (NOG), and one second NOT gate NTG-2 arranged sequentially along the second direction X2. That is, each second logic circuit group 01-2 may include 3 logic circuits 011. The NOT gate can also be called an inverter.

[0069] exist Figure 5 Based on the structure shown, Figure 6 The equivalent circuit diagram of the first NOT gate NTG-1 is shown (the same applies to the second NOT gate NTG-2). Figure 7 The equivalent circuit diagram of the two-input NAND gate NAG-2 is shown. Figure 8 The equivalent circuit diagram of the NOR gate NOG is shown. Figure 9 The equivalent circuit diagram of the three-input NAND gate NAG-3 is shown.

[0070] refer to Figure 6 It can be seen that both the first NOT gate NTG-1 and the second NOT gate NTG-2 can include an N-type transistor 011-N and a P-type transistor 011-P. The gates of both the P-type transistor 011-P and the N-type transistor 011-N can be connected to the input terminal in. The first terminal of the P-type transistor 011-P can be connected to the power supply terminal vdd. The second terminals of both the P-type transistor 011-P and the N-type transistor 011-N can be connected to the output terminal out. The first terminal of the N-type transistor 011-N is connected to the ground terminal GND, i.e., grounded.

[0071] refer to Figure 7 and Figure 8It can be seen that both the two-input NAND gate NAG-2 and the NOR gate NOG can include two N-type transistors 011-N and two P-type transistors 011-P. Furthermore, in the two-input NAND gate NAG-2, the gates of the two P-type transistors 011-P and the gates of the two N-type transistors 011-N can be connected to the two input terminals a and b, respectively. The first terminals of the two P-type transistors 011-P can be connected to the power supply terminal vdd. The second terminals of the two P-type transistors 011-P and the second terminal of the one N-type transistor 011-N can be connected to the output terminal out. The first terminal of one N-type transistor 011-N can be connected to the second terminal of the other N-type transistor 011-N, and the first terminal of the other N-type transistor 011-N can be grounded. In a NOR gate (NOG), the gates of the two P-type transistors 011-P and the gates of the two N-type transistors 011-N can be connected to the two input terminals a and b, respectively. The first terminal of one P-type transistor 011-P can be connected to the power supply terminal vdd. The second terminal of the one P-type transistor 011-P can be connected to the first terminal of the other P-type transistor 011-P. The second terminal of the other P-type transistor 011-P and the second terminals of the two N-type transistors 011-N can both be connected to the output terminal out. The first terminals of the two N-type transistors 011-N can both be grounded.

[0072] refer to Figure 9 As can be seen, the three-input NAG-3 NAND gate can include three N-type transistors 011-N and three P-type transistors 011-P. The gates of the three N-type transistors 011-N and the three P-type transistors 011-P can be connected to the three input terminals a, b, and c, respectively. The first terminals of the three P-type transistors 011-P can all be connected to the power supply terminal vdd. The second terminals of the three P-type transistors 011-P and one of the N-type transistors 011-N can both be connected to the output terminal out. The first terminal of one N-type transistor 011-N can be connected to the second terminal of another N-type transistor 011-N, and the first terminal of yet another N-type transistor 011-N can be grounded.

[0073] Furthermore, the inputs (labeled as in, a, b, and / or c) and outputs out of the three first NOT gates NTG-1 can be connected to the inputs of each of the eight second logic circuit groups 01-2 three-input NAND gates NAG-3, the output of the two-input NAND gate NAG-2 can be connected to one input of the NOR gate NOG in each second logic circuit group 01-2, and in each second logic circuit group 01-2, the output of the three-input NAND gate NAG-3 is connected to the other input of the NOR gate NOG, and the output of the NOR gate NOG is connected to the input of the second NOT gate NTG-2.

[0074] Figure 5 The diagram also schematically shows the three input terminals A0, A1, and A2 of the three first NOT gates NTG-1, the two input terminals A3 and A4 of the two-input NAND gates NAG-2, and the output terminals Z_n_ and Z_n of each of the second NOT gates NTG-2, where n refers to the nth second logic circuit group 01-2, and n is less than or equal to 8. For example, for Figure 5 Regarding the second logic circuit group 01-2 shown, the output terminals of its second NOT gate NTG-2 are labeled Z_2_ and Z_2, respectively. The output of the 3-to-8 decoder can be derived from the input signals A0, A1, and A2. The input signals A3 and A4 are used to enable the 3-to-8 decoder to have a selection function; the output timing of the 3-to-8 decoder is only valid when both input signals A3 and A4 are at active levels.

[0075] by Figures 5 to 9 The structure shown. Figure 10 The circuit structure diagram of the second second logic circuit group 011-2, arranged from top to bottom along the first direction X1, is shown. (Reference) Figure 10 It can be further seen that the second logic circuit group 011-2 includes a three-input NAND gate NAG-3+ an OR gate NOG+ a second NOT gate NTG-2 connected sequentially along the second direction X2.

[0076] exist Figure 10 Based on the structure shown, Figure 11 and Figure 12 The structural layout of the second logic circuit group 011-2 is shown respectively. Figure 11 and Figure 12 The difference lies in the drawing method. (Reference) Figure 11 and Figure 12 It can be seen that both the N-type transistor 011-N and the P-type transistor 011-P can have a gate layer G1 and a source / drain metal layer SD1 that are rectangular in top view. Furthermore, the gate layer G1 and the source / drain metal layer SD1 can overlap each other, and the length direction of the gate layer G1 can extend along a first direction X1, while the length direction of the source / drain metal layer SD1 can extend along a second direction X2. That is, the length directions of the gate layer G1 and the source / drain metal layer SD1 intersect. This further achieves the goal of making efficient use of space. The overlapping area of ​​the gate layer G1 and the source / drain metal layer SD1 is the channel region A1. Among them, Figure 11 The ditch area A1 is also schematically marked.

[0077] Optional, continue to refer to Figure 11 and Figure 12It can be seen that, in the two adjacent substrate isolation regions S1 of adjacent P-type transistors and N-type transistors in the first direction X1, the distance c between the side of one substrate isolation region S1 (e.g., the substrate isolation region S1 located below the channel region A1 in a P-type transistor) away from the other substrate isolation region S1 (e.g., the substrate isolation region S1 located above the channel region A1 in an N-type transistor) and the side of the other substrate isolation region S1 away from one substrate isolation region S1 is greater than the distance b between the channel regions A1 of two adjacent transistors of the same type in the second direction (i.e., c>b). This further ensures that a sufficiently large spacing can be maintained between the P-type transistors and the N-type transistors.

[0078] Optional, continue to refer to Figure 11 and Figure 12 It can also be seen that, for each of the P-type transistors and N-type transistors adjacent in the first direction X1, the spacing between the substrate isolation region S1 closer to the adjacent transistor and the channel region A1 of the transistor in the substrate isolation region included by the transistor is greater than the spacing between the substrate isolation region S1 farther from the adjacent transistor and the channel region A1 of the transistor.

[0079] like, Figure 11 and Figure 12 All examples use P-type transistors, see reference. Figure 11 and Figure 12 It can be seen that, within the substrate isolation region of a P-type transistor, the distance d between the substrate isolation region S1 closest to the adjacent N-type transistor (i.e., the substrate isolation region S1 located below the channel region A1) and the channel region A1 of the transistor is greater than the distance e between the substrate isolation region S1 furthest from the adjacent transistor (i.e., the substrate isolation region S1 located above the channel region A1) and the channel region A1 of the transistor. (i.e., d>e). This further ensures that a sufficiently large spacing is maintained between the P-type and N-type transistors.

[0080] Optional, combined Figure 11 and Figure 12 It can be seen that the spacing 'a' between the channel regions of adjacent P-type and N-type transistors in the first direction X1 can be greater than the difference between the width d01 of the P-type transistor's channel region and the width d02 of the N-type transistor, i.e., a > d01 - d02. Furthermore, the width d01 of the P-type transistor's channel region can also be greater than the width d02 of the N-type transistor. The direction of this width can be parallel to the first direction; that is, it can be the width of the longer side of the channel region. This further ensures that a sufficiently large spacing is maintained between the P-type and N-type transistors.

[0081] Optional, combined Figure 11 and Figure 12As can be seen, in this embodiment, the area of ​​the substrate isolation region S1 of the P-type transistor can be larger than the area of ​​the substrate isolation region S2 of the N-type transistor. Furthermore, for Figure 11 In the structure shown, the area of ​​the uppermost substrate isolation region S1 (i.e., the substrate isolation region S1 above the channel region A1 of the P-type transistor) can generally be the largest.

[0082] Optional, continue to refer to Figure 11 and Figure 12 As can be seen, in each logic circuit 011, the substrate isolation regions S1 of each P-type transistor 011-P located on the same side can be adjacent and flush in the second direction X2. The channel regions A1 of each P-type transistor 011-P can be spaced apart, and at least one side can be flush in the second direction X2. Similarly, the substrate isolation regions S1 of each N-type transistor 011-N located on the same side are adjacent and flush in the second direction X2. The channel regions A1 of each N-type transistor 011-N can be spaced apart, and at least one side can be flush in the second direction X2. That is, the substrate isolation regions S1 of each transistor located in the same row can be considered as a single unit, with the row direction parallel to the second direction X2. This achieves the goal of efficient space utilization and a rational layout.

[0083] exist Figure 11 and Figure 12 Based on the structure shown, Figure 13 and Figure 14 The layout diagrams of the second second logic circuit group 011-2 and its adjacent third second logic circuit group 011-2 are also shown. (Reference) Figure 13 and Figure 14 As can be seen, each pair of adjacent logic circuit groups 01 described in this embodiment can be mirror-symmetrically arranged along an axis L1 extending in the second direction X2. Accordingly, the transistors located on both sides of axis L1 can be of the same type. That is, for each pair of adjacent logic circuit groups 01, the two adjacent rows of transistors can both be N-type transistors or both be P-type transistors.

[0084] Example, Figure 13 and Figure 14 In the illustrated structure, the transistors located on both sides of axis L1 are N-type transistors for explanation. That is, in the second second logic circuit group 011-2 and its adjacent third second logic circuit group 011-2, along the first direction X1, they can be arranged in the order of one row of P-type transistors, one row of N-type transistors, one row of N-type transistors, and one row of P-type transistors.

[0085] Based on this, continue to refer to Figure 13 and Figure 14It can also be seen that, in the embodiments of this disclosure, in every two adjacent logic circuit groups 01, the transistors located on both sides of axis L1 can share the same substrate isolation region S1. This simplifies the structure, saves costs, and further facilitates layout. For example, for Figure 13 and Figure 14 In the structure shown, in the second second logic circuit group 011-2 and its adjacent third second logic circuit group 011-2, the two adjacent rows of N-type transistors share the same substrate isolation region S1.

[0086] Optional, see reference Figures 5 to 9 It can also be seen that each logic circuit 011 described in this embodiment can be connected to a first DC power line V1 and a second DC power line V2 respectively, and can be used to perform logic processing based on the signals provided by the first DC power line V1 and the second DC power line V2. For example, the first DC power line V1 can be a charging power line Vdd that provides a high-potential signal as shown in the figure. The second DC power line V2 can be a ground line GND that provides a low-potential signal.

[0087] Optional, combined Figure 15 In the partial structural layout shown in this embodiment of the disclosure, at least one of the first DC power line V1 and the second DC power line V2 has a width d1 in the second direction X2 that is greater than or equal to a width threshold. For example, the width threshold can be 5 micrometers (μm). The width d1 of both the first DC power line V1 and the second DC power line V2 in the second direction X2 can be equal to 5 μm.

[0088] In other words, the width of the DC power supply line connected to the decoding circuit described in this embodiment can be relatively wide. This configuration reduces the sheet resistance on the signal line, thereby reducing the IR drop and further preventing latch-up. Sheet resistance refers to the resistance of a rectangular conductor in the direction of current flow. Within the limits of the overall area of ​​the decoding circuit, the wider the DC power supply line, the better.

[0089] Continue to refer to Figure 15 It can be seen that the first DC power line V1 (e.g., Vdd) and the second DC power line V2 (e.g., GND) can be located on both sides of the multiple logic circuit groups O1 in the second direction X2, and can both extend along the first direction X1. Furthermore, the width of the first DC power line V1 in the second direction X2 and the width of the second DC power line V2 in the second direction X2 can be equal. This further achieves the goal of making reasonable use of space and ensures that the voltage drop on the two DC power lines providing different potentials is equal.

[0090] In addition, combined Figure 11It can also be seen that the substrate isolation region S1 located on both sides of the channel region A1 in the P-type transistor can be connected to the first DC power line V1 (e.g., vdd) to receive power signals at the same potential. The substrate isolation region S1 located on both sides of the channel region A1 in the N-type transistor can be connected to the second DC power line V1 (e.g., GND) to receive power signals at the same potential.

[0091] Optional, in Figure 15 Based on the structure shown, Figure 16 A partial routing layout is shown. Figure 17 A cross-sectional view of the trace is shown. (Reference) Figure 16 and Figure 17 As can be seen, the decoding circuit described in this embodiment can be located on one side of the substrate (or a substrate). Furthermore, in this decoding circuit, the interconnected parts can be connected by multiple layers of metal traces stacked sequentially in a direction away from the substrate, and each pair of adjacent metal traces can overlap each other through vias. The overlap area of ​​each pair of adjacent metal traces can be less than an area threshold. That is, a smaller overlap area reduces parasitic capacitance and also achieves efficient use of space, further increasing the linewidth.

[0092] Example, Figure 16 and Figure 17 In the decoding circuit shown, the interconnected parts are connected by three layers of metal traces: a first metal trace M1, a second metal trace M2, and a third metal trace M3, which are stacked sequentially along the direction away from the substrate isolation region S1.

[0093] Among them, reference Figure 16 As can be seen, the first metal trace M1 may include multiple line segments extending along the first direction X1 and multiple line segments extending along the second direction X2, the second metal trace M2 may include multiple line segments extending along the second direction X2, and the third metal trace M3 may include multiple line segments extending along the first direction X1. The first DC power supply line V1 (e.g., Vdd) and the second DC power supply line V2 (e.g., GND) connected to each logic circuit 011 can both be located on the same layer as the third metal trace M3. That is, excluding the first metal trace M1, the second metal trace M2 can be laid out in a horizontal (length direction extending along the second direction X2) routing manner, and the third metal trace M3 can be laid out in a vertical (length direction extending along the first direction X1) routing manner.

[0094] It should be noted that, Figure 17 In the cross-sectional diagram shown, PWELL refers to a P-well, NWELL to an N-well, N+ to a doped N-ion, P+ to a doped P-ion, and PSUB to the substrate isolation region. poly refers to the active layer, and CT, V1, and V2 all refer to vias used to connect different layers. Figure 17 The one shown is an NMOS.

[0095] Taking the above attached diagram as an example, Figure 18 The overall layout of a 3-to-8 decoder is shown. Figure 19 The routing layout of a 3-to-8 decoder is shown in the overall structure diagram. (Reference) Figure 18 and Figure 19 As described in the above embodiments, the layout design provided by this disclosure can be used to implement 3-8 decoding functions. Of course, in some other embodiments, other decoding functions can also be implemented. Furthermore, on one hand, this disclosure reduces latch-up effects by increasing the spacing between NMOS and PMOS transistors and by increasing the connection method of the substrate isolation region contact holes. Based on this, by mirroring each two adjacent logic circuit groups, transistors of the same type in different logic circuit groups can be adjacent, thereby achieving the goal of sharing the substrate isolation region and making reasonable use of space. On the other hand, this disclosure reduces sheet resistance and lowers the impact of voltage by increasing the linewidth of the DC power supply lines. Furthermore, this disclosure can also reduce the impact of parasitic capacitance on the operation of the decoding circuit by rationally arranging metal traces, reducing overlapping area, and widening traces. Through layout optimization, this disclosure not only follows the original design rules but also achieves better beneficial effects and improves layout reliability.

[0096] In summary, this disclosure provides a decoding circuit. The decoding circuit includes multiple logic circuit groups arranged along a first direction. Each logic circuit group includes multiple logic circuits arranged along a second direction intersecting the first direction. Each logic circuit also includes N-type transistors and P-type transistors. Furthermore, in each logic circuit group, each N-type transistor and each P-type transistor are arranged along the second direction, while the N-type and P-type transistors are arranged along the first direction. The substrate isolation region of each transistor is located on both sides of the transistor in the first direction, and a transition hole arranged along the second direction is formed on the substrate isolation region. Thus, the P-type transistor and N-type transistor can be isolated by the substrate isolation region with the transition hole, making the spacing between adjacent P-type and N-type transistors greater than the spacing between two adjacent transistors of the same type (e.g., N-type or P-type transistors), ensuring that the N-type and P-type transistors maintain a sufficiently large spacing. This avoids mutual interference between different types of transistors, resulting in better circuit stability and preventing latch-up effects.

[0097] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 20As shown, the display device includes a panel driving circuit 100 and a display panel 000. The panel driving circuit 100 is connected to the display panel 000 and is used to drive the display panel 000 to display. The panel driving circuit 000 may include a decoding circuit 00 as described in the above embodiments.

[0098] Optionally, the display device described in this disclosure can be a silicon-based microdisplay. That is, the decoding circuit described in this disclosure can be applied to silicon-based products, such as silicon-based organic light-emitting diode (OLED) products. Of course, in some other embodiments, the display device can also be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, or navigator.

[0099] It should be understood that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0100] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0101] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0102] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0103] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "linkage" refers to an electrical connection.

[0104] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0105] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A decoding circuit, characterized in that, The decoding circuit is a 3-to-8 decoding circuit; The decoding circuit includes: a plurality of logic circuit groups arranged sequentially and interconnected along a first direction; The plurality of logic circuit groups are divided into a first logic circuit group and eight second logic circuit groups arranged sequentially along the first direction. Each of the logic circuit groups includes: a plurality of logic circuits arranged sequentially and interconnected along a second direction, the second direction intersecting the first direction; each of the logic circuits includes: at least one N-type transistor and at least one P-type transistor interconnected. The first logic circuit group includes multiple logic circuits: three first NOT gates and one two-input NAND gate arranged sequentially along the second direction; each second logic circuit group includes multiple logic circuits: one three-input NAND gate, one NOR gate and one second NOT gate arranged sequentially along the second direction; the first NOT gate and the second NOT gate each include one N-type transistor and one P-type transistor, the two-input NAND gate and the NOR gate each include two N-type transistors and two P-type transistors, and the three-input NAND gate includes three N-type transistors and three P-type transistors. Furthermore, the input and output terminals of the three first NOT gates are respectively connected to the input terminals of each three-input NAND gate in the eight second logic circuit groups, the output terminal of the two-input NAND gate is connected to one input terminal of the NOR gate in each second logic circuit group, and in each second logic circuit group, the output terminal of the three-input NAND gate is connected to the other input terminal of the NOR gate, and the output terminal of the NOR gate is connected to the input terminal of the second NOT gate; Furthermore, both the N-type transistor and the P-type transistor have a channel region and a substrate isolation region. The substrate isolation region is located on both sides of the channel region in the first direction, and a plurality of transition holes are formed on the substrate isolation region in sequence along the second direction for connecting the required parts. In each of the logic circuit groups, the N-type transistors and P-type transistors of the multiple logic circuits are arranged sequentially along the second direction. The P-type transistors and the N-type transistors are arranged sequentially along the first direction, and the spacing between the channel regions of adjacent P-type transistors and N-type transistors in the first direction is greater than the spacing between the channel regions of two adjacent transistors of the same type in the second direction. The transistors of the same type include P-type transistors and N-type transistors.

2. The decoding circuit according to claim 1, characterized in that, Each pair of adjacent logic circuit groups is arranged in a mirror image symmetrically along an axis extending in the second direction.

3. The decoding circuit according to claim 2, characterized in that, In each pair of adjacent logic circuit groups, the transistors located on both sides of the axis share the same substrate isolation region.

4. The decoding circuit according to any one of claims 1 to 3, characterized in that, In the first direction, the distance between the side of one substrate isolation region away from the other substrate isolation region and the side of the other substrate isolation region away from the first substrate isolation region in the adjacent P-type transistor and N-type transistor is greater than the distance between the channel regions of two adjacent transistors of the same type in the second direction.

5. The decoding circuit according to any one of claims 1 to 3, characterized in that, For each of the P-type and N-type transistors adjacent in the first direction, the spacing between the substrate isolation region of the transistor closer to the adjacent transistor and the channel region of the transistor is greater than the spacing between the substrate isolation region of the transistor farther from the adjacent transistor and the channel region of the transistor.

6. The decoding circuit according to any one of claims 1 to 3, characterized in that, The spacing between the channel regions of adjacent P-type transistors and N-type transistors in the first direction is greater than the difference between the width of the channel region of the P-type transistor and the width of the N-type transistor, and the width of the channel region of the P-type transistor is greater than the width of the N-type transistor, wherein the direction of the width is parallel to the first direction.

7. The decoding circuit according to any one of claims 1 to 3, characterized in that, The area of ​​the substrate isolation region of the P-type transistor is larger than the area of ​​the substrate isolation region of the N-type transistor.

8. The decoding circuit according to any one of claims 1 to 3, characterized in that, In each of the logic circuits, the substrate isolation regions of each P-type transistor are adjacent on the same side and are flush in the second direction, and the channel regions of each P-type transistor are spaced apart from each other and at least one side is flush in the second direction. Furthermore, the substrate isolation regions of each N-type transistor are adjacent on the same side and flush in the second direction, and the channel regions of each N-type transistor are spaced apart from each other and at least one side is flush in the second direction.

9. The decoding circuit according to any one of claims 1 to 3, characterized in that, Both the N-type transistor and the P-type transistor have a gate layer and a source / drain metal layer that are rectangular in top view. Furthermore, the gate layer and the source / drain metal layer overlap each other, and the length direction of the gate layer extends along the first direction, while the length direction of the source / drain metal layer extends along the second direction; The overlapping region of the gate layer and the source / drain metal layer is the channel region.

10. The decoding circuit according to any one of claims 1 to 3, characterized in that, Each of the logic circuits is also connected to a first DC power line and a second DC power line respectively, and is used to perform logic processing based on the signals provided by the first DC power line and the signals provided by the second DC power line. Among them, at least one of the first DC power lines and the second DC power lines has a width in the second direction that is greater than or equal to a width threshold.

11. The decoding circuit according to claim 10, characterized in that, The first DC power line and the second DC power line are respectively located on both sides of the plurality of logic circuit groups in the second direction, and both extend along the first direction, and the width of the first DC power line in the second direction and the width of the second DC power line in the second direction are equal.

12. The decoding circuit according to any one of claims 1 to 3, characterized in that, The decoding circuit is located on one side of the substrate, and the interconnected parts of the decoding circuit are connected by multiple layers of metal traces stacked sequentially in a direction away from the substrate, and each pair of adjacent metal traces overlaps with each other through vias, and the overlapping area is less than the area threshold.

13. The decoding circuit according to claim 12, characterized in that, In the decoding circuit, the interconnected parts are connected by three layers of metal traces: a first metal trace, a second metal trace, and a third metal trace, which are stacked sequentially along a direction away from the substrate. Wherein, the first metal trace includes multiple line segments extending along the first direction and multiple line segments extending along the second direction, the second metal trace includes multiple line segments extending along the second direction, and the third metal trace includes multiple line segments extending along the first direction. Furthermore, the first DC power line and the second DC power line connected to each of the logic circuits are located on the same layer as the third metal trace.

14. A display device, characterized in that, The display device includes: a panel driving circuit and a display panel, wherein the panel driving circuit is connected to the display panel and is used to drive the display panel to display; The panel driving circuit includes the decoding circuit as described in any one of claims 1 to 13.

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