List-based Hierarchical Statistical Decoding Method, Device, Apparatus and Storage Medium

Abstract

The present invention provides a list-based hierarchical statistical decoding method, device, apparatus and storage medium. By obtaining a first log-likelihood ratio sequence, a first hard decision bit sequence and a first parity check matrix corresponding to a sequence to be decoded and performing a first reordering; based on the first hard decision bit sequence after the first reordering, obtaining a second hard decision bit sequence; starting from the last bit of the second hard decision bit sequence, performing a decoding path search in the reverse order, performing path expansion at each non-parity check bit and performing path update at each parity check bit to determine the path metric value of each current sub-path; selecting the sub-path with the smallest total path metric value, determining the decoded codeword corresponding to the second hard decision bit sequence, and performing sequential recovery to obtain the decoded codeword result of the sequence to be decoded, which improves the performance of the linear block code decoding algorithm in the scenario of short codes and high code rates and reduces the complexity.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to an ordered statistics decoding method, device, apparatus, and storage medium based on a list. Background Art

[0002] All linear block codes can be decoded by near-maximum likelihood (near-ML) methods, such as guessing random additive noise decoding (GRAND), sphere decoding (SD), and ordered statistics decoding (OSD). So far, there has not been a linear block code decoding algorithm with good performance and low complexity in the scenario of short codes and high code rates. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention provides an ordered statistics decoding method, device, apparatus, and storage medium based on a list.

[0004] In a first aspect, the present invention provides an ordered statistics decoding method based on a list, including:

[0005] Obtaining a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity-check matrix corresponding to a sequence to be decoded; wherein, the lengths of the first log-likelihood ratio sequence and the first hard decision bit sequence are N, the number of parity-check bits in the first hard decision bit sequence is M, the first parity-check matrix is a matrix of M×N, M and N are integers greater than 0, and N is greater than M;

[0006] Performing a first reordering on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly performing a first reordering on the first hard decision bit sequence and the columns of the first parity-check matrix;

[0007] Obtaining a second hard decision bit sequence based on the first hard decision bit sequence after the first reordering; the first M bits of the second hard decision bit sequence are parity-check bits, and the last N-M bits of the second hard decision bit sequence are non-parity-check bits;

[0008] Starting from the last bit of the second hard decision bit sequence, perform a decoding path search in reverse order. Perform path extension at each non-parity bit and determine the path metric value of each sub-path after the current extension corresponding to the non-parity bit. Perform path update at each parity bit and determine the path metric value of each sub-path corresponding to the parity bit for the current path.

[0009] Select the sub-path with the minimum total path metric value, determine the decoded codeword corresponding to the second hard decision bit sequence, and perform sequential recovery to obtain the decoded codeword result of the sequence to be decoded.

[0010] Optionally, performing path extension at any non-parity bit includes:

[0011] Perform path extension according to the two cases where the decoded bit value at the non-parity bit is 0 and 1, to obtain l×2 sub-paths; where l is the number of sub-paths before the current path extension.

[0012] Optionally, determining the path metric value of each sub-path after the current extension corresponding to any non-parity bit includes:

[0013] When the decoded bit value of the target sub-path corresponding to the non-parity bit is the same as the hard decision bit value at the non-parity bit, determine that the path metric value of the non-parity bit corresponding to the target sub-path is equal to the path metric value of the target sub-path corresponding to the bit after the non-parity bit in the second hard decision bit sequence.

[0014] When the decoded bit value of the target sub-path corresponding to the non-parity bit is different from the hard decision bit value at the non-parity bit, add the absolute value of the log-likelihood ratio corresponding to the non-parity bit to the path metric value of the target sub-path corresponding to the bit after the non-parity bit in the second hard decision bit sequence, to obtain the path metric value of the non-parity bit corresponding to the target sub-path.

[0015] Optionally, performing path update at each parity bit and determining the path metric value of each sub-path corresponding to any parity bit includes:

[0016] Determine the decoded bit value of the target sub-path corresponding to the m-th parity bit in the second hard decision bit sequence according to the result obtained by performing binary addition after multiplying each element in the m-th row of the second matrix by the decoded bit value of each non-parity bit corresponding to the target sub-path in the second hard decision bit sequence; where the second matrix is a sub-matrix of the last N - M columns of the parity check matrix obtained by performing the first reordering on the columns of the first parity check matrix and then performing Gaussian elimination; m is an integer greater than 0 and less than or equal to M.

[0017] Determine the path metric value corresponding to the m-th check bit for the target sub-path according to the decoded bit value corresponding to the m-th check bit for the target sub-path.

[0018] Optionally, the determining the path metric value corresponding to the m-th check bit for the target sub-path according to the decoded bit value corresponding to the m-th check bit for the target sub-path includes:

[0019] Multiply the result obtained by performing binary addition on the decoded bit value corresponding to the m-th check bit for the target sub-path and the hard decision bit value on the m-th check bit by the absolute value of the log-likelihood ratio corresponding to the m-th check bit, and add the result of the multiplication to the path metric value corresponding to the target sub-path of the bit after the m-th check bit in the second hard decision bit sequence, to obtain the path metric value corresponding to the m-th check bit for the target sub-path.

[0020] Optionally, the obtaining the second hard decision bit sequence based on the first hard decision bit sequence after the first reordering includes:

[0021] Use the first hard decision bit sequence after the first reordering as the second hard decision bit sequence; or,

[0022] Perform Gaussian elimination on the first check matrix after the first reordering, and according to the arrangement order of the columns in the first check matrix after Gaussian elimination, perform a second reordering on the first hard decision bit sequence after the first reordering to obtain the second hard decision bit sequence.

[0023] In a second aspect, the present invention further provides a list-based hierarchical statistical decoder, including: a Gaussian elimination module, a pivot memory, a metric sorter, a path memory, and a check memory;

[0024] The Gaussian elimination module is configured to perform Gaussian elimination on the received check matrix after the first reordering; wherein, the check matrix after the first reordering is a matrix obtained by reordering the first check matrix corresponding to the sequence to be decoded according to the ascending order of the absolute values of the elements in the first log-likelihood ratio sequence corresponding to the sequence to be decoded.

[0025] The pivot memory is configured to store and store the sorting index after the Gaussian elimination module performs Gaussian elimination on the check matrix;

[0026] The metric sorter is used to receive the decoded bit values sent by the path memory and the parity check memory, calculate the path metrics corresponding to the decoded bit values based on the decoded bit values, the log-likelihood ratio sequence after the first reordering, and the hard decision bit sequence corresponding to the log-likelihood ratio sequence, calculate the total path metrics of each sub-path of the decoded paths, and sort each sub-path of the decoded paths based on the total path metrics of each sub-path of the decoded paths and store the total path metrics of each sub-path of the decoded paths;

[0027] The path memory is used to perform path extension on the decoded paths at each non-parity check bit and determine the decoded bit values corresponding to each sub-path of the decoded paths at the non-parity check bit after the path extension;

[0028] The parity check memory is used to receive the matrix sent by the Gaussian elimination module and the decoded bit values corresponding to the non-parity check bits on each sub-path of the decoded paths sent by the path memory, and determine the decoded bit values corresponding to the parity check bits on each sub-path of the decoded paths based on the matrix and the decoded bit values corresponding to the non-parity check bits on each sub-path of the decoded paths.

[0029] Optionally, the decoder further includes:

[0030] A bitonic sorter, a log-likelihood ratio memory, a parity check matrix memory, and an order recovery module;

[0031] The bitonic sorter is used to sort the elements in the received sequence in ascending order of absolute value and output the sorting index;

[0032] The log-likelihood ratio memory is used to obtain and store the log-likelihood ratio sequence, obtain and store the hard decision bit sequence corresponding to the log-likelihood ratio sequence based on the log-likelihood ratio sequence; it is further used to receive the sorting index sent by the bitonic sorter, and read and output the stored log-likelihood ratio sequence and the hard decision bit sequence corresponding to the log-likelihood ratio sequence based on the sorting index;

[0033] The parity check matrix memory is used to obtain and store the parity check matrix, and receive the sorting index sent by the bitonic sorter, and read and output the columns of the stored parity check matrix based on the sorting index;

[0034] The pivot memory is further used to receive and store the sorting index sent by the bitonic sorter;

[0035] The metric sorter is further used to receive the log-likelihood ratio sequence after the first reordering and the hard decision bit sequence corresponding to the log-likelihood ratio sequence sent by the log-likelihood ratio memory;

[0036] The sequential recovery module is configured to receive the total path metrics and the corresponding codewords of each decoding path sub-path sent by the path memory and the parity memory, and the sorting index sent by the pivot memory. Based on the total path metrics of each decoding path sub-path, it determines the decoding path sub-path with the smallest total path metric, and based on the received sorting index, sequentially recovers the codeword corresponding to the decoding path sub-path with the smallest total path metric to obtain the decoded bits and output them.

[0037] In a third aspect, the present invention further provides a list-based hierarchical statistical decoding device, including:

[0038] A first acquisition module, configured to acquire a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity-check matrix corresponding to a sequence to be decoded; wherein the lengths of the first log-likelihood ratio sequence and the first hard decision bit sequence are N, the number of parity-check bits in the first hard decision bit sequence is M, the first parity-check matrix is an M×N matrix, M and N are integers greater than 0, and N is greater than M;

[0039] A sorting module, configured to perform a first re-sorting on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly perform a first re-sorting on the first hard decision bit sequence and the columns of the first parity-check matrix;

[0040] A second acquisition module, configured to obtain a second hard decision bit sequence based on the first hard decision bit sequence after the first re-sorting; the first M bits of the second hard decision bit sequence are parity-check bits, and the last N-M bits of the second hard decision bit sequence are non-parity-check bits;

[0041] A first determination module, starting from the last bit position of the second hard decision bit sequence, performs decoding path search in reverse order, performs path extension at each non-parity-check bit position and determines the path metric of each sub-path after the current extension corresponding to the non-parity-check bit position, and performs path update at each parity-check bit position to determine the path metric of each current sub-path corresponding to the parity-check bit position;

[0042] A second determination module, selects the sub-path with the smallest total path metric, determines the decoding codeword corresponding to the second hard decision bit sequence, and sequentially recovers to obtain the decoding codeword result of the sequence to be decoded.

[0043] In a fourth aspect, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, it implements the list-based hierarchical statistical decoding method described in the first aspect above.

[0044] In a fifth aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the list-based hierarchical statistical decoding method described in the first aspect above is implemented.

[0045] The list-based hierarchical statistical decoding method, device, apparatus, and storage medium provided by the present invention reorder the hard decision bit sequence corresponding to the sequence to be decoded, and start the decoding path search from the non-parity bit positions with high reliability, and perform path extension on the non-parity bit positions, improving the performance of the decoding algorithm in the scenario of short codes and high code rates. While not performing path extension on the parity bit positions and only performing path update, it can effectively reduce the complexity of the decoding algorithm, so that the decoding algorithm provided by the present invention can not only improve the performance in the scenario of short codes and high code rates, but also reduce the complexity of the algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0047] Figure 1 is one of the flow diagrams of the list-based hierarchical statistical decoding method provided by the present invention;

[0048] Figure 2 is the second flow diagram of the list-based hierarchical statistical decoding method provided by the present invention;

[0049] Figure 3 is the structural diagram of the list-based hierarchical statistical decoder provided by the present invention;

[0050] Figure 4 is the structural diagram of the list-based hierarchical statistical decoding apparatus provided by the present invention;

[0051] Figure 5 is the structural diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0053] Channel coding and decoding is an essential part of communication systems. The polar code proposed in 2009 is the coding scheme for the control channel in the 5th generation mobile communication (5G) standard. The classic decoding scheme for polar codes is the successive cancellation (SC) decoding algorithm. The SC algorithm calculates the log-likelihood ratio (LLR) corresponding to each bit one by one based on recursive coding constraints. However, since only one estimated codeword is output, the performance of the SC decoding algorithm for finite-length codes is not ideal. The successive cancellation list (SCL) decoding algorithm improves performance by maintaining a list of candidate codewords. However, SC and SCL decoding also bring problems with internal LLR storage. Specifically, when the code length is N, in addition to the N received LLRs, the SC decoder requires N - 1 additional internal LLRs. If the list size of the SCL decoder is L, the storage requirement for internal LLRs increases to L(N - 1).

[0054] All linear block codes can be decoded by near-ML methods such as GRAND, SD, and OSD. The near-ML decoding algorithm reduces the search space of the maximum likelihood (ML) decoding algorithm and returns the codeword closest to the received signal within this search space. Therefore, different from SC and SCL, the near-ML decoding algorithm only requires the received LLRs and does not require a large number of internal LLRs.

[0055] The three near-ML decoding algorithms mentioned above are as follows:

[0056] 1. GRAND is a simple and practical algorithm that guesses the noise sequence by bit flipping. Ordered Reliability Bits (ORB) GRAND is a soft-input GRAND. ORBGRAND uses the logistic weight (LW) to generate effective error types, significantly reducing the number of attempts.

[0057] 2. SD serially estimates from the last bit, encodes, and calculates the path metric value. Once the path metric value of a certain attempt exceeds the cardinality of a predefined sphere, the search stops. Finally, the SD algorithm returns the ML solution within the sphere. List sphere decoding (List-SD) applies breadth-first search to SD, and for each bit estimate, at most L candidate codeword paths will be retained.

[0058] 3. First, the OSD divides the codewords into two groups according to the magnitudes of the absolute values of the received LLRs: K bits at the most reliable independent positions (MRIPs) and M bits at the least reliable positions (LRPs). The OSD decoder obtains the K bits at the MRIPs by hard decision, and then regenerates the M bits at the LRPs by using the generator matrix G. By flipping at most ω bits at the MRIPs, the OSD of order ω, i.e., OSD-ω, can obtain more candidate codewords.

[0059] The SCL decoder has the following problems:

[0060] 1. The decoder requires a large amount of internal LLR storage, which will increase the resources and area in circuit implementation.

[0061] 2. The short code performance of the SCL algorithm is not ideal enough to meet the performance requirements in short code scenarios.

[0062] The three near-ML algorithms face the following problems:

[0063] 1. GRAND has very poor bit error rate performance in medium and low code rate scenarios, and has a relatively high worst-case hardware latency.

[0064] 2. List-SD is significantly affected by forward error propagation when the confidence of the last bit is low, resulting in a large gap in bit error rate performance compared with the SCL algorithm.

[0065] 3. OSD is difficult to be efficiently implemented in hardware due to the high complexity of the Gaussian elimination it requires.

[0066] So far, there has not been a linear block code decoding algorithm with good performance and low complexity in short code scenarios at various code rates, and there has not been an application specific integrated circuit (ASIC) implementation result of a decoder based on OSD.

[0067] Therefore, the present invention proposes a list-based hierarchical statistical decoding algorithm and its hardware implementation method to solve the above problems.

[0068] Figure 1 One of the flow diagrams of the list-based hierarchical statistical decoding method provided by the present invention is as Figure 1 shown, and the method includes:

[0069] Step 100: Obtain a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity-check matrix corresponding to the sequence to be decoded; wherein, the length of the first log-likelihood ratio sequence and the first hard decision bit sequence is N, the number of parity-check bits in the first hard decision bit sequence is M, the first parity-check matrix is an M×N matrix, M and N are integers greater than 0, and N is greater than M.

[0070] Specifically, the element at each position in the first log-likelihood ratio sequence is the value of the log-likelihood ratio corresponding to the corresponding bit position of the sequence to be decoded.

[0071] The first hard decision bit sequence can be determined according to the sign of each element in the first log-likelihood ratio sequence. For example, if the element at a certain position in the first log-likelihood ratio sequence is greater than or equal to 0, the value of the corresponding bit position in the first hard decision bit sequence is 0; if the element at a certain position in the first log-likelihood ratio sequence is less than 0, the value of the corresponding bit position in the first hard decision bit sequence is 1.

[0072] The result of multiplying the first parity-check matrix by the transpose of the sequence to be decoded is 0.

[0073] In one implementation, the relationship between the first parity-check matrix and the sequence to be decoded can be expressed as:

[0074] H·C T =0

[0075] wherein, H is the first parity-check matrix, C is the sequence to be decoded, and C T is the transpose of the sequence to be decoded.

[0076] The length of the first log-likelihood ratio sequence and the first hard decision bit sequence is N, the number of parity-check bits in the first hard decision bit sequence is M, the first parity-check matrix is an M×N matrix, M and N are integers greater than 0, and N is greater than M.

[0077] Step 101: Perform a first reordering on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly perform a first reordering on the first hard decision bit sequence and the columns of the first parity-check matrix.

[0078] Specifically, arrange the elements in the first log-likelihood ratio sequence in ascending order of their absolute values, and record the order of change of the elements in the rearranged first log-likelihood ratio sequence relative to the elements in the original first log-likelihood ratio sequence as the first order. Reorder the first hard decision bit sequence and the columns of the first parity-check matrix according to the first order as well.

[0079] For example, the first log-likelihood ratio sequence is (0.3, -0.1, 0.4, -0.2), the first hard decision bit sequence is (0, 1, 0, 1), and the first parity-check matrix is After sorting the first pair of log-likelihood ratio sequences in the first order, the new sequence is (-0.1, -0.2, 0.3, 0.4). The first order is: swap the element in the original first position to the third position, swap the element in the original second position to the first position, swap the element in the original third position to the fourth position, and swap the element in the original fourth position to the second position. Sort the first hard decision bit sequence in the first order, and the new sequence obtained is (1, 1, 0, 0). Sort the columns of the first parity-check matrix in the first order, and the new matrix obtained is

[0080] Step 102: Obtain a second hard decision bit sequence based on the first hard decision bit sequence after the first reordering; the first M bits of the second hard decision bit sequence are parity bits, and the last N - M bits of the second hard decision bit sequence are non-parity bits.

[0081] Specifically, after obtaining the first hard decision bit sequence after the first reordering, the second hard decision bit sequence can be obtained according to the first hard decision bit sequence after the first reordering.

[0082] Optionally, obtaining the second hard decision bit sequence based on the first hard decision bit sequence after the first reordering can be taking the first hard decision bit sequence after the first reordering as the second hard decision bit sequence; or, it can be performing Gaussian elimination on the first parity-check matrix after the first reordering, and sorting the first hard decision bit sequence after the first reordering in the second order according to the arrangement order of the columns in the first parity-check matrix after Gaussian elimination to obtain the second hard decision bit sequence.

[0083] In one implementation, the first hard decision bit sequence after the first reordering can be directly used as the second hard decision bit sequence for subsequent operations.

[0084] In one implementation, Gaussian elimination can also be performed on the first parity-check matrix after the first reordering, and the arrangement order of the columns of the first parity-check matrix after Gaussian elimination relative to the first parity-check matrix after the first reordering is denoted as the second order. Sorting the first hard decision bit sequence after the first reordering in the second order can obtain the second hard decision bit sequence, and this process is similar to sorting each sequence in the first order above and will not be described in detail here.

[0085] Step 103: Starting from the last bit of the second hard decision bit sequence, perform decoding path search in the reverse order. At each non - parity bit, perform path extension and determine the path metric value of each sub - path after the current extension corresponding to the non - parity bit. At each parity bit, perform path update and determine the path metric value of each sub - path corresponding to the parity bit at the current time.

[0086] Specifically, after obtaining the second hard decision bit sequence, decoding path search can be performed starting from the last bit of the second hard decision bit sequence in the reverse order. For example, if the length of the second hard decision bit sequence is 9, decoding path search can start from the ninth bit of the second hard decision bit sequence, then the eighth bit, the seventh bit... until the first bit of the second hard decision bit sequence.

[0087] When performing decoding path search in the second hard decision bit sequence, when a non - parity bit is searched, path extension can be performed on the decoding path at this non - parity bit.

[0088] Optionally, path extension at any non - parity bit can be performed according to the two cases where the decoded bit value at the non - parity bit is 0 and 1, to obtain l×2 sub - paths; where l is the number of sub - paths before the current path extension.

[0089] For example, starting decoding path search from the last bit of the second hard decision bit sequence, the initial decoding path has only one, which is empty. At this time, the target bit of the second hard decision bit sequence is a non - parity bit, so the current decoding path can be extended. According to the two cases where the decoded bit value at the non - parity bit is 0 and 1, two decoding path sub - paths are obtained, which are 0 and 1 respectively; then perform path search from the penultimate bit of the second hard decision bit sequence. If the target bit is a non - parity bit, the current decoding path can continue to be extended. According to the two cases where the decoded bit value at the non - parity bit is 0 and 1, four decoding path sub - paths are obtained, which are 0 - 0, 0 - 1, 1 - 0, and 1 - 1 respectively.

[0090] The path metric value can be used to indicate the reliability of the decoding path. The smaller the path metric value, the higher the reliability of the path.

[0091] When performing decoding path search in the second hard decision bit sequence, when a parity bit is searched, there is no need to perform path extension on the decoding path. Instead, according to the current path extension result of the non - parity bits and the second matrix, calculate the decoded bit value of this parity bit on each decoding path sub - path, and then update the path metric value of the decoding path sub - path.

[0092] If the decoding path is extended, it is necessary to determine the path metric value of each sub-path after the current extension corresponding to the non-parity bits; if the decoding path is not extended, it is necessary to determine the path metric value of each sub-path corresponding to the parity bits.

[0093] In one implementation, in order to reduce the complexity of the decoding process, when the decoding path is extended and the number of sub-paths of the decoding path is greater than the preset upper limit L of the number of sub-paths, the current sub-paths of the decoding path can be sorted in ascending order of the total path metric value, and the L sub-paths of the decoding path with the lowest total path metric value (i.e., the most reliable ones) are selected and retained.

[0094] Step 104: Select the sub-path with the smallest total path metric value, determine the decoded codeword corresponding to the second hard decision bit sequence, and perform sequential recovery to obtain the decoded codeword result of the sequence to be decoded.

[0095] Specifically, when the search for the decoding path in the second hard decision bit sequence is completed, the sub-path with the smallest total path metric value can be selected from the obtained multiple sub-paths of the decoding path, and the decoded codeword corresponding to this sub-path is used as the decoded codeword corresponding to the second hard decision bit sequence.

[0096] If the second hard decision bit sequence is the first hard decision bit sequence after the first reordering, the decoded codeword corresponding to the second hard decision bit sequence is sequentially recovered according to the operation opposite to the first reordering, and the decoded codeword result of the sequence to be decoded can be obtained. If the second hard decision bit sequence is a sequence obtained by performing a second reordering on the first hard decision bit sequence after the first reordering, then first perform the operation opposite to the second reordering, and then perform the operation opposite to the first reordering on the decoded codeword corresponding to the second hard decision bit sequence to obtain the decoded codeword result of the sequence to be decoded.

[0097] For example, the length of the first hard decision bit sequence is 4, and the order of the first reordering is: swap the element in the original first position to the third position, swap the element in the original second position to the first position, swap the element in the original third position to the fourth position, and swap the element in the original fourth position to the second position.

[0098] Then the operation opposite to the first reordering is: swap the element in the original second position to the fourth position, swap the element in the original fourth position to the third position, swap the element in the original first position to the second position, and swap the element in the original third position to the first position. For example, for a certain sequence (1, 2, 3, 4), the sequence obtained by sequential recovery according to the operation opposite to the first reordering is (3, 1, 4, 2).

[0099] The same understanding can also be applied to the operation with reversed second-level sorting.

[0100] The list-based hierarchical statistical decoding method provided by the present invention reorders the hard decision bit sequence corresponding to the sequence to be decoded, and starts the decoding path search from the non-parity bit positions with high reliability. Path expansion is performed on the non-parity bit positions, improving the performance of the decoding algorithm in the scenario of short codes with high code rates. While path expansion is not performed on the parity bit positions, only path update is carried out, which can effectively reduce the complexity of the decoding algorithm. Thus, the decoding algorithm provided by the present invention can not only improve the performance in the scenario of short codes with high code rates, but also reduce the complexity of the algorithm.

[0101] Optionally, determining the path metric value of each sub-path after current expansion corresponding to any non-parity bit position includes:

[0102] When the decoded bit value of the target sub-path corresponding to the non-parity bit position is the same as the hard decision bit value on the non-parity bit position, determining that the path metric value of the target sub-path corresponding to the non-parity bit position is equal to the path metric value of the target sub-path corresponding to the next bit position of the non-parity bit position in the second hard decision bit sequence;

[0103] When the decoded bit value of the target sub-path corresponding to the non-parity bit position is different from the hard decision bit value on the non-parity bit position, adding the absolute value of the log-likelihood ratio corresponding to the non-parity bit position to the path metric value of the target sub-path corresponding to the next bit position of the non-parity bit position in the second hard decision bit sequence to obtain the path metric value of the target sub-path corresponding to the non-parity bit position.

[0104] Specifically, when it is necessary to determine the path metric value of each sub-path after current expansion corresponding to any non-parity bit position, the decoded bit value of the target sub-path corresponding to the non-parity bit position can be first compared with the hard decision bit value on the non-parity bit position.

[0105] When the decoded bit value of the target sub-path corresponding to the non-parity bit position is the same as the hard decision bit value on the non-parity bit position, the path metric value of the target sub-path corresponding to the non-parity bit position is equal to the path metric value of the target sub-path corresponding to the next bit position of the non-parity bit position in the second hard decision bit sequence.

[0106] When the decoded bit value of the target sub-path corresponding to the non-parity bit position is different from the hard decision bit value on the non-parity bit position, the path metric value of the target sub-path corresponding to the non-parity bit position is equal to the sum of the path metric value of the target sub-path corresponding to the next bit position of the non-parity bit position in the second hard decision bit sequence and the absolute value of the log-likelihood ratio corresponding to the non-parity bit position, thereby improving the reliability of the decoding process.

[0107] In one implementation, the calculation formula for determining the path metric value of each sub-path corresponding to any non-parity bit after current expansion can be:

[0108]

[0109] where PM m is the path metric value of the target sub-path corresponding to the m-th non-parity bit, and PM m+1 is the path metric value of the target sub-path corresponding to the (m + 1)-th non-parity bit. is the decoded bit value of the target sub-path corresponding to the m-th non-parity bit, and y m is the m-th hard decision bit value in the second hard decision bit sequence.

[0110] Optionally, path update is performed on each parity bit to determine the path metric value of each sub-path corresponding to any parity bit, including:

[0111] Determine the decoded bit value of the target sub-path corresponding to the m-th parity bit in the second hard decision bit sequence according to the result obtained by performing binary addition after multiplying each element in the m-th row of the second matrix by the decoded bit value of the target sub-path corresponding to each non-parity bit in the second hard decision bit sequence; where the second matrix is a sub-matrix of the last N - M columns in the parity check matrix obtained by first reordering the columns of the first parity check matrix and then performing Gaussian elimination; m is an integer greater than 0 and less than or equal to M.

[0112] Determine the path metric value of the target sub-path corresponding to the m-th parity bit according to the decoded bit value of the target sub-path corresponding to the m-th parity bit.

[0113] Specifically, when it is necessary to determine the path metric value of each sub-path corresponding to any parity bit, the decoded bit value of the target sub-path corresponding to each parity bit in the second hard decision bit sequence can be determined first.

[0114] Gaussian elimination can be performed on the parity check matrix obtained by first reordering the columns of the first parity check matrix, and the last N - M columns of the obtained parity check matrix are taken as the second matrix.

[0115] Then, multiply each element in the m-th row of the second matrix by the decoded bit value of the corresponding target sub-path of each non-parity bit in the second hard decision bit sequence. For example, multiply the first element in the m-th row of the second matrix by the decoded bit value of the corresponding target sub-path of the first non-parity bit in the second hard decision bit sequence; multiply the second element in the m-th row of the second matrix by the decoded bit value of the corresponding target sub-path of the second non-parity bit in the second hard decision bit sequence;... multiply the (N - M)-th element in the m-th row of the second matrix by the decoded bit value of the corresponding target sub-path of the (N - M)-th non-parity bit in the second hard decision bit sequence.

[0116] Then, perform a binary addition operation on the obtained N - M products to obtain the decoded bit value of the corresponding target sub-path of the m-th parity bit in the second hard decision bit sequence. Where m is an integer greater than 0 and less than or equal to M.

[0117] According to the decoded bit value of the corresponding target sub-path of the m-th parity bit in the second hard decision bit sequence, the path metric value of the corresponding target sub-path of the m-th parity bit can be obtained, thereby improving the error correction performance of the decoding process.

[0118] In one implementation, the calculation formula for determining the decoded bit value of the corresponding target sub-path of each parity bit in the second hard decision bit sequence can be:

[0119]

[0120] Where is the decoded bit value of the corresponding target sub-path of the m-th parity bit, P m,j is the element in the m-th row and j-th column of the second matrix, is the decoded bit value of the corresponding target sub-path of the j-th non-parity bit.

[0121] Optionally, determining the path metric value of the corresponding target sub-path of the m-th parity bit according to the decoded bit value of the corresponding target sub-path of the m-th parity bit includes:

[0122] Multiply the result obtained by performing a binary addition on the decoded bit value of the corresponding target sub-path of the m-th parity bit and the hard decision bit value on the m-th parity bit by the absolute value of the log-likelihood ratio corresponding to the m-th parity bit, and add the multiplication result to the path metric value of the corresponding target sub-path of the bit after the m-th parity bit in the second hard decision bit sequence to obtain the path metric value of the corresponding target sub-path of the m-th parity bit.

[0123] Specifically, when it is necessary to determine the path metric value of the target sub-path corresponding to the m-th parity bit according to the decoded bit value of the target sub-path corresponding to the m-th parity bit, the decoded bit value of the target sub-path corresponding to the m-th parity bit can be first subjected to binary addition with the hard decision bit value on the m-th parity bit, and the obtained result is multiplied by the absolute value of the log-likelihood ratio corresponding to the m-th parity bit, and then the obtained product is added to the path metric value of the target sub-path corresponding to the bit after the m-th parity bit in the second hard decision bit sequence, that is, the path metric value of the target sub-path corresponding to the m-th parity bit can be obtained, thereby making the decoding process more reliable.

[0124] In one implementation, the calculation formula for determining the path metric value of the target sub-path corresponding to the m-th parity bit according to the decoded bit value of the target sub-path corresponding to the m-th parity bit can be:

[0125]

[0126] where PM m is the path metric value of the target sub-path corresponding to the m-th parity bit, PM m+1 is the path metric value of the target sub-path corresponding to the (m + 1)-th parity bit, λ m is the log-likelihood ratio corresponding to the m-th parity bit, is the decoded bit value of the target sub-path corresponding to the m-th parity bit, y m is the hard decision bit value on the m-th parity bit in the second hard decision bit sequence.

[0127] The method provided by the present invention is illustrated by the following specific application scenarios.

[0128] Figure 2 This is the second flow diagram of the list-based hierarchical statistical decoding method provided by the present invention. As Figure 2 shown, the method divides the bits into two groups of reliable non-parity bits and unreliable parity bits according to the received LLR, sorts them according to the reliability of the bits, and starts the estimation from the most reliable bit; for non-parity bits, both cases where the bit is 0 and the bit is 1 are considered, and path extension and optimal selection are performed on the paths in the list; for parity bits, the estimated value of the parity bit is obtained by using the parity check matrix after Gaussian elimination and the estimation of the non-parity bits. The main processes of the method include:

[0129] 1. The decoder performs an initialization operation, sets the bit index i = N, the number of paths l = 1 in the list, the path metric (PM) is PM N = 0, the parity bit path and the non-parity bit path All are set to 0.

[0130] 2. The decoder sorts the received log-likelihood ratios λ in ascending order of absolute value to obtain λ′ = Π1(λ), and respectively rearranges the hard-decision bits y and the columns of the M×N parity-check matrix H to obtain y′ = Π1(y) and H′ = Π1(H).

[0131] 3. Perform Gaussian elimination on H′ to obtain the matrix after elimination matrix The first M columns of which are the M×M identity matrix, i.e., P is the matrix composed of the last M - N columns of the matrix Denote the column rearrangement order of Gaussian elimination on H′ as Π2, and obtain λ″ = Π2(λ′), y″ = Π2(y′). The first M bits of y″ are called parity bits, and the remaining N - M bits are called non-parity bits.

[0132] 4. For the bit index i - 1, if the corresponding bit is a parity bit, execute step 6; if the corresponding bit is a non-parity bit, consider both cases where the bit is 0 and 1 simultaneously, perform path expansion to obtain l = l×2 sub-paths, and update the PM values of the sub-paths according to the PM calculation formula. The PM calculation formula is as follows:

[0133]

[0134] where PM i-1 is the path metric value corresponding to the (i - 1)-th bit position in the sub-path of the decoding path; PM i is the path metric value corresponding to the i-th bit position in the sub-path of the decoding path; y″ i-1 is the value of the (i - 1)-th element in y″; λ″ i-1 is the value of the (i - 1)-th element in λ″; is the value of the (i - 1 - M)-th bit in the non-parity bit sub-path.

[0135] 5. Sort the expanded sub-paths in ascending order of PM value. If the current number of sub-paths is greater than the maximum number of paths L, retain the L sub-paths with the smallest PM value, i.e., the most reliable ones; execute step 8.

[0136] 6. For the sub-path of the parity bit, calculate the (i - 1)-th bit through the constraint relationship of the parity-check equation of the parity-check matrix, and then update the path. The calculation formula is:

[0137]

[0138] where is the value of the (i - 1)-th bit in the sub-path of the parity bit; p i-1,jis the element at the (i - 1)-th row and j-th column of matrix P; is the value of the j-th bit in the non-parity-bit sub-path.

[0139] 7. Update the PM value, and the calculation formula is:

[0140]

[0141] where PM i-1 is the path metric value corresponding to the (i - 1)-th bit position in the decoding path sub-path; PM i is the path metric value corresponding to the i-th bit position in the decoding path sub-path; y″ i-1 is the value of the (i - 1)-th element in y″; λ″ i-1 is the value of the (i - 1)-th element in λ″; is the value of the (i - 1)-th bit in the parity-bit sub-path.

[0142] 8. Decrease the value of bit index i by 1. When i = 0, the calculation of the extension of non-parity bits and parity bits ends. Select the sub-path with the minimum PM value as the optimal path, and obtain the estimated codeword in the rearranged order and restore the original order to obtain the estimated codeword If i > 0, execute step 4.

[0143] 9. Terminate the decoding and output as the decoding codeword result.

[0144] Figure 3 is the structural schematic diagram of the list-based hierarchical statistical decoder provided by the present invention. As Figure 3 shown, the decoder includes:

[0145] a Gaussian elimination module, a pivot memory, a metric sorter, a path memory, and a parity memory;

[0146] The Gaussian elimination module is used to perform Gaussian elimination on the received parity-check matrix after the first reordering; wherein, the parity-check matrix after the first reordering is the matrix obtained by reordering the first parity-check matrix corresponding to the to-be-decoded sequence according to the ascending order of the absolute values of the elements in the first log-likelihood ratio sequence corresponding to the to-be-decoded sequence, and correspondingly reordering the columns of the first parity-check matrix corresponding to the to-be-decoded sequence;

[0147] The pivot memory is used to store and store the sorting index after the Gaussian elimination module performs Gaussian elimination on the parity-check matrix;

[0148] The metric sorter is used to receive the decoded bit values sent by the path memory and the parity check memory, calculate the path metric values corresponding to the decoded bit values based on the decoded bit values, the logarithm likelihood ratio sequence after the first re - sorting, and the hard - decision bit sequence corresponding to the logarithm likelihood ratio sequence, calculate the total path metric values of each sub - path of the decoded path, sort each sub - path of the decoded path based on the total path metric values of each sub - path of the decoded path, and store the total path metric values of each sub - path of the decoded path;

[0149] The path memory is used to perform path extension on the decoded path at each non - parity - check bit, and determine the decoded bit values corresponding to each sub - path of the decoded path at the non - parity - check bit after path extension;

[0150] The parity check memory is used to receive the matrix sent by the Gaussian elimination module and the decoded bit values corresponding to the non - parity - check bits on each sub - path of the decoded path sent by the path memory, and determine the decoded bit values corresponding to the parity - check bits on each sub - path of the decoded path based on the matrix and the decoded bit values corresponding to the non - parity - check bits on each sub - path of the decoded path.

[0151] Optionally, the decoder may further include:

[0152] A bitonic sorter, a logarithm likelihood ratio memory, a parity - check matrix memory, and an order recovery module;

[0153] The bitonic sorter is used to sort the elements in the received sequence in ascending order of absolute value and output the sorting index;

[0154] The logarithm likelihood ratio memory is used to obtain and store the logarithm likelihood ratio sequence, obtain and store the hard - decision bit sequence corresponding to the logarithm likelihood ratio sequence based on the logarithm likelihood ratio sequence; it is also used to receive the sorting index sent by the bitonic sorter, and read and output the stored logarithm likelihood ratio sequence and the hard - decision bit sequence corresponding to the logarithm likelihood ratio sequence based on the sorting index;

[0155] The parity - check matrix memory is used to obtain and store the parity - check matrix, and receive the sorting index sent by the bitonic sorter, and read and output the columns of the stored parity - check matrix based on the sorting index;

[0156] The pivot memory is further used to receive and store the sorting index sent by the bitonic sorter;

[0157] The metric sorter is further used to receive the logarithm likelihood ratio sequence after the first re - sorting and the hard - decision bit sequence corresponding to the logarithm likelihood ratio sequence sent by the logarithm likelihood ratio memory;

[0158] The sequential recovery module is used to receive the total path metrics and corresponding codewords of each decoded path sub-path sent by the path memory and the parity check memory, as well as the sorting index sent by the pivot memory. Based on the total path metrics of each decoded path sub-path, it determines the decoded path sub-path with the minimum total path metric, and based on the received sorting index, sequentially recovers the codeword corresponding to the decoded path sub-path with the minimum total path metric to obtain decoded bits and output them.

[0159] Specifically, this decoder can be used to implement the above list-based hierarchical statistical decoding method.

[0160] Among them, the Gaussian elimination module adopts an efficient architecture. For an M×N matrix, the Gaussian elimination module consists of M elimination units, and each unit has a pivot position corresponding to the M "1"s in the M×M identity matrix. When the Gaussian elimination module performs Gaussian elimination, it is divided into two stages: the establishment stage and the elimination stage. In the establishment stage, the M columns located at the parity check bit positions are sent into the Gaussian elimination module one by one. For each unit, when receiving a column, if the unit has not completed the establishment, it checks whether the position of the pivot in this column is "1". If so, the unit saves this column and then activates the binary addition operation. Once the unit has completed the establishment, that is, it enters the elimination stage, the unit will perform binary addition between the positions corresponding to the newly received column according to the content of the saved column. The Gaussian elimination module composed of M units will start to output the elimination result after M + N clocks. The path extension and path update operations are completed by multiple selectors. The path extension operation requires N×L L-way selectors, and the path update operation requires M×L L-way selectors.

[0161] The path extension and path update are respectively performed in the path memory and the parity check memory. For non-parity check bits, the corresponding log-likelihood ratio is output simultaneously with the columns of the parity check matrix after elimination. At this time, the hardware adds the PM values of the L paths reserved in the previous round of extension to the absolute value of the log-likelihood ratio. Together with the reserved PM values, there are a total of 2L values. In the next clock, the smaller L PM values and the corresponding paths among these 2L PM values are selected and reserved. There is no need for strict sorting among these L smaller PM values. The copy and update operations in the path memory use a simultaneous read and write mechanism and are implemented by N L-out-of-L selectors. In one clock, according to the current non-parity check bit index, the hard decision bits and the highest bits of the indexes of the previously selected L paths generate L new bits, which are written into the path memory. The operations in the parity check memory are similar to those in the path memory. The simultaneous read and write mechanism is implemented by M L-out-of-L selectors. Once the new bits corresponding to the non-parity check bits are generated, a binary addition operation is performed on two L×m matrices.

[0162] In one implementation, the decoder may further include a log-likelihood ratio memory, a bitonic sorter, a parity-check matrix memory, a sequential recovery module, etc. The log-likelihood ratio memory stores log-likelihood ratios in signed-magnitude format. The bitonic sorter can sort the log-likelihood ratios in ascending order of absolute value and output indices one by one, and then read the columns of the parity-check matrix stored in the parity-check matrix memory. Subsequently, Gaussian elimination, path extension, and path update are completely performed in a pipeline. The sequential recovery module can combine the parity bits and non-parity bits according to the stored order of the parity bits and output the best codeword.

[0163] When the decoder is operating, the Gaussian elimination module can perform Gaussian elimination on the received re-ordered parity-check matrix and send the result obtained from Gaussian elimination to the parity memory. Among them, the re-ordered parity-check matrix can be a matrix obtained by re-ordering the columns of the first parity-check matrix corresponding to the sequence to be decoded according to the ascending order of the absolute values of the elements in the first log-likelihood ratio sequence corresponding to the sequence to be decoded.

[0164] The pivot memory can store the sorting indices after the Gaussian elimination module performs Gaussian elimination on the received re-ordered parity-check matrix.

[0165] The path memory can perform path extension on the decoding paths at each non-parity bit position according to the received re-ordered hard decision bit sequence, and determine the decoding bit values corresponding to the current non-parity bit positions of each decoding path sub-path. The specific methods for performing path extension and determining the decoding bit values can refer to the above method embodiments and will not be elaborated here.

[0166] The parity memory can determine the decoding bit values corresponding to the current parity bit positions of each decoding path sub-path according to the received parity-check matrix after Gaussian elimination, the re-ordered log-likelihood ratio sequence, and the hard decision bit sequence. The specific methods for determining the decoding bit values can refer to the above method embodiments and will not be elaborated here.

[0167] The metric sorter can calculate the path metric values corresponding to the decoded bit values based on the decoded bit values, log-likelihood ratio sequences, and hard decision bit sequences of each sub-path of the decoding path, calculate the total path metric values of each sub-path of the decoding path, and sort each sub-path of the decoding path based on the total path metric values of each sub-path of the decoding path. The sorting result can be sent to the path memory and the parity check memory. For example, the decoded bit value of the target sub-path corresponding to the non-parity check bit can be compared with the hard decision bit value on the non-parity check bit, so as to calculate the path metric value of the target sub-path corresponding to the non-parity check bit, and the path metric value of the target sub-path corresponding to the parity check bit can be determined according to the decoded bit value of the target sub-path corresponding to the parity check bit. The specific calculation method can refer to the method embodiment above and will not be elaborated here.

[0168] In one implementation, the working process of the decoder may further include that the log-likelihood ratio memory first obtains the log-likelihood ratio sequence corresponding to the sequence to be decoded, and obtains the hard decision bit sequence corresponding to the sequence to be decoded according to the log-likelihood ratio sequence.

[0169] The log-likelihood ratio memory sends the log-likelihood ratio sequence corresponding to the sequence to be decoded to the bitonic sorter, and the bitonic sorter can sort the elements in the log-likelihood ratio sequence in ascending order of absolute value and output the sorting index.

[0170] The log-likelihood ratio memory can receive the sorting index sent by the bitonic sorter, read the log-likelihood ratio sequence and the hard decision bit sequence corresponding to the sequence to be decoded according to the sorting index, and then send the re-sorted log-likelihood ratio sequence and hard decision bit sequence to the metric sorter and the order recovery module.

[0171] At the same time, the parity check matrix memory can also receive the sorting index sent by the bitonic sorter, read the columns of the parity check matrix corresponding to the sequence to be decoded stored according to the sorting index, and send the re-sorted parity check matrix to the Gaussian elimination module.

[0172] The pivot memory can also receive the sorting index sent by the bitonic sorter, and send the sorting index and the sorting index after the Gaussian elimination of the received re-sorted parity check matrix by the Gaussian elimination module stored together to the order recovery module.

[0173] The metric sorter can also receive the re-sorted log-likelihood ratio sequence and hard decision bit sequence sent by the log-likelihood ratio memory, and send the re-sorted hard decision bit sequence to the parity check memory and the path memory.

[0174] The sequential recovery module can select the sub-path with the minimum total path metric value based on the total path metric values and corresponding codewords of each decoded path sub-path sent by the path memory and the parity memory, and the sorting index sent by the pivot memory, and perform sequential recovery on the codewords corresponding to the sub-path in the reverse order of the sorting index to obtain decoded bits and output them.

[0175] The present invention preferentially performs path extension on reliable bits, and has better error correction performance than SCL decoding in the scenario of short code and high code rate. Compared with the prior art, the present invention does not require the storage of internal LLR, has a smaller decoder hardware area, and adopts a highly pipelined design.

[0176] The list-based hierarchical statistical decoding device provided by the present invention will be described below. The list-based hierarchical statistical decoding device described below can be correspondingly referred to the list-based hierarchical statistical decoding method described above.

[0177] Figure 4 is a schematic structural diagram of the list-based hierarchical statistical decoding device provided by the present invention, as Figure 4 shown, the device includes:

[0178] A first acquisition module 400, configured to acquire a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity check matrix corresponding to a sequence to be decoded; wherein, the lengths of the first log-likelihood ratio sequence and the first hard decision bit sequence are N, the number of parity check bits in the first hard decision bit sequence is M, the first parity check matrix is a matrix of M×N, M and N are integers greater than 0, and N is greater than M;

[0179] A sorting module 401, configured to perform a first re-sorting on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly perform a first re-sorting on the first hard decision bit sequence and the columns of the first parity check matrix;

[0180] A second acquisition module 402, configured to obtain a second hard decision bit sequence based on the first hard decision bit sequence after the first re-sorting; the first M bits of the second hard decision bit sequence are parity check bits, and the last N-M bits of the second hard decision bit sequence are non-parity check bits;

[0181] A first determination module 403 starts from the last bit position of the second hard decision bit sequence, performs decoded path search in reverse order, performs path extension at each non-parity check bit position and determines the path metric value of each sub-path after the current extension corresponding to the non-parity check bit position, and performs path update at each parity check bit position to determine the path metric value of each sub-path corresponding to the parity check bit position;

[0182] The second determination module 404 selects the sub-path with the smallest total path metric value, determines the decoded codeword corresponding to the second hard decision bit sequence, and performs sequential recovery to obtain the decoded codeword result of the sequence to be decoded.

[0183] Optionally, path extension is performed on any non-parity bit, including:

[0184] According to the two cases where the decoded bit value on the non-parity bit is 0 and 1, path extension is performed to obtain l×2 sub-paths; where l is the number of sub-paths before the current path extension.

[0185] Optionally, determining the path metric value of each sub-path corresponding to any non-parity bit after the current extension includes:

[0186] When the decoded bit value of the target sub-path corresponding to the non-parity bit is the same as the hard decision bit value on the non-parity bit, it is determined that the path metric value of the target sub-path corresponding to the non-parity bit is equal to the path metric value of the target sub-path corresponding to the next bit of the non-parity bit in the second hard decision bit sequence;

[0187] When the decoded bit value of the target sub-path corresponding to the non-parity bit is different from the hard decision bit value on the non-parity bit, the path metric value of the target sub-path corresponding to the next bit of the non-parity bit in the second hard decision bit sequence is added to the absolute value of the log-likelihood ratio corresponding to the non-parity bit to obtain the path metric value of the target sub-path corresponding to the non-parity bit.

[0188] Optionally, path update is performed on each parity bit to determine the path metric value of each sub-path corresponding to any parity bit, including:

[0189] According to the result obtained by performing binary addition after multiplying each element in the m-th row of the second matrix by the decoded bit values of the target sub-paths corresponding to each non-parity bit in the second hard decision bit sequence, the decoded bit value of the target sub-path corresponding to the m-th parity bit in the second hard decision bit sequence is determined; where the second matrix is the sub-matrix of the last N-M columns in the parity check matrix obtained by performing the first reordering on the columns of the first parity check matrix and then performing Gaussian elimination; m is an integer greater than 0 and less than or equal to M;

[0190] According to the decoded bit value of the target sub-path corresponding to the m-th parity bit, the path metric value of the target sub-path corresponding to the m-th parity bit is determined.

[0191] Optionally, determining the path metric value of the target sub-path corresponding to the m-th parity bit according to the decoded bit value of the target sub-path corresponding to the m-th parity bit includes:

[0192] The result obtained by performing binary addition on the decoded bit value of the target subpath corresponding to the m-th parity bit and the hard decision bit value on the m-th parity bit is multiplied by the absolute value of the log-likelihood ratio corresponding to the m-th parity bit, and the result of the multiplication is added to the path metric value of the target subpath corresponding to the bit after the m-th parity bit in the second hard decision bit sequence, to obtain the path metric value of the target subpath corresponding to the m-th parity bit.

[0193] Optionally, obtaining a second hard decision bit sequence based on the first hard decision bit sequence after the first reordering includes:

[0194] Taking the first hard decision bit sequence after the first reordering as the second hard decision bit sequence; or,

[0195] Performing Gaussian elimination on the first parity check matrix after the first reordering, and according to the arrangement order of each column in the first parity check matrix after Gaussian elimination, performing a second reordering on the first hard decision bit sequence after the first reordering, to obtain the second hard decision bit sequence.

[0196] It should be noted here that the above device provided by the present invention can implement all the method steps implemented by the above method embodiments, and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments in this embodiment will not be specifically described herein again.

[0197] Figure 5 It is a schematic structural diagram of an electronic device provided by the present invention. As Figure 5 shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530, and a communication bus 550. Among them, the processor 510, the communication interface 520, and the memory 530 complete communication with each other through the communication bus 550. The processor 510 can call the logical instructions in the memory 530 to execute any list-based hierarchical statistical decoding method provided by the above embodiments.

[0198] In addition, when the logical instructions in the above-mentioned memory 530 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0199] It should be noted here that the electronic device provided by the present invention can implement all the method steps implemented in the above method embodiments and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described in this embodiment.

[0200] On the other hand, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is configured to execute any one of the list-based hierarchical statistical decoding methods provided in the above embodiments.

[0201] It should be noted here that the non-transitory computer-readable storage medium provided by the present invention can implement all the method steps implemented in the above method embodiments and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described in this embodiment.

[0202] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0203] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A list-based hierarchical statistical decoding method, characterized in that, Including: Obtain a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity-check matrix corresponding to a sequence to be decoded; wherein, the lengths of the first log-likelihood ratio sequence and the first hard decision bit sequence are N, the number of parity-check bits in the first hard decision bit sequence is M, the first parity-check matrix is a matrix of M×N, M and N are integers greater than 0, and N is greater than M; Perform a first reordering on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly perform a first reordering on the first hard decision bit sequence and the columns of the first parity-check matrix; Based on the first hard decision bit sequence after the first reordering, obtain a second hard decision bit sequence; the first M bits of the second hard decision bit sequence are parity-check bits, and the last N−M bits of the second hard decision bit sequence are non-parity-check bits; Starting from the last bit position of the second hard decision bit sequence, perform a decoding path search in reverse order. Perform path expansion at each non-parity-check bit position and determine the path metric value of each sub-path after the current expansion corresponding to the non-parity-check bit position. Perform path update at each parity-check bit position and determine the path metric value of each sub-path corresponding to the parity-check bit position. Select the sub-path with the smallest total path metric value, determine the decoded codeword corresponding to the second hard decision bit sequence, and perform sequential recovery to obtain the decoded codeword result of the sequence to be decoded.

2. The list-based hierarchical statistical decoding method according to claim 1, wherein Performing path expansion at any non-parity-check bit position includes: According to the two cases where the decoded bit value at the non-parity-check bit position is 0 and 1, perform path expansion to obtain l×2 sub-paths; wherein, l is the number of sub-paths before the current path expansion.

3. The list-based hierarchical statistical decoding method according to claim 2, wherein Determining the path metric value of each sub-path after the current expansion corresponding to any non-parity-check bit position includes: When the decoded bit value of the target sub-path corresponding to the non-parity-check bit position is the same as the hard decision bit value at the non-parity-check bit position, determine that the path metric value of the target sub-path corresponding to the non-parity-check bit position is equal to the path metric value of the target sub-path corresponding to the next bit position of the non-parity-check bit position in the second hard decision bit sequence; When the decoded bit value of the target sub-path corresponding to the non-parity-check bit position is different from the hard decision bit value at the non-parity-check bit position, add the absolute value of the log-likelihood ratio corresponding to the non-parity-check bit position to the path metric value of the target sub-path corresponding to the next bit position of the non-parity-check bit position in the second hard decision bit sequence to obtain the path metric value of the target sub-path corresponding to the non-parity-check bit position.

4. The list-based hierarchical statistical decoding method according to claim 1, wherein Performing path update at each parity-check bit position and determining the path metric value of each sub-path corresponding to any parity-check bit position includes: Determine the decoded bit value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path according to the result obtained by performing binary addition after multiplying each element in the m-th row of the second matrix by the decoded bit value of the corresponding target sub-path of each non-parity bit position in the second hard decision bit sequence; wherein, the second matrix is a sub-matrix of the last N - M columns in the parity check matrix obtained by performing Gaussian elimination after the first reordering of the columns of the first parity check matrix; m is an integer greater than 0 and less than or equal to M; Determine the path metric value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path according to the decoded bit value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path.

5. The list-based hierarchical statistical decoding method according to claim 4, wherein The determining the path metric value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path according to the decoded bit value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path includes: Multiply the result obtained by performing binary addition on the decoded bit value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path and the hard decision bit value at the m-th parity bit by the absolute value of the log-likelihood ratio corresponding to the m-th parity bit, and add the result of the multiplication to the path metric value of the target sub-path corresponding to the bit immediately following the m-th parity bit in the second hard decision bit sequence, to obtain the path metric value of the m-th parity bit in the second hard decision bit sequence corresponding to the target sub-path.

6. The list-based hierarchical statistical decoding method according to any one of claims 1 to 5, characterized in that The obtaining the second hard decision bit sequence based on the first hard decision bit sequence after the first reordering includes: Taking the first hard decision bit sequence after the first reordering as the second hard decision bit sequence; or, Performing Gaussian elimination on the first parity check matrix after the first reordering, and according to the arrangement order of the columns in the first parity check matrix after Gaussian elimination, performing a second reordering on the first hard decision bit sequence after the first reordering to obtain the second hard decision bit sequence.

7. A list-based hierarchical statistical decoder, characterized in that, Includes: A Gaussian elimination module, a pivot memory, a metric sorter, a path memory, and a parity check memory; The Gaussian elimination module is used to perform Gaussian elimination on the received parity check matrix after the first reordering; wherein, the parity check matrix after the first reordering is a matrix obtained by reordering the columns of the first parity check matrix corresponding to the to-be-decoded sequence correspondingly according to the ascending order of the absolute values of the elements in the first log-likelihood ratio sequence corresponding to the to-be-decoded sequence; The pivot memory is used to store and store the sorting index after the Gaussian elimination module performs Gaussian elimination on the parity check matrix; The metric sorter is configured to receive the decoded bit values sent by the path memory and the parity memory, calculate the path metrics corresponding to the decoded bit values based on the decoded bit values, the log-likelihood ratio sequence after the first reordering, and the hard decision bit sequence corresponding to the log-likelihood ratio sequence, calculate the total path metrics of each sub-path of the decoded paths, sort each sub-path of the decoded paths based on the total path metrics of each sub-path of the decoded paths, and store the total path metrics of each sub-path of the decoded paths; The path memory is configured to perform path extension on the decoded paths at each non-parity bit position, and determine the decoded bit values corresponding to each sub-path of the decoded paths at the non-parity bit position after the path extension; The parity memory is configured to receive the matrix sent by the Gaussian elimination module and the decoded bit values corresponding to the non-parity bit positions on each sub-path of the decoded paths sent by the path memory, and determine the decoded bit values corresponding to the parity bit positions on each sub-path of the decoded paths based on the matrix and the decoded bit values corresponding to the non-parity bit positions on each sub-path of the decoded paths.

8. The list-based hierarchical statistical decoder according to claim 7, wherein The decoder further includes: A bitonic sorter, a log-likelihood ratio memory, a parity-check matrix memory, and an order recovery module; The bitonic sorter is configured to sort the elements in the received sequence in ascending order of absolute value and output a sorting index; The log-likelihood ratio memory is configured to obtain and store the log-likelihood ratio sequence, obtain and store the hard decision bit sequence corresponding to the log-likelihood ratio sequence based on the log-likelihood ratio sequence; it is further configured to receive the sorting index sent by the bitonic sorter, and read and output the stored log-likelihood ratio sequence and the hard decision bit sequence corresponding to the log-likelihood ratio sequence based on the sorting index; The parity-check matrix memory is configured to obtain and store the parity-check matrix, and receive the sorting index sent by the bitonic sorter, and read and output the columns of the stored parity-check matrix based on the sorting index; The pivot memory is further configured to receive and store the sorting index sent by the bitonic sorter; The metric sorter is further configured to receive the log-likelihood ratio sequence after the first reordering and the hard decision bit sequence corresponding to the log-likelihood ratio sequence sent by the log-likelihood ratio memory; The order recovery module is configured to receive the total path metrics and the corresponding codewords of each sub-path of the decoded paths sent by the path memory and the parity memory, and the sorting index sent by the pivot memory, determine the sub-path of the decoded path with the minimum total path metric based on the total path metrics of each sub-path of the decoded paths, and perform order recovery on the codeword corresponding to the sub-path of the decoded path with the minimum total path metric based on the received sorting index to obtain the decoded bits and output them.

9. A list-based hierarchical statistical decoding device, characterized in that including: A first acquisition module, configured to acquire a first log-likelihood ratio sequence, a first hard decision bit sequence, and a first parity check matrix corresponding to a sequence to be decoded; wherein, the lengths of the first log-likelihood ratio sequence and the first hard decision bit sequence are N, the number of parity check bits in the first hard decision bit sequence is M, the first parity check matrix is an M×N matrix, M and N are integers greater than 0, and N is greater than M; A sorting module, configured to perform a first re-sorting on the first log-likelihood ratio sequence in ascending order of the absolute values of the elements in the first log-likelihood ratio sequence, and correspondingly perform a first re-sorting on the first hard decision bit sequence and the columns of the first parity check matrix; A second acquisition module, configured to obtain a second hard decision bit sequence based on the first hard decision bit sequence after the first re-sorting; the first M bits of the second hard decision bit sequence are parity check bits, and the last N - M bits of the second hard decision bit sequence are non-parity check bits; A first determination module, starting from the last bit position of the second hard decision bit sequence, performing a decoding path search in reverse order, performing path extension at each non-parity check bit position and determining the path metric value of each sub-path after the current extension corresponding to the non-parity check bit position, and performing path update at each parity check bit position to determine the path metric value of each sub-path corresponding to the parity check bit position; A second determination module, selecting the sub-path with the smallest total path metric value, determining the decoded codeword corresponding to the second hard decision bit sequence, and performing sequential recovery to obtain the decoded codeword result of the sequence to be decoded.

10. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the list-based hierarchical statistical decoding method according to any one of claims 1 to 6.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the list-based hierarchical statistical decoding method according to any one of claims 1 to 6.

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