A double-chain LVDS synchronous communication method

Abstract

The present application relates to LVDS synchronous communication, in particular to a double-chain LVDS synchronous communication method, which utilizes PXIe_DSTARA bus of PXIe backboard to realize global clock synchronization, and based on this, realizes LVDS link clock homologous of PXIe_DSTARB and PXIe_DSTARC bus, only through two LVDS links for link training verification, and adaptively realizes double-chain LVDS synchronous communication; the technical scheme provided by the present application can effectively overcome the defects that the prior art cannot realize double-chain LVDS stable synchronous communication based on PXIe backboard.

Description

Technical Field

[0001] This invention relates to LVDS synchronous communication, and more specifically to a dual-chain LVDS synchronous communication method. Background Technology

[0002] The Xilinx SelectIO IPCore can instantiate and configure I / O logic as required, implementing input SERDES, output SERDES, and delay functions. This IPCore features: support for input, output, or bidirectional buses and data buses up to 16 bits wide; the ability to create the clock circuitry required to drive the I / O logic; optional data or clock delay insertion; and single and dual data rates. Therefore, this IPCore can be used to implement SERDES communication between Field Programmable Logic Arrays (FPGAs), but the user needs to adjust the data-to-clock relative delay (TAP) value and select the correct bit-edge alignment (bitslip) value to achieve serial-to-parallel data conversion.

[0003] The PXIe chassis adds three high-performance differential star trigger buses—PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC—to the PXI chassis, enabling synchronization and communication between the system clock slot and peripheral slots. In experimental physics, the PXIe chassis's system clock slot acts as the chassis's central node, outputting a synchronization clock to the peripheral slots via the PXIe backplane and exchanging information with them to achieve global synchronization and coincident triggering. Implementing dual-chain LVDS synchronous communication based on the PXIe backplane is of great significance to the PXIe chassis. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a dual-chain LVDS synchronous communication method, which can effectively overcome the defect that the existing technology cannot achieve stable synchronous communication of dual-chain LVDS based on PXIe backplane.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A dual-chain LVDS synchronous communication method is proposed, which utilizes the PXIe_DSTARA bus of the PXIe backplane to achieve global clock synchronization, and based on this, achieves the same clock source for the LVDS links of the PXIe_DSTARB and PXIe_DSTARC buses. The method adaptively realizes dual-chain LVDS synchronous communication by only transmitting and receiving two LVDS links for link training and verification.

[0009] Preferably, the global clock synchronization achieved using the PXIe_DSTARA bus on the PXIe backplane includes:

[0010] The clock card outputs a synchronous clock to all peripheral cards via the PXIe_DSTARA bus, providing a synchronous clock source for the transmitter and receiver of the LVDS link;

[0011] The clock card is the system clock slot card of the PXIe chassis, and the peripheral card is the peripheral slot card.

[0012] Preferably, the LVDS link clocks for implementing the PXIe_DSTARB and PXIe_DSTARC buses are from the same source, and link training and verification are performed only through the transmission and reception of two LVDS links to adaptively achieve dual-link LVDS synchronous communication, including:

[0013] The clock card sends serial data via the SelectIO internal serializer to the peripheral card through the PXIe_DSTARB bus, and the peripheral card uses the SelectIO internal deserializer to receive the data.

[0014] The peripheral card sends serial data to the clock card via the PXIe_DSTARC bus through the internal serializer of SelectIO, and the clock card uses the internal deserializer of SelectIO to receive the data.

[0015] Preferably, for the transmitting end that transmits serial data, the serial parameter m of its SelectIO is set in the range of 1 to 16;

[0016] For the receiver that receives serial data, the SelectIO data-clock relative delay TAP value and bit edge alignment bitslip value need to be adjusted to correctly receive serial data and achieve serial-to-parallel data conversion.

[0017] Preferably, the link from the clock card to the peripheral card is designated as LVDS link 1, and TX1 represents the transmitting end in LVDS link 1, and RX1 represents the receiving end in LVDS link 1.

[0018] The link from the peripheral card to the clock card is designated as LVDS link 2, with TX2 representing the transmitter in LVDS link 2 and RX2 representing the receiver in LVDS link 2.

[0019] Preferably, TX1 in the LVDS link 1 is divided into 5 states:

[0020] The first state of TX1, Tx_State1, is when RX2 has not established a connection, and the signature code K1 is sent. If RX2 establishes a connection, then TX1 enters the second state, Tx_State2.

[0021] The second state Tx_State2 of TX1 indicates that RX2 has established a connection, and the signature code K2 is sent: if RX1 establishes a connection, it enters the third state Tx_State3 of TX1; if RX2 disconnects, it enters the first state Tx_State1 of TX1.

[0022] In the third state Tx_State3 of TX1, both RX1 and RX2 are connected. If RX2's buffer is full, it sends the signature code K3; otherwise, it sends the signature code K2. If RX1's buffer is full, it enters the fourth state Tx_State4 of TX1. If there is data transmission on LVDS link 1, it enters the fifth state Tx_State5 of TX1. If RX2 disconnects, it enters the first state Tx_State1 of TX1. If RX1 disconnects, it enters the second state Tx_State2 of TX1.

[0023] The fourth state of TX1, Tx_State4, is the state where the RX1 buffer is full. If the RX2 buffer is full, the signature code K3 is sent; otherwise, the signature code K2 is sent. If the RX1 buffer is not full, it enters the third state of TX1, Tx_State3.

[0024] The fifth state of TX1, Tx_State5, is the data transmission state of TX1. After sending a feature code K4, n data codes are sent and the transmission ends with feature code K5. After the data transmission is completed, TX1 enters the third state, Tx_State3.

[0025] Preferably, RX1 in the LVDS link 1 is divided into 7 states:

[0026] The first state of RX1, Rx_State1, is the bit edge alignment bitslip value adjustment state. At this time, the data and clock relative delay TAP value is scanned from 0 to the serial parameter m. If RX1 receives the feature code K1 / K2 / K3, it enters the third state of RX1, Rx_State3. If the scan ends and RX1 still does not receive the feature code K1 / K2 / K3, it enters the second state of RX1, Rx_State2.

[0027] The second state Rx_State2 of RX1 is the state for adjusting the relative delay TAP value between data and clock. The TAP value is incremented by 1: if the TAP scan is completed, it enters the fourth state Rx_State4 of RX1; otherwise, it enters the first state Rx_State1 of RX1.

[0028] The third state of RX1, Rx_State3, is the data-clock relative delay TAP value recording state. It records the usable TAP value and enters the second state of RX1, Rx_State2.

[0029] The fourth state of RX1, Rx_State4, is the selection state for the relative delay TAP value between data and clock. Since the TAP value represents the relative delay relationship between data and clock, each TAPbin is much smaller than the data setup and hold time. Therefore, a connection can be established with any consecutive TAP value. This state selects the middle value of consecutive available TAP values ​​as the final value used by RX1 and enters the fifth state of RX1, Rx_State5.

[0030] The fifth state of RX1, Rx_State5, is the bit edge alignment bitslip value confirmation state. The bitslip value is adjusted again according to the final TAP value to establish a connection. If a connection is established, it enters the sixth state of RX1, Rx_State6. If the bitslip scan ends but a connection is not established, it enters the first state of RX1, Rx_State1, to reselect a TAP value.

[0031] In the sixth state Rx_State6 of RX1, RX1 is connected and sends an RX1 connected signal to TX2. If the RX1 buffer has less than 3n data frames, it sends an RX1 buffer full signal to TX2. If the signature K2 is received, it sends an RX2 connected signal to TX2. If the signature K3 is received, it sends an RX2 buffer full signal to TX2. If the signature K4 is received, it enters the seventh state Rx_State7 of RX1. If other signatures are received, it enters the first state Rx_State1 of RX1 and pulls the RX1 connected signal low.

[0032] The seventh state of RX1, Rx_State7, is the data receiving state of RX1, receiving n data codes: if the feature code K5 is received after the nth data code, it enters the sixth state of RX1, Rx_State6; if the feature code K5 is not received, it enters the first state of RX1, Rx_State1, and pulls the RX1 connected signal low.

[0033] (III) Beneficial Effects

[0034] Compared with existing technologies, the dual-chain LVDS synchronous communication method provided by this invention realizes adaptive synchronous communication between the system clock slot and peripheral slot on the PXIe backplane, and can establish an adaptive, fixed-delay, and stable LVDS data transmission link. The technical solution of this application has the following advantages:

[0035] (1) No additional signal link is required; dual-chain LVDS adaptive connection

[0036] The clocks of the nodes at both ends of the LVDS link are from the same source, and data transmission is carried out by mutually verifying the link establishment status.

[0037] (2) Fixed transmission delay

[0038] Data output is in the clock domain of the receiving end. Since the transmission path and clock output path are fixed, the data transmission delay between the transmitting and receiving ends is fixed.

[0039] (3) High reliability

[0040] By adjusting the relative delay (TAP) value between data and clock and the bitslip value using SelectIO, a range of consecutive available TAP values ​​is selected as the connection. This ensures that the establishment of data and clock has the maximum time margin and can stably establish the connection. In addition, the connection will automatically reconnect after being broken to ensure stable data transmission.

[0041] 4) Scalability

[0042] This method is not limited to PXIe chassis and can be used as long as the transmitting and receiving clocks are from the same source, thus it is scalable. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0044] Figure 1 This is a schematic diagram showing the connection between the clock card and the peripheral card inside the PXIe chassis in this invention;

[0045] Figure 2 This is the dual-chain LVDS synchronous communication model between the clock card and peripheral cards in this invention;

[0046] Figure 3 This is a schematic diagram of the state of the transmitting end in the LVDS link from the clock card to the peripheral card in this invention;

[0047] Figure 4 This is a schematic diagram of the receiver's status in the LVDS link from the clock card to the peripheral card in this invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0049] A dual-chain LVDS synchronous communication method, such as Figure 1 As shown, global clock synchronization is achieved using the PXIe_DSTARA bus on the PXIe backplane, and based on this, the LVDS links of the PXIe_DSTARB and PXIe_DSTARC buses are made to have the same clock source. Link training and verification are performed by transmitting and receiving only two LVDS links, and adaptive dual-link LVDS synchronous communication is achieved.

[0050] ① Global clock synchronization is achieved using the PXIe_DSTARA bus on the PXIe backplane, including:

[0051] The clock card outputs a synchronous clock to all peripheral cards via the PXIe_DSTARA bus, providing a synchronous clock source for the transmitter and receiver of the LVDS link;

[0052] The clock card is the system clock slot card of the PXIe chassis, and the peripheral card is the peripheral slot card.

[0053] ② To achieve clock synchronization between the PXIe_DSTARB and PXIe_DSTARC buses' LVDS links, link training and verification are performed only through the transmission and reception of two LVDS links, adaptively realizing dual-link LVDS synchronous communication, including:

[0054] The clock card sends serial data via the SelectIO internal serializer to the peripheral card through the PXIe_DSTARB bus, and the peripheral card uses the SelectIO internal deserializer to receive the data.

[0055] The peripheral card sends serial data to the clock card via the PXIe_DSTARC bus through the internal serializer of SelectIO, and the clock card uses the internal deserializer of SelectIO to receive the data.

[0056] In the technical solution of this application, for the transmitting end that transmits serial data, the serial parameter m of its SelectIO is set in the range of 1 to 16;

[0057] For the receiver that receives serial data, the SelectIO data-clock relative delay TAP value and bit edge alignment bitslip value need to be adjusted to correctly receive serial data and achieve serial-to-parallel data conversion.

[0058] like Figure 1As shown, the PXIe chassis adds three high-performance differential star-topic trigger buses—PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC—to the PXI chassis, enabling star interconnection between the system clock slot and peripheral slots within the chassis. Specifically, PXIe_DSTARA uses the LVPECL level standard, with the direction from the system clock slot to the peripheral slot; PXIe_DSTARB uses the LVDS level standard, with the direction from the system clock slot to the peripheral slot; and PXIe_DSTARC uses the LVDS level standard, with the direction from the peripheral slot to the system clock slot.

[0059] like Figure 2 As shown, the link from the clock card to the peripheral card is designated as LVDS link 1, and TX1 represents the transmitting end in LVDS link 1, and RX1 represents the receiving end in LVDS link 1.

[0060] The link from the peripheral card to the clock card is designated as LVDS link 2, with TX2 representing the transmitter in LVDS link 2 and RX2 representing the receiver in LVDS link 2.

[0061] like Figure 3 As shown, TX1 in LVDS link 1 is divided into 5 states:

[0062] The first state of TX1, Tx_State1, is when RX2 has not established a connection, and the signature code K1 is sent. If RX2 establishes a connection, then TX1 enters the second state, Tx_State2.

[0063] The second state Tx_State2 of TX1 indicates that RX2 has established a connection, and the signature code K2 is sent: if RX1 establishes a connection, it enters the third state Tx_State3 of TX1; if RX2 disconnects, it enters the first state Tx_State1 of TX1.

[0064] In the third state Tx_State3 of TX1, both RX1 and RX2 are connected. If RX2's buffer is full, it sends the signature code K3; otherwise, it sends the signature code K2. If RX1's buffer is full, it enters the fourth state Tx_State4 of TX1. If there is data transmission on LVDS link 1, it enters the fifth state Tx_State5 of TX1. If RX2 disconnects, it enters the first state Tx_State1 of TX1. If RX1 disconnects, it enters the second state Tx_State2 of TX1.

[0065] The fourth state of TX1, Tx_State4, is the state where the RX1 buffer is full. If the RX2 buffer is full, the signature code K3 is sent; otherwise, the signature code K2 is sent. If the RX1 buffer is not full, it enters the third state of TX1, Tx_State3.

[0066] The fifth state of TX1, Tx_State5, is the data transmission state of TX1. After sending a feature code K4, n data codes are sent and the transmission ends with feature code K5. After the data transmission is completed, TX1 enters the third state, Tx_State3.

[0067] like Figure 4 As shown, RX1 in LVDS link 1 has 7 states:

[0068] The first state of RX1, Rx_State1, is the bit edge alignment bitslip value adjustment state. At this time, the data and clock relative delay TAP value is scanned from 0 to the serial parameter m. If RX1 receives the feature code K1 / K2 / K3, it enters the third state of RX1, Rx_State3. If the scan ends and RX1 still does not receive the feature code K1 / K2 / K3, it enters the second state of RX1, Rx_State2.

[0069] The second state Rx_State2 of RX1 is the state for adjusting the relative delay TAP value between data and clock. The TAP value is incremented by 1: if the TAP scan is completed, it enters the fourth state Rx_State4 of RX1; otherwise, it enters the first state Rx_State1 of RX1.

[0070] The third state of RX1, Rx_State3, is the data-clock relative delay TAP value recording state. It records the usable TAP value and enters the second state of RX1, Rx_State2.

[0071] The fourth state of RX1, Rx_State4, is the selection state for the relative delay TAP value between data and clock. Since the TAP value represents the relative delay relationship between data and clock, each TAPbin is much smaller than the data setup and hold time. Therefore, a connection can be established with any consecutive TAP value. This state selects the middle value of consecutive available TAP values ​​as the final value used by RX1 and enters the fifth state of RX1, Rx_State5.

[0072] The fifth state of RX1, Rx_State5, is the bit edge alignment bitslip value confirmation state. The bitslip value is adjusted again according to the final TAP value to establish a connection. If a connection is established, it enters the sixth state of RX1, Rx_State6. If the bitslip scan ends but a connection is not established, it enters the first state of RX1, Rx_State1, to reselect a TAP value.

[0073] In the sixth state Rx_State6 of RX1, RX1 is connected and sends an RX1 connected signal to TX2. If the RX1 buffer has less than 3n data frames, it sends an RX1 buffer full signal to TX2. If the signature K2 is received, it sends an RX2 connected signal to TX2. If the signature K3 is received, it sends an RX2 buffer full signal to TX2. If the signature K4 is received, it enters the seventh state Rx_State7 of RX1. If other signatures are received, it enters the first state Rx_State1 of RX1 and pulls the RX1 connected signal low.

[0074] The seventh state of RX1, Rx_State7, is the data receiving state of RX1, receiving n data codes: if the feature code K5 is received after the nth data code, it enters the sixth state of RX1, Rx_State6; if the feature code K5 is not received, it enters the first state of RX1, Rx_State1, and pulls the RX1 connected signal low.

[0075] In this application's technical solution, the connection processes of LVDS link 1 and LVDS link 2 are mirror images of each other. After both RX1 and RX2 are established, the dual-link LVDS realizes a data transmission channel. Since the global clock source is output by the clock card through the PXIe_DSTARA bus, the data output is in the clock domain of the receiving end, and the LVDS link transmission path is fixed, thus achieving synchronous data transmission. Furthermore, this method implements link reconnection operations, enabling adaptive reconnection after a link is disconnected, ensuring stable data transmission.

[0076] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-chain LVDS synchronous communication method, characterized in that: Global clock synchronization is achieved using the PXIe_DSTARA bus on the PXIe backplane, and based on this, the LVDS links of the PXIe_DSTARB and PXIe_DSTARC buses are made to have the same clock source. Link training and verification are performed by transmitting and receiving only two LVDS links, and dual-link LVDS synchronous communication is adaptively realized. The implementation of global clock synchronization using the PXIe_DSTARA bus on the PXIe backplane includes: The clock card outputs a synchronous clock to all peripheral cards via the PXIe_DSTARA bus, providing a synchronous clock source for the transmitter and receiver of the LVDS link; Among them, the clock card is the system clock slot card of the PXIe chassis, and the peripheral card is the peripheral slot card; The link from the clock card to the peripheral card is designated as LVDS link 1, and TX1 represents the transmitter in LVDS link 1, while RX1 represents the receiver in LVDS link 1. The link from the peripheral card to the clock card is designated as LVDS link 2, and TX2 represents the transmitting end in LVDS link 2, while RX2 represents the receiving end in LVDS link 2. In the LVDS link 1, TX1 is divided into 5 states: The first state of TX1, Tx_State1, is when RX2 has not established a connection, and the signature code K1 is sent. If RX2 establishes a connection, then TX1 enters the second state, Tx_State2. The second state Tx_State2 of TX1 indicates that RX2 has established a connection, and the signature code K2 is sent: if RX1 establishes a connection, it enters the third state Tx_State3 of TX1; if RX2 disconnects, it enters the first state Tx_State1 of TX1. In the third state Tx_State3 of TX1, both RX1 and RX2 are connected. If RX2's buffer is full, it sends the signature code K3; otherwise, it sends the signature code K2. If RX1's buffer is full, it enters the fourth state Tx_State4 of TX1. If there is data transmission on LVDS link 1, it enters the fifth state Tx_State5 of TX1. If RX2 disconnects, it enters the first state Tx_State1 of TX1. If RX1 disconnects, it enters the second state Tx_State2 of TX1. The fourth state of TX1, Tx_State4, is the state where the RX1 buffer is full. If the RX2 buffer is full, the signature code K3 is sent; otherwise, the signature code K2 is sent. If the RX1 buffer is not full, it enters the third state of TX1, Tx_State3. The fifth state of TX1, Tx_State5, is the data transmission state of TX1. After sending a feature code K4, n data codes are sent and the transmission ends with feature code K5. After the data transmission is completed, TX1 enters the third state, Tx_State3. In the LVDS link 1, RX1 is divided into 7 states: The first state of RX1, Rx_State1, is the bit edge alignment bitslip value adjustment state. At this time, the data and clock relative delay TAP value is scanned from 0 to the serial parameter m. If RX1 receives the feature code K1 / K2 / K3, it enters the third state of RX1, Rx_State3. If the scan ends and RX1 still does not receive the feature code K1 / K2 / K3, it enters the second state of RX1, Rx_State2. The second state Rx_State2 of RX1 is the state for adjusting the relative delay TAP value between data and clock. The TAP value is incremented by 1: if the TAP scan is completed, it enters the fourth state Rx_State4 of RX1; otherwise, it enters the first state Rx_State1 of RX1. The third state of RX1, Rx_State3, is the data-clock relative delay TAP value recording state. It records the usable TAP value and enters the second state of RX1, Rx_State2. The fourth state of RX1, Rx_State4, is the selection state for the relative delay TAP value between data and clock. Since the TAP value represents the relative delay relationship between data and clock, each TAP bin has a much smaller relative data establishment and hold time. Therefore, a connection can be established with any consecutive TAP value. This state selects the middle value of consecutive available TAP values ​​as the final value used by RX1 and enters the fifth state of RX1, Rx_State5. The fifth state of RX1, Rx_State5, is the bit edge alignment bitslip value confirmation state. The bitslip value is adjusted again according to the final TAP value to establish a connection. If a connection is established, it enters the sixth state of RX1, Rx_State6. If the bitslip scan ends but a connection is not established, it enters the first state of RX1, Rx_State1, to reselect a TAP value. In the sixth state Rx_State6 of RX1, RX1 is connected and sends an RX1 connected signal to TX2. If the RX1 buffer has less than 3n data frames, it sends an RX1 buffer full signal to TX2. If the signature K2 is received, it sends an RX2 connected signal to TX2. If the signature K3 is received, it sends an RX2 buffer full signal to TX2. If the signature K4 is received, it enters the seventh state Rx_State7 of RX1. If other signatures are received, it enters the first state Rx_State1 of RX1 and pulls the RX1 connected signal low. The seventh state of RX1, Rx_State7, is the data receiving state of RX1, receiving n data codes: if the feature code K5 is received after the nth data code, it enters the sixth state of RX1, Rx_State6; if the feature code K5 is not received, it enters the first state of RX1, Rx_State1, and pulls the RX1 connected signal low.

2. The dual-chain LVDS synchronous communication method according to claim 1, characterized in that: The implementation of LVDS link clocks for PXIe_DSTARB and PXIe_DSTARC buses is based on the same source. Link training and verification are performed only through the transmission and reception of two LVDS links, adaptively achieving dual-link LVDS synchronous communication, including: The clock card sends serial data via the SelectIO internal serializer to the peripheral card through the PXIe_DSTARB bus, and the peripheral card uses the SelectIO internal deserializer to receive the data. The peripheral card sends serial data to the clock card via the PXIe_DSTARC bus through the internal serializer of SelectIO, and the clock card uses the internal deserializer of SelectIO to receive the data.

3. The dual-chain LVDS synchronous communication method according to claim 2, characterized in that: For the transmitting end that sends serial data, the serial parameter m of its SelectIO is set in the range of 1~16; For the receiver that receives serial data, the SelectIO data-clock relative delay TAP value and bit edge alignment bitslip value need to be adjusted to correctly receive serial data and achieve serial-to-parallel data conversion.

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