Display device

Abstract

A display device includes a display panel including gate lines and data lines, a controller generating a source output enable signal that determines output timing of a data voltage output to the data lines, and a data driver including a signal changer generating a final source output enable signal by using the source output enable signal and randomly changing the output timing of the data voltage of each gate line by using the final source output enable signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0186125, filed on December 23, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Recently, display devices that utilize spread spectrum clock generation (SSCG) have been proposed.

[0005] In display devices that utilize SSCG, electromagnetic interference (EMI) can be reduced by leveraging the periodic dispersion of digital data and the extended effect of analog output.

[0006] However, with the increase in display devices with high resolution, the speed of digital data transmission has increased, and therefore, the applicable level of SSCG is limited.

[0007] In particular, in display devices that use SSCG, the effect of reducing EMI is reduced because the timing of outputting the data voltage to the horizontal line is fixed. Summary of the Invention

[0008] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0009] One aspect of this disclosure is to provide a display device that can randomly change the output timing of the data voltage of each gate line.

[0010] Further advantages and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained from the written description and its claims, as well as the structures specifically pointed out in the accompanying drawings.

[0011] To achieve these and other advantages and in accordance with the purposes of this disclosure, as specifically implemented and generally described herein, a display device is provided, comprising: a display panel including gate lines and data lines; a controller that generates a source output enable signal that determines the output timing of a data voltage output to the data lines; and a data driver including a signal changer that generates a final source output enable signal using the source output enable signal and randomly changes the output timing of the data voltage of each gate line using the final source output enable signal.

[0012] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0013] This disclosure includes accompanying drawings to provide a further understanding of the disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0014] Figure 1 This is an example diagram illustrating the configuration of a display device according to the present disclosure;

[0015] Figure 2 This is an example diagram illustrating the structure of pixels applied to a display device according to the present disclosure;

[0016] Figure 3 This is an example diagram illustrating the configuration of a controller applied to a display device according to the present disclosure;

[0017] Figure 4 This is an example diagram illustrating the configuration of a gate driver applied to a display device according to the present disclosure;

[0018] Figure 5 This is an example diagram illustrating the configuration of a data driver applied to a display device according to the present disclosure;

[0019] Figure 6 This is an example diagram showing the waveforms of the gate signal and data voltage applied to the display device according to the present disclosure;

[0020] Figure 7 and Figure 8 This is an example diagram used to describe the output timing of the data voltage output by the display device according to this disclosure. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0022] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the embodiments described below in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0023] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals always refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the essence of this disclosure. When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0024] When interpreting components, even without an explicit description of the error or tolerance range, the component is interpreted as including the error or tolerance range.

[0025] When describing positional relationships, for example, when the positional relationship between two components is described as such as “on top of,” “above,” “below,” and “near,” one or more other components may be positioned between the two components unless more restrictive terms such as “only” or “directly” are used.

[0026] When describing temporal relationships, such as when time sequence is described as "after," "following," "next," and "before," discontinuous situations may be included unless more restrictive terms such as "just," "immediately," or "directly" are used.

[0027] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify the corresponding element from other elements, and the nature, order, or number of the corresponding elements shall not be limited by these terms. The expression that an element is “connected,” “coupled,” or “adhered” to another element or layer means that, unless otherwise stated, the element or layer may not only be directly connected or adhered to another element or layer, but may also be indirectly connected or adhered to another element or layer through one or more intermediate elements or layers “set” or “inserted” between the elements or layers.

[0029] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more items from the first, second, and third items, as well as all items proposed from the first, second, or third item.

[0030] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may interoperate with each other in various ways and be technically driven. Embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent manner.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is an example diagram illustrating the configuration of a display device according to the present disclosure. Figure 2 This is an example diagram illustrating the structure of pixels applied to a display device according to the present disclosure. Figure 3 This is an example diagram illustrating the configuration of a controller applied to a display device according to the present disclosure. Figure 4 This is an example diagram illustrating the configuration of a gate driver applied to a display device according to the present disclosure.

[0033] The display device according to this disclosure can be configured with various electronic devices. For example, the electronic devices may include smartphones, tablet PCs, televisions (TVs), and monitors.

[0034] like Figure 1As shown, the display device according to this disclosure may include: a display panel 100, including a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a gate driver 200 for supplying gate signals to a plurality of gate lines GL1 to GLg disposed in the display area 120 of the display panel 100; a data driver 300 for supplying data voltage to a plurality of data lines DL1 to DLd disposed in the display panel 100; a controller 400 for controlling the driving of the gate driver 200 and the data driver 300; and a power supply 500 for supplying power to the controller, the gate driver, the data driver, and the display panel.

[0035] First, the display panel 100 may include a display area 120 and a non-display area 130. Gate lines GL1 to Glg, data lines DL1 to DLd, and pixels 110 may be disposed in the display area 120. Therefore, the display area 120 can display an image. Here, g and d can be natural numbers. The non-display area 130 may surround the outside of the display area 120.

[0036] like Figure 2 As shown, the pixels 110 included in the display panel 100 may include a light-emitting area, which includes a pixel driving circuit PDC and a light-emitting device ED. The pixel driving circuit PDC includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2.

[0037] The first terminal of the driving transistor Tdr can be connected to the high voltage supply line PLA via which the high voltage EVDD is supplied, and the second terminal of the driving transistor Tdr can be connected to the light-emitting device ED.

[0038] The first terminal of the switching transistor Tsw1 can be connected to the data line DL, the second terminal of the switching transistor Tsw1 can be connected to the gate of the driving transistor Tdr, and the gate of the switching transistor Tsw1 can be connected to the gate line GL.

[0039] The data voltage Vdata can be supplied to the data line DL, and the gate signal GS can be supplied to the gate line GL.

[0040] The sensing transistor Tsw2 can be configured to measure the threshold voltage or mobility of the driving transistor. The first terminal of the sensing transistor Tsw2 can be connected to the second terminal of the driving transistor Tdr and the light-emitting device ED. The second terminal of the sensing transistor Tsw2 can be connected to the sensing line SL through which the reference voltage Vref is supplied. The gate of the sensing transistor Tsw2 can be connected to the sensing control line through which the sensing control signal is supplied.

[0041] The sensing line SL can be connected to the data driver 300 and can also be connected to the power supply 500 through the data driver 300. That is, the reference voltage Vref supplied from the power supply 500 can be supplied to the pixel through the sensing line SL, and the sensing signal transmitted from the pixel can be processed by the data driver 300.

[0042] The structure of pixel 110 applied in this disclosure is not limited to Figure 2 The structure shown. Therefore, the structure of pixel 110 can be changed into various shapes.

[0043] Furthermore, this disclosure can be applied to liquid crystal display (LCD) devices including liquid crystal display panels and devices including… Figure 2 The light-emitting display device shown is a light-emitting device. That is to say, this disclosure can be applied to various display devices currently in use. However, in the following description, for ease of description, the light-emitting display device will be described as an example of this disclosure.

[0044] The controller 400 can rearrange the input video data transmitted from the external system using a timing synchronization signal transmitted from the external system, and can generate a data control signal DCS to be supplied to the data driver 300 and a gate control signal GCS to be supplied to the gate driver 200.

[0045] Therefore, such as Figure 3 As shown, the controller 400 may include: a data adjuster 430, which rearranges input video data to generate image data Data and supplies the image data Data to the data driver 300; a control signal generator 420, which generates a gate control signal GCS and a data control signal DCS using a timing synchronization signal; an input unit 410, which receives the timing synchronization signal and input video data transmitted from an external system and transmits the timing synchronization signal and input video data to the data adjuster and the control signal generator 420, respectively; and an output unit 440, which supplies the image data Data generated by the data adjuster and the data control signal DCS generated by the control signal generator 420 to the data driver 300, and supplies the gate control signal GCS generated by the control signal generator 420 to the gate driver 200.

[0046] The controller 400 may include a storage unit 450 for storing various information.

[0047] The data control signal DCS generated by the control signal generator 420 may include a source output enable signal SOE, which controls the timing of the data voltage being output to the data line.

[0048] The source output enable signal SOE generated by the control signal generator 420 can be transmitted to the data driver 300.

[0049] In other words, the controller 400 can generate a source output enable signal SOE that determines the output timing of the data voltage Vdata to the data line DL, and can transmit the generated source output enable signal SOE to the data driver 300.

[0050] An external system can perform the functions of the controller 400 and the electronic device. For example, when the electronic device is a TV, the external system can receive various audio, video, and text information via a communication network and transmit the received video information to the controller 400. In this case, the image information may include input video data.

[0051] The power supply 500 can generate various types of electricity and can supply the generated electricity to the controller 400, the gate driver 200, the data driver 300, and the display panel 100.

[0052] The gate driver 200 can be configured as an IC and mounted in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) type. When using the GIP type, the transistors constituting the gate driver 200 can be disposed in the non-display area using the same process as the transistors included in each pixel 110.

[0053] The gate driver 200 can supply gate pulses GP1 to GPg to gate lines GL1 to GLg.

[0054] When a gate pulse generated by the gate driver 200 is supplied to the switching transistor Tsw1 included in the pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, the data voltage supplied through the data line can be supplied to the pixel 110.

[0055] When the gate cutoff signal generated by the gate driver 200 is supplied to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, data voltage can no longer be supplied to the pixel 110.

[0056] The gate signal GS supplied to the gate line GL may include the gate pulse GP and the gate cutoff signal.

[0057] Therefore, such as Figure 4 As shown, the gate driver 200 may include multiple stages 201.

[0058] Each stage 201 can be connected to at least one gate line GL. Each stage 201 can be driven by a start signal transmitted from the controller 400, or by a start signal transmitted from the previous stage or the next stage.

[0059] Each stage 201 may include at least two transistors and can be configured in various forms.

[0060] Finally, the data driver 300 can be included in a chip-on-film (COF) attached to the display panel 100, or it can be directly mounted in the display panel 100.

[0061] The data driver 300 can supply the data voltage Vdata to the data lines DL1 to DLd.

[0062] The data driver 300 can shift the source start pulse transmitted from the controller 400 based on the source shift clock to generate a sampling signal. Furthermore, the data driver 300 can latch multiple image data lines based on the sampling signal, convert the latched image data lines into data voltages, and supply the corresponding data voltages to the data lines DL1 to DLd based on the final source output enable signal.

[0063] Specifically, the data driver 300 can perform the function of randomly changing the output timing of the data voltage Vdata for each gate line by using the source output enable signal SOE transmitted from the controller 400.

[0064] In the following text, reference will be made to Figures 1 to 8 Describe the structure and function of data drive 300.

[0065] Figure 5 This is an example diagram illustrating the configuration of a data driver applied to a display device according to the present disclosure.

[0066] As described above, the data driver 300 can latch multiple image data transmitted from the controller 400 based on the sampling signal, convert the latched multiple image data into data voltage, and supply the data voltage corresponding to the gate line to the data lines DL1 to DLd based on the final source output enable signal.

[0067] In particular, the data driver 300 applied in this disclosure can perform the function of randomly changing the output timing of the data voltage Vdata of each gate line by using the source output enable signal SOE transmitted from the controller 400.

[0068] The source output enable signal SOE can have at least four bits. Each of the four bits can have a value of 0 or 1.

[0069] In other words, the data driver 300 can determine the output timing of each data voltage based on the source output enable signal SOE, which consists of four bits.

[0070] However, the data driver 300 may not use the source output enable signal SOE as is. That is, the data driver 300 can generate a final source output enable signal SOEF by using the source output enable signal SOE, and can randomly change the output timing of the data voltage Vdata of each gate line by using the final source output enable signal SOEF.

[0071] In this configuration, the data driver 300 can change at least two of the four bits to generate the final source output enable signal SOEF, and can randomly change the output timing of the data voltage for each gate line by using the final source output enable signal SOEF.

[0072] The timing of outputting the data voltage Vdata to the data line DL can vary based on the falling timing of the gate pulses GP1 to GPg that are output to the gate lines GL1 to GLg.

[0073] Therefore, such as Figure 5 As shown, the data driver 300 may include: a shift register 310 that outputs a sampling signal; a latch unit 320 that latches image data Data received from the controller 400; a digital-to-analog converter (DAC) 330 that converts the image data Data transmitted from the latch unit 310 into a data voltage Vdata and outputs the data voltage Vdata; an output buffer 340 that outputs the data voltage transmitted from the DAC 330 to the data line DL based on the final source output enable signal SOEF; and a signal changer that generates the final source output enable signal SOEF using the final source output enable signal SOEF and randomly changes the output timing of the data voltage of each gate line using the final source output enable signal SOEF.

[0074] First, the shift register 310 can output a sampled signal using the data control signal DCS received from the controller 400.

[0075] The latch unit 320 can latch multiple image data Data received sequentially from the controller 400, and can simultaneously output multiple image data Data to the DAC 330.

[0076] DAC 330 can simultaneously convert multiple image data Data transmitted from latch unit 320 into data voltages Vdata1 to Vdatad and can output data voltages Vdata1 to Vdatad.

[0077] The output buffer 340 can simultaneously output the data voltages Vdata1 to Vdatad transmitted from the DAC 330 to the data lines DL1 to DLd of the display panel based on the final source output enable signal SOEF transmitted from the signal changer 350.

[0078] For this purpose, the output buffer 340 may include a buffer 341 for storing the data voltage Vdata transmitted from the DAC 330 and a switch 342 for transmitting the data voltage Vdata stored in the buffer 341 to the data line DL.

[0079] In other words, the output buffer 340 may include a switch 342 and a buffer 341 corresponding to the data lines DL1 to DLd.

[0080] More specifically, when switch 342 is turned on based on the final source output enable signal SOEF simultaneously supplied to switch 342, the data voltage Vdata stored in buffer 341 can be supplied to data lines DL1 to DLd through switch 342.

[0081] The data voltages Vdata1 to Vdatad supplied to the data lines DL1 to DLd can be supplied to the pixel connected to the gate line GL of the supplied gate pulse GP.

[0082] Therefore, the timing of the data voltages Vdata1 to Vdatad being output to data lines DL1 to DLd can be determined based on the final source output enable signal SOEF.

[0083] Finally, the signal changer 350 can generate a final source output enable signal SOEF by using the source output enable signal SOE, and can randomly change the output timing of the data voltage Vdata of each gate line by using the final source output enable signal SOEF.

[0084] For this purpose, the signal changer 350 may include a random bit generator 351 that generates at least two random bits and a bit mixer 352 that replaces at least two of the at least four bits of the source output enable signal SOE with at least two random bits to generate the final source output enable signal SOEF.

[0085] In other words, the source output enable signal SOE generated by the controller 400 and supplied to the data driver 300 may include at least four bits, and the signal changer 350 may change at least two of the at least four bits to generate the final source output enable signal SOEF.

[0086] For this purpose, the random bit generator 351 can generate at least two random bits.

[0087] For example, when the final source output enable signal SOEF consists of eight bits, and each of the eight bits has a value of 0 or 1, the random bit generator 351 can generate two random bits. The value of each of these two bits can be 0 or 1.

[0088] In this case, based on two random bits, the number of occurrences in the bit mixer 352 can be four. Therefore, the timing of outputting the data voltage to the data line DL can be divided into four timings.

[0089] For example, when the source output enable signal SOE, which consists of eight bits, has a value of [10111010], the last two bits of the eight bits can be changed to one of four values ​​(i.e., [00,01,10,11]) generated by two random bits.

[0090] Therefore, the final source output enable signal SOEF generated by the bit mixer 352 can be one of the values ​​[10111000], [10111001], [10111010], and [10111011].

[0091] In other words, the signal changer 350 can generate one of four final source output enable signals SOEF by using the source output enable signal SOE transmitted from the controller 400.

[0092] In this case, the random bit generator 351 can randomly generate two random bits, and therefore the bit mixer 352 can also randomly generate the final source output enable signal SOEF.

[0093] Therefore, the timing of outputting the data voltage to the data line DL can be divided into four timing steps.

[0094] However, as mentioned above, the source output enable signal SOE can consist of at least four bits, and the random bit generator 351 can generate at least two random bits.

[0095] Therefore, as the number of random bits generated by the random bit generator 351 increases, the timing of the data voltage being output to the data line DL can also be divided differently.

[0096] For example, when the number of random bits is three, the number of combinations that can be generated by the three random bits can be eight (e.g.,

[000] ,

[001] ,

[010] ,

[011] ,

[100] ,

[101] ,

[110] , and

[111] ). Therefore, when the number of random bits is three, the timing of the output data voltage can be divided into eight timings.

[0097] More specifically, the switch 342 constituting the output buffer 340 can be turned on based on the final source output enable signal SOEF and can output the data voltage to the data line.

[0098] In this case, the timing of switch 342 being turned on can be determined by the value of the bit of the final source output enable signal SOEF.

[0099] Therefore, when there are four cases where the final source output enable signal SOEF is received, the timing of outputting the data voltage to the data line DL can be divided into four timing steps.

[0100] In this case, the timing of outputting the data voltage to the data line can vary based on the falling timing of the gate pulse output to the gate line.

[0101] In the following text, reference will be made to Figures 6 to 8 Describe its detailed examples.

[0102] Figure 6 This is an example diagram showing the waveforms of the gate signal and data voltage applied to the display device according to this disclosure.

[0103] In the following description, a display device having an eight-bit source output enable signal SOE and two random bits generated by a random bit generator 351 will be used as an example of this disclosure.

[0104] In other words, as described above, when the source output enable signal SOE generated by the controller 400 and supplied to the data driver 300 consists of eight bits and two random bits are generated by the random bit generator 351, the number of final source output enable signals SOEF that can be generated by using one source output enable signal SOE can be four.

[0105] In this case, such as Figure 6 As shown, the interval between the final source output enable signal SOEF and the fall timing of each gate pulse output to the gate line can be controlled based on two random bits.

[0106] For example, such as Figure 1 and 6 As shown, the five gate pulses GPn to GPn+4 output to the five consecutive gate lines GLn to GLn+4 can have the same pulse width and the same interval. That is, the timing of the rise of the gate pulses GPn to GPn+4 and the timing of the fall of the gate pulses GPn to GPn+4 can be repeated at the same interval.

[0107] In this case, the data voltage Vdata supplied through the data line at the timing of the gate pulse GP falling can eventually be charged into pixel 110, and light corresponding to the charging voltage can be emitted from pixel 110.

[0108] Therefore, when the data voltage Vdata overlaps with the timing of the gate pulse GP falling, the overlapped data voltage Vdata can be supplied to the pixel.

[0109] In this case, such as Figure 6 As shown, the interval between the final source output enable signal SOEF and the falling timing of each of the gate pulses GPn to GPn+4 can be controlled based on two random bits. Therefore, the timing of outputting the data voltage to the data line can vary based on the falling timing of the gate pulse.

[0110] Specifically, according to the embodiment, four final source output enable signals SOEF can be output based on two random bits, thus the timing of the output data voltage can be divided into four timings.

[0111] For example, the nth data voltage n, which is output to the data line at the timing of the nth gate pulse GPn being output to the nth gate line GLn, can be based on the nth final source output enable signal SOEFn. The final source output enable signal SOEF, which includes the nth final source output enable signal SOEFn, can have a digital value, but for ease of description, it is... Figure 6 The waveform of the final source output enable signal SOEF is shown in the figure. In this case, the nth final source output enable signal SOEFn may include random bits

[00] .

[0112] In other words, the nth data voltage n can be output to the pixel connected to the nth gate line GLn based on the nth final source output enable signal SOEFn, which includes the random bit

[00] .

[0113] In this case, such as Figure 6 As shown, the interval between the timing of the nth gate pulse GPn falling and the timing of the nth data voltage n being output to the data line can be interval A.

[0114] Furthermore, the (n+1)th data voltage n+1 can be output to the data line based on the (n+1)th final source output enable signal SOEFn+1. In this case, the (n+1)th final source output enable signal SOEFn+1 may include random bits

[01] .

[0115] In other words, the (n+1)th data voltage n+1 can be output to the pixel connected to the (n+1)th gate line GLn+1 based on the (n+1)th final source output enable signal SOEFn+1 including the random bit

[01] .

[0116] In this case, such as Figure 6As shown, the interval between the timing of the (n+1)th gate pulse GPn+1 falling and the timing of the (n+1)th data voltage n+1 being output to the data line can be interval B.

[0117] Furthermore, the (n+2)th data voltage n+2 can be output to the data line based on the (n+2)th final source output enable signal SOEFn+2. In this case, the (n+2)th final source output enable signal SOEFn+2 may include random bits

[10] .

[0118] In other words, the n+2 data voltage n+2 can be output to the pixel connected to the n+2 gate line GLn+2 based on the n+2 final source output enable signal SOEFn+2 including the random bit

[10] .

[0119] In this case, such as Figure 6 As shown, the interval between the timing of the (n+2)th gate pulse GPn+2 falling and the timing of the (n+2)th data voltage n+2 being output to the data line can be an interval C.

[0120] In addition, the (n+3)th data voltage n+3 can be output to the data line based on the (n+3)th final source output enable signal SOEFn+3. In this case, the (n+3)th final source output enable signal SOEFn+3 may include random bits

[11] .

[0121] In other words, the n+3 data voltage n+3 can be output to the pixel connected to the n+3 gate line GLn+3 based on the n+3 final source output enable signal SOEFn+3 including the random bit

[11] .

[0122] In this case, such as Figure 6 As shown, the interval between the timing of the (n+3)th gate pulse GPn+3 falling and the timing of the (n+3)th data voltage n+3 being output to the data line can be an interval D.

[0123] In this case, intervals A, B, C, and D can be different. Therefore, the data voltage output through a single data line DL can be output at different timings for each gate line.

[0124] However, at least two of intervals A, B, C, and D can be the same, and intervals A, B, C, and D can be non-repeating.

[0125] In other words, in this disclosure, the random bit generator 351 can randomly select two random bits. Therefore, it is not necessary to select random bits

[00] , random bits

[01] , random bits

[10] and random bits

[11] in sequence, and the order of selecting random bits

[00] , random bits

[01] , random bits

[10] and random bits

[11] is not fixed.

[0126] For example, in the above embodiments, the final source output enable signals SOEFn, SOEFn+1, SOEFn+2 and SOEFn+3 can be generated by sequentially selecting random bits

[00] , random bits

[01] , random bits

[10] and random bits

[11] , or the final source output enable signals SOEFn, SOEFn+1, SOEFn+2 and SOEFn+3 can be generated in the order of random bits

[00] , random bits

[11] , random bits

[10] and random bits

[01] .

[0127] In addition, final source output enable signals SOEFn and SOEFn+1, including random bit

[00] and random bit

[11] , can be generated. Then, final source output enable signals SOEFn+2 and SOEFn+3, including random bit

[01] and random bit

[10] , can be generated.

[0128] Furthermore, the (n+4)th data voltage n+4 can be output to the data line based on the (n+4)th final source output enable signal SOEFn+4, which is the timing output of the (n+4)th gate pulse GPn+4 to the (n+4)th gate line GLn+4. In this case, the (n+4)th final source output enable signal SOEFn+4 may include one of random bit

[00] , random bit

[01] , random bit

[10] , and random bit

[11] .

[0129] For example, in Figure 6 The example shown is based on the output of the (n+4)th final source output enable signal SOEFn+4 using random bit

[01] . Therefore, as Figure 6 As shown, the interval between the timing of the (n+4)th gate pulse GPn+4 falling and the timing of the (n+4)th data voltage n+4 being output to the data line can be interval B.

[0130] Therefore, the timing of outputting the (n+4)th data voltage n+4 to the data line based on the (n+4)th final source output enable signal SOEFn+4 can be the same as the timing of outputting the (n+1)th data voltage n+1 to the data line based on the (n+1)th final source output enable signal SOEFn+1.

[0131] In other words, the four pairs of random bits mentioned above do not have to be selected every four times, and their order can also be changed in various ways.

[0132] Therefore, according to this disclosure, the timing of outputting the data voltage to the gate line does not need to be based on a certain rule. Therefore, according to this disclosure, EMI caused by outputting the data voltage at a constant timing can be prevented or minimized.

[0133] Figure 7 and Figure 8 This is an example diagram used to describe the output timing of the data voltage output by the display device according to this disclosure. Specifically, Figure 7 This is an example diagram that visually illustrates different timings of data voltage being output to the gate line.

[0134] In other words, as described above, the timing for outputting the nth data voltage Vdatan to the pixel connected to the nth gate line GLn can be different from the timing for outputting the (n+1)th data voltage Vdatan+1 to the pixel connected to the (n+1)th gate line GLn+1.

[0135] Therefore, as Figure 7 As shown, the timing of the output data voltage of each gate line can be different. In particular, the timing of outputting the data voltage to the data line can be different based on the falling timing of the gate pulse GP output to the gate line.

[0136] In addition, such as Figure 7 As shown, the rise timing R and fall timing F of each gate pulse GP output to gate lines n to n+4 can be constant.

[0137] However, based on the falling timing F of the gate pulse GP, the timing of outputting the nth data voltage Vdatan to the (n+4th)th data voltage Vdatan+4 can be different. However, the timing of outputting the nth data voltage Vdatan to the (n+4th)th data voltage Vdatan+4 can include the same timing. That is, in Figure 6 and Figure 7 In the embodiment, the timing B for outputting the (n+4)th data voltage Vdatan+4 to the data line via the (n+4)th final source output enable signal SOEFn+4 can be the same as the timing for outputting the (n+1)th data voltage Vdatan+1 to the data line via the (n+1)th final source output enable signal SOEFn+1.

[0138] Therefore, as Figure 8 As shown, the time intervals K1 to K4 between the output of data voltages Vdatan to Vdatan+4 to the data line can also be changed randomly.

[0139] As described above, according to this disclosure, the timing of outputting the data voltage to the gate line does not need to be based on a certain rule. Therefore, according to this disclosure, EMI caused by outputting the data voltage at a constant timing can be prevented or minimized.

[0140] In this disclosure, the timing of the data voltage being output to the data line can be randomly varied for each gate line. Therefore, according to this disclosure, EMI caused by outputting data voltage at a constant timing can be prevented or minimized.

[0141] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, anything relating to combinations and modifications should be understood within the scope of this disclosure.

[0142] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes gate lines and data lines; A controller that generates a source output enable signal, which determines the output timing of the data voltage output to the data line; as well as A data driver, comprising a signal changer, generates a final source output enable signal using the source output enable signal, and randomly changes the output timing of the data voltage for each gate line using the final source output enable signal. The source output enable signal includes at least four bits, and The signal changer includes: A random bit generator that generates at least two random bits; and A bit mixer that replaces at least two of the at least four bits with the at least two random bits to generate the final source output enable signal.

2. The display device according to claim 1, wherein, The data driver changes at least two of the at least four bits to generate the final source output enable signal, and randomly changes the output timing of the data voltage of each gate line by using the final source output enable signal.

3. The display device according to claim 1, wherein, The data driver includes: A latching unit that latches image data received from the controller; A digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage and outputs the data voltage. An output buffer that outputs the data voltage transmitted from the digital-to-analog converter to the data line based on the final source output enable signal; and The signal changer, and The output timing is based on the final source output enable signal, which randomly changes the data voltage of each gate line.

4. The display device according to claim 3, wherein, The output buffer includes: A buffer that stores the data voltage transmitted from the digital-to-analog converter; and A switch that transmits the data voltage stored in the buffer to the data line based on the final source output enable signal.

5. The display device according to claim 1, wherein, The timing of outputting the data voltage to the data line is divided into at least four timing intervals.

6. The display device according to claim 5, wherein, The timing of outputting the data voltage to the data line varies based on the falling timing of the gate pulses output to the gate lines included in the display panel.

7. The display device according to claim 1, wherein, The timing of outputting the nth data voltage to the pixel connected to the nth gate line among the gate lines included in the display panel via the data line is different from the timing of outputting the (n+1)th data voltage to the pixel connected to the (n+1)th gate line via the data line.

8. The display device according to claim 1, wherein, The timing of outputting the data voltage to the data line varies based on the falling timing of the gate pulses output to the gate lines included in the display panel.

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