Drive Circuit, Driving Method, and Display Device

Abstract

The present application discloses a driving circuit, a driving method, and a display device, relating to the field of display technologies. The driving circuit includes a memory, a timing controller, and a power supply chip. The memory is connected to the timing controller and the power supply chip. The power supply chip includes a first parsing module and a working module, and the working module includes a fault output terminal. The timing controller includes a second parsing module and a reset terminal. During the startup phase, the timing controller reads the driving data located in the memory through the second parsing module and parses it. The timing controller transmits the parsed driving data to the first parsing module of the power supply chip for the power supply chip to use. During the fault phase, the fault output terminal outputs a fault signal, and the reset terminal receives the fault signal to control the timing controller and the power supply chip to be reset together. The driving circuit of the present application does not require a non-volatile memory to be provided in the power supply chip, reducing the labor cost and the material cost.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a driving circuit, a driving method, and a display device. Background Art

[0002] In order to solve the problem that a large number of pins are required when a traditional power chip (Power IC) is set through an analog resistor, which brings a complex layout of a printed circuit board (PCB), more and more power chips are designed in a digital manner using an Inter-Integrated Circuit (I2C); however, a non-volatile memory (NVM) usually needs to be set in the power chip designed by this solution to store the setting configuration information of the power chip, so as to ensure that the configuration information after power-off can be saved and avoid the inability to store the setting configuration information of the power chip when power-off.

[0003] However, since an additional non-volatile memory needs to be set in the power chip, the structure of the printed circuit board in the display device is complicated, and at the same time, the test steps are also increased during package testing, increasing the labor cost and material cost, which is very inconvenient. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, a driving method, and a display device, which do not need to set a non-volatile memory in the power chip, reducing the labor cost and material cost.

[0005] This application discloses a driving circuit. The driving circuit includes a memory, a timing controller, and a power chip. The memory is connected to the timing controller and the power chip. The power chip includes a first parsing module and a working module. The input end of the first parsing module is connected to the timing controller, and the output end of the first parsing module is connected to the working module. The working module includes a fault output end; the timing controller includes a second parsing module and a reset end. The input end of the second parsing module is connected to the output end of the memory, and the reset end is connected to the fault output end; wherein, during the power-on stage, the timing controller reads the driving data located in the memory through the second parsing module and parses it, and the timing controller transmits the parsed driving data to the first parsing module of the power chip for the power chip to use; during the fault stage, the fault output end outputs a fault signal, and the reset end receives the fault signal to control the timing controller and the power chip to be reset together.

[0006] Optionally, the working module includes a register, a logic module, a delay control module, and a transistor. The input end of the register is connected to the output end of the first parsing module, the output end of the register is connected to the input end of the logic module, the output end of the logic module is connected to the input end of the delay control module, the output end of the delay control module is connected to the gate of the transistor. The power supply chip further includes a first grounding end, the first grounding end is connected to the drain of the transistor, and the fault output end is connected to the source of the transistor. Wherein, in the fault stage, the logic module outputs a high-level signal, which is output to the gate of the transistor after being delayed by the delay control module to control the transistor to conduct, so that the fault output end outputs a corresponding fault signal.

[0007] Optionally, the delay control module includes an inverter, a delay controller, and a logic OR gate. The input end of the inverter and the input end of the delay controller are both connected to the output end of the logic module. The output end of the inverter and the output end of the delay controller are both connected to the input end of the logic OR gate. The output end of the logic OR gate is connected to the gate of the transistor. Wherein, in the normal display stage, the logic module outputs a low-level signal, the inverter and the delay controller receive the low-level signal output by the logic module and output a low-level signal. At this time, the logic OR gate outputs a low-level signal. In the fault stage, the logic module outputs a high-level signal, the inverter and the delay controller receive the high-level signal output by the logic module. The inverter outputs a high-level signal to the logic OR gate, and the delay controller outputs a low-level signal to the logic OR gate. At this time, the output of the logic OR gate is a low-level signal. After delaying for N seconds, the delay controller outputs a high-level signal to the logic OR gate. At this time, the output of the logic OR gate is a high-level signal to turn on the transistor. Wherein, N is greater than 0.

[0008] Optionally, the timing controller includes a reset control module, and the input end of the reset control module is connected to the reset end. Wherein, after receiving the fault signal, the reset end transmits it to the reset control module, and the reset control module controls the timing controller to be reset.

[0009] Optionally, the driving circuit further includes a power supply interface, a pull-up resistor, a storage capacitor, and a second grounding end. The power supply interface is connected to the input end of the pull-up resistor, the output end of the pull-up resistor is connected to the reset end, the fault output end, and the input end of the storage capacitor. The output end of the storage capacitor is connected to the second grounding end.

[0010] Optionally, the connection between the memory and the timing controller and the power supply chip is an integrated circuit bus connection.

[0011] Optionally, the memory is an electrically erasable programmable read-only memory.

[0012] Optionally, the driving circuit includes a printed circuit board, and the memory, the timing controller, and the power supply chip are all disposed on the printed circuit board.

[0013] The present application also discloses a driving method, which is applied to the driving circuit as described above, and includes the steps of:

[0014] The timing controller reads the driving data located in the memory and parses it;

[0015] Transmit the parsed driving data corresponding to the power supply chip to the first parsing module of the power supply chip; and,

[0016] Drive the power supply chip to work according to the parsed driving data.

[0017] The present application also discloses a display device, which includes a display panel and the driving circuit as described above, and the driving circuit is used to drive the display panel.

[0018] Compared with the solution of setting a non-volatile memory in the power supply chip, in the present application, by setting a first parsing module, a second parsing module, and a memory, the second parsing module reads the driving data stored in the memory and parses it, and transmits a part of the parsed driving data to the first parsing module for the power supply chip to use. Therefore, there is no need to set a non-volatile memory in the power supply chip, which reduces the labor cost and material cost. At the same time, the fault output terminal of the power supply chip is connected to the reset terminal of the timing controller. When the power supply chip fails, the fault output terminal of the power supply chip will output a fault signal to the reset terminal, and the reset terminal receives the fault signal to control the timing controller and the power supply chip to be reset together, so that the timing controller does not need to set a read-back function, reducing the design complexity of the timing controller. Description of the Drawings

[0019] The included drawings are used to provide a further understanding of the embodiments of the present application, and they form a part of the specification, are used to illustrate the implementation manners of the present application, and are used to explain the principles of the present application together with the text description. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings. In the drawings:

[0020] Figure 1 is a schematic diagram of the overall structure of a driving circuit according to the first embodiment of the present application;

[0021] Figure 2 is a schematic diagram of the structure of the delay control module in the first embodiment of the present application;

[0022] Figure 3It is a timing diagram at the reset terminal, fault output terminal, and power supply interface in the first embodiment of the present application;

[0023] Figure 4 It is a schematic structural diagram of a driving circuit in the second embodiment of the present application;

[0024] Figure 5 It is a flowchart of the steps of a driving method in the third embodiment of the present application;

[0025] Figure 6 It is a schematic structural diagram of a display device in the fourth embodiment of the present application.

[0026] Among them, 100, driving circuit; 110, memory; 120, timing controller; 121, second parsing module; 122, reset control module; 130, power chip; 131, first parsing module; 132, working module; 133, register; 134, logic module; 135, delay control module; 137, inverter; 138, delay controller; 139, logic OR gate; 140, pull-up resistor; 150, storage capacitor; 160, printed circuit board; 200, display panel; 300, display device. Detailed implementation manners

[0027] It should be understood that the terms, specific structures, and functional details disclosed herein are only for the purpose of describing specific embodiments, which are representative, but the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments set forth herein.

[0028] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any variation thereof means an inclusive inclusion, and there may be one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0029] In addition, the terms indicating the orientation or positional relationship such as "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only for the purpose of facilitating the simplified description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0030] In addition, unless otherwise clearly defined and limited, the terms "install", "connect", and "couple" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, or a communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, on the premise of no conflict, the following-described embodiments or technical features can be arbitrarily combined to form new embodiments.

[0032] As Figure 1 shown, as the first embodiment of the present application, a driving circuit 100 is disclosed. The driving circuit 100 includes a memory 110, a timing controller 120 (TCON IC, Timing Control IC), and a power chip 130 (Power IC). The memory 110 is connected to the timing controller 120 and the power chip 130. The power chip 130 includes a first parsing module 131 and a working module 132. The input end of the first parsing module 131 is connected to the timing controller 120, and the output end of the first parsing module 131 is connected to the working module 132. The working module 132 includes a fault output end Fault. The timing controller 120 includes a second parsing module 121 and a reset end Reset. The input end of the second parsing module 121 is connected to the output end of the memory 110, and the reset end Reset is connected to the fault output end Fault;

[0033] During the startup phase, the timing controller 120 reads and parses the driving data located in the memory 110 through the second parsing module 121. The timing controller 120 transmits the parsed driving data to the first parsing module 131 of the power supply chip 130 for the power supply chip 130 to use. Thus, there is no need to set a non-volatile memory 110 in the power supply chip 130. Compared with the solution of setting a non-volatile memory 110 in the power supply chip 130, the cost and manufacturing process of the non-volatile memory 110 are saved, and further the material cost and labor cost of the power supply chip 130 are reduced. In the fault phase, the fault output terminal Fault outputs a fault signal, and the reset terminal Reset receives the fault signal to control the timing controller 120 and the power supply chip 130 to be reset together. During this process, the power supply chip 130 will actively output a fault signal from the fault output terminal Fault. Since the reset terminal Reset of the timing controller 120 is connected to the fault output terminal Fault, the reset terminal Reset of the timing controller 120 will receive the fault signal output from the fault output terminal Fault, so that the timing controller 120 knows that the power supply chip 130 is in the fault phase at this time. The timing controller 120 can know whether the power supply chip 130 is in the fault phase without setting a read-back function, and the timing controller 120 can also be reset together with the power supply chip 130, reducing the setting complexity of the timing controller 120. That is, the original timing controller 120 in the original design can be used without improving the timing controller 120, reducing the setting cost of the driving circuit 100. When the timing controller 120 and the power supply chip 130 are reset, the timing controller 120 reads and parses the driving data located in the memory 110 through the second parsing module 121, and transmits the parsed driving data to the first parsing module 131 of the power supply chip 130 for the power supply chip 130 to use to complete the reset and display the normal picture. It should be noted that the memory 110 stores the first driving data for driving the timing controller 120 and the second driving data for driving the power supply chip 130, making full use of the space in the memory 110. The first driving data and the second driving data need to be parsed by the timing controller 120 before they can be supplied for use.

[0034] In this embodiment, the connection between the memory 110, the timing controller 120, and the power supply chip 130 is an Inter-Integrated Circuit (I2C) connection. With the I2C communication protocol, only one data line and one clock line are required to complete half-duplex communication. After the power supply chip 130 adopts I2C, the relevant settings can be modified through I2C. The first parsing module 131 and the second parsing module 121 are both I2C control modules, which are used to receive the data transmitted through the I2C bus. The timing controller 120 serves as the communication master device, and the power supply chip 130 serves as the communication slave device. Since the timing controller 120 has better functional expandability than the power supply chip 130, using it as the communication master device can effectively reduce the cost of the power supply chip 130 and make full use of the processing power of the timing controller 120. The memory 110 is an Electrically Erasable Programmable Read Only Memory (EEPROM). EEPROM is a user-modifiable read-only memory that can erase existing information and reprogram new data on special devices such as computers. It has good stability and security, and a flexible and wide range of applications, making it an ideal memory for use in display driver devices.

[0035] Further, the working module 132 includes a register 133 (Register), a logic module 134 (Logic), a delay control module 135, and a transistor. The input end of the register 133 is connected to the output end of the first parsing module 131. The output end of the register 133 is connected to the input end of the logic module 134. The output end of the logic module 134 is connected to the input end of the delay control module 135. The output end of the delay control module 135 is connected to the gate of the transistor. The power supply chip 130 also includes a first ground terminal GND1, and the first ground terminal GND1 is connected to the drain of the transistor. The fault output terminal Fault is connected to the source of the transistor.

[0036] During the fault stage, the logic module 134 determines that the power supply chip 130 is faulty. The logic module 134 outputs a high-level signal, which is output to the gate of the transistor after being delayed by the delay control module 135 to control the transistor to conduct, so that the fault output terminal Fault outputs a corresponding fault signal. The reset terminal Reset receives the fault signal to enable the timing controller 120 to know that the power supply chip 130 is faulty at this time, and then controls the timing controller 120 and the power supply chip 130 to be reset together to restore the drive data when the normal display screen is restored. During the normal display stage, the logic module 134 determines that the power supply chip 130 is in a normal working state. The logic module 134 outputs a low-level signal, which is output to the gate of the transistor through the delay control module 135. At this time, the transistor does not conduct, the fault output terminal Fault does not output a fault signal, and the reset terminal Reset does not receive a fault signal, so that the timing controller 120 continues to work normally. Among them, the setting of the delay control module 135 is to reserve sufficient time for the voltages of the timing controller 120 and the power supply chip 130 to drop from high level to low level and then recover from low level to high level to complete a reset during the reset. It should be noted that the setting of the delay control module 135 can be to set the delay value during the manufacture of the power supply chip 130, or to modify the delay value through other external settings. The specific details are not elaborated, and the designer can choose the design according to actual needs.

[0037] Specifically, as Figure 2 shown, the delay control module 135 includes an inverter 137, a delay controller 138 (DelayControl), and a logic OR gate 139. The input terminal of the inverter 137 and the input terminal of the delay controller 138 are both connected to the output terminal of the logic module 134. The output terminal of the inverter 137 and the output terminal of the delay controller 138 are both connected to the input terminal of the logic OR gate 139. The output terminal of the logic OR gate 139 is connected to the gate of the transistor;

[0038] During the normal display stage, the logic module 134 determines that the power supply chip 130 is in a normal operating state. The logic module 134 outputs a low-level signal. At this time, the inverter 137 and the delay controller 138 receive the low-level signal output by the logic module 134 and output a low-level signal to the OR gate 139. After receiving the low-level signal, the OR gate 139 outputs a low-level signal to the gate of the transistor. At this time, the transistor will not conduct, and both the fault output terminal Fault and the reset terminal Reset are high-level signals. The timing controller 120 and the power supply chip 130 will not be reset. During the fault stage, the logic module 134 determines that the power supply chip 130 is in a fault state. The logic module 134 outputs a high-level signal. The inverter 137 and the delay controller 138 receive the high-level signal output by the logic module 134. The inverter 137 outputs a high-level signal to the OR gate 139. At this time, the delay controller 138 will still output a low-level signal to the OR gate 139 under its own setting, causing the OR gate 139 to output a low-level signal, and the transistor will not conduct temporarily. After a delay of N seconds preset by the delay controller 138, the delay controller 138 will output a high-level signal to the OR gate 139 at this time. The OR gate 139 receives the high-level signals from both the delay controller 138 and the inverter 137 simultaneously and outputs a high-level signal to the gate of the transistor to turn on the transistor. At this time, the fault output terminal Fault of the power supply chip 130 and the reset terminal Reset of the timing controller 120 are low-level signals. When the timing controller 120 detects that the reset terminal Reset is a low-level signal, it determines that the power supply chip 130 is in the fault stage at this time, so that the timing controller 120 and the power supply chip 130 are reset to restore the normal display of the display screen. Generally speaking, by setting the delay controller 138, when the power supply chip 130 has an abnormal fault, the power supply chip 130 will not perform a reset process immediately, but will inform the timing controller 120 after a delay of a period of time by the delay controller 138, so as to reserve a time for the voltages of the timing controller 120 and the power supply chip 130 to drop from a high level to a low level, and then the timing controller 120 and the power supply chip 130 will perform a reset operation together. The voltages of the timing controller 120 and the power supply chip 130 will return from a low level to a high level to complete the reset. Among them, the timing diagrams of the reset terminal Reset and the fault output terminal Fault are as Figure 3 shown; in this embodiment, N is greater than 0; it should be noted that the delay time of the delay controller 138 is set to N seconds. The setting of N can be a numerical setting during the manufacturing of the power supply chip 130, or the numerical setting can be modified through other external settings. This will not be elaborated here.

[0039] Further, the timing controller 120 includes a reset control module 122 (Reset Control), and the input end of the reset control module 122 is connected to the reset terminal Reset; when an abnormal fault occurs in the power chip 130, the fault output end of the power chip 130 will output a fault signal, that is, output a low-level signal as described above. After the reset terminal receives the fault signal and transmits it to the reset control module 122, after detecting the fault signal, the reset control module 122 controls the timing controller 120 to be reset; when the power chip 130 is operating normally, the fault output end of the power chip 130 outputs a high-level signal, and the reset terminal is also a high-level signal. When the reset control terminal detects that the reset terminal is a high-level signal, it does not perform a reset.

[0040] As Figure 1 shown, the driving circuit 100 further includes a power supply interface VDD, a pull-up resistor 140, a storage capacitor 150, and a second ground terminal GND2. The power supply interface is connected to the input end of the pull-up resistor 140. The output end of the pull-up resistor 140 is connected to the reset terminal Reset, the fault output end Fault, and the input end of the storage capacitor 150. The output end of the storage capacitor 150 is connected to the second ground terminal GND2. In this embodiment, since the fault output end Fault and the reset terminal Reset are connected, the output end of the pull-up resistor 140 is simultaneously connected to the reset terminal Reset and the fault output end Fault, and there is no need to separately set a pull-up resistor 140 for the reset terminal Reset and the fault output end Fault, saving a pull-up resistor 140 device, thereby reducing the material cost of the driving circuit 100.

[0041] As Figure 4As shown in the figure, as the second embodiment of the present application, which is an improvement of the first embodiment, a driving circuit 100 is disclosed. The driving circuit 100 includes a printed circuit board 160. The memory 110, the timing controller 120, and the power supply chip 130 are all disposed on the printed circuit board 160. With the layout of the printed circuit board 160 formed by the memory 110, the timing controller 120, and the power supply chip 130 set in this embodiment, the printed circuit board 160 not only has a simple layout, but also can make full use of the space inside the memory 110, saving the non-volatile memory 110 of the power supply chip 130 on the printed circuit board 160, reducing the space occupied by the power supply chip 130. Moreover, the fault output terminal of the power supply chip 130 is connected to the reset terminal of the timing controller 120, so that only one pull-up resistor 140 needs to be set between the fault output terminal of the power supply chip 130 and the reset terminal of the timing controller 120, saving a pull-up resistor 140 device and reducing the material cost. All in all, the design of the driving circuit 100 in this embodiment complements each other. It can not only reduce the material cost and labor cost of the power supply chip 130, but also the power supply chip 130 and the timing controller 120 can be linked during reset and reset simultaneously. The timing controller 120 also does not need to set a read-back function, reducing the complexity of the timing controller 120, so that designers can use the original timing controller 120 without design improvement on the timing controller 120.

[0042] As Figure 5 shown, as the third embodiment of the present application, a driving method is disclosed, which is applied to the driving circuit as described above. The driving method includes the steps:

[0043] The timing controller reads and parses the driving data located in the memory;

[0044] Transmit the parsed driving data corresponding to the power supply chip to the first parsing module of the power supply chip;

[0045] Drive the power supply chip to work according to the parsed driving data;

[0046] During the startup phase, the timing controller reads and parses the driving data located in the memory through the second parsing module, and transmits the parsed driving data to the first parsing module of the power supply chip for the power supply chip to use, so that there is no need to set a non-volatile memory in the power supply chip, making full use of the space in the memory, saving the cost and manufacturing process of the non-volatile memory, and further reducing the material cost and labor cost of the power supply chip;

[0047] The driving method further includes the steps:

[0048] The power supply chip outputs a fault signal;

[0049] The timing controller receives a fault signal;

[0050] The timing controller and the power supply chip are reset together;

[0051] The timing controller reads and parses the driving data located in the memory;

[0052] The parsed driving data corresponding to the power supply chip is transmitted to the first parsing module of the power supply chip;

[0053] The power supply chip is driven to work according to the parsed driving data;

[0054] In the fault stage, the fault output terminal of the power supply chip outputs a fault signal, and the fault output terminal is connected to the reset terminal of the timing controller. After the reset terminal of the timing controller receives the fault signal, the timing controller and the power supply chip are reset together, so that the reset terminal of the timing controller and the fault output terminal of the power supply chip are linked. When resetting, the timing controller reads and parses the driving data located in the memory through the second parsing module, and transmits the parsed driving data to the first parsing module of the power supply chip for the power supply chip to use, so as to complete the reset and the power supply chip works normally.

[0055] As Figure 6 shown, as the fourth embodiment of the present application, a display device 300 is disclosed. The display device 300 includes a display panel 200 and the driving circuit 100 as described above. The driving circuit 100 is used to drive the display panel 200. In the display device 300 of this embodiment, by setting the first parsing module 131, the second parsing module 121 and the memory 110, the second parsing module 121 reads and parses the driving data stored in the memory 110, and transmits a part of the parsed driving data to the first parsing module 131 for the power supply chip 130 to use, so that there is no need to set a non-volatile memory 110 in the power supply chip 130, reducing the labor cost and material cost, making full use of the space in the memory 110. At the same time, the fault output terminal of the power supply chip 130 is connected to the service terminal of the timing controller 120. When the power supply chip 130 fails, there is no need for the timing controller 120 to read back the state of the power supply chip 130. The fault output terminal will output a fault signal to the reset terminal to inform the timing controller 120, so that the timing controller 120 and the power supply chip 130 are reset together, reducing the design complexity of the timing controller 120.

[0056] It should be noted that, without affecting the implementation of the specific solution, the limitations of each step involved in this solution do not determine the order of the steps. The steps written in the front can be executed first, or can be executed later, or even can be executed simultaneously. As long as the solution can be implemented, it should be regarded as falling within the protection scope of this application.

[0057] The technical solution of this application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, and the above solutions are all applicable.

[0058] It should be noted that the inventive concept of this application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments. After the combination of each embodiment or technical feature, the original technical effect will be enhanced.

[0059] The above content is a further detailed description of this application in combination with specific optional implementation manners. It cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, several simple deductions or substitutions can still be made, and all should be regarded as falling within the protection scope of this application.

Claims

1. A driving circuit, the driving circuit includes a memory, a timing controller and a power supply chip, the memory is connected to the timing controller and the power supply chip, and is characterized in that, The power supply chip includes a first parsing module and a working module. The input end of the first parsing module is connected to a timing controller, the output end of the first parsing module is connected to the working module, and the working module includes a fault output end; The timing controller includes a second parsing module and a reset end. The input end of the second parsing module is connected to the output end of the memory, and the reset end is connected to the fault output end; The working module includes a register, a logic module, a delay control module, and a transistor. The input end of the register is connected to the output end of the first parsing module, the output end of the register is connected to the input end of the logic module, the output end of the logic module is connected to the input end of the delay control module, the output end of the delay control module is connected to the gate of the transistor. The power supply chip also includes a first grounding end, the first grounding end is connected to the drain of the transistor, and the fault output end is connected to the source of the transistor; Wherein, during the power-on stage, the timing controller reads the driving data located in the memory through the second parsing module and performs parsing, and the timing controller transmits the parsed driving data to the first parsing module of the power supply chip for the power supply chip to use; during the fault stage, the fault output end outputs a fault signal, and the reset end receives the fault signal to control the timing controller and the power supply chip to be reset together; wherein, during the fault stage, the logic module outputs a high-level signal, which is output to the gate of the transistor after being delayed by the delay control module to control the transistor to conduct, so that the fault output end outputs a corresponding fault signal.

2. The drive circuit according to claim 1, wherein The delay control module includes an inverter, a delay controller, and a logic OR gate. The input end of the inverter and the input end of the delay controller are both connected to the output end of the logic module. The output end of the inverter and the output end of the delay controller are both connected to the input end of the logic OR gate. The output end of the logic OR gate is connected to the gate of the transistor; wherein, during the normal display stage, the logic module outputs a low-level signal, and the inverter and the delay controller receive the low-level signal output by the logic module and output a low-level signal. At this time, the logic OR gate outputs a low-level signal; during the fault stage, the logic module outputs a high-level signal, the inverter and the delay controller receive the high-level signal output by the logic module, the inverter outputs a high-level signal to the logic OR gate, and the delay controller outputs a low-level signal to the logic OR gate. At this time, the output of the logic OR gate is a low-level signal. After delaying for N seconds, the delay controller outputs a high-level signal to the logic OR gate. At this time, the output of the logic OR gate is a high-level signal to turn on the transistor; wherein, N is greater than 0.

3. The drive circuit according to claim 1, wherein The timing controller includes a reset control module, and the input end of the reset control module is connected to the reset end; Wherein, after the reset end receives the fault signal, it is transmitted to the reset control module, and the reset control module controls the timing controller to be reset.

4. The drive circuit according to claim 1, wherein It further includes a power supply interface, a pull-up resistor, a storage capacitor, and a second grounding terminal. The power supply interface is connected to the input terminal of the pull-up resistor. The output terminal of the pull-up resistor is connected to the reset terminal, the fault output terminal, and the input terminal of the storage capacitor. The output terminal of the storage capacitor is connected to the second grounding terminal.

5. The drive circuit according to claim 1, wherein The connection between the memory and the timing controller and the power supply chip is an integrated circuit bus connection.

6. The drive circuit according to claim 1, wherein The memory is an electrically erasable programmable read-only memory.

7. The drive circuit according to claim 1, wherein The driving circuit includes a printed circuit board, and the memory, the timing controller, and the power supply chip are all disposed on the printed circuit board.

8. A driving method, applied to the driving circuit according to any one of claims 1 to 7, characterized in that It includes the steps of: The timing controller reads and analyzes the driving data located in the memory; Transmitting the analyzed driving data corresponding to the power supply chip to the first parsing module of the power supply chip; And driving the power supply chip to operate according to the analyzed driving data.

9. A display device, characterized in that, It includes a display panel and the driving circuit according to any one of claims 1 to 7, and the driving circuit is used to drive the display panel.

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