Organic light emitting diode display device and driving method thereof

Abstract

An organic light emitting diode display device and a driving method thereof are provided. The organic light emitting diode display device includes a plurality of pixels arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of gate 1 lines in contact with the plurality of pixels and providing gate 1 voltages to the plurality of pixels, a plurality of gate 2 lines in contact with the plurality of pixels of a portion of the plurality of columns and providing gate 2 voltages to the plurality of pixels of the portion of the plurality of columns, a plurality of gate 3 lines in contact with the plurality of pixels of another portion of the plurality of columns and providing gate 3 voltages to the plurality of pixels of the other portion of the plurality of columns, and a plurality of left data lines and a plurality of right data lines respectively positioned at both sides of the plurality of pixels of the plurality of columns. Accordingly, variation (ripple) of a high level voltage is reduced and distortion of a data voltage is minimized. Furthermore, degradation such as crosstalk is reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0185661, filed on December 23, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to an organic light-emitting diode (OLED) display device, and more specifically, to an OLED display device including a low-level line that minimizes coupling between the gate electrode and the anode by providing a low-level line between the gate electrode and the anode of each sub-pixel. Background Technology

[0004] With the development of the information society, the field of display devices has developed rapidly. Flat panel display (FPD) devices with thin profiles, light weight, and low power consumption have been developed.

[0005] Among various flat panel display devices, organic light-emitting diode (OLED) displays are light-emitting devices and do not include the backlight unit used in non-light-emitting devices such as liquid crystal displays (LCDs). As a result, OLED displays have advantages in viewing angle, contrast ratio, and power consumption, and are therefore used in a wide range of fields.

[0006] In OLED display devices, data voltage output from the data driving unit is supplied to the pixels of the display panel to display images. Because the application time of the data voltage to the pixels is reduced due to increases in resolution and driving speed, the charging time of the data lines is also reduced.

[0007] To address the aforementioned issues, an OLED display device has been proposed that uses two multiplexed transistors and two data lines to provide data voltage to a single pixel column.

[0008] In OLED display devices using two multiplexed transistors and two data lines, one data line floats for one horizontal time period because two adjacent pixel rows are driven to overlap. Furthermore, the data voltage of the floating data line is distorted due to variations in the high-level voltage (ripple) caused by the switching of the data voltage of the other data line. As a result, degradation such as crosstalk occurs. Summary of the Invention

[0009] Therefore, this disclosure relates to an organic light-emitting diode display device and a driving method thereof, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0010] One object of this disclosure is to provide an organic light-emitting display device and a driving method thereof, in which the number of pixel columns corresponding to floating data lines is reduced by dividing multiple pixel columns into odd and even arrays and assigning different sampling periods to the multiple pixel columns of the odd and even arrays, the distortion of the data lines due to changes in high-level voltage (ripple) is reduced, and crosstalk is reduced.

[0011] Another objective of this disclosure is to provide an organic light-emitting diode (OLED) display device and its driving method. In this OLED display device, by setting a common block for two pixels, multiple pixel columns are divided into odd and even arrays, and different sampling periods are assigned to the multiple pixel columns of the odd and even arrays. This stabilizes the operation of the pixel columns corresponding to the common block, reduces the number of pixel columns corresponding to the floating data lines, reduces the distortion of the data lines caused by changes in high-level voltage (ripple), and reduces crosstalk.

[0012] Additional features and advantages of this disclosure will be set forth in the following description, and some of these additional features and advantages will become apparent from the description or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained through the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0013] To achieve these and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, an organic light-emitting diode (OLED) display device includes: a plurality of pixels arranged in a matrix of a plurality of rows and a plurality of columns; a plurality of gate 1 lines contacting the plurality of pixels and providing a gate 1 voltage to the plurality of pixels; a plurality of gate 2 lines contacting a plurality of pixels in a portion of the plurality of columns and providing a gate 2 voltage to the plurality of pixels in the portion of the plurality of columns; a plurality of gate 3 lines contacting a plurality of pixels in another portion of the plurality of columns and providing a gate 3 voltage to the plurality of pixels in the other portion of the plurality of columns; and a plurality of left data lines and a plurality of right data lines respectively located on either side of the plurality of pixels in the plurality of columns.

[0014] In another aspect, a method for driving an organic light-emitting diode display device includes: initializing a plurality of pixels in a plurality of rows according to a gate 1 voltage; sampling a plurality of pixels in a portion of a plurality of columns according to a gate 2 voltage; sampling a plurality of pixels in another portion of the plurality of columns according to a gate 3 voltage; and emitting light from the plurality of pixels according to a light-emitting voltage.

[0015] It should be understood that the foregoing general description and the following detailed description are interpretive and intended to provide further explanation of the claimed contents of this disclosure. Attached Figure Description

[0016] The accompanying drawings, included to provide a further understanding of this disclosure, are incorporated in and form part of this specification. These drawings illustrate various embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0017] Figure 1 This is a diagram illustrating an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0018] Figure 2 This is a diagram showing the multiplexing unit and display panel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0019] Figure 3 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0020] Figure 4 This is a diagram illustrating multiple signals used in a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0021] Figures 5A to 5C This is a diagram illustrating the connection and operation of pixels in an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0022] Figure 6A and Figure 6B These are diagrams illustrating the high-level voltage changes of the organic light-emitting diode display device according to the comparative example and the first embodiment of the present disclosure, respectively.

[0023] Figure 7 This is a diagram showing the connection of pixels in an organic light-emitting diode display device according to a second embodiment of the present disclosure;

[0024] Figures 8A to 8D This is a plan view showing pixels 1-1 to 2-4 of an organic light-emitting diode display device according to a second embodiment of the present disclosure; and

[0025] Figure 9 This is a cross-sectional view showing the transistors and gate lines of an organic light-emitting diode display device according to a second embodiment of the present disclosure. Detailed Implementation

[0026] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following exemplary embodiments described in conjunction with the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0027] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples. Therefore, this disclosure is not limited to the details shown. The same reference numerals always denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations may be omitted when it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure. Where the terms “comprising,” “having,” and “including” are used as described in this specification, additional parts may be added unless more restrictive terms such as “only” are used. Unless otherwise stated, singular terms may include plural forms.

[0028] When interpreting components, even if such an error or tolerance range is not explicitly described, the component is interpreted as including an error or tolerance range.

[0029] When describing positional relationships, if the positional relationship between two components is described as such as "up," "above," "below," or "next," one or more additional components may be placed between the two components unless more restrictive terms such as "only" or "directly" are used.

[0030] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other or together in a mutually dependent relationship.

[0032] In the following description, an organic light-emitting diode (OLED) display device and a method for driving an OLED display device according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals always denote the same elements. Detailed descriptions of well-known functions or configurations related to this document will be omitted or simplified when it is determined that such detailed descriptions unnecessarily obscure the spirit of the present disclosure concept.

[0033] Figure 1 This is a diagram illustrating an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0034] exist Figure 1 According to the first embodiment of the present disclosure, the organic light-emitting diode (OLED) display device 110 includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, a multiplexing unit 150, and a display panel 160.

[0035] The timing control unit 120 uses image signals transmitted from an external system such as a graphics card or television system, and multiple timing signals including a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, to generate image data, data control signals, and gate control signals. The image data and data control signals are transmitted to the data drive unit 130, and the gate control signals are transmitted to the gate drive unit 140.

[0036] The data drive unit 130 uses the data control signal and image data transmitted from the timing control unit 120 to generate a data voltage (data signal) and transmits the data voltage to the multiplexing unit 150.

[0037] The gate driving unit 140 uses the gate control signal transmitted from the timing control unit 120 to generate a gate voltage (gate signal) and applies the gate voltage to the gate line GL of the display panel 160.

[0038] The gate driving unit 140 may have an in-panel gate (GIP) type, and be formed in the display panel 160 together with the gate line GL, the left data line DLL, the right data line DLR, and the pixel P.

[0039] The multiplexing unit 150 selectively applies the data voltage of the data driving unit 120 to one of the left data line DLL and the right data line DLR of the display panel 160.

[0040] The multiplexing unit 150 is positioned corresponding to the short side of the display panel 160 and is connected to the left data line DLL and the right data line DLR. The multiplexing unit 150 may include ( Figure 2 The first multiplexed transistor Tm1 and the second multiplexed transistor Tm2.

[0041] Display panel 160 uses gate voltage and data voltage to display images. Display panel 160 includes a display area DA for displaying images and a non-display area NDA surrounding the display area DA. Multiple pixels P, multiple gate lines GL, multiple left data lines DLL, and multiple right data lines DLR are disposed in the display area DA, and gate driving unit 140 and multiplexing unit 150 are disposed in the non-display area NDA.

[0042] Each of the multiple pixels P includes multiple subpixels SP. For example, the multiple subpixels SP may include a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb.

[0043] Gate line GL intersects with left data line DLL and right data line DLR to define sub-pixel SP.

[0044] The left data line DLL and the right data line DLR are set to the left and right of each subpixel SP, and each subpixel SP is connected to one of the left data line DLL and the right data line DLR.

[0045] For example, the sub-pixel SP of the odd-numbered row (odd-numbered horizontal pixel row) HLo can be connected to the gate line GL and the left data line DLL, and the sub-pixel SP of the even-numbered row HLe can be connected to the gate line GL and the right data line DLR.

[0046] The multiplexing unit of the OLED display device 110 will be described with reference to the accompanying drawings.

[0047] Figure 2 This is a diagram showing the multiplexing unit and display panel of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0048] exist Figure 2 In the first embodiment of the OLED display device 110 according to this disclosure, the multiplexing unit 150 includes a first multiplexing transistor Tm1 and a second multiplexing transistor Tm2. The first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 may be positive (P) type.

[0049] The first multiplexing transistor Tm1 is switched (on or off) according to the first multiplexing voltage MUX1 to transmit the data voltage Vdata of the data driving unit 130 to the left data line DLL of the display panel 160, and the second multiplexing transistor Tm2 is switched according to the second multiplexing voltage MUX2 to transmit the data voltage Vdata of the data driving unit 130 to the right data line DLR of the display panel 160.

[0050] For example, the first multiplexer voltage MUX1 and the second multiplexer voltage MUX2 may include square waves with opposite polarities and a width of a horizontal time period (1H).

[0051] During a horizontal period in which the first multiplexing transistor Tm1 is turned on and the second multiplexing transistor Tm2 is turned off, the data voltage Vdata of the data driving unit 130 is supplied by the multiplexing unit 150 to the sub-pixels SP of the odd-numbered rows HLo through the left data line DLL of the display panel 160.

[0052] During a horizontal period in which the first multiplexing transistor Tm1 is off and the second multiplexing transistor Tm2 is on, the data voltage Vdata of the data driving unit 130 is provided by the multiplexing unit 150 to the sub-pixels SP of the even-numbered rows HLe through the right data line DLR of the display panel 160.

[0053] During one horizontal time period, a data voltage Vdata is supplied to the left data line DLL, and during the next horizontal time period, when the data voltage Vdata is supplied to the sub-pixel SP of even-numbered rows HLe via the right data line DLR, the data voltage Vdata remains in the floating left data line DLL. As a result, the application time for each sub-pixel SP increases to two horizontal time periods, and the charging time of the data voltage Vdata increases.

[0054] The operation of pixel P of OLED display device 110 will be described with reference to the accompanying drawings.

[0055] Figure 3 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure, and Figure 4 This is a diagram illustrating multiple signals used in a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0056] exist Figure 3 middle,( Figure 2 The display panel 160 has multiple pixels P, including pixel Pn1 in the (n-1)th row and first column, pixel Pn2 in the (n-2)th row and second column, pixel P(n+1)1 in the (n+1)th row and first column, and pixel P(n+1)2 in the (n+1)th row and second column. Each of pixel Pn1, pixel Pn2, pixel P(n+1)1, and pixel P(n+1)2 includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb. Here, n can be odd and (n+1) can be even.

[0057] Each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb includes a driving transistor Td, a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, and a light-emitting diode De, and the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb further include a seventh transistor T7 to a ninth transistor T9.

[0058] The driving transistor Td, the first transistor T1 to the sixth transistor T6, the storage capacitor Cst and the light-emitting diode De are disposed in each of the red sub-pixel SPr, the green sub-pixel SPg and the blue sub-pixel SPb, and the seventh transistor T7 to the ninth transistor T9 are disposed in a pixel P composed of the red sub-pixel SPr, the green sub-pixel SPg and the blue sub-pixel SPb.

[0059] For example, the driving transistor Td and the first transistor T1 to the ninth transistor T9 may include positive (P) type polycrystalline silicon thin film transistors.

[0060] In the red sub-pixel SPr of the (n-1)th pixel Pn1, the driving transistor Td switches according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the driving transistor Td is connected to the first electrode of the storage capacitor Cst, the drain electrode of the first transistor T1, and the source electrode of the sixth transistor T6. The source electrode of the driving transistor Td is connected to the drain electrode of the second transistor T2 and the source electrode of the third transistor T3. Furthermore, the drain electrode of the driving transistor Td is connected to the source electrode of the first transistor T1 and the source electrode of the fourth transistor T4.

[0061] The first transistor T1 is switched according to the nth gate 2 voltage S2(n). The gate electrode of the first transistor T1 is connected to the nth gate 2 voltage S2(n), the source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor Td and the source electrode of the fourth transistor T4, and the drain electrode of the first transistor T1 is connected to the gate electrode of the driving transistor Td, the first electrode of the storage capacitor Cst and the source electrode of the sixth transistor T6.

[0062] The second transistor T2 in the switching transistor is switched according to the nth gate 2 voltage S2(n). The gate electrode of the second transistor T2 is connected to the nth gate 2 voltage S2(n), the source electrode of the second transistor T2 is connected to the odd data voltage Vdatao, and the drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor Td and the source electrode of the third transistor T3.

[0063] The third transistor T3 is switched according to the nth emission voltage Em(n). The gate electrode of the third transistor T3 is connected to the nth emission voltage Em(n), the source electrode of the third transistor T3 is connected to the drain electrode of the second transistor T2 and the source electrode of the driving transistor Td, and the drain electrode of the third transistor T3 is connected to the high-level voltage Vdd and the source electrode of the seventh transistor T7.

[0064] The fourth transistor T4, acting as a light-emitting transistor, switches according to the nth light-emitting voltage Em(n). The gate electrode of the fourth transistor T4 is connected to the nth light-emitting voltage Em(n), the source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor Td and the source electrode of the first transistor T1, and the drain electrode of the fourth transistor T4 is connected to the anode of the light-emitting diode De, the source electrode of the fifth transistor T5 of the (n+1)-1th pixel P(n+1)1 in the next row, and the drain electrode of the sixth transistor T6.

[0065] The fifth transistor T5 is switched according to the nth gate 1 voltage S1(n). The gate electrode of the fifth transistor T5 is connected to the nth gate 1 voltage S1(n), the source electrode of the fifth transistor T5 is connected to the drain electrode of the sixth transistor T6, the drain electrode of the fourth transistor T4 of the red sub-pixel SPr of the (n-1)-1 pixel P(n-1)1 in the previous row, and the anode of the light-emitting diode De, and the drain electrode of the fifth transistor T5 is connected to the initial voltage Vini.

[0066] The sixth transistor T6 is switched according to the nth gate 1 voltage S1(n). The gate electrode of the sixth transistor T6 is connected to the nth gate 1 voltage S1(n), the source electrode of the sixth transistor T6 is connected to the gate electrode of the driving transistor Td, the first electrode of the storage capacitor Cst and the drain electrode of the first transistor T1, and the drain electrode of the sixth transistor T6 is connected to the source electrode of the fifth transistor T5, the drain electrode of the fourth transistor T4 of the red sub-pixel SPr of the (n-1)-1 pixel P(n-1)1 in the previous row and the anode of the light-emitting diode De.

[0067] The storage capacitor Cst stores the odd data voltage Vdatao, the threshold voltage Vth, and the high-level voltage Vdd. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor Td, the drain electrode of the first transistor T1, and the source electrode of the sixth transistor T6, and the second electrode of the storage capacitor Cst is connected to the drain electrode of the seventh transistor T7, the source electrode of the eighth transistor T8, and the source electrode of the ninth transistor T9.

[0068] The light-emitting diode De is connected between the fourth transistor T4 and the low-level voltage Vss, and emits light with a brightness proportional to the current driving the transistor Td. The anode of the light-emitting diode De is connected to the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5 of the (n+1)-1 pixel P(n+1)1, and the drain electrode of the sixth transistor T6, and the cathode of the light-emitting diode De is connected to the low-level voltage Vss.

[0069] The connection structure of the driving transistor Td, the first transistor T1 to the sixth transistor T6, the storage capacitor Cst, and the light-emitting diode De of the green sub-pixel SPg and the blue sub-pixel SPb of the (n-1)th pixel Pn1 is the same as that of the driving transistor Td, the first transistor T1 to the sixth transistor T6, the storage capacitor Cst, and the light-emitting diode De of the red sub-pixel SPr of the (n-1)th pixel Pn1.

[0070] In the (n-1)th pixel Pn1, the seventh transistor T7 switches according to the nth luminous voltage Em(n). The gate electrode of the seventh transistor T7 is connected to the nth luminous voltage Em(n), the source electrode of the seventh transistor T7 is connected to the drain electrode of the third transistor T3 of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb and the high-level voltage Vdd, and the drain electrode of the seventh transistor T7 is connected to the source electrode of the eighth transistor T8, the source electrode of the ninth transistor T9, and the second electrode of the storage capacitor Cst of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb.

[0071] The eighth transistor T8 switches according to the nth gate voltage S1(n). The gate electrode of the eighth transistor T8 is connected to the nth gate voltage S1(n), the source electrode of the eighth transistor T8 is connected to the source electrode of the ninth transistor T9 (red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb), the drain electrode of the seventh transistor T7, and the second electrode of the storage capacitor Cst, and the drain electrode of the eighth transistor T8 is connected to the reference voltage Vref.

[0072] The ninth transistor T9 switches according to the nth gate 2 voltage S2(n). The gate electrode of the ninth transistor T9 is connected to the nth gate 2 voltage S2(n), the source electrode of the ninth transistor T9 is connected to the source electrode of the eighth transistor T8 (red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb), the drain electrode of the seventh transistor T7, and the second electrode of the storage capacitor Cst, and the drain electrode of the ninth transistor T9 is connected to the reference voltage Vref.

[0073] Except that the gate electrodes of the first transistor T1, the second transistor T2, and the ninth transistor T9 are connected to the nth gate 3 voltage S3(n) and the first transistor T1, the second transistor T2, and the ninth transistor T9 are switched according to the nth gate 3 voltage S3(n), the structure of the driving transistor Td, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light-emitting diode De of the (n-2)th pixel Pn2 is the same as the structure of the driving transistor Td, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light-emitting diode De of the (n-1)th pixel Pn1.

[0074] Except that the first transistor T1 to the ninth transistor T9 are switched according to the (n+1)th voltage such as the (n+1)th gate 1 voltage S1(n+1), the (n+1)th gate 2 voltage S2(n+1), and the (n+1)th light emission voltage Em(n+1), and the source electrode of the second transistor T2 is connected to the even data voltage Vdatae, the structure of the driving transistor Td of the (n+1)-1 pixel P(n+1)1, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light emission diode De are the same as the structure of the driving transistor Td of the (n-1)-1 pixel Pn1, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light emission diode De.

[0075] Except that the gate electrodes of the first transistor T1, the second transistor T2, and the ninth transistor T9 are connected to the (n+1)th gate 3 voltage S3(n+1) and the first transistor T1, the second transistor T2, and the ninth transistor T9 are switched according to the (n+1)th gate 3 voltage S3(n+1), the structure of the driving transistor Td of the (n+1)-2 pixel P(n+1)2, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light-emitting diode De are the same as the structure of the driving transistor Td of the (n+1)-1 pixel P(n+1)1, the first transistor T1 to the ninth transistor T9, the storage capacitor Cst, and the light-emitting diode De.

[0076] Although not shown, the structure of pixel P in odd-numbered rows HL and odd-numbered columns (vertical pixel rows) VL is the same as the structure of pixel Pn1 (n-1), and the structure of pixel P in odd-numbered rows HL and even-numbered columns VL is the same as the structure of pixel Pn2 (n-2). The structure of pixel P in even-numbered rows HL and odd-numbered columns VL is the same as the structure of pixel P(n+1)1 (n+1)1 (n+1)1 (n+1)2 ...

[0077] exist Figure 4In this context, the frames used to display the image include a first time period TP1 to a sixth time period TP6. Each of the first time periods TP1 to the sixth time period TP6 may be a horizontal time period 1H in which a data voltage Vdata is applied to a row HL of the display panel 160.

[0078] During the first time period TP1, the second multiplexer voltage MUX2 and the nth gate 1 voltage S1(n) become low level voltage Vl, and the first multiplexer voltage MUX1, the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the (n+1)th gate 2 voltage S2(n+1), the nth gate 3 voltage S3(n), the (n+1)th gate 3 voltage S3(n+1), the nth light emission voltage Em(n), and the (n+1)th light emission voltage Em(n+1) become high level voltage Vh. The second multiplexing transistor Tm2; and the fifth transistor T5, sixth transistor T6, and eighth transistor T8 of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 are turned on, and the first multiplexing transistor Tm1; the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, seventh transistor T7, and ninth transistor T9 of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2; and the first transistor T1 to the ninth transistor T9 of the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 are turned off. The first and second electrodes of the storage capacitor Cst of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 become the initial voltage Vini and the reference voltage Vref, respectively, and the gate electrode of the driving transistor Td of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 is initialized.

[0079] During the second time period TP2, the first multiplexer voltage MUX1 and the (n+1)th gate 1 voltage S1(n+1) become low level voltages Vl, and the second multiplexer voltage MUX2, the nth gate 1 voltage S1(n), the (n+1)th gate 2 voltage S2(n+1), the nth gate 3 voltage S3(n), the (n+1)th gate 3 voltage S3(n+1), the nth light emission voltage Em(n), and the (n+1)th light emission voltage Em(n+1) become high level voltages Vh. The first multiplexing transistor Tm1; the first transistor T1, the second transistor T2, and the ninth transistor T9 of the (n-1)th pixel Pn1; and the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 of the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 are turned on, and the second multiplexing transistor Tm2; the third transistor T3 to the eighth transistor T8 of the (n-1)th pixel Pn1; the first transistor T1 to the ninth transistor T9 of the (n-2)th pixel Pn2; and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the ninth transistor T9 of the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 are turned off. The first electrode of the storage capacitor Cst for the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst. The first electrode and the second electrode of the storage capacitor Cst for the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 become the initial voltage Vini and the reference voltage Vref, respectively, and the gate electrode of the driving transistor Td for the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 is initialized.

[0080] During the third time period TP3, the second multiplexer voltage MUX2, the nth gate 2 voltage S2(n) and the (n+1)th gate 2 voltage S2(n+1) become low level voltages Vl, and the first multiplexer voltage MUX1, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 3 voltage S3(n), the (n+1)th gate 3 voltage S3(n+1), the nth light emission voltage Em(n) and the (n+1)th light emission voltage Em(n+1) become high level voltages Vh. The second multiplexing transistor Tm2; and the first transistor T1, the second transistor T2, and the ninth transistor T9 of the (n-1)th pixel Pn1 and the (n+1)-1th pixel P(n+1)1 are turned on, and the first multiplexing transistor Tm1; the third transistor T3 to the eighth transistor T8 of the (n-1)th pixel Pn1 and the (n+1)-1th pixel P(n+1)1; and the first transistor T1 to the ninth transistor T9 of the (n-2)th pixel Pn2 and the (n+1)-2th pixel P(n+1)2 are turned off. The first electrode of the storage capacitor Cst of the (n-1)th pixel Pn1 and the (n+1)-1th pixel P(n+1)1 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst.

[0081] During the fourth time period TP4, the first multiplexer voltage MUX1 and the (n+1)th gate 2 voltage S2(n+1) become low-level voltages Vl, and the second multiplexer voltage MUX2, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the nth gate 3 voltage S3(n), the (n+1)th gate 3 voltage S3(n+1), the nth light emission voltage Em(n), and the (n+1)th light emission voltage Em(n+1) become high-level voltages Vh. The first multiplexing transistor Tm1; and the first transistor T1, the second transistor T2, and the ninth transistor T9 of the (n+1)-1th pixel P(n+1)1 are turned on, and the second multiplexing transistor Tm2; the first transistors T1 to the ninth transistor T9 of the (n+1)-1th pixel Pn1, the (n-2)th pixel Pn2, and the (n+1)-2th pixel P(n+1)2; and the third transistors T3 to the eighth transistor T8 of the (n+1)-1th pixel P(n+1)1 are turned off. The first electrode of the storage capacitor Cst of the (n+1)-1th pixel P(n+1)1 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst.

[0082] During the fifth time period TP5, the second multiplexer voltage MUX2 and the nth gate 3 voltage S3(n) become low-level voltages Vl, and the first multiplexer voltage MUX1, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the (n+1)th gate 2 voltage S2(n+1), the (n+1)th gate 3 voltage S3(n+1), the nth emission voltage Em(n), and the (n+1)th emission voltage Em(n+1) become high-level voltages Vh. The second multiplexing transistor Tm2; and the first transistor T1, the second transistor T2, and the ninth transistor T9 of the (n-2)th pixel Pn2 are turned on, and the first multiplexing transistor Tm1; the first transistors T1 to T9 of the (n-1)th pixel Pn1, the (n+1)-1th pixel P(n+1)1, and the (n+1)-2th pixel P(n+1)2; and the third transistors T3 to T8 of the (n-2)th pixel Pn2 are turned off. The first electrode of the storage capacitor Cst of the (n-2)th pixel Pn2 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst.

[0083] During the sixth time period TP6, the first multiplexer voltage MUX1 and the nth gate 3 voltage S3(n) become low level voltage Vl, and the second multiplexer voltage MUX2, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the (n+1)th gate 2 voltage S2(n+1), the nth light emission voltage Em(n), and the (n+1)th light emission voltage Em(n+1) become high level voltage Vh. The first multiplexing transistor Tm1; and the first transistor T1, the second transistor T2, and the ninth transistor T9 of the (n-2)th pixel Pn2 and the (n+1)-2nd pixel P(n+1)2 are turned on, and the second multiplexing transistor Tm2; the first transistors T1 to the ninth transistor T9 of the (n-1)th pixel Pn1 and the (n+1)-1st pixel P(n+1)1; and the third transistors T3 to the eighth transistor T8 of the (n-2)th pixel Pn2 and the (n+1)-2nd pixel P(n+1)2 are turned off. The first electrode of the storage capacitor Cst of the (n-2)th pixel Pn2 and the (n+1)-2nd pixel P(n+1)2 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst.

[0084] During the seventh period TP7, the second multiplexer voltage MUX2 and the (n+1)th gate 3 voltage S3(n+1) become low-level voltages Vl, and the first multiplexer voltage MUX1, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the (n+1)th gate 2 voltage S2(n+1), the nth gate 3 voltage S3(n), the nth emission voltage Em(n), and the (n+1)th emission voltage Em(n+1) become high-level voltages Vh. The second multiplexing transistor Tm2 and the first transistor T1, second transistor T2, and ninth transistor T9 of the (n+1)-2nd pixel P(n+1)2 are turned on, and the first multiplexing transistor Tm1; the first transistors T1 to the ninth transistor T9 of the (n-1)th pixel Pn1, the (n-2)th pixel Pn2, and the (n+1)-1th pixel P(n+1)1; and the third transistors T3 to the eighth transistor T8 of the (n+1)-2nd pixel P(n+1)2 are turned off. The first electrode of the storage capacitor Cst of the (n+1)-2nd pixel P(n+1)2 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst.

[0085] During the eighth period TP8, the second multiplexer voltage MUX2 and the nth emission voltage Em(n) become low-level voltage Vl, and the first multiplexer voltage MUX1, the nth gate 1 voltage S1(n), the (n+1)th gate 1 voltage S1(n+1), the nth gate 2 voltage S2(n), the (n+1)th gate 2 voltage S2(n+1), the nth gate 3 voltage S3(n), the (n+1)th gate 3 voltage S3(n+1), and the (n+1)th emission voltage Em(n+1) become high-level voltage Vh. The second multiplexing transistor Tm2; and the third transistor T3, the fourth transistor T4 and the seventh transistor T7 of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 are turned on, and the first multiplexing transistor Tm1; the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2; and the first transistor T1 to the ninth transistor T9 of the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 are turned off. The second electrode of the storage capacitor Cst for the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 becomes a high-level voltage Vdd, and the first electrode of the storage capacitor Cst for the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 becomes a value (Vdd-Vref+Vdata+Vth) obtained by adding the difference between the high-level voltage Vdd and the reference voltage Vref (Vdd-Vref) to the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth). As a result, a current flows into the driving transistor Td proportional to the square of the value (Vdd-Vref) obtained by subtracting the threshold voltage Vth from the gate-source voltage (Vgs=(Vg-Vs)=(Vdd-Vref+Vdata+Vth)-Vdd=Vdata-Vref+Vth). The data voltage Vdata and the threshold voltage Vth are stored in the storage capacitor Cst, and the light-emitting diode De emits light with a brightness corresponding to the current of the driving transistor Td.

[0086] Although not shown, the light-emitting diodes De of the (n+1)-1 pixel P(n+1)1 and the (n+1)-2 pixel P(n+1)2 begin to emit light from the end of the eighth time period TP8.

[0087] During the first time period TP1, the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 are initialized (initialization time period of odd-numbered rows HLo).

[0088] During the second time period TP2 and the third time period TP3, the sum of the data voltage Vdata and the threshold voltage Vth (Vdd + Vth) is stored in the gate electrode of the driving transistor Td of the (n-1)th pixel Pn1 and the first electrode of the storage capacitor Cst (sampling periods for odd-numbered rows HLo and odd-numbered columns VLo). During the fifth time period TP5 and the sixth time period TP6, the sum of the data voltage Vdata and the threshold voltage Vth (Vdd + Vth) is stored in the gate electrode of the driving transistor Td of the (n-2)th pixel Pn2 and the first electrode of the storage capacitor Cst (sampling periods for odd-numbered rows HLo and even-numbered columns VLe).

[0089] Here, during the second time period TP2, the first multiplexing transistor Tm1 is turned on, and the left data line DLL of the odd-numbered rows HLo and odd-numbered columns VLo is charged with data voltage Vdata. During the third time period TP3, the first multiplexing transistor Tm1 is turned off, and the left data line DLL of the odd-numbered rows HLo and odd-numbered columns VLo is floated, so that the data voltage Vdata charged in the left data line DLL is maintained.

[0090] During the fifth time period (TP5), the second multiplexing transistor Tm2 is turned on, and the right data line DLR of the odd-numbered row (HLo) and even-numbered column (VLe) is charged with the data voltage Vdata. During the sixth time period (TP3), the second multiplexing transistor Tm2 is turned off, and the right data line DLR of the odd-numbered row (HLo) and even-numbered column (VLe) is floated, so that the data voltage Vdata charged into the right data line DLR is maintained.

[0091] During the third time period TP3, the second multiplexing transistor Tm2 is turned on, and the right data line DLR of the even-numbered row HLe and the odd-numbered column VLo is charged with the data voltage Vdata. During the fourth time period TP4, the second multiplexing transistor Tm2 is turned off, and the right data line DLR of the even-numbered row HLe and the odd-numbered column VLo is floated, so that the data voltage Vdata charged into the right data line DLR is maintained.

[0092] During the sixth time period TP6, the first multiplexing transistor Tm1 is turned on, and the left data line DLL of even-numbered rows HLe and even-numbered columns VLe is charged with data voltage Vdata. During the seventh time period TP7, the first multiplexing transistor Tm1 is turned off, and the left data line DLL of even-numbered rows HLe and even-numbered columns VLe is floated, so that the data voltage Vdata charged in the left data line DLL is maintained.

[0093] During the second time period TP2, the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst of the (n+1)-1 pixel P(n+1)1 and the (n+1)-2 pixel P(n+1)2 are initialized (initialization time period of even row HLe).

[0094] During the third time period TP3 and the fourth time period TP4, the sum of the data voltage Vdata and the threshold voltage Vth (Vdd+Vth) is stored in the gate electrode of the driving transistor Td of the (n+1)-1th pixel P(n+1)1 and the first electrode of the storage capacitor Cst (sampling periods for even-numbered rows HLe and odd-numbered columns VLo). During the sixth time period TP6 and the seventh time period TP7, the sum of the data voltage Vdata and the threshold voltage Vth (Vdd+Vth) is stored in the gate electrode of the driving transistor Td of the (n+1)-2th pixel P(n+1)2 and the first electrode of the storage capacitor Cst (sampling periods for even-numbered rows HLe and even-numbered columns VLe).

[0095] After the eighth time period TP8, the LEDs De of the (n-1)th pixel Pn1 and the (n-2)th pixel Pn2 emit light (the emitting period of the odd-numbered rows HLo). After the end of the eighth time period TP8, the LEDs De1 of the (n+1)-1th pixel P(n+1)1 and the (n+1)-2th pixel P(n+1)2 emit light (the emitting period of the even-numbered rows HLe).

[0096] The OLED display device according to the first embodiment of this disclosure is driven such that the sampling periods of odd-numbered rows HLo and odd-numbered columns VLo do not overlap with the sampling periods of odd-numbered rows HLo and even-numbered columns VLe, and the sampling periods of even-numbered rows HLe and odd-numbered columns VLo do not overlap with the sampling periods of even-numbered rows HLe and even-numbered columns VLe.

[0097] As a result, when the data voltage Vdata is applied to the next row HL, the number of floating data lines DL in the current row decreases, and the change (ripple) in the high-level voltage Vdd due to the change in the data voltage Vdata applied to the next row HL is reduced. Furthermore, the distortion of the floating data voltage Vdata in the current row HL due to the change in the high-level voltage Vdd is reduced, and degradation such as crosstalk is minimized.

[0098] The reduction in data voltage variation in the OLED display device 110 will be explained with reference to the accompanying drawings.

[0099] Figures 5A to 5C This is a diagram illustrating the connection and operation of pixels in an organic light-emitting diode display device according to a first embodiment of the present disclosure, and Figure 6A and Figure 6B These are diagrams showing the high-level voltage changes of an organic light-emitting diode display device according to a comparative example and a first embodiment of the present disclosure.

[0100] exist Figures 5A to 5CIn the first embodiment of the present disclosure, the display panel 160 of the OLED display device 110 includes first-1 pixels P11 to sixth-6 pixels P66 divided into first row HL1 to sixth row HL6 and first column VL1 to sixth column VL6.

[0101] Gate line G1L for transmitting gate voltage S1, gate line G2L for transmitting gate voltage S2, and gate line G3L for transmitting gate voltage S3 are disposed in each of the first row HL1 to the sixth row HL6. Gate line G1L contacts each sub-pixel SP of pixel P in the first column VL1 to the sixth column VL6 of each of the first row HL1 to the sixth row HL6, gate line G2L contacts each sub-pixel SP of pixel P in the first column VL1, third column VL3, and fifth column VL5 (odd columns) of each of the first row HL1 to the sixth row HL6, and gate line G3L contacts each sub-pixel SP of pixel P in the second column VL2, fourth column VL4, and sixth column VL6 (even columns) of each of the first row HL1 to the sixth row HL6.

[0102] exist Figure 5A In the first row HL1, the initialization of columns VL1 to VL6 is performed.

[0103] During the initialization period of the first row HL1 of the odd-numbered rows, the gate 1 voltage S1 is provided to the first-1 pixel P11 to the first-6 pixel P16 through the gate 1 line G1L.

[0104] For example, during the first time period TP1, pixels P11 to P16 of the first row HL1 of odd-numbered rows can be initialized.

[0105] exist Figure 5B In the process, the initialization of the first column VL1 to the sixth column VL6 of the third row HL3 is performed simultaneously, as well as the sampling of the first column VL1, the third column VL3 and the fifth column VL5 of the second row HL2 and the first row HL1.

[0106] During the initialization period of the third row HL3 in odd-numbered rows, the gate 1 voltage S1 is provided to pixels P31 to P36 (3-1) through the gate 1 line G1L.

[0107] Meanwhile, during the sampling period of the second row HL2 of even-numbered rows and the first column VL1, third column VL3 and fifth column VL5 of the first row HL1 of odd-numbered rows, the gate 2 voltage S2 is provided to the second-1 pixel P21, the second-3 pixel P23 and the second-5 pixel P25, as well as the first-1 pixel P11, the first-3 pixel P13 and the first-5 pixel P15 through the gate 2 line G2L.

[0108] For example, during the third time period TP3, pixels P31 to P36 of the third row HL3 in odd-numbered rows can be initialized, and pixels P21, P23, and P25 of the second row HL2 in even-numbered rows, as well as pixels P11, P13, and P15 of the first row HL1 in odd-numbered rows, can be sampled.

[0109] While the right data line DLR of the second row HL2, the second-1st pixel P21, the second-3rd pixel P23, and the second-5th pixel P25, is charged with data voltage Vdata, the first row HL1, the first-1st pixel P11, the first-3rd pixel P13, and the first-5th pixel P15 are floated, so that the data voltage Vdata charged in the left data line DLL is maintained.

[0110] Half of the six pixels, namely pixels 2-1 (P21), 2-3 (P23), and 2-5 (P25), have their right data lines DLR charged with data voltage Vdata, instead of all the right data lines DLR of pixels 2-1 (P21) to 2-6 (P26) in the second row HL2 being charged with data voltage Vdata. As a result, due to the right data lines DLR of the second row HL2 and ( Figures 8A to 8D The change (ripple) of the high-level voltage Vdd of the first power line PL1 caused by the coupling of the first power line PL1 is reduced, and the distortion of the floating data voltage Vdata of the left data line DLL of the first row HL1 caused by the coupling of the first power line PL1 and the left data line DLL of the first row HL1 is reduced.

[0111] exist Figure 5C In the process, the initialization of the first column VL1 to the sixth column VL6 of the fifth row HL5 is performed simultaneously; the sampling of the first column VL1, the third column VL3 and the fifth column VL5 of the fourth row HL4 and the third row HL3 is performed simultaneously; and the sampling of the second column VL2, the fourth column VL4 and the sixth column VL6 of the second row HL2 and the first row HL1 is performed simultaneously.

[0112] During the initialization period of the fifth row HL5 in odd-numbered rows, the gate 1 voltage S1 is provided to the fifth-1 pixel P51 to the fifth-6 pixel P56 through the gate 1 line G1L.

[0113] Meanwhile, during the sampling period of the first column VL1, third column VL3 and fifth column VL5 of the odd columns in the third row of odd rows HL3 and the fourth row of even rows HL4, the gate 2 voltage S2 is provided to the fourth-1 pixel P41, the fourth-3 pixel P43 and the fourth-5 pixel P45, as well as the third-1 pixel P31, the third-3 pixel P33 and the third-5 pixel P35 through the gate 2 line G2L.

[0114] Meanwhile, during the sampling period of the second row HL2 of even-numbered rows and the second column VL2, fourth column VL4 and sixth column VL6 of the first row HL1 of odd-numbered rows, the gate 3 voltage S3 is provided to the second-2 pixel P22, the second-4 pixel P24 and the second-6 pixel P26, as well as the first-2 pixel P12, the first-4 pixel P14 and the first-6 pixel P16 through the gate 3 line G3L.

[0115] For example, during the fifth time period TP5, pixels P51 to P56 of the fifth row HL5 in odd-numbered rows can be initialized, pixels P41, P43, and P45 of the fourth row HL4 in even-numbered rows, pixels P31, P33, and P35 of the third row HL3 in odd-numbered rows can be sampled, and pixels P22, P24, and P26 of the second row HL2 in even-numbered rows, pixels P12, P14, and P16 of the first row HL1 in odd-numbered rows can be sampled.

[0116] While the right data line DLR of the fourth row HL4 (pixels 4-1, P41, 4-3, P43, and 4-5, P45) is charged with data voltage Vdata, the left data line DLL of the third row HL3 (pixels 3-1, P31, 3-3, P33, and 3-5, P35) is floated, so that the data voltage Vdata charged in the left data line DLL is maintained.

[0117] Half of the six pixels, namely the right data lines DLR of pixels 4-1 (P41), 4-3 (P43), and 4-5 (P45), are charged with data voltage Vdata, instead of the right data lines DLR of all pixels 4-1 (P41) to 4-6 (P46) in the fourth row HL4. This results in (…) the coupling between the right data lines DLR of the fourth row HL4 and the first power line PL1. Figures 8A to 8D The change (ripple) of the high-level voltage Vdd of the first power line PL1 is reduced, and the distortion of the floating data voltage Vdata of the left data line DLL of the third row HL3 caused by the coupling of the first power line PL1 and the left data line DLL of the third row HL3 is reduced.

[0118] While the right data line DLR of the second row HL2, pixels 2-2 (P22), 2-4 (P24), and 2-6 (P26), is charged with data voltage Vdata, the left data line DLL of the first row HL1, pixels 1-2 (P12), 1-4 (P14), and 1-6 (P16), is floated, so that the data voltage Vdata charged in the left data line DLL is maintained.

[0119] Half of the six pixels, namely pixels 2-2 (P22), 2-4 (P24), and 2-6 (P26), have their right data lines DLR charged with data voltage Vdata, instead of all the right data lines DLR of pixels 2-1 (P21) to 2-6 (P26) in the second row HL2. This results in ( ) being charged with data voltage Vdata due to the coupling between the right data lines DLR of the second row HL2 and the first power line PL1. Figures 8A to 8D The variation (ripple) of the high-level voltage Vdd of the first power line PL1 is reduced, and the distortion of the floating data voltage Vdata of the left data line DLL of the first row HL1 caused by the coupling of the first power line PL1 and the left data line DLL of the first row HL1 is reduced.

[0120] exist Figure 6A In the comparative example, the sampling period of the organic light-emitting diode display device is not divided according to column VL. When the data voltage Vdata supplied to the odd-numbered column VLo and even-numbered column VLe of the next row HL transitions from low to high in the rising region RA and from high to low in the falling region FA during the sampling period, a change in the first voltage V1 RP occurs in the high-level voltage Vdd of the first power supply line PL1 due to the coupling of the left data line DLL and the right data line DLR of the next row HL with the first power supply line PL1.

[0121] exist Figure 6B In the OLED display device 110 according to the first embodiment of the present disclosure, the sampling period is divided into columns VL. When the data voltage Vdata provided to the odd-numbered column VLo of the next row HL changes from low to high in the odd-rising region RAo and from high to low in the odd-falling region FAo during the sampling period, and the data voltage Vdata provided to the even-numbered column VLe of the next row HL changes from low to high in the even-rising region RAe and from high to low in the even-falling region FAe, the high-level voltage Vdd of the first power line PL1 changes due to the coupling between the left data line DLL and the right data line DLR of the next row HL and the first power line PL1.

[0122] Since the columns VL associated with coupling are divided into odd and even columns and the number of columns VL associated with coupling is reduced by half, the change RP of the high-level voltage Vdd of the OLED display device 110 according to the first embodiment of this disclosure has a second voltage V2 (V2) that is smaller than the first voltage V1 of the change RP of the high-level voltage Vdd of the comparative example. <V1)。

[0123] As a result, the distortion of the data voltage Vdata of the current row HL decreases according to the change of the second voltage V2 of RP based on the high-level voltage Vdd.

[0124] In the OLED display device 110 according to the first embodiment of this disclosure, since gate line 2 G2L and gate line 3 G3L are respectively connected to the odd-numbered column VLo and the even-numbered column VLe, and the odd-numbered column VLo and the even-numbered column VLe are driven at different sampling periods according to the gate 2 voltage S2 and the gate 3 voltage S3, the variation (ripple) of the high-level voltage Vdd is reduced, and the distortion of the data voltage Vdata is minimized. As a result, degradation such as crosstalk is reduced.

[0125] In another implementation, the columns of pixels can be divided into odd pairs and even pairs.

[0126] Figure 7 This is a diagram illustrating the connection of pixels in an organic light-emitting diode display device according to a second embodiment of the present disclosure. Figures 8A to 8D This is a plan view showing the first to second-fourth pixels of an organic light-emitting diode display device according to the second embodiment of this disclosure, and Figure 9 This is a cross-sectional view showing the transistors and gate lines of an organic light-emitting diode display device according to a second embodiment of the present disclosure. Illustrations of a portion of the second embodiment that is identical to a portion of the first embodiment will be omitted.

[0127] exist Figure 7 middle,( Figures 8A to 8D The organic light-emitting diode (OLED) display device 210 includes pixels P11 to P66, which are divided into first rows HL1 to sixth rows HL6 and first columns VL1 to sixth columns VL6, and the first columns VL1 to sixth columns VL6 can be divided into first column pairs VLP1 to third column pairs VLP3.

[0128] The gate 1 line G1L for transmitting gate 1 voltage S1, the gate 2 line G2L for transmitting gate 2 voltage S2, and the gate 3 line G3L for transmitting gate 3 voltage S3 are arranged in each of the first row HL1 to the sixth row HL6.

[0129] Gate line G1L contacts each sub-pixel SP of pixel P in the first column VL1 to the sixth column VL6 of each of the first row HL1 to the sixth row HL6.

[0130] Gate line 2 G2L contacts each sub-pixel SP of pixel P in the first column pair VLP1 and the third column pair VLP3 of the odd-numbered pairs in each of the first row HL1 to the sixth row HL6, specifically the first column VL1, second column VL2, fifth column VL5, and sixth column VL6. Gate line 3 G3L contacts each sub-pixel SP of pixel P in the third column VL3 and fourth column VL4 of the second column pair VLP2 of the even-numbered pairs in each of the first row HL1 to the sixth row HL6.

[0131] exist Figures 8A to 8D In the second embodiment of the present disclosure, the OLED display device 210 includes first-1 pixel P11 to second-4 pixel P24 and a common block CB and a power block PB disposed between adjacent pixels, and each of the first-1 pixel P11 to second-4 pixel P24 includes a red sub-pixel SPr, a green sub-pixel SPg and a blue sub-pixel SPb.

[0132] The OLED display device 210 also includes multiple gate 1 lines G1L for transmitting gate 1 voltage S1, multiple gate 2 lines G2L for transmitting gate 2 voltage S2, multiple gate 3 lines G3L for transmitting gate 3 voltage S3, multiple light-emitting lines EL for transmitting light-emitting voltage Em, multiple initial lines IL for transmitting initial voltage Vini, multiple reference lines RL for transmitting reference voltage Vref, multiple first power lines PL1 for transmitting high-level voltage Vdd, multiple second power lines PL2 for transmitting low-level voltage Vss, and multiple left data lines DLL and right data lines DLR for transmitting data voltage Vdata.

[0133] Gate line 1 (G1L), gate line 2 (G2L), gate line 3 (G3L), and light-emitting line (EL) are configured to be horizontally parallel to the long side of the OLED display device 210, and the initial line (IL), reference line (RL), second power line (PL2), left data line (DLL), and right data line (DLR) are configured to be vertically parallel to the short side of the OLED display device 210. The first power line (PL1) is configured to be parallel to both the horizontal and vertical directions.

[0134] Gate line G1L, first power line PL1 in the horizontal direction, left data line DLL and initial line IL intersect each other to define red sub-pixel SPr, green sub-pixel SPg and blue sub-pixel SPb.

[0135] For example, in each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb, the first power line PL1, the light-emitting line EL, the gate 3 line G3L, the gate 2 line G2L, and the gate line G1L can be arranged sequentially along the vertical direction, and the left data line DLL, the right data line DLR, and the initial line IL can be arranged sequentially along the horizontal direction.

[0136] The first power line PL1 and the reference line RL in the vertical direction are set in the common block CB, and the first power line PL1 and the second power line PL2 in the vertical direction are set in the power block PB.

[0137] The first power line PL1, the reference line RL, and the seventh transistor T7 through the ninth transistor T9 are located in the common block CB, while the first power line PL1 and the second power line PL2 are located in the power block PB. This allows the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb to share the common block CB and the power block PB. As a result, the linewidths of the first power line PL1 and the second power line PL2, which transmit the high-level voltage Vdd and the low-level voltage Vss, can be maximized, and the voltage drop of the high-level voltage Vdd and the voltage rise of the low-level voltage Vss caused by the resistance and current of the lines can be minimized.

[0138] Each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb includes a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, and a light-emitting diode D, and the common block CB includes a seventh transistor T7 to a ninth transistor T9.

[0139] Each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb constituting a pixel P includes a first transistor T1 to a sixth transistor T6, and two adjacent pixels P include a seventh transistor T7 to a ninth transistor T9.

[0140] For example, each of the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb of pixel 1-1 P11 and pixel 1-2 P12 may include a first transistor T1 through a sixth transistor T6, and the common block CB between pixel 1-1 P11 and pixel 1-2 P12 may include a seventh transistor T7 through a ninth transistor T9. The seventh transistor T7 through the ninth transistor T9 of the common block CB may be connected together to the first transistor T1 through the sixth transistor T6 of each of the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb of pixel 1-1 P11 and pixel 1-2 P12.

[0141] Similarly, each of the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb of the first-3 pixels P13, the first-4 pixels P14, the second-1 pixels P21, the second-2 pixels P22, the second-3 pixels P23, and the second-4 pixels P24 may include the first transistor T1 to the sixth transistor T6, and each of the common blocks CB between the first-3 pixels P13 and the first-4 pixels P14, between the second-1 pixels P21 and the second-2 pixels P22, and between the second-3 pixels P23 and the second-4 pixels P24 may include the seventh transistor T7 to the ninth transistor T9. The seventh transistor T7 to the ninth transistor T9 of the common block CB can be connected together to the first transistor T1 to the sixth transistor T6 of each of the red sub-pixels SPr, green sub-pixels SPg and blue sub-pixels SPb of the first-3 pixels P13, the first-4 pixels P14, the second-1 pixels P21, the second-2 pixels P22, the second-3 pixels P23 and the second-4 pixels P24.

[0142] Gate line 1 G1L contacts pixels 1-1 to 2-4 P24, gate line 2 G2L contacts the first column pair of odd-numbered pairs VLP1, namely pixels 1-1 P11, 1-2 P12, 2-1 P21 and 2-2 P22, and gate line 3 G3L contacts the second column pair of even-numbered pairs VLP2, namely pixels 1-3 P13, 1-4 P14, 2-3 P23 and 2-4 P24.

[0143] For example, gate line G1L can be connected to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 of each of the red sub-pixels SPr, green sub-pixels SPg and blue sub-pixels SPb of pixels P11 to P24 and the gate electrode of the eighth transistor T8 of the common block CB.

[0144] Gate line G2L can be connected to the gate electrodes of the first transistor T1 and the second transistor T2 of each of the red sub-pixels SPr, green sub-pixels SPg and blue sub-pixels SPb of the first-1 pixel P11, the first-2 pixel P12, the second-1 pixel P21 and the second-2 pixel P22, and the gate electrode of the ninth transistor T9 of the common block CB between the second-1 pixel P21 and the second-2 pixel P22 and between the first-1 pixel P11 and the first-2 pixel P12.

[0145] Gate line G3L can be connected to the gate electrodes of the first transistor T1 and the second transistor T2 of each of the red sub-pixels SPr, green sub-pixels SPg and blue sub-pixels SPb of the first-3 pixels P13, the first-4 pixels P14, the second-3 pixels P23 and the second-4 pixels P24, and the gate electrode of the ninth transistor T9 of the common block CB between the first-3 pixels P13 and the first-4 pixels P14 and between the second-3 pixels P23 and the second-4 pixels P24.

[0146] Odd-numbered columns sample pixels P on VLPo according to gate 2 voltage S2, while even-numbered columns sample pixels P on VLPe according to gate 3 voltage S3. As a result, the number of left data lines DLL and right data lines DLR contributing to coupling is reduced, and the variation (ripple) of the high-level voltage Vdd and the distortion of the data voltage Vdata are minimized.

[0147] exist Figure 9 In this process, a buffer layer 222 is provided on the entire substrate 220, and a semiconductor layer 224 is provided on the buffer layer 222 in the region corresponding to the first transistor T1 to the ninth transistor T9.

[0148] The substrate 220 may be formed of glass or polyimide (PI), and the buffer layer 222 may have a double layer of inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2).

[0149] The buffer layer 222 can block moisture from the lower part.

[0150] Semiconductor layer 224 can be formed of a semiconductor material such as silicon or an oxide semiconductor material. When semiconductor layer 224 includes polysilicon, semiconductor layer 224 can have an active region in the center and source-drain regions on both sides of the active region.

[0151] A gate insulating layer 226 is disposed on the entire semiconductor layer 224, and a gate electrode 230 and a first gate pattern 232 are disposed on the gate insulating layer 226.

[0152] Although not shown, a first capacitor electrode connected to the gate electrode of the driving transistor Td may be provided in the region on the gate insulating layer 226 corresponding to the storage capacitor Cst.

[0153] The gate insulating layer 226 may be formed of an inorganic insulating material such as silicon oxide (SiO2), and the gate electrode 230, the first gate pattern 232 and the first capacitor electrode may be formed of a metallic material such as molybdenum (Mo).

[0154] The gate electrode 230 can be disposed in the region corresponding to the first transistor T1 to the ninth transistor T9, and the first gate pattern 232 can be disposed in the region corresponding to the gate line G1L, the gate line G2L and the gate line G3L.

[0155] The gate electrode 230, the first gate pattern 232, and the first capacitor electrode may have the same layer and the same material as each other.

[0156] A first interlayer insulating layer 234 is provided on the entire gate electrode 230, and a second gate pattern 236 is provided in the region on the first interlayer insulating layer 234 corresponding to the first gate pattern 232.

[0157] Although not shown, a second capacitor electrode connected to the drain electrode of the seventh transistor T7 may be provided in the region corresponding to the storage capacitor Cst on the first interlayer insulating layer 234.

[0158] The first interlayer insulating layer 234 may be formed of an inorganic insulating material such as silicon nitride (SiNx), and the second gate pattern 236 and the second capacitor electrode may be formed of a metallic material such as molybdenum (Mo).

[0159] The first capacitor electrode, the first interlayer insulating layer 234, and the second capacitor electrode constitute the storage capacitor Cst.

[0160] A second interlayer insulating layer 240 is formed over the entire second gate pattern 2236 and the second capacitor electrode. A source electrode, a drain electrode 242, and a first connection electrode 244 are formed in the region on the second interlayer insulating layer 240 corresponding to the first transistor T1 to the ninth transistor T9, and a second connection electrode 246 and a third connection electrode 250 are formed in the region on the second interlayer insulating layer 240 corresponding to the second gate pattern 236.

[0161] The second interlayer insulating layer 240 may have a double layer of inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), and the source electrode, drain electrode 242, and the first to third connecting electrodes 244, 246 and 250 may have a triple layer of metallic material such as titanium (Ti) and aluminum (Al).

[0162] The source electrode and drain electrode 242 are connected to both sides of the semiconductor layer 224 through contact holes in the gate insulating layer 226, the first interlayer insulating layer 234, and the second interlayer insulating layer 240. The semiconductor layer 224, the gate electrode 230, the source electrode, and the drain electrode 242 constitute the first transistor T1 to the ninth transistor T9.

[0163] A first planarization layer 252 is formed on the entire source electrode, drain electrode 242, and the first to third connecting electrodes 244, 246, and 250. An auxiliary electrode 254 is formed in the region on the first planarization layer 252 corresponding to the light-emitting diode De, and gate line G1L, gate line G2L, and gate line G3L are formed in the region on the first planarization layer 252 corresponding to the second gate pattern 236.

[0164] The first planarization layer 252 can be formed of an organic insulating material such as photoacrylic acid, and the auxiliary electrode 254, gate line 1 G1L, gate line 2 G2L and gate line 3 G3L can have three layers of metallic materials such as titanium (Ti) and aluminum (Al).

[0165] The auxiliary electrode 254 is connected to the drain electrode 242 of the fourth transistor T4 through the contact hole of the first planarization layer 252.

[0166] The auxiliary electrode 254, gate line 1 G1L, gate line 2 G2L and gate line 3 G3L can be formed from the same layer and the same material.

[0167] A second planarization layer 260 is provided on the entire auxiliary electrode 254, gate line 1 G1L, gate line 2 G2L and gate line 3 G3L, and an anode 262 is provided in the region on the second planarization layer 260 corresponding to the light-emitting diode De.

[0168] The second planarization layer 260 can be formed of an organic insulating material such as photoacrylic acid, and the anode 262 can have three layers of a transparent conductive material such as indium tin oxide (ITO) and a metallic material such as a silver palladium copper (APC) alloy.

[0169] The anode 262 is connected to the auxiliary electrode 254 through the contact hole of the second planarization layer 260.

[0170] A dam 264 is provided on the edge portion of the anode 262, and a light-emitting layer 270 is provided on the anode 262 exposed through the opening of the dam 264.

[0171] The dam layer 264 can be formed of an organic insulating material such as polyimide (PI), and the light-emitting layer 270 can emit red light, green light and blue light in the red sub-pixel SPr, the green sub-pixel SPg and the blue sub-pixel SPb, respectively.

[0172] A spacer 266 is provided on the embankment 270, and a cathode 272 is provided on the entire spacer 266.

[0173] The spacer 266 can be formed of an organic insulating material such as polyimide (PI), and a low-level voltage Vss can be applied to the cathode 272.

[0174] Anode 262, light-emitting layer 270 and cathode 272 constitute a light-emitting diode De.

[0175] The OLED display device 110 according to the first embodiment of the present disclosure may have the same structure as the OLED display device 210 according to the second embodiment of the present disclosure.

[0176] In the OLED display device 210 according to the second embodiment of this disclosure, gate line 2 G2L and gate line 3 G3L are respectively connected to the odd-numbered column pair VLPo and the even-numbered column pair VLPe, and the odd-numbered column pair VLPo and the even-numbered column pair VLPe are driven according to different sampling periods based on the gate 2 voltage S2 and the gate 3 voltage S3, respectively. As a result, the variation (ripple) of the high-level voltage Vdd is reduced and the distortion of the data voltage Vdata is minimized. In addition, degradation such as crosstalk is reduced.

[0177] A common block CB is set in each of the odd-numbered column pairs VLPo and even-numbered column pairs VLPe, and the odd-numbered column pair VLPo or even-numbered column pair connected to a common block CB is driven during the sampling period based on the gate 2 voltage S2 and the gate 3 voltage S3. As a result, the operation of the odd-numbered column pair VLPo or even-numbered column pair VLPe connected to a common block CB is stabilized.

[0178] Therefore, in the OLED display device according to the embodiments of this disclosure, since multiple pixel columns are divided into odd and even groups, and the pixel columns in the odd and even groups have different sampling periods, the number of pixel columns corresponding to the floating data lines is reduced. As a result, the distortion of the data voltage caused by the change of high-level voltage (ripple) is reduced, and degradation such as crosstalk is reduced.

[0179] In the OLED display device according to embodiments of the present disclosure, a single common block is provided in two pixels, and the pixel columns corresponding to the common block have the same sampling period. Furthermore, multiple pixel columns are divided into odd-pair groups and even-pair groups, with the pixel columns in the odd-pair groups and even-pair groups having different sampling periods. As a result, the operation of the pixel columns corresponding to the common block is stabilized. In addition, the number of pixel columns corresponding to floating data lines is reduced, data voltage distortion caused by changes in high-level voltage (ripple) is reduced, and degradation such as crosstalk is minimized.

[0180] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover any modifications and variations that fall within the scope of the appended claims.

Claims

1. An organic light-emitting diode (OLED) display device, comprising: Multiple pixels, the multiple pixels being arranged in a matrix of multiple rows and multiple columns; Multiple first gate lines are connected to the multiple pixels and provide a first gate voltage to the multiple pixels; Multiple second gate lines are connected to multiple pixels in an odd number of columns and provide a second gate voltage to the multiple pixels in the odd number of columns. Multiple third gate lines, the multiple third gate lines contacting multiple pixels in even-numbered columns of the multiple columns and providing a third gate voltage to the multiple pixels in even-numbered columns of the multiple columns; and Multiple left data lines and multiple right data lines located on both sides of multiple pixels in the multiple columns, respectively. The time period for sampling the plurality of pixels in the odd-numbered columns according to the second gate voltage is separate from the time period for sampling the plurality of pixels in the even-numbered columns according to the third gate voltage. The second gate voltage includes the nth second gate voltage and the (n+1)th second gate voltage, and the third gate voltage includes the nth third gate voltage and the (n+1)th third gate voltage, where n is odd and (n+1) is even. The time period for sampling the plurality of pixels in the odd-numbered rows of the odd-numbered column according to the nth second gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the odd-numbered column according to the (n+1)th second gate voltage by a horizontal time period, and The time period for sampling the plurality of pixels in the odd-numbered rows of the even-numbered column according to the nth third gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the even-numbered column according to the (n+1)th third gate voltage by a horizontal time period.

2. The display device according to claim 1, wherein when the second gate voltage is provided to the plurality of pixels in the odd-numbered columns of the plurality of columns, the third gate voltage is not provided to the plurality of pixels in the even-numbered columns of the plurality of columns, and When the third gate voltage is provided to the pixels in the even-numbered columns of the plurality of columns, the second gate voltage is not provided to the pixels in the odd-numbered columns of the plurality of columns.

3. The display device according to claim 1, wherein the odd-numbered columns include pixels 1-1 and 1-3, and the even-numbered columns include pixels 1-2 and 1-4. Each of the first-1 pixel, the first-2 pixel, the first-3 pixel, and the first-4 pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and a common block is provided between the first-1 pixel and the first-2 pixel, and between the first-3 pixel and the first-4 pixel. Each of the red sub-pixel, the green sub-pixel, and the blue sub-pixel includes a first transistor through a sixth transistor, and The common block includes the seventh to ninth transistors connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

4. The display device according to claim 1, wherein the plurality of left data lines contact a plurality of pixels in the odd-numbered rows of the plurality of rows, and The multiple right data lines contact multiple pixels in the even-numbered rows of the multiple rows.

5. The display device according to claim 4, further comprising a multiplexing unit connected to the plurality of left data lines and the plurality of right data lines. The multiplexing unit includes a first multiplexing transistor connected to the plurality of left data lines and a second multiplexing transistor connected to the plurality of right data lines.

6. The display device according to claim 1, wherein the time period for sampling the plurality of pixels in the odd-numbered rows of the odd-numbered columns according to the nth second gate voltage is separated from the time period for sampling the plurality of pixels in the odd-numbered rows of the even-numbered columns according to the nth third gate voltage by a horizontal time period, and The time period for sampling the plurality of pixels in the even-numbered rows of the odd-numbered column according to the (n+1)th second gate voltage is separated from the time period for sampling the plurality of pixels in the even-numbered rows of the even-numbered column according to the (n+1)th third gate voltage by a horizontal time period.

7. An organic light-emitting diode display device, comprising: Multiple pixels, the multiple pixels being arranged in a matrix of multiple rows and multiple columns; Multiple first gate lines are connected to the multiple pixels and provide a first gate voltage to the multiple pixels; Multiple second gate lines are connected to multiple pixels in an odd number of column pairs of the multiple columns and provide a second gate voltage to the multiple pixels in the odd number of column pairs of the multiple columns; Multiple third gate lines, the multiple third gate lines contacting multiple pixels in even-numbered column pairs of the multiple columns and providing a third gate voltage to the multiple pixels in even-numbered column pairs of the multiple columns; and Multiple left data lines and multiple right data lines located on both sides of multiple pixels in the multiple columns, respectively. The time period for sampling the plurality of pixels in the odd-numbered column pairs according to the second gate voltage is separate from the time period for sampling the plurality of pixels in the even-numbered column pairs according to the third gate voltage. The second gate voltage includes the nth second gate voltage and the (n+1)th second gate voltage, and the third gate voltage includes the nth third gate voltage and the (n+1)th third gate voltage, where n is odd and (n+1) is even. The time period for sampling the plurality of pixels in the odd-numbered rows of the odd-numbered column pair according to the nth second gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the odd-numbered column pair according to the (n+1)th second gate voltage by a horizontal time period, and The time period for sampling the plurality of pixels in the odd row of the even column pair according to the nth third gate voltage overlaps with the time period for sampling the plurality of pixels in the even row of the even column pair according to the (n+1)th third gate voltage by a horizontal time period.

8. The display device according to claim 7, wherein the odd-numbered column pairs include pixels 1-1 and 1-2, and the even-numbered column pairs include pixels 1-3 and 1-4. Each of the first-1 pixel, the first-2 pixel, the first-3 pixel, and the first-4 pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A common block is provided between the first-1 pixel and the first-2 pixel, and between the first-3 pixel and the first-4 pixel. Each of the red sub-pixel, the green sub-pixel, and the blue sub-pixel includes a first transistor through a sixth transistor, and The common block includes the seventh to ninth transistors connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

9. A method for driving an organic light-emitting diode display device, comprising: Multiple pixels in multiple rows are initialized based on the first gate voltage; Based on the second gate voltage, multiple pixels in the odd-numbered columns of multiple columns are sampled; Multiple pixels in even-numbered columns of multiple columns are sampled based on the third gate voltage; as well as Light is emitted from multiple pixels based on the emission voltage. The time period for sampling the plurality of pixels in the odd-numbered columns according to the second gate voltage is separate from the time period for sampling the plurality of pixels in the even-numbered columns according to the third gate voltage. The second gate voltage includes the nth second gate voltage and the (n+1)th second gate voltage, and the third gate voltage includes the nth third gate voltage and the (n+1)th third gate voltage, where n is odd and (n+1) is even. The time period for sampling the plurality of pixels in the odd-numbered rows of the odd-numbered column according to the nth second gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the odd-numbered column according to the (n+1)th second gate voltage by a horizontal time period, and The time period for sampling the plurality of pixels in the odd-numbered rows of the even-numbered column according to the nth third gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the even-numbered column according to the (n+1)th third gate voltage by a horizontal time period.

10. The method of claim 9, wherein when the second gate voltage is provided to the plurality of pixels in the odd-numbered columns of the plurality of columns, the third gate voltage is not provided to the plurality of pixels in the even-numbered columns of the plurality of columns, and When the third gate voltage is provided to the pixels in the even-numbered columns of the plurality of columns, the second gate voltage is not provided to the pixels in the odd-numbered columns of the plurality of columns.

11. A method for driving an organic light-emitting diode display device, comprising: Multiple pixels in multiple rows are initialized based on the first gate voltage; Based on the second gate voltage, multiple pixels of odd-numbered column pairs in multiple columns are sampled; Based on the third gate voltage pair, multiple pixels in even-numbered column pairs of the plurality of columns are sampled; as well as Light is emitted from multiple pixels based on the emission voltage. The time period for sampling the plurality of pixels in the odd-numbered column pairs according to the second gate voltage is separate from the time period for sampling the plurality of pixels in the even-numbered column pairs according to the third gate voltage. The second gate voltage includes the nth second gate voltage and the (n+1)th second gate voltage, and the third gate voltage includes the nth third gate voltage and the (n+1)th third gate voltage, where n is odd and (n+1) is even. The time period for sampling the plurality of pixels in the odd-numbered rows of the odd-numbered column pair according to the nth second gate voltage overlaps with the time period for sampling the plurality of pixels in the even-numbered rows of the odd-numbered column pair according to the (n+1)th second gate voltage by a horizontal time period, and The time period for sampling the plurality of pixels in the odd row of the even column pair according to the nth third gate voltage overlaps with the time period for sampling the plurality of pixels in the even row of the even column pair according to the (n+1)th third gate voltage by a horizontal time period.

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